Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a semiconductor body including a first surface and a second surface; the semiconductor body further comprises a well region, a first region and a first insulating layer; the first gate is located on one side of the first insulating layer away from the semiconductor body; the second insulating cushion layer is positioned on one side, far away from the first surface, of the well region and the first region; the second grid electrode is located on the side, away from the well region and the first region, of the second insulating cushion layer, and the second grid electrode comprises a two-dimensional electron gas layer or a two-dimensional hole gas layer; the first insulating cushion layer is positioned on one side, far away from the second insulating cushion layer, of the second gate; a source electrode; and a drain electrode. According to the technical scheme of the embodiment of the invention, the buried layer epitaxy technology is adopted, the second grid electrode with the two-dimensional electron gas or two-dimensional hole gas structure is introduced into the channel region, the electric field distribution and the carrier concentration in the channel are controlled, the reliability of the semiconductor device is improved, the on-resistance is reduced, and the transconductance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide-bandgap semiconductor materials such as silicon carbide (SiC) possess excellent high-temperature performance, electronic properties, and chemical stability. For a P-type silicon carbide metal-oxide-semiconductor field-effect transistor (MOSFET), a positive voltage is applied to the source and a negative voltage to the gate. When the threshold voltage is reached, an inversion layer forms in the N-type well region. Current flows from the metal conductive layer through the doped region formed by P-type ion implantation to the inversion layer, then through the silicon carbide substrate to the drain.

[0003] However, in the existing technology, high-temperature, high-dose and high-energy ion implantation can cause lattice damage to silicon carbide, resulting in an increase in interface states. The isolation oxide layer may also have defects during preparation, causing silicon carbide semiconductor devices to have low electron mobility, transconductance lower than theoretical expectations, and excessive on-resistance. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to solve the problems of large on-resistance, low transconductance and low reliability of semiconductor devices.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0006] A semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on the first surface; the well region and the first region being in contact with each other; and the semiconductor body further comprising a first insulating layer, the first insulating layer being located on the first surface and covering the well region and a portion of the first region.

[0007] A first gate is located on a side of the first insulating layer away from the semiconductor body; the first insulating layer is used to insulate the semiconductor body from the first gate;

[0008] a second insulating pad layer, located on a side of the well region and the first region away from the first surface;

[0009] a second gate, located on a side of the second insulating pad away from the well region and the first region, the second gate comprising a two-dimensional electron gas layer or a two-dimensional hole gas layer;

[0010] a first insulating pad layer, located on a side of the second gate away from the second insulating pad layer;

[0011] a source electrode, located on the first surface;

[0012] The drain is located on the second surface.

[0013] Optionally, the semiconductor body includes a first sub-semiconductor body and a second sub-semiconductor body, and the first sub-semiconductor body includes a fifth surface and a sixth surface arranged opposite to each other;

[0014] The second sub-semiconductor body includes a third surface and a fourth surface arranged opposite to each other; the fourth surface and the fifth surface are in contact; the third surface is the first surface of the semiconductor body; the sixth surface is the second surface of the semiconductor body; the second sub-semiconductor body is located on a side of the fifth surface of the first sub-semiconductor body away from the sixth surface; the second sub-semiconductor body also includes a well region and a first region, the first region is configured as a first conductivity type and is located on the third surface, and the well region is configured as a second conductivity type and is located on the third surface; the well region and the first region are in contact with each other; the second sub-semiconductor body also includes a first insulating layer, the first insulating layer is located on the third surface and covers the well region and a portion of the first region;

[0015] The first gate is located on a side of the first insulating layer away from the second sub-semiconductor body; the first insulating layer is used to insulate the second sub-semiconductor body from the first gate;

[0016] The first insulating pad is located on the fifth surface of the first sub-semiconductor body;

[0017] The second gate is located on a side of the first insulating pad away from the fifth surface, the second gate includes a two-dimensional electron gas layer or a two-dimensional hole gas layer, and is located on a side of the well region and the first region away from the third surface;

[0018] The second insulating pad is located on a side of the second gate away from the first sub-semiconductor body;

[0019] The source is located on the third surface;

[0020] The drain is located on the sixth surface.

[0021] Optionally, the second gate includes a first gallium nitride layer and a second gallium nitride layer; the first gallium nitride layer is located on a side of the first insulating pad layer away from the fifth surface; the second gallium nitride layer is located on a side of the first gallium nitride layer away from the first insulating pad layer, and the second gallium nitride layer is a gallium nitride material doped with the second conductivity type;

[0022] The second insulating pad is located on a side of the second gallium nitride layer away from the first gallium nitride layer;

[0023] The first conductivity type is N-type, and a two-dimensional electron gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer; the first conductivity type is P-type, and a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0024] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0025] Optionally, the semiconductor body further includes a second region; the second region is set to the second conductivity type and is located on the first surface; the second region is in contact with the first region.

[0026] Optionally, the second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

[0027] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:

[0028] A semiconductor body is provided, the semiconductor body including a first surface and a second surface; the semiconductor body also including a well region and a first region, the first region being set to a first conductivity type and located on the first surface, and the well region being set to a second conductivity type and located on the first surface; the well region and the first region being in contact with each other; the semiconductor body also including a first insulating layer, the first insulating layer being located on the first surface and covering the well region and a portion of the first region; a second insulating pad layer being located on a side of the well region and the first region away from the first surface; a second gate being located on a side of the second insulating pad layer away from the well region and the first region, the second gate including a two-dimensional electron gas layer or a two-dimensional hole gas layer; and the first insulating pad layer being located on a side of the second gate away from the second insulating pad layer;

[0029] A first gate is formed on a side of the first insulating layer away from the semiconductor body; the first insulating layer is used to insulate the semiconductor body and the first gate;

[0030] forming a source electrode on the first surface;

[0031] A drain electrode is formed on the second surface.

[0032] Optionally, providing a semiconductor body includes:

[0033] Providing a first semiconductor sub-body, the first semiconductor sub-body comprising a fifth surface and a sixth surface disposed opposite to each other;

[0034] forming a first insulating pad layer on the fifth surface of the first sub-semiconductor body;

[0035] A second gate is formed on a side of the first insulating pad away from the fifth surface; the second gate includes a two-dimensional electron gas layer or a two-dimensional hole gas layer;

[0036] forming a second insulating pad layer on a side of the second gate away from the first sub-semiconductor body;

[0037] A second sub-semiconductor body is provided, the second sub-semiconductor body including a third surface and a fourth surface arranged opposite to each other; the fourth surface and the fifth surface are in contact; the second sub-semiconductor body is located on a side of the fifth surface of the first sub-semiconductor body away from the sixth surface; the second sub-semiconductor body also includes a well region and a first region, the first region is set to a first conductivity type and is located on the third surface, and the well region is set to a second conductivity type and is located on the third surface; the well region and the first region are in contact with each other; the second sub-semiconductor body also includes a first insulating layer, the first insulating layer is located on the third surface and covers the well region and a portion of the first region.

[0038] Optionally, forming a second gate on a side of the first insulating pad away from the fifth surface includes:

[0039] forming a first gallium nitride layer on a side of the first insulating pad away from the fifth surface;

[0040] A second gallium nitride layer is formed on a side of the first gallium nitride layer away from the first insulating pad layer; the second gallium nitride layer is a gallium nitride material doped with the second conductivity type, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0041] Optionally, providing the second semiconductor sub-body includes:

[0042] providing a second semiconductor sub-body, wherein the second semiconductor sub-body includes a third surface and a fourth surface disposed opposite to each other;

[0043] A well region and a first region are formed on the third surface; the first region is set to the first conductivity type and is located on the third surface; the well region is set to the second conductivity type and is located on the third surface;

[0044] A first insulating layer is formed on the third surface; the first insulating layer covers the well region and a portion of the first region.

[0045] Optionally, after forming the well region and the first region on the third surface, the method further includes:

[0046] A second region is formed on the third surface. The second region is configured to be of the second conductivity type and is in contact with the first region.

[0047] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0048] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0049] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0050] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0051] The technical solution of the embodiment of the present invention is to set a second gate on the side of the well region away from the first surface, and set a first gate on the side of the well region close to the first surface, thereby increasing the number of gates and the length of the channel, improving the control capability of the gate, reducing the on-resistance of the device, and improving the transconductance, thereby improving the reliability of the device. In addition, depending on the conductivity type of the MOSFET device, the second gate includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Since the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and has a high conductivity and carrier concentration, the on-resistance of the device is further reduced and the transconductance is improved without increasing the thickness of the device. In addition, the first insulating pad is provided as a transition layer, which not only facilitates lattice matching but also insulates the second gate from the semiconductor body.

[0052] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0055] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0056] Figure 3 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0057] Figure 4 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0058] Figure 5-Figure 11 are cross-sectional views corresponding to various steps of another method for manufacturing a semiconductor device provided in accordance with an embodiment of the present invention;

[0059] Figure 12 According to an embodiment of the present invention, Figure 4 A schematic diagram of the process included in S130;

[0060] Figure 13 According to an embodiment of the present invention, Figure 4 Schematic diagram of the process included in S150. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0063] In order to improve the reliability of semiconductor devices, reduce on-resistance, and improve transconductance, the embodiments of the present invention provide the following technical solutions:

[0064] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention, such as Figure 1As shown, the semiconductor device includes: a semiconductor body 600, including a first surface 601 and a second surface 602 arranged opposite to each other; the semiconductor body 600 also includes a well region 203 and a first region 204, the first region 204 is set to a first conductivity type and is located on the first surface 601, and the well region 203 is set to a second conductivity type and is located on the first surface 601; the well region 203 and the first region 204 are in contact with each other; the semiconductor body 600 also includes a first insulating layer 205, the first insulating layer 205 is located on the first surface 601 and covers the well region 203 and a portion of the first region 204; a first gate 300 is located on the first surface 601 The insulating layer 205 is located on a side away from the semiconductor body 600; the first insulating layer 205 is used to insulate the semiconductor body 600 and the first gate 300; the second insulating pad 50 is located on a side of the well region 203 and the first region 204 away from the first surface 601; the second gate 40 is located on a side of the second insulating pad 50 away from the well region 203 and the first region 204, and the second gate 40 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer; the first insulating pad 30 is located on a side of the second gate 40 away from the second insulating pad 50; the source 400 is located on the first surface 601; the drain 500 is located on the second surface 602.

[0065] In the embodiment of the present invention, Figure 1 As shown, the semiconductor body 600 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 600 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 600 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0066] Semiconductor devices include but are not limited to N-type MOSFETs or P-type MOSFETs. The semiconductor body 600 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 204 in the semiconductor body 600 is an N+ doped region, and the N-type dopant ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 203 is a P-well region, and the P-type dopant ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0067] The first gate 300 may be polysilicon. The first insulating layer 205 is used to insulate the semiconductor body 600 from the first gate 300. The first insulating layer 205 may be a gate oxide layer. When forming the second gate 40, a first insulating pad layer 30 is provided.

[0068] In an embodiment of the present invention, the semiconductor device further includes an interlayer dielectric layer 301. The interlayer dielectric layer 301 provides electrical isolation between the first gate 300 and the source 400, preventing electron migration between different metal layers and preventing diffusion or penetration between substances. The interlayer dielectric layer 301 may be made of silicon dioxide. The interlayer dielectric layer 301 may be formed by plasma-enhanced chemical vapor deposition.

[0069] In an embodiment of the present invention, the second gate 40 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Since the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and a high conductivity, for an N-type MOSFET device, the second gate 40 includes a two-dimensional electron gas layer, which includes a large amount of two-dimensional electron gas, wherein the carrier mobility is greater than that of silicon carbide or gallium nitride. The side of the well region 203 away from the first surface 601 and the side of the well region 203 close to the first surface 601 both serve as a conductive channel, increasing the length of the channel and reducing the conductive resistance.

[0070] The technical solution of the embodiment of the present invention is to set a second gate 40 on the side of the well region 203 away from the first surface 601, and to set a first gate 300 on the side of the well region 203 close to the first surface 601. This increases the number of gates and the length of the channel, improves the control capability of the gate, reduces the on-resistance of the device, and improves the transconductance, thereby improving the reliability of the device. In addition, depending on the conductivity type of the MOSFET device, the second gate 40 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Because the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and has a high conductivity and carrier concentration, the on-resistance of the device is further reduced and the transconductance is improved without increasing the thickness of the device. In addition, the first insulating pad layer 30 is provided as a transition layer, which not only facilitates lattice matching but also insulates the second gate 40 from the semiconductor body 600.

[0071] In an optional embodiment of the present invention, reference Figure 1The semiconductor body 600 includes a first sub-semiconductor body 100 and a second sub-semiconductor body 200. The first sub-semiconductor body 100 includes a fifth surface 101 and a sixth surface 102 arranged opposite to each other; the second sub-semiconductor body 200 includes a third surface 201 and a fourth surface 202 arranged opposite to each other; the fourth surface 202 is in contact with the fifth surface 101; the third surface 201 is the first surface 601 of the semiconductor body 600; the sixth surface 102 is the second surface 602 of the semiconductor body 600; the second sub-semiconductor body 200 is located on the side of the fifth surface 101 of the first sub-semiconductor body 100 away from the sixth surface 102; the second sub-semiconductor body 200 further includes a well region 203 and a first region 204, the first region 204 is set to the first conductivity type and is located on the third surface 201, the well region 203 is set to the second conductivity type and is located on the third surface 201; the well region 203 and the first region 204 are in contact with each other; the second sub-semiconductor body 200 also includes a first insulating layer 205, the first insulating layer 205 is located on the third surface 201 and covers the well region 203 and part of the first region 204; the first gate 300 is located on the side of the first insulating layer 205 away from the second sub-semiconductor body 200; the first insulating layer 205 is used to insulate the second sub-semiconductor body 200 and the first gate 300; the first insulating pad 30 is located on the fifth surface 101 of the first sub-semiconductor body 100; the second gate 40 is located on the side of the first insulating pad 30 away from the fifth surface 101, the second gate 40 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer, and is located on the side of the well region 203 and the first region 204 away from the third surface 201; the second insulating pad 50 is located on the side of the second gate 40 away from the first sub-semiconductor body 100; the source 400 is located on the third surface 201; the drain 500 is located on the sixth surface 102.

[0072] In the embodiment of the present invention, Figure 1 As shown, the first semiconductor sub-body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the first semiconductor sub-body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the first semiconductor sub-body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE). The second semiconductor sub-body 200 can be formed through an epitaxial process based on the first semiconductor sub-body 100.

[0073] Semiconductor devices include but are not limited to N-type MOSFETs or P-type MOSFETs. The first sub-semiconductor body 100 and the second sub-semiconductor body 200 may include third-generation wide bandgap semiconductor materials such as silicon carbide semiconductor bodies. For N-type MOSFETs, the first conductivity type is N-type and the second conductivity type is P-type. For P-type MOSFETs, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for N-type MOSFETs, the first region 204 in the second sub-semiconductor body 200 is an N+ doped region, and the N-type dopant ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 203 is a P-well region, and the P-type dopant ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0074] The first gate 300 may be polysilicon. The first insulating layer 205 is used to insulate the second semiconductor sub-body 200 from the first gate 300. The first insulating layer 205 may be a gate oxide layer. The first insulating pad 30 is provided when the second gate 40 is formed on the fifth surface 101 of the first semiconductor sub-body 100. Before the second semiconductor sub-body 200 is formed on the side of the second gate 40 facing away from the first semiconductor sub-body 100, a second insulating pad 50 is provided on the side of the second gate 40 facing away from the first semiconductor sub-body 100.

[0075] In an optional embodiment of the present invention, reference Figure 1 The second gate 40 includes a first gallium nitride layer 401 and a second gallium nitride layer 402; the first gallium nitride layer 401 is located on a side of the first insulating pad 30 away from the fifth surface 101; the second gallium nitride layer 402 is located on a side of the first gallium nitride layer 401 away from the first insulating pad 30, and the second gallium nitride layer 402 is a gallium nitride material doped with the second conductivity type; the second insulating pad 50 is located on a side of the second gallium nitride layer 402 away from the first gallium nitride layer 401; the first conductivity type is N-type, and a two-dimensional electron gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer 401 and the second gallium nitride layer 402; the first conductivity type is P-type, and a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer 401 and the second gallium nitride layer 402.

[0076] Specifically, a two-dimensional electron gas (2DEG) is a quantum system in which electrons are confined to a two-dimensional plane under specific conditions, allowing them to move freely. It typically occurs at heterojunction interfaces, where the two semiconductor materials forming the heterojunction interface have different band structures. A two-dimensional hole gas (2DHG) is a quantum system in which holes are confined to a two-dimensional plane under specific conditions. When the first conductivity type is N-type, a two-dimensional electron gas (2DHG) exists at the interface of the heterojunction structure formed by the first gallium nitride layer 401 and the second gallium nitride layer 402. When the first conductivity type is P-type, a two-dimensional hole gas (2DHG) exists at the interface of the heterojunction structure formed by the first gallium nitride layer 401 and the second gallium nitride layer 402. Carrier mobility can be improved through modulation doping techniques.

[0077] In an optional embodiment of the present invention, reference Figure 1 , the semiconductor body 600 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0078] The semiconductor body 600 is made of silicon carbide. The semiconductor device is a silicon carbide MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0079] The semiconductor body 600 is made of gallium nitride. The semiconductor device is a gallium nitride MOSFET semiconductor device. Gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0080] When the second gate 40 is a gallium nitride epitaxial layer and a doped gallium nitride epitaxial layer, the lattice matching between the gallium nitride epitaxial layer and the doped gallium nitride epitaxial layer is high when grown on silicon carbide or gallium nitride through an epitaxial process. This reduces the difficulty of forming the first gallium nitride layer 401 through the epitaxial process, and also reduces the difficulty of forming the second sub-semiconductor body 200 through the epitaxial process on the side of the second gallium nitride layer 402 away from the first gallium nitride layer 401. The second gallium nitride layer 402 is a gallium nitride layer of the second conductivity type and can form a space charge region with the first sub-semiconductor body 100 of the first conductivity type to prevent leakage current from the source 400 to the drain 500.

[0081] In an optional embodiment of the present invention, the second gallium nitride layer 402 includes magnesium gallium nitride or aluminum gallium nitride.

[0082] In an embodiment of the present invention, a gallium nitride epitaxial layer and a gallium nitride epitaxial layer doped with magnesium ions or aluminum ions can be sequentially grown on the fifth surface 101 of the first sub-semiconductor body 100, and then the formed gallium nitride epitaxial layer is etched, and a silicon carbide epitaxial layer is secondary grown on the gallium nitride epitaxial layer to form the second sub-semiconductor body 200, so as to form a structure of silicon carbide-first insulating pad layer 30-first gallium nitride layer 401-second gallium nitride layer 402-second insulating pad layer 50-silicon carbide, and a second gate 40 with a two-dimensional electron gas layer or a two-dimensional hole gas layer is formed in the channel region.

[0083] In nanoelectronics and optoelectronics, in order to achieve specific quantum effects, the thickness of the heterojunction needs to be controlled within a relatively thin range. For example, in the heterojunction composed of a gallium nitride epitaxial layer and a magnesium gallium nitride epitaxial layer or a gallium aluminum nitride epitaxial layer, when the thickness of the magnesium gallium nitride epitaxial layer or the gallium aluminum nitride epitaxial layer is between a few nanometers and tens of nanometers, electrons and holes will be confined to this very thin spatial region, thereby more effectively controlling the behavior of carriers. Therefore, the heterojunction composed of a gallium nitride epitaxial layer and a magnesium gallium nitride epitaxial layer or a gallium aluminum nitride epitaxial layer has a relatively thin thickness and a very high conductivity. By doping the magnesium gallium nitride epitaxial layer or the gallium aluminum nitride epitaxial layer, its conductivity type can be controlled.

[0084] The second gate 40 formed by the first gallium nitride layer 401 and the second gallium nitride layer 402 can be separately connected or connected to the first gate 300. When a positive voltage is applied to the semiconductor device, the well region 203 near the second gate 40 forms an inversion layer, conducting current. When a negative voltage or zero potential is applied to the silicon carbide epitaxial layer, the second gallium nitride layer 402 doped with magnesium ions or aluminum ions becomes of the second conductivity type and forms a space charge region with the silicon carbide epitaxial layer of the first conductivity type, preventing leakage current from the source 400 to the drain 500, thereby reducing on-resistance, increasing transconductance, and improving the reliability of the semiconductor device.

[0085] In an optional embodiment of the present invention, reference Figure 1 The semiconductor body 600 further includes a second region 206 ; the second region 206 is configured as a second conductivity type and is located on the first surface 601 ; the second region 206 is in contact with the first region 204 .

[0086] In the embodiment of the present invention, the conductivity type of the second region 206 is the same as that of the well region 203, and both are set to the second conductivity type. For an N-type MOSFET, the second region 206 can be a P+ doped region, and its doping concentration is greater than the doping concentration of the well region 203. The second region 206 can form a good ohmic contact with the source 400.

[0087] Figure 2FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0088] S101. Provide a semiconductor body, which includes a first surface and a second surface; the semiconductor body also includes a well region and a first region, the first region is set to a first conductive type and is located on the first surface, and the well region is set to a second conductive type and is located on the first surface; the well region and the first region are in contact with each other; the semiconductor body also includes a first insulating layer, the first insulating layer is located on the first surface and covers the well region and part of the first region; a second insulating pad is located on a side of the well region and the first region away from the first surface; a second gate is located on a side of the second insulating pad away from the well region and the first region, the second gate includes a two-dimensional electron gas layer or a two-dimensional hole gas layer; the first insulating pad is located on a side of the second gate away from the second insulating pad.

[0089] refer to Figure 3 , providing a semiconductor body 600, the semiconductor body 600 includes a first surface 601 and a second surface 602 arranged opposite to each other; the semiconductor body 600 also includes a well region 203 and a first region 204, the first region 204 is set to a first conductivity type and is located on the first surface 601, and the well region 203 is set to a second conductivity type and is located on the first surface 601; the well region 203 and the first region 204 are in contact with each other; the semiconductor body 600 also includes a first insulating layer 205, the first insulating layer 205 is located on the first surface 601 and covers the well region 203 and part of the first region 204; a second insulating pad 50 is located on a side of the well region 203 and the first region 204 away from the first surface 601; a second gate 40 is located on a side of the second insulating pad 50 away from the well region 203 and the first region 204, the second gate 40 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer; the first insulating pad 30 is located on a side of the second gate 40 away from the second insulating pad 50.

[0090] In the embodiment of the present invention, Figure 3 As shown, the semiconductor body 600 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 600 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 600 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0091] Semiconductor devices include but are not limited to N-type MOSFETs or P-type MOSFETs. The semiconductor body 600 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 204 in the semiconductor body 600 is an N+ doped region, and the N-type dopant ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 203 is a P-well region, and the P-type dopant ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0092] S102 , forming a first gate on a side of the first insulating layer away from the semiconductor body; the first insulating layer is used to insulate the semiconductor body and the first gate.

[0093] refer to Figure 1 A first gate 300 is formed on a side of the first insulating layer 205 away from the semiconductor body 600 ; the first insulating layer 205 is used to insulate the semiconductor body 600 and the first gate 300 .

[0094] The first gate 300 may be polysilicon. The first insulating layer 205 is used to insulate the semiconductor body 600 from the first gate 300. The first insulating layer 205 may be a gate oxide layer.

[0095] S103 , forming a source electrode on the first surface.

[0096] refer to Figure 1 , metal is deposited on the first surface 601 to form the source 400. The deposited metal can be titanium (Ti), nickel (Ni) or silver (Ag). Before forming the source 400, an interlayer dielectric layer 301 is formed on the side of the first gate 300 away from the semiconductor body 600. The interlayer dielectric layer 301 forms an electrical isolation between the first gate 300 and the source 400 to prevent electron migration between different metal layers and avoid diffusion or penetration between substances. The material of the interlayer dielectric layer 301 can be silicon dioxide. The interlayer dielectric layer 301 can be formed by plasma enhanced chemical vapor deposition.

[0097] S104 , forming a drain on the second surface.

[0098] refer to Figure 1 , metal is deposited on the second surface 602 to form the drain 500. The deposited metal includes but is not limited to titanium (Ti), nickel (Ni) or silver (Ag).

[0099] The technical solution of the embodiment of the present invention forms a second gate 40 on the side of the well region 203 away from the first surface 601, and forms a first gate 300 on the side of the well region 203 close to the first surface 601. This increases the number of gates and the length of the channel, improves the gate control capability, reduces the on-resistance of the device, and improves the transconductance, thereby improving the reliability of the device. Furthermore, depending on the conductivity type of the MOSFET device, a second gate 40 is formed that includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Because the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and high conductivity and carrier concentration, the on-resistance of the device is further reduced and the transconductance is improved without increasing the thickness of the device. Furthermore, the formation of a first insulating pad layer 30 as a transition layer not only facilitates lattice matching but also insulates the second gate 40 from the semiconductor body 600.

[0100] Figure 2 In the method for manufacturing a semiconductor device, a Figure 1 In the semiconductor device shown, a trench can be formed in the semiconductor body 600, and the second gate 40 can be formed in the trench; or a first sub-semiconductor body can be formed first, and the second gate 40 and the second sub-semiconductor body can be formed on one side of the first sub-semiconductor body by epitaxy, which is not specifically limited here. The following specifically describes the manufacturing method of the semiconductor device of the embodiment of the present application using the buried layer epitaxy technology:

[0101] Figure 4 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the method for manufacturing the semiconductor device includes:

[0102] S110 , providing a first semiconductor sub-body, wherein the first semiconductor sub-body includes a fifth surface and a sixth surface that are oppositely disposed.

[0103] refer to Figure 5 , providing a first sub-semiconductor body 100, the first sub-semiconductor body 100 includes a fifth surface 101 and a sixth surface 102 arranged opposite to each other. The first sub-semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the first sub-semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the first sub-semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0104] S120 , forming a first insulating pad layer on the fifth surface of the first sub-semiconductor body.

[0105] refer to Figure 6 A first insulating pad layer 30 is formed on the fifth surface 101 of the first sub-semiconductor body 100. The first insulating pad layer 30 serves as a transition layer and facilitates lattice matching.

[0106] S130 , forming a second gate on a side of the first insulating pad away from the fifth surface; the second gate includes a two-dimensional electron gas layer or a two-dimensional hole gas layer.

[0107] refer to Figure 6 A second gate 40 is formed on a side of the first insulating pad layer 30 away from the fifth surface 101 ; the second gate 40 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer.

[0108] Forming a second gate 40 comprising a two-dimensional electron gas layer or a two-dimensional hole gas layer can improve the electron mobility of the semiconductor device. Forming the second gate 40 increases the number of gates and the length of the channel, improving gate control capabilities, reducing the on-resistance of the semiconductor device, and increasing transconductance, thereby improving the reliability of the resulting semiconductor device. If the first conductivity type is N-type, the second gate 40 includes a two-dimensional electron gas layer; if the first conductivity type is P-type, the second gate 40 includes a two-dimensional hole gas layer.

[0109] Optional, reference Figure 7 After forming the first insulating pad layer 30 and the second gate 40 , the second gate 40 is etched.

[0110] S140 , forming a second insulating pad layer on a side of the second gate away from the first sub-semiconductor body.

[0111] refer to Figure 8 A second insulating pad layer 50 is formed on a side of the second gate 40 away from the first sub-semiconductor body 100. The second insulating pad layer 50 serves as a transition layer, which is beneficial to lattice matching.

[0112] S150. Provide a second sub-semiconductor body, the second sub-semiconductor body including a third surface and a fourth surface arranged opposite to each other; the fourth surface and the fifth surface are in contact; the second sub-semiconductor body is located on the side of the fifth surface of the first sub-semiconductor body away from the sixth surface; the second sub-semiconductor body also includes a well region and a first area, the first area is set to the first conductivity type and is located on the third surface, and the well region is set to the second conductivity type and is located on the third surface; the well region and the first area are in contact with each other; the second sub-semiconductor body also includes a first insulating layer, the first insulating layer is located on the third surface and covers the well region and part of the first area.

[0113] refer to Figure 8A second semiconductor sub-body 200 is provided. The second semiconductor sub-body 200 includes a third surface 201 and a fourth surface 202 disposed opposite each other. The fourth surface 202 is in contact with the fifth surface 101. The second semiconductor sub-body 200 is located on a side of the fifth surface 101 of the first semiconductor sub-body 100 that is away from the sixth surface 102. The second semiconductor sub-body 200 can be formed by an epitaxial process.

[0114] refer to Figure 9 The second sub-semiconductor body 200 also includes a well region 203 and a first region 204, the first region 204 is set to the first conductivity type and is located on the third surface 201, and the well region 203 is set to the second conductivity type and is located on the third surface 201; the well region 203 and the first region 204 are in contact with each other; the second sub-semiconductor body 200 also includes a first insulating layer 205, the first insulating layer 205 is located on the third surface 201 and covers the well region 203 and part of the first region 204.

[0115] In an embodiment of the present invention, the first sub-semiconductor body 100 and the second sub-semiconductor body 200 may comprise a third-generation wide bandgap semiconductor material, such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. For an N-type MOSFET, the well region 203 and the first region 204 may be formed by ion implantation. The first region 204 is an N+ doped region; the well region 203 is a P- well region. Optionally, the second sub-semiconductor body 200 also includes a second region 206, which may be formed by ion implantation. The well region 203, the first region 204, and the second region 206 are formed by ion implantation and high-temperature annealing. Subsequently, sacrificial oxidation and oxide layer removal are performed. A first insulating layer 205 is then formed on one side of the third surface 201, covering the well region 203 and a portion of the first region 204, by gate oxide deposition or thermal oxidation.

[0116] The first insulating pad layer 30 serves as a transition layer, not only facilitating lattice matching, but also insulating the second gate 40 from the first sub-semiconductor body 100. When forming the second sub-semiconductor body 200, the second insulating pad layer 50 serves as a transition layer, not only facilitating lattice matching, but also insulating the second gate 40 from the second sub-semiconductor body 200.

[0117] S160 , forming a first gate on a side of the first insulating layer away from the second sub-semiconductor body; the first insulating layer is used to insulate the second sub-semiconductor body from the first gate.

[0118] refer to Figure 10A first gate 300 is formed on a side of the first insulating layer 205 away from the second semiconductor sub-body 200. The first insulating layer 205 is used to insulate the second semiconductor sub-body 200 from the first gate 300. The first gate 300 may be formed by depositing polysilicon.

[0119] S170 , forming a source on the third surface.

[0120] refer to Figure 11 Metal is deposited on the third surface 201 to form the source electrode 400. Before forming the source electrode 400, an interlayer dielectric layer 301 is formed on a side of the first gate 300 away from the second sub-semiconductor body 200. The interlayer dielectric layer 301 electrically isolates the first gate 300 from the source electrode 400, preventing electron migration between different metal layers and diffusion or penetration between substances. The interlayer dielectric layer 301 can be made of silicon dioxide. The interlayer dielectric layer 301 can be formed by plasma-enhanced chemical vapor deposition.

[0121] S180, forming a drain on the sixth surface.

[0122] refer to Figure 1 , metal is deposited on the sixth surface 102 to form a drain 500. The deposited metal can be titanium (Ti), nickel (Ni) or silver (Ag).

[0123] The technical solution of the embodiment of the present invention forms a second gate 40 on the side of the well region 203 close to the fifth surface 101, and forms a first gate 300 on the side of the well region 203 close to the third surface 201. This increases the number of gates and the length of the channel, improves the gate control capability, reduces the on-resistance of the device, and improves the transconductance, thereby improving the reliability of the device. Furthermore, depending on the conductivity type of the MOSFET device, the second gate 40 is formed to include a two-dimensional electron gas layer or a two-dimensional hole gas layer. Because the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and high conductivity and carrier concentration, the on-resistance of the device is further reduced and the transconductance is improved without increasing the thickness of the device. Furthermore, the first insulating pad layer 30 is formed as a transition layer, which not only facilitates lattice matching but also insulates the second gate 40 from the first sub-semiconductor body 100. When forming the second sub-semiconductor body 200, the second insulating pad layer 50 serves as a transition layer, which not only facilitates lattice matching but also insulates the second gate 40 from the second sub-semiconductor body 200.

[0124] Figure 12 According to an embodiment of the present invention, Figure 4 The flow chart of S130 is shown in FIG. Figure 12 As shown, in an optional embodiment of the present invention, S130, forming a second gate on a side of the first insulating pad away from the fifth surface, includes:

[0125] S1301 , forming a first gallium nitride layer on a side of the first insulating pad away from the fifth surface.

[0126] refer to Figure 6 and Figure 8 A first gallium nitride layer 401 is formed on a side of the first insulating spacer layer 30 away from the fifth surface 101. Exemplarily, the first semiconductor sub-body 100 is made of silicon carbide. The first insulating spacer layer 30 is formed on the first semiconductor sub-body 100. The first insulating spacer layer 30 serves as a lattice buffer layer, facilitating epitaxial formation of the first gallium nitride layer 401 on the first semiconductor sub-body 100.

[0127] S1302. Form a second gallium nitride layer on a side of the first gallium nitride layer away from the first insulating pad layer; the second gallium nitride layer is a gallium nitride material doped with the second conductivity type, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0128] refer to Figure 6 and Figure 8 A second gallium nitride layer 402 is formed on the side of the first gallium nitride layer 401 away from the first insulating pad 30; the second gallium nitride layer 402 is a gallium nitride material doped with the second conductivity type. For example, for an N-type MOSFET, the second conductivity type is P-type. When the silicon carbide epitaxial layer is at a positive voltage, the structure formed by the first gallium nitride layer 401 and the second gallium nitride layer 402 can conduct the two-dimensional electron gas formed. At this time, when a positive voltage is applied to the gallium nitride layer, an inversion layer is formed in the well region 203 close to the gallium nitride. When a negative voltage is applied to the silicon carbide epitaxial layer or the potential is 0, the second gallium nitride layer 402 is a P-type gallium nitride layer, forming a space charge region with the N-type silicon carbide epitaxial layer, preventing leakage current from the source to the drain, improving transconductance, and reducing the on-resistance of the semiconductor device.

[0129] Figure 13 According to an embodiment of the present invention, Figure 4 The flow chart of S150 is shown in FIG. Figure 13 As shown, in an optional embodiment of the present invention, S150, providing a second sub-semiconductor body includes:

[0130] S1501. Provide a second sub-semiconductor body, where the second sub-semiconductor body includes a third surface and a fourth surface that are opposite to each other.

[0131] refer to Figure 8 A second semiconductor sub-body 200 is provided. The second semiconductor sub-body 200 includes a third surface 201 and a fourth surface 202 that are opposite to each other. The second semiconductor sub-body 200 can be formed by an epitaxial process based on the first semiconductor sub-body 100.

[0132] S1502, forming a well region and a first region on the third surface; the first region is set to the first conductivity type and is located on the third surface; the well region is set to the second conductivity type and is located on the third surface.

[0133] In an optional embodiment of the present invention, after forming the well region and the first region on the third surface, the method further includes: forming a second region on the third surface, wherein the second region is set to be of the second conductivity type and contacts the first region.

[0134] refer to Figure 9 , semiconductor devices include but are not limited to N-type MOSFET or P-type MOSFET. The first sub-semiconductor body 100 and the second sub-semiconductor body 200 may include third-generation wide bandgap semiconductor materials such as silicon carbide semiconductor body. For N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for N-type MOSFET, a first region 204 is formed in the second sub-semiconductor body 200 by ion implantation, and the first region 204 is an N+ doped region, and the N-type doping ions of the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions. A well region 203 is formed in the second sub-semiconductor body 200 by ion implantation, and the well region 203 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The conductivity type of the second region 206 is the same as that of the well region 203, and both are set to the second conductivity type. For an N-type MOSFET, the second region 206 is formed in the second sub-semiconductor body 200 by ion implantation. The second region 206 can be a P+ doped region with a doping concentration greater than that of the well region 203. The formation of the second region 206 can form a good ohmic contact with the source 400.

[0135] S1503, forming a first insulating layer on the third surface; the first insulating layer covers the well region and a portion of the first region.

[0136] refer to Figure 9 A first insulating layer 205 is formed on the third surface 201 by gate oxide deposition or thermal oxidation. The first insulating layer 205 covers the well region 203 and a portion of the first region 204. The first insulating layer 205 is used to insulate the second semiconductor sub-body 200 from the first gate 300.

[0137] In an optional embodiment of the present invention, reference Figure 1 Before forming the drain 500 on the second surface 602 , the method further includes: performing a thinning process on the second surface 602 .

[0138] Specifically, before forming the drain 500 on the second surface 602 , thinning the second surface 602 can reduce the on-resistance of the semiconductor device and improve the quality of the formed drain 500 .

[0139] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0140] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0141] Therefore, the power conversion circuit includes the beneficial effects of the semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0142] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0143] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0144] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0145] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: The semiconductor body comprises a first surface and a second surface opposite to each other; The semiconductor body further includes a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on the first surface; the well region and the first region being in contact with each other; and the semiconductor body further includes a first insulating layer being located on the first surface and covering the well region and a portion of the first region. a first gate, located on a side of the first insulating layer away from the semiconductor body; The first insulating layer is used to insulate the semiconductor body and the first gate; a second insulating pad layer, located on a side of the well region and the first region away from the first surface; a second gate located on a side of the second insulating pad away from the well region and the first region, the second gate comprising a two-dimensional electron gas layer or a two-dimensional hole gas layer; a first insulating pad layer, located on a side of the second gate away from the second insulating pad layer; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The semiconductor body includes a first sub-semiconductor body and a second sub-semiconductor body, the first sub-semiconductor body includes a fifth surface and a sixth surface arranged opposite to each other; the second sub-semiconductor body includes a third surface and a fourth surface arranged opposite to each other; the fourth surface and the fifth surface are in contact with each other; the third surface is the first surface of the semiconductor body; the sixth surface is the second surface of the semiconductor body; the second sub-semiconductor body is located on a side of the fifth surface of the first sub-semiconductor body away from the sixth surface; the second sub-semiconductor body also includes the well region and the first region, the first region is set to the first conductivity type and is located on the third surface, and the well region is set to the second conductivity type and is located on the third surface; the well region and the first region are in contact with each other; the second sub-semiconductor body also includes the first insulating layer, the first insulating layer is located on the third surface and covers the well region and a portion of the first region; The first gate is located on a side of the first insulating layer away from the second sub-semiconductor body; the first insulating layer is used to insulate the second sub-semiconductor body from the first gate; The first insulating pad layer is located on the fifth surface of the first sub-semiconductor body; The second gate is located on a side of the first insulating pad away from the fifth surface, the second gate includes a two-dimensional electron gas layer or a two-dimensional hole gas layer, and is located on a side of the well region and the first region away from the third surface; The second insulating pad is located on a side of the second gate away from the first sub-semiconductor body; The source electrode is located on the third surface; The drain is located on the sixth surface.

3. The semiconductor device according to claim 2, wherein The second gate includes a first gallium nitride layer and a second gallium nitride layer; the first gallium nitride layer is located on a side of the first insulating pad layer away from the fifth surface; the second gallium nitride layer is located on a side of the first gallium nitride layer away from the first insulating pad layer, and the second gallium nitride layer is a gallium nitride material doped with the second conductivity type; The second insulating pad is located on a side of the second gallium nitride layer away from the first gallium nitride layer; The first conductivity type is N-type, and a two-dimensional electron gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer; the first conductivity type is P-type, and a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

4. The semiconductor device according to claim 1, wherein The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

5. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region; the second region is configured as a second conductivity type and is located on the first surface; the second region is in contact with the first region.

6. The semiconductor device according to claim 3, wherein The second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

7. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on the first surface; the well region and the first region being in contact with each other; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on the first surface and covering the well region and a portion of the first region; a second insulating pad layer, located on a side of the well region and the first region away from the first surface; a second gate, located on a side of the second insulating pad layer away from the well region and the first region, the second gate including a two-dimensional electron gas layer or a two-dimensional hole gas layer; and a first insulating pad layer, located on a side of the second gate away from the second insulating pad layer; A first gate is formed on a side of the first insulating layer away from the semiconductor body; the first insulating layer is used to insulate the semiconductor body and the first gate; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The semiconductor body provided includes: Providing a first semiconductor sub-body, wherein the first semiconductor sub-body includes a fifth surface and a sixth surface disposed opposite to each other; forming a first insulating pad layer on the fifth surface of the first sub-semiconductor body; A second gate is formed on a side of the first insulating pad away from the fifth surface; the second gate includes a two-dimensional electron gas layer or a two-dimensional hole gas layer; forming a second insulating pad layer on a side of the second gate away from the first sub-semiconductor body; A second sub-semiconductor body is provided, wherein the second sub-semiconductor body includes a third surface and a fourth surface arranged opposite to each other; the fourth surface is in contact with the fifth surface; the second sub-semiconductor body is located on a side of the fifth surface of the first sub-semiconductor body away from the sixth surface; the second sub-semiconductor body also includes a well region and a first region, the first region is set to a first conductivity type and is located on the third surface, and the well region is set to a second conductivity type and is located on the third surface; the well region and the first region are in contact with each other; the second sub-semiconductor body also includes a first insulating layer, the first insulating layer is located on the third surface and covers the well region and a portion of the first region.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: forming a second gate on a side of the first insulating pad layer away from the fifth surface, comprising: forming a first gallium nitride layer on a side of the first insulating pad away from the fifth surface; A second gallium nitride layer is formed on a side of the first gallium nitride layer away from the first insulating pad layer; the second gallium nitride layer is a gallium nitride material doped with a second conductivity type, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: Providing the second semiconductor sub-body includes: providing a second semiconductor sub-body, wherein the second semiconductor sub-body includes a third surface and a fourth surface disposed opposite to each other; A well region and a first region are formed on the third surface; the first region is set to a first conductivity type and is located on the third surface; the well region is set to a second conductivity type and is located on the third surface; A first insulating layer is formed on the third surface; the first insulating layer covers the well region and a portion of the first region.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: After forming the well region and the first region on the third surface, the method further comprises: A second region is formed on the third surface. The second region is configured to be of a second conductive type and is in contact with the first region.

12. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 6, wherein the substrate is used to support the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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