Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body; the semiconductor body further comprises a well region and a first region; the two-dimensional conductive layer comprises a first conductive part and a second conductive part; the first conductive part is located on the first surface and covers one side of the well region away from the second surface; the second conductive part is connected with the first conductive part, is positioned on one side, far away from the first region, of the well region and is positioned between the drift region and the first surface; the grid is located on one side of the insulating layer away from the semiconductor body; the source electrode is located on the first surface; the drain electrode is located on the second surface. According to the technical scheme, the on-resistance of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a third-generation wide-bandgap semiconductor such as silicon carbide or gallium nitride, has the characteristics of large critical breakdown electric field strength, high thermal conductivity, large bandgap width, and high electron saturation drift velocity, and is increasingly used in the field of power devices.

[0003] For a planar metal-oxide-semiconductor field-effect transistor (MOSFET), the semiconductor body on one side of the well region is the junction field-effect transistor (JFET) region. The device's on-resistance includes the JFET resistance, resulting in a relatively high on-resistance. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the on-resistance of the semiconductor device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0006] A semiconductor body comprising a first surface and a second surface opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and at least partially located on the first surface;

[0007] a two-dimensional conductive layer comprising a first conductive portion and a second conductive portion; the first conductive portion being located on the first surface and covering a side of the well region away from the second surface; and the second conductive portion being connected to the first conductive portion, being located on a side of the well region away from the first region and between the drift region and the first surface;

[0008] an insulating layer, located on the first surface;

[0009] a gate, located on a side of the insulating layer away from the semiconductor body, the insulating layer being used to insulate the semiconductor body from the gate;

[0010] a source electrode, located on the first surface;

[0011] The drain is located on the second surface.

[0012] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and at least partially located on the first surface; forming a two-dimensional conductive layer within the semiconductor body, the two-dimensional conductive layer comprising a first conductive portion and a second conductive portion; the first conductive portion being located on the first surface and covering a side of the well region remote from the second surface; the second conductive portion being connected to the first conductive portion, being located on a side of the well region remote from the first region, and being located between a drift region and the first surface;

[0013] forming an insulating layer on the first surface;

[0014] forming a gate on a side of the insulating layer away from the semiconductor body, wherein the insulating layer is used to insulate the semiconductor body from the gate;

[0015] forming a source electrode on the first surface;

[0016] A drain is formed on the second surface. According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described above, wherein the substrate is used to support the semiconductor device.

[0017] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0018] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0019] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0020] The semiconductor device and manufacturing method, power module, power conversion circuit and vehicle provided by the embodiments of the present invention, when the device is turned on, the current passes through the source, the first region, the first conductive portion in the two-dimensional conductive layer, the second conductive portion in the two-dimensional conductive layer, and then passes through the drift region to reach the drain. According to the conductivity type of the MOSFET semiconductor device, the two-dimensional conductive layer includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Since the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and has a high conductivity and carrier mobility, the mobility of the carriers flowing through the two-dimensional conductive layer is greatly improved, and the on-resistance of the device is reduced without increasing the thickness of the device. Among them, the provision of the second conductive portion in the two-dimensional conductive layer replaces the JFET region as the current channel, and there is no need to provide a JFET region of sufficient lateral size on one side of the well region in the planar MOSFET device so that the JFET region has a resistance that matches the on-current, thereby reducing the lateral size of the semiconductor body on the well region side, thereby reducing the lateral size of the semiconductor device.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;

[0024] Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0025] Figure 3 This is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0026] Figure 4-Figure 6 It is a structural schematic diagram corresponding to each relevant step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0027] Figure 7 yes Figure 3 A schematic diagram of the process included in S110;

[0028] Figures 8-12 yes Figure 7Structural diagram corresponding to each relevant step in;

[0029] Figure 13 This is a flow chart of S1103 in step 7. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] like Figure 1 As shown, Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art. The semiconductor device is a planar MOSFET device. The semiconductor device includes that during the device conduction process, the current passes through the source 300-first region 101-well region 102-JFET region 103-drift region 104 and then reaches the drain 400. The on-resistance of the device includes the JFET resistance, which results in a relatively large on-resistance of the semiconductor device. In addition, during the formation of the first region 101 and the well region 102, due to the high temperature, high dose and high energy ion implantation, the semiconductor body will be damaged by the lattice, and the isolation oxide layer may also have defects during preparation. Therefore, semiconductor devices often have large interface states and low channel electron mobility, which makes the device unable to exert the characteristics of the third wide bandgap semiconductor such as silicon carbide material or gallium nitride material, and has a larger on-resistance than the theoretical value. Among them, Figure 1 The reference numerals in FIG. 1 are described as follows: semiconductor substrate 100 , first region 101 , well region 102 , gate 200 , source 300 , drain 400 , JFET region 103 , drift region 104 .

[0033] In order to solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0034] like Figure 2 As shown, Figure 2 : is a structural schematic diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 500, comprising a first surface 501 and a second surface 502 arranged opposite to each other; the semiconductor body 500 further comprising a well region 503 and a first region 504, the first region 504 being configured as a first conductivity type and being located on the first surface 501, the well region 503 being configured as a second conductivity type and being at least partially located on the first surface 501; a two-dimensional conductive layer 600, comprising a first conductive portion 601 and a second conductive portion 602; the first conductive portion 601 being located on the first conductive portion 601; surface 501 and covers the side of the well region 503 away from the second surface 502; the second conductive portion 602 is connected to the first conductive portion 601, is located on the side of the well region 503 away from the first region 504, and is located between the drift region 505 and the first surface 501; the insulating layer 700 is located on the first surface 501; the gate 701 is located on the side of the insulating layer 700 away from the semiconductor body 500, and the insulating layer 700 is used to insulate the semiconductor body 500 and the gate 701; the source 800 is located on the first surface 501; the drain 900 is located on the second surface 502.

[0035] For example, Figure 2 As shown, the semiconductor body 500 includes a substrate 50, an epitaxial layer 51, and an epitaxial layer 52. In some embodiments of the present invention, the semiconductor body 500 may also include only the epitaxial layer. In other embodiments of the present invention, the semiconductor body 500 may also include the substrate 50 and a semiconductor layer formed by other processes. The epitaxial layer is a semiconductor layer formed on the substrate through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0036] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 500 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 504 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 503 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0037] The insulating layer 700 may be silicon oxide, which is prepared by an oxidation process. The gate 701 may be polysilicon.

[0038] In the embodiment of the present invention, an interlayer insulating layer 702 may be further included to insulate the gate 701 and the source 800 .

[0039] The technical solution provided by the embodiment of the present invention is that when the device is turned on, the current passes through the source 800, the first region 504, the first conductive portion 601 in the two-dimensional conductive layer 600, the second conductive portion 602 in the two-dimensional conductive layer 600, and then passes through the drift region 505 to reach the drain 900. The two-dimensional conductive layer 600 has a very thin thickness and has a high conductivity and electron mobility. The mobility of carriers flowing through the two-dimensional conductive layer 600 is greatly improved, and the on-resistance of the device is reduced without increasing the thickness of the device. Among them, the second conductive portion 602 in the two-dimensional conductive layer 600 is provided to replace the JFET region as the current channel. There is no need to provide a JFET region of sufficient lateral size on one side of the well region 503 in the planar MOSFET device so that the JFET region has a resistance that matches the on-current. In addition, the lateral size of the semiconductor body on the side of the well region 503 can be reduced, thereby reducing the lateral size of the semiconductor device. It should be noted that in this embodiment, the lateral size refers to the size in the direction perpendicular to the first surface 501 and pointing to the second surface 502.

[0040] Optionally, based on the above technical solution, the first conductivity type is N-type, and the two-dimensional conductive layer 600 includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer 600 includes a two-dimensional hole gas layer.

[0041] Specifically, according to the conductivity type of the MOSFET semiconductor device, the two-dimensional conductive layer 600 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Since the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and has a very high conductivity and carrier mobility, the mobility of the carriers flowing through the two-dimensional conductive layer 600 is greatly improved, thereby reducing the on-resistance of the device without increasing the thickness of the device.

[0042] It should be noted that the two-dimensional electron gas layer is typically a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperature conditions), due to differences in material properties at its heterojunction interface, a large concentration of two-dimensional electron gas is formed, achieving excellent electron mobility, which is far greater than the electron mobility of silicon, silicon carbide, and gallium nitride, far exceeding the carrier requirements of the device and significantly improving the carrier mobility of the device. Moreover, the movement of electrons in the two-dimensional electron gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent electron mobility on the two-dimensional surface where the heterojunction interface is located. Correspondingly, the movement of holes in the two-dimensional hole gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent hole mobility on the two-dimensional surface where the heterojunction interface is located.

[0043] Alternatively, as Figure 1 As shown, the first conductive portion 601 is away from the surface of the semiconductor body 500 and is flush with the first surface 501 .

[0044] Optionally, based on the above technical solution, Figure 2 As shown, the semiconductor body 500 includes a first semiconductor body 01 and a second semiconductor body 02; the second semiconductor body 02 is located on one side of the first semiconductor body 01, the surface of the second semiconductor body 02 away from the first semiconductor body 01 is the first surface 501, and the surface of the first semiconductor body 01 away from the second semiconductor body 02 is the second surface 502; the first semiconductor body 01 is provided with a groove T1, the groove T1 is located on the third surface of the first semiconductor body 01 and extends into the first semiconductor body 01, and the third surface and the second surface 502 are arranged opposite to each other; the second conductive portion 602 is located on the sidewall of the groove T1 ; The first conductive portion 601 is located on a partial surface of the third surface, and the surface of the first conductive portion 601 away from the first semiconductor body 01 is flush with the first surface 501; the second semiconductor body 02 includes a first semiconductor portion 021 and a second semiconductor portion 022, and the first semiconductor portion 021 is filled in the groove and is flush with the first surface 501; the second semiconductor portion 022 is located on the third surface and connected to the first conductive portion 601, and the surface of the second semiconductor portion 022 away from the first semiconductor body 01 is the first surface 501; the first region 504 and the well region 503 are located in the second semiconductor body 02 and the first semiconductor body 01.

[0045] Specifically, the semiconductor body 500 includes a first semiconductor body 01 and a second semiconductor body 02. The second semiconductor body 02 is divided into two parts. The first semiconductor portion 021 fills the groove T1 and is flush with the first surface 501; the second semiconductor portion 022 is located on the third surface and connected to the first conductive portion 601. The second semiconductor body 02 and the first semiconductor body 01 are used to form the first region 504 and the well region 503. The above technical solution allows the preparation process of the two-dimensional conductive layer 600 to be completed after the first semiconductor body 01 is formed. Then, the second semiconductor body 02 is formed on one side of the first semiconductor body 01, facilitating the formation of the two-dimensional conductive layer 600 within the semiconductor body 500, thereby improving the carrier efficiency of the device and reducing the on-resistance of the device.

[0046] Optionally, based on the above technical solution, Figure 2 As shown, the two-dimensional conductive layer 600 includes a first gallium nitride layer and a second gallium nitride layer. The first gallium nitride layer is in contact with the well region 503. The second gallium nitride layer is located on a side of the first gallium nitride layer away from the well region 503. The second gallium nitride layer is a doped gallium nitride material. A two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first and second gallium nitride layers. Optionally, based on the above technical solution, the second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

[0047] The two-dimensional conductive layer 600 includes a first gallium nitride layer and a second gallium nitride layer. The first gallium nitride layer comprises an undoped gallium nitride material, and the second gallium nitride layer comprises magnesium gallium nitride or aluminum gallium nitride. The first and second gallium nitride layers are stacked to form a heterojunction semiconductor layer. Under specific conditions (such as a specific electric field and a specific temperature), due to the difference in material properties, a large concentration of two-dimensional electron gas or two-dimensional hole gas is formed at the heterojunction interface. The carrier mobility of these two-dimensional electron gas or two-dimensional hole gas is much greater than that of silicon, silicon carbide, and gallium nitride, far exceeding the carrier mobility of the device, significantly improving the device's carrier mobility and reducing the device's on-resistance. Taking an N-type MOSFET device as an example, the magnesium gallium nitride or aluminum gallium nitride second gallium nitride layer, which is P-type doped, can form a space charge region between it and the first conductivity type semiconductor body 500. When the device is in the off state, it can prevent current from flowing from the source to the drain.

[0048] Optionally, based on the above technical solution, semiconductor body 500 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device; or, semiconductor body 500 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0049] Optionally, based on the above technical solution, Figure 2 As shown, the semiconductor body 500 further includes a second region 506 , which is set to the second conductivity type and is located on the first surface 501 ; the second region 506 contacts the first region 504 , and the ion concentration of the second region 506 is greater than the ion concentration of the well region 503 .

[0050] Specifically, the conductivity type of the second region 506 is opposite to that of the first region 504. For example, using an N-type MOSFET semiconductor device as an example, if the first conductivity type is N-type, the second conductivity type is P-type, and the second region 506 includes a P+ doped region. The ion concentration of the second region 506 is greater than the ion concentration of the well region 503. The second region 506 is provided to form a better ohmic contact with the source 800.

[0051] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 3 As shown, Figure 3 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, the method for manufacturing a semiconductor device comprising the following steps:

[0052] S110. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other; the semiconductor body also including a well region and a first region, the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is at least partially located on the first surface; a two-dimensional conductive layer is formed in the semiconductor body, the two-dimensional conductive layer including a first conductive part and a second conductive part; the first conductive part is located on the first surface and covers a side of the well region away from the second surface; the second conductive part is connected to the first conductive part, is located on a side of the well region away from the first region, and is located between the drift region and the first surface.

[0053] like Figure 4As shown, a semiconductor body 500 is provided, which includes a first surface 501 and a second surface 502 arranged opposite to each other; the semiconductor body 500 also includes a well region 503 and a first region 504, the first region 504 is set to a first conductivity type and is located on the first surface 501, and the well region 503 is set to a second conductivity type and is at least partially located on the first surface 501; a two-dimensional conductive layer 600 includes a first conductive part 601 and a second conductive part 602; the first conductive part 601 is located on the first surface 501 and covers the side of the well region 503 away from the second surface 502; the second conductive part 602 is connected to the first conductive part 601, is located on the side of the well region 503 away from the first region 504, and is located between the drift region 505 and the first surface 501.

[0054] Exemplarily, the semiconductor body 500 includes a substrate 50, an epitaxial layer 51, and an epitaxial layer 52. In some embodiments of the present invention, the semiconductor body 500 may also include only the epitaxial layer. In other embodiments of the present invention, the semiconductor body 500 may also include the substrate 50 and a semiconductor layer formed by other processes. The epitaxial layer is a semiconductor layer formed on the basis of the substrate through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0055] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 500 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 504 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 503 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0056] S120 , forming an insulating layer on the first surface.

[0057] like Figure 5 As shown, the insulating layer 700 may be silicon oxide, which is prepared by a deposition process or a thermal oxidation process.

[0058] S130 , forming a gate on a side of the insulating layer away from the semiconductor body, where the insulating layer is used to insulate the semiconductor body from the gate.

[0059] like Figure 5As shown, a gate 701 is formed on a side of the insulating layer 700 away from the semiconductor body 500 through a deposition process. The insulating layer 700 is used to insulate the semiconductor body 500 and the gate 701 .

[0060] S140 , forming a source electrode on the first surface.

[0061] like Figure 6 As shown, before forming the source 800 , an interlayer insulating layer 702 is further formed. The interlayer insulating layer 702 is used to insulate the gate 701 and the source 800 .

[0062] like Figure 2 As shown, the source electrode 800 is formed by a metal conductive layer deposition process.

[0063] S150 , forming a drain on the second surface.

[0064] like Figure 2 As shown, the drain electrode 900 is formed by a metal conductive layer deposition process. Optionally, before forming the drain electrode 900, the substrate 50 may be thinned to reduce the on-resistance of the device.

[0065] The technical solution provided by the embodiment of the present invention is that when the device is turned on, the current passes through the source 800, the first region 504, the first conductive portion 601 in the two-dimensional conductive layer 600, the second conductive portion 602 in the two-dimensional conductive layer 600, and then passes through the drift region 505 to reach the drain 900. The two-dimensional conductive layer 600 has a very thin thickness and has a high conductivity and electron mobility. The mobility of carriers flowing through the two-dimensional conductive layer 600 is greatly improved, and the on-resistance of the device is reduced without increasing the thickness of the device. Among them, the second conductive portion 602 in the two-dimensional conductive layer 600 is provided to replace the JFET region as the current channel. There is no need to provide a JFET region of sufficient lateral size on one side of the well region 503 in the planar MOSFET device so that the JFET region has a resistance that matches the on-current. In addition, the lateral size of the semiconductor body on the side of the well region 503 can be reduced, thereby reducing the lateral size of the semiconductor device. It should be noted that in this embodiment, the lateral size refers to the size in the direction perpendicular to the first surface 501 and pointing to the second surface 502.

[0066] Optionally, based on the above technical solution, the first conductivity type is N-type, and the two-dimensional conductive layer 600 includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

[0067] Specifically, according to the conductivity type of the MOSFET semiconductor device, the two-dimensional conductive layer 600 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Since the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and has a very high conductivity and carrier mobility, the mobility of the carriers flowing through the two-dimensional conductive layer 600 is greatly improved, thereby reducing the on-resistance of the device without increasing the thickness of the device.

[0068] It should be noted that the two-dimensional electron gas layer is typically a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperature conditions), due to differences in material properties at its heterojunction interface, a large concentration of two-dimensional electron gas is formed, achieving excellent electron mobility, which is far greater than the electron mobility of silicon, silicon carbide, and gallium nitride, far exceeding the carrier requirements of the device and significantly improving the carrier mobility of the device. Moreover, the movement of electrons in the two-dimensional electron gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent electron mobility on the two-dimensional surface where the heterojunction interface is located. Correspondingly, the movement of holes in the two-dimensional hole gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent hole mobility on the two-dimensional surface where the heterojunction interface is located.

[0069] Optionally, the first conductive portion 601 is away from a surface of the semiconductor body 500 and flush with the first surface 501 .

[0070] Optionally, based on the above technical solution, Figure 7 As shown, Figure 7 yes Figure 3 The process diagram of S110 includes: S110 provides a semiconductor body including:

[0071] S1101. Provide a first semiconductor body.

[0072] like Figure 8 As shown, a substrate 50 is prepared, and an epitaxial layer 51 is formed on one side of the substrate 50 by an epitaxial process.

[0073] S1102 , forming a groove in the first semiconductor body, where the groove is located on the third surface of the first semiconductor body and extends into the first semiconductor body, and the third surface and the second surface are arranged opposite to each other.

[0074] like Figure 9 As shown, a groove T1 is formed in the first semiconductor body 01 by a trench etching process. The groove T1 is located on the third surface of the first semiconductor body 01 and extends into the first semiconductor body 01 . The third surface and the second surface 502 are arranged opposite to each other.

[0075] S1103. Form a two-dimensional conductive layer on the sidewall of the groove and a portion of the third surface, the two-dimensional conductive layer including a first conductive portion and a second conductive portion; the second conductive portion is located on the sidewall of the groove; the first conductive portion is located on a portion of the third surface, and the first conductive portion is away from the surface of the first semiconductor body and is flush with the first surface.

[0076] Alternatively, as Figure 13 As shown, Figure 13 7 is a schematic diagram of the process included in S1103, where S1103 forms a two-dimensional conductive layer on the sidewall of the groove and a portion of the third surface, including:

[0077] S11031 , forming a first gallium nitride layer on the sidewalls of the groove and a portion of the third surface.

[0078] like Figure 10 As shown, a first gallium nitride layer is formed on the sidewalls, bottom surface and third surface of the groove T1. The first gallium nitride layer includes undoped gallium nitride material.

[0079] S11032. Form a second gallium nitride layer on a side of the first gallium nitride layer away from the first semiconductor body; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0080] like Figure 10 As shown, a second gallium nitride layer is formed on a side of the first gallium nitride layer away from the first semiconductor body 01. The second gallium nitride layer is a doped gallium nitride material. Two-dimensional electron gas or two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0081] like Figure 11 As shown, the two-dimensional conductive layer 600 located at the bottom surface of the groove T1 and a portion of the two-dimensional conductive layer 600 located on the third surface are removed through an etching process.

[0082] Optionally, based on the above technical solution, the second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

[0083] The two-dimensional conductive layer 600 includes a first gallium nitride layer and a second gallium nitride layer. The first gallium nitride layer comprises an undoped gallium nitride material, and the second gallium nitride layer comprises magnesium gallium nitride or aluminum gallium nitride. The first and second gallium nitride layers are stacked to form a heterojunction semiconductor layer. Under specific conditions (such as a specific electric field and a specific temperature), due to the difference in material properties, a large concentration of two-dimensional electron gas or two-dimensional hole gas is formed at the heterojunction interface. The carrier mobility of these two-dimensional electron gas or two-dimensional hole gas is much greater than that of silicon, silicon carbide, and gallium nitride, far exceeding the carrier mobility of the device, significantly improving the device's carrier mobility and reducing the device's on-resistance. Taking an N-type MOSFET device as an example, the magnesium gallium nitride or aluminum gallium nitride second gallium nitride layer, which is P-type doped, can form a space charge region between it and the first conductivity type semiconductor body 500. When the device is in the off state, it can prevent current from flowing from the source to the drain.

[0084] S1104. A second semiconductor body is formed on one side of the first semiconductor body, wherein the surface of the second semiconductor body away from the first semiconductor body is the first surface, and the surface of the first semiconductor body away from the second semiconductor body is the second surface; the second semiconductor body includes a first semiconductor portion and a second semiconductor portion, the first semiconductor portion is filled in the groove and is flush with the first surface; the second semiconductor portion is located on the third surface and connected to the first conductive portion, and the surface of the second semiconductor portion away from the first semiconductor body is the first surface.

[0085] like Figure 12 As shown, through the secondary epitaxial process, an epitaxial layer 52 is formed on one side of the first semiconductor body 01, and the epitaxial layer 52 is the second semiconductor body 02. The surface of the second semiconductor body 02 away from the first semiconductor body 01 is the first surface 501, and the surface of the first semiconductor body 01 away from the second semiconductor body 02 is the second surface 502; the second semiconductor body 02 includes a first semiconductor portion 021 and a second semiconductor portion 022, the first semiconductor portion 021 is filled in the groove T1, and is flush with the first surface 501; the second semiconductor portion 022 is located on the third surface and connected to the first conductive portion 601, and the surface of the second semiconductor portion 022 away from the first semiconductor body 01 is the first surface 501.

[0086] S1105 , forming a first region and a well region in the second semiconductor body and the first semiconductor body.

[0087] Optionally, before the second semiconductor body and the first semiconductor body form the first region and the well region, S1105 further includes: performing a planarization process on the first surface.

[0088] like Figure 12As shown, the first surface 501 is planarized by a chemical mechanical polishing (CMP) process to form a flat surface, which has the effect of reducing surface defects, thereby improving the first region and the well region.

[0089] like Figure 4 As shown, a first region 504 and a well region 503 are formed in the second semiconductor body 02 and the first semiconductor body 01 through an ion doping process and a high temperature annealing process.

[0090] Specifically, the semiconductor body 500 includes a first semiconductor body 01 and a second semiconductor body 02. The second semiconductor body 02 is divided into two parts. The first semiconductor portion 021 is filled in the groove T1 and is flush with the first surface 501; the second semiconductor portion 022 is located on the third surface and connected to the first conductive portion 601. The second semiconductor body 02 and the first semiconductor body 01 are used to form the first region 504 and the well region 503. The above technical solution allows the preparation process of the two-dimensional conductive layer 600 to be completed after the first semiconductor body 01 is formed. Then, the second semiconductor body 02 is formed on one side of the first semiconductor body 01, facilitating the formation of the two-dimensional conductive layer 600 within the semiconductor body 500, thereby improving the carrier efficiency of the device and reducing the on-resistance of the device. Before the second semiconductor body 02 and the first semiconductor body 01 form the first region 504 and the well region 503, the first surface 501 is also flattened to improve the formation quality of the first region 504 and the well region 503.

[0091] Optionally, S110 providing the semiconductor body further includes:

[0092] A semiconductor body is provided which includes a silicon carbide semiconductor body or a silicon nitride semiconductor body.

[0093] Specifically, semiconductor body 500 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device; alternatively, semiconductor body 500 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0094] Optionally, based on the above technical solution, S110 providing the semiconductor body further includes:

[0095] A semiconductor body including a second region is provided; the second region is set to a second conductivity type and is located on the first surface; the second region contacts the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0096] like Figure 4As shown, while forming the first region 504 and the well region 503, the second region 506 is prepared. The conductivity type of the second region 506 is opposite to that of the first region 504. For example, taking an N-type MOSFET semiconductor device as an example, the first conductivity type is N-type, and the second conductivity type is P-type. The second region 506 includes a P+ doped region. The ion concentration of the second region 506 is greater than the ion concentration of the well region 503. The second region 506 is provided to form a better ohmic contact with the source 800.

[0097] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device provided by any of the embodiments of the present invention, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of the power module including any of the semiconductor devices provided by the embodiments of the present invention are not further described here.

[0098] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device provided by any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0099] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device provided by the embodiments of the present invention will not be repeated here.

[0100] An embodiment of the present invention further provides a vehicle, including a load and a power conversion circuit as provided in any embodiment of the present invention. The power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. Therefore, the beneficial effects of including any power conversion circuit provided in any embodiment of the present invention in the vehicle are not further elaborated here.

[0101] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0102] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and at least partially located on the first surface; a two-dimensional conductive layer comprising a first conductive portion and a second conductive portion; the first conductive portion being located on the first surface and covering a side of the well region away from the second surface; and the second conductive portion being connected to the first conductive portion, being located on a side of the well region away from the first region and between the drift region and the first surface; an insulating layer, located on the first surface; a gate, located on a side of the insulating layer away from the semiconductor body, the insulating layer being used to insulate the semiconductor body from the gate; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

3. The semiconductor device according to claim 1, wherein A surface of the first conductive portion away from the semiconductor body is flush with the first surface.

4. The semiconductor device according to claim 1, wherein The semiconductor body includes a first semiconductor body and a second semiconductor body; The second semiconductor body is located on one side of the first semiconductor body, a surface of the second semiconductor body away from the first semiconductor body is the first surface, and a surface of the first semiconductor body away from the second semiconductor body is the second surface; The first semiconductor body is provided with a groove, the groove is located on the third surface of the first semiconductor body and extends into the first semiconductor body, and the third surface and the second surface are arranged opposite to each other; The second conductive portion is located on a sidewall of the groove; The first conductive portion is located on a portion of the third surface, and the surface of the first conductive portion is away from the first semiconductor body and is flush with the first surface; The second semiconductor body includes a first semiconductor portion and a second semiconductor portion, the first semiconductor portion is filled in the groove and is flush with the first surface; the second semiconductor portion is located on the third surface and connected to the first conductive portion, and the surface of the second semiconductor portion away from the first semiconductor body is the first surface; The first region and the well region are located in the second semiconductor body and the first semiconductor body.

5. The semiconductor device according to claim 1, wherein The two-dimensional conductive layer includes a first gallium nitride layer and a second gallium nitride layer; The first gallium nitride layer is in contact with the well region; The second gallium nitride layer is located on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

6. The semiconductor device according to claim 1 or 5, characterized in that The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride body.

7. The semiconductor device according to claim 5, wherein The second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

8. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region, which is set to a second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

9. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and at least partially located on the first surface; a two-dimensional conductive layer being formed within the semiconductor body, the two-dimensional conductive layer comprising a first conductive portion and a second conductive portion; the first conductive portion being located on the first surface and covering a side of the well region remote from the second surface; and the second conductive portion being connected to the first conductive portion, being located on a side of the well region remote from the first region, and being located between a drift region and the first surface. forming an insulating layer on the first surface; forming a gate on a side of the insulating layer away from the semiconductor body, wherein the insulating layer is used to insulate the semiconductor body from the gate; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: A surface of the first conductive portion away from the semiconductor body is flush with the first surface.

12. The method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor body provided includes: providing a first semiconductor body; forming a groove in the first semiconductor body, the groove being located on a third surface of the first semiconductor body and extending into the first semiconductor body, the third surface being arranged opposite to the second surface; forming a two-dimensional conductive layer on the sidewall of the groove and a portion of the third surface, the two-dimensional conductive layer comprising a first conductive portion and a second conductive portion; the second conductive portion is located on the sidewall of the groove; the first conductive portion is located on a portion of the third surface, and the surface of the first conductive portion away from the first semiconductor body is flush with the first surface; A second semiconductor body is formed on one side of the first semiconductor body, wherein a surface of the second semiconductor body away from the first semiconductor body is the first surface, and a surface of the first semiconductor body away from the second semiconductor body is the second surface; the second semiconductor body includes a first semiconductor portion and a second semiconductor portion, the first semiconductor portion is filled in the groove and is flush with the first surface; the second semiconductor portion is located on the third surface and connected to the first conductive portion, and a surface of the second semiconductor portion away from the first semiconductor body is the first surface; A first region and a well region are formed in the second semiconductor body and the first semiconductor body.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: Before the second semiconductor body and the first semiconductor body form the first region and the well region, the method further includes: The first surface is planarized.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: Forming a two-dimensional conductive layer on the sidewall of the groove and a portion of the third surface includes: forming a first gallium nitride layer on the sidewall of the groove and a portion of the third surface; A second gallium nitride layer is formed on a side of the first gallium nitride layer away from the first semiconductor body; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

15. The method for manufacturing a semiconductor device according to claim 9 or 14, wherein: Providing a semiconductor body also includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a silicon nitride semiconductor body.

16. The method for manufacturing a semiconductor device according to claim 9, wherein: Providing a semiconductor body also includes: A semiconductor body is provided, comprising a second region; the second region is set to a second conductivity type and is located on the first surface; the second region contacts the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

17. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 8, wherein the substrate is used to support the semiconductor device.

18. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

19. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 18, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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