Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes a semiconductor body including a well region and a first region; the well region is heavily doped; the first surface is also provided with a gate trench; the semiconductor body further comprises a first insulating layer which is located on the side wall of the gate trench. The two-dimensional conductive layer is located on the side wall of the gate trench; the two-dimensional conductive layer is at least located between the well region and the first insulating layer; the trench gate is positioned on one side, far away from the semiconductor body, of the first insulating layer in the gate trench; the source electrode is located on the first surface; the drain electrode is located on the second surface. According to the technical scheme, the on-resistance of the device is reduced, and the voltage resistance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a third-generation wide-bandgap semiconductor such as silicon carbide or gallium nitride, has the characteristics of large critical breakdown electric field strength, high thermal conductivity, large bandgap width, and high electron saturation drift velocity, and is increasingly used in the field of power devices.

[0003] Trench-gate MOSFETs offer advantages such as high current density and small unit size. However, high-temperature, high-dose, and high-energy ion implantation can cause lattice damage to third-generation wide-bandgap semiconductors such as SiC, and the isolation oxide layer may also contain defects during fabrication. Consequently, SiC and other third-generation wide-bandgap semiconductor devices often exhibit large interface states and channel electron mobility lower than theoretical values. This prevents the devices from fully utilizing the properties of third-generation wide-bandgap semiconductor materials such as SiC, resulting in relatively high on-resistance. Furthermore, in trench-gate MOSFET devices, the large electric field at the bottom of the gate trench results in a relatively low breakdown voltage (BV) and poor withstand voltage performance. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the on-resistance of the device and improve the withstand voltage performance of the device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0006] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and being located on the first surface, the well region being configured as a second conductivity type, being located on a side of the first region away from the first surface and extending along an edge of the first region to the first surface; the well region being heavily doped; a gate trench being further provided on the first surface, the gate trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on sidewalls of the gate trench; the semiconductor body further comprising a two-dimensional conductive layer, the two-dimensional conductive layer being located on sidewalls of the gate trench; the two-dimensional conductive layer being located at least between the well region and the first insulating layer;

[0007] a trench gate, the trench gate being located in the gate trench on a side of the first insulating layer away from the semiconductor body;

[0008] a source electrode, located on the first surface;

[0009] The drain is located on the second surface.

[0010] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0011] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, the well region being configured as a second conductivity type, being located on a side of the first region away from the first surface, and extending along an edge of the first region to the first surface; the ion concentration of the well region being greater than or equal to the ion concentration of the first region; and a gate trench being further disposed on the first surface, the gate trench extending from the first surface into the semiconductor body.

[0012] forming a two-dimensional conductive layer on the sidewall of the gate trench;

[0013] forming a first insulating layer on the sidewall of the gate trench, wherein the two-dimensional conductive layer is at least located between the well region and the first insulating layer;

[0014] forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench;

[0015] forming a source electrode on the first surface;

[0016] A drain electrode is formed on the second surface.

[0017] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0018] According to another aspect of the present invention, a power conversion circuit is provided, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0019] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0020] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0021] The semiconductor device and manufacturing method, power module, power conversion circuit and vehicle provided by the embodiments of the present invention, when the device is turned on, the current passes through the source, the first region, the two-dimensional conductive layer located on the sidewall of the gate trench, and then passes through the drift region to reach the drain. The two-dimensional conductive layer has a very thin thickness and has a high conductivity and electron mobility. The mobility of carriers flowing through the two-dimensional conductive layer is greatly improved. On the basis of not increasing the thickness of the device, the on-resistance of the device is reduced. The lattice damage caused by high temperature, high dose and high energy ion implantation to the semiconductor can be completely ignored. The isolation oxide layer may also have defects during preparation, which has an impact on the increase in the on-resistance of the semiconductor device. Since when the device is turned on, the current passes through the two-dimensional conductive layer and no longer flows through the well region, there is no need to set a well region with a low ion concentration as an inversion layer. A heavily doped well region can be set so that the well region and the drift region form a depletion layer, which improves the electric field distribution at the bottom of the gate trench, increases the breakdown voltage of the semiconductor body device, and improves the withstand voltage performance of the semiconductor device. Furthermore, there's no need to create a low-ion-concentration well region as an inversion layer. Instead, a heavily doped well region of the second conductivity type is directly used during the well formation process, allowing for a good ohmic contact between the source and the semiconductor body. Compared to prior art methods that typically create a high-ion-concentration region of the second conductivity type on one side of the first region to achieve a good ohmic contact between the source and the semiconductor body, this structural arrangement reduces the number of ion implantation steps and improves the device's withstand voltage performance.

[0022] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0025] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0026] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0027] Figure 4 This is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0028] Figure 5-Figure 9 It is a structural schematic diagram corresponding to each relevant step of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0029] Figure 10 yes Figure 4 A schematic diagram of the process included in S110;

[0030] Figure 11-12 yes Figure 9 Structural diagram corresponding to each relevant step in;

[0031] Figure 13 This is a flowchart of S120 in step 4. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] In order to reduce the on-resistance of a MOSFET semiconductor device with a trench gate and improve its withstand voltage performance, the embodiments of the present invention provide the following technical solutions:

[0035] like Figure 1 As shown, Figure 11 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 100, comprising a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 100 further comprising a well region 103 and a first region 104, the first region 104 being of a first conductivity type and being located on the first surface 101; the well region 103 being of a second conductivity type, being located on a side of the first region 104 away from the first surface 101 and extending along an edge of the first region 104 to the first surface 101; the well region 103 being heavily doped; the first surface 101 further comprising a gate trench T1, the gate trench T 1 extends from the first surface 101 into the semiconductor body 100; the semiconductor body 100 further includes a first insulating layer 200, which is located on the sidewalls of the gate trench T1; the semiconductor body 100 further includes a two-dimensional conductive layer 300, which is located on the sidewalls of the gate trench T1; the two-dimensional conductive layer 300 is located at least between the well region 103 and the first insulating layer 200; a trench gate 201, which is located on a side of the first insulating layer 200 in the gate trench T1 away from the semiconductor body 100; a source 400, which is located on the first surface 101; and a drain 500, which is located on the second surface 102.

[0036] For example, Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer is a semiconductor layer formed on the substrate through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0037] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P+ well region, and the P-type doping ions in the P+ well region may be aluminum (Al) ions or boron (B) ions.

[0038] The first insulating layer 200 may be silicon oxide, which is prepared by an oxidation process. The trench gate 201 may be polysilicon.

[0039] In the technical solution provided by the embodiments of the present invention, when the device is turned on, current flows through the source 400, the first region 104, the two-dimensional conductive layer 300 located on the sidewalls of the gate trench T1, and then through the drift region 105 to the drain 500. The two-dimensional conductive layer 300 is very thin, has high conductivity and electron mobility, and the mobility of carriers flowing through the two-dimensional conductive layer 300 is greatly improved. Without increasing the thickness of the device, the on-resistance of the device is reduced. The effects of semiconductor lattice damage caused by high-temperature, high-dose, and high-energy ion implantation, as well as possible defects in the isolation oxide layer during fabrication, which increase the on-resistance of the semiconductor device, can be completely ignored. Because the current flows through the two-dimensional conductive layer 300 and no longer through the well region 103 when the device is turned on, there is no need to provide a low-ion concentration well region 103 as an inversion layer. Instead, a heavily doped well region 103 can be provided, so that the well region 103 and the drift region 105 form a depletion layer, improving the electric field distribution at the bottom of the gate trench T1, increasing the breakdown voltage of the semiconductor device, and enhancing the withstand voltage performance of the semiconductor device. Furthermore, there is no need to provide a low-ion concentration well region 103 as an inversion layer. During the preparation of the well region 103, a second conductivity type and heavily doped well region 103 is directly used, allowing the source 400 to form a good ohmic contact with the semiconductor body 100. Compared to the prior art, in order to form a good ohmic contact between the source 400 and the semiconductor body 100, a region of the second conductivity type and high ion concentration is usually provided on one side of the first region 104. This structural arrangement can reduce the ion implantation process while improving the withstand voltage performance of the device.

[0040] Optionally, based on the above technical solution, the first conductivity type is N-type, and the two-dimensional conductive layer 300 includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

[0041] Specifically, depending on the conductivity type of the MOSFET semiconductor device, the two-dimensional conductive layer 300 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Since the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and has a very high conductivity and carrier mobility, the mobility of the carriers flowing through the two-dimensional conductive layer 300 is greatly improved, thereby reducing the on-resistance of the device without increasing the thickness of the device.

[0042] It should be noted that the two-dimensional electron gas layer is typically a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperature conditions), due to differences in material properties at its heterojunction interface, a large concentration of two-dimensional electron gas is formed, achieving excellent electron mobility, which is far greater than the electron mobility of silicon, silicon carbide, and gallium nitride, far exceeding the carrier requirements of the device and significantly improving the carrier mobility of the device. Moreover, the movement of electrons in the two-dimensional electron gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent electron mobility on the two-dimensional surface where the heterojunction interface is located. Correspondingly, the movement of holes in the two-dimensional hole gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent hole mobility on the two-dimensional surface where the heterojunction interface is located.

[0043] Optionally, based on the above technical solution, for an N-type MOSFET device, the first conductivity type is N-type, the first region 104 is an N+ region, and the well region 103 is a P+ region; or, for a P-type MOSFET device, the first conductivity type is P-type, the first region 104 is a P+ region, and the well region 103 is an N+ region.

[0044] It should be noted that in existing semiconductor devices, for N-type MOSFET devices, the first conductivity type is N-type, the first region 104 is an N+ region, and the well region 103 is a P-type region; alternatively, for P-type MOSFET devices, the first conductivity type is P-type, the first region 104 is a P+ region, and the well region is an N-type region. The ion concentration of the well region 103 is not that of a heavily doped region. Because in existing semiconductor devices, when the device is turned on, current flows through the well region 103, it is necessary to provide a well region 103 with a low ion concentration as an inversion layer.

[0045] Therefore, for an N-type MOSFET device, the first conductivity type is N-type, the first region 104 is an N+ region, and the well region 103 is a heavily doped well region 103 of a P+ region, which increases the ion concentration of the well region 103, so that the well region 103 and the drift region 105 form a depletion layer, improve the electric field distribution at the bottom of the gate trench T1, increase the breakdown voltage of the semiconductor body device, and improve the voltage resistance performance of the semiconductor device. There is no need to set a well region 103 with a low ion concentration as an inversion layer. In the process of preparing the well region 103, ion implantation with a P+ ion concentration is directly used. Compared to forming a P+ region on one side of the first region 104 in order to form a good ohmic contact between the source 400 and the semiconductor body 100, the above-mentioned structural setting can reduce the ion implantation process and improve the voltage resistance performance of the device.

[0046] For a P-type MOSFET device, the first conductivity type is P-type, the first region 104 is a P+ region, and the well region 103 is a heavily doped well region 103 of an N+ region, which increases the ion concentration of the well region 103, so that the well region 103 and the drift region 105 form a depletion layer, improve the electric field distribution at the bottom of the gate trench T1, increase the breakdown voltage of the semiconductor body device, and improve the voltage resistance performance of the semiconductor device. There is no need to set a well region 103 with a low ion concentration as an inversion layer. In the process of preparing the well region 103, ion implantation with an N+ ion concentration is directly used. Compared with the N+ region usually set on one side of the first region 104 in order to form a good ohmic contact between the source 400 and the semiconductor body 100, the above-mentioned structural setting can reduce the ion implantation process and improve the voltage resistance performance of the device.

[0047] The two-dimensional conductive layer 300 is located on the sidewalls of the gate trench T1. The longer the length of the two-dimensional conductive layer 300 from the first surface 101 to the second surface 102, the more significant the effect of the two-dimensional conductive layer 300 on improving the carrier mobility and reducing the on-resistance of the device. The two-dimensional conductive layer 300 is located at least between the well region 103 and the first insulating layer 200 and includes the following structure:

[0048] In the first structure, the two-dimensional conductive layer 300 is located between the well region 103 and the first insulating layer 200;

[0049] In the second structure, the two-dimensional conductive layer 300 is located between the well region 103 and the first insulating layer 200 , and the two-dimensional conductive layer 300 is located between the drift region 105 and the first insulating layer 200 ;

[0050] In the third structure, the two-dimensional conductive layer 300 is located between the first region 104 and the first insulating layer 200 , the two-dimensional conductive layer 300 is located between the well region 103 and the first insulating layer 200 , and the two-dimensional conductive layer 300 is located on the side of the well region 103 away from the first region 104 .

[0051] Optionally, based on the above technical solution, Figure 1 and Figure 2 As shown, Figure 1 and Figure 2 shows the second structure mentioned above, Figure 2It is a structural schematic diagram of another semiconductor device provided by an embodiment of the present invention, wherein the gate trench T1 extends from the first surface 101 through the first region 104, the well region 103 and to the side of the well region 103 away from the first region 104; the two-dimensional conductive layer 300 includes a first conductive portion 301 and a second conductive portion 302 located on the sidewall of the gate trench T1 and connected, and the second conductive portion 302 is located on the side of the first conductive portion 301 away from the first surface 101; the first conductive portion 301 is located between the well region 103 and the first insulating layer 200; the second conductive portion 302 is located on the side of the well region 103 away from the first region 104.

[0052] Optionally, based on the above technical solution, Figure 3 As shown, Figure 3 is a structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 3 The third structure mentioned above is shown. The two-dimensional conductive layer 300 further includes a third conductive portion 303 located on the sidewall of the gate trench T1 and connected to the first conductive portion 301 . The third conductive portion 303 is located between the first region 104 and the first insulating layer 200 .

[0053] Optionally, based on the above technical solution, Figure 1-Figure 3 As shown, the two-dimensional conductive layer 300 includes a first gallium nitride layer and a second gallium nitride layer. The first gallium nitride layer is in contact with at least the well region 103. The second gallium nitride layer is located on a side of the first gallium nitride layer away from the well region 103. The second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first and second gallium nitride layers. Optionally, based on the above technical solution, the second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

[0054] The two-dimensional conductive layer 300 includes a first gallium nitride layer and a second gallium nitride layer. The first gallium nitride layer comprises an undoped gallium nitride material, and the second gallium nitride layer comprises magnesium gallium nitride or aluminum gallium nitride. The first and second gallium nitride layers are stacked to form a heterojunction semiconductor layer. Under specific conditions (e.g., a specific electric field and a specific temperature), due to differences in material properties, a high concentration of a two-dimensional electron gas or a two-dimensional hole gas is formed at the heterojunction interface. This two-dimensional electron gas or a two-dimensional hole gas has carrier mobility far exceeding that of silicon, silicon carbide, and gallium nitride, far exceeding the carrier mobility requirements of the device. This significantly improves the device's carrier mobility and reduces its on-resistance. For example, in an N-type MOSFET device, magnesium gallium nitride or aluminum gallium nitride forms a P-type doped second gallium nitride layer, forming a space charge region between it and the first conductivity type semiconductor body 100. This prevents current from flowing from the source 400 to the drain 500 when the device is in the off state.

[0055] Optionally, based on the above technical solution, semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device; or, semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0056] Optionally, based on the above structure, a plurality of gate trenches T1 are provided on the first surface 101 , and the plurality of gate trenches T1 are located on the first surface 101 and are arranged at intervals.

[0057] Specifically, a semiconductor device with multiple gate trenches T1 can further improve the gate control capability of the trench gate 201, thereby improving the performance of the semiconductor device. It should be noted that the figure does not show a semiconductor device including multiple gate trenches T1.

[0058] For trench MOSFET devices, including Figure 1 The single trench structure shown also includes Figure 2 and Figure 3 The double trench structure shown. Figure 2 and Figure 3 As shown, the first surface 101 is also provided with a source trench T2, which extends from the first surface 101 into the semiconductor body 100; the semiconductor device also includes a source trench structure 401, and the source trench structure 401 includes a filling layer 402 and a second insulating layer 403; the second insulating layer 403 is located on the bottom surface and sidewall of the source trench T2; the filling layer 402 is located in the source trench T2 on a side away from the second insulating layer 403 and away from the semiconductor body 100.

[0059] Specifically, the provision of the source trench T2 and the source trench structure 401 improves the electric field distribution of the gate trench T1 near the bottom of the second surface 102, further improving the withstand voltage of the insulating layer at the bottom of the gate trench T1, thereby further improving the breakdown voltage of the semiconductor device and enhancing device performance.

[0060] In other optional embodiments, in a single-trench MOSFET device, the two-dimensional conductive layer 300 may also include a third conductive portion 303 located on the sidewall of the gate trench T1 and connected to the first conductive portion 301, and the third conductive portion 303 is located between the first region 104 and the first insulating layer 200, so as to further improve the carrier migration speed of the device and reduce the on-resistance of the device. Figure 2 and Figure 3As shown, the semiconductor body 100 also includes a second region 404, which is set to the second conductivity type and surrounds the bottom surface and sidewalls of the source trench T2. The ion concentration of the second region 404 is greater than the ion concentration of the first region 104. The second region 404 is connected to the well region 103. Specifically, the second region 404 of the second conductivity type and the drift region 105 of the first conductivity type can form a depletion layer to improve the electric field distribution at the bottom of the gate trench T1, further improving the withstand voltage of the insulating layer at the bottom of the gate trench T1, thereby further improving the breakdown voltage of the semiconductor device and enhancing device performance. Exemplarily, for an N-type MOSFET, the second region 404 is a P+ doped region.

[0061] Optionally, the vertical distance d1 between the second region 404 and the second surface 102 is smaller than the vertical distance d2 between the gate trench T1 and the second surface 102, which can increase the depth of the depletion layer formed by the second conductive type second region 404 and the first conductive type drift region 105, and further improve the voltage resistance effect.

[0062] Optionally, based on the above technical solution, Figure 1-Figure 3 As shown, the semiconductor device further includes an ohmic contact layer 600 located between the source 400 and the first surface 101 .

[0063] Specifically, the ohmic contact layer 600 includes an ohmic metal layer, which helps to form a good ohmic contact between the semiconductor body 100 and the source 400 .

[0064] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 4 As shown, Figure 4 This is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 1 Taking the semiconductor device shown as an example, the semiconductor device includes the following steps:

[0065] S110. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body also including a well region and a first region, the first region is set to a first conductive type and is located on the first surface, the well region is set to a second conductive type, is located on a side of the first region away from the first surface and extends along an edge of the first region to the first surface; the well region is heavily doped; the first surface is also provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body.

[0066] like Figure 5As shown, a semiconductor body 100 is provided, which includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 also includes a well region 103 and a first region 104. The first region 104 is set to a first conductive type and is located on the first surface 101. The well region 103 is set to a second conductive type, is located on a side of the first region 104 away from the first surface 101 and extends along the edge of the first region 104 to the first surface 101; the well region 103 is heavily doped; and a gate trench T1 is further provided on the first surface 101, which extends from the first surface 101 to the semiconductor body 100.

[0067] For example, Figure 5 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer is a semiconductor layer formed on the substrate through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0068] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P+ well region, and the P-type doping ions in the P+ well region may be aluminum (Al) ions or boron (B) ions.

[0069] It should be noted that for Figure 2 and Figure 3 For the dual-trench MOSFET shown, the source trench T2 is prepared simultaneously with the formation of the gate trench T1. Furthermore, before forming the two-dimensional conductive layer 300, the second region 404 is prepared at the bottom and sidewalls of the source trench T2 by an ion implantation process. Ion implantation can be performed by ion implantation, ion diffusion, or vapor deposition.

[0070] For a MOSFET device including a plurality of gate trenches T1 , it is necessary to form a plurality of gate trenches T1 spaced apart on the first surface 101 .

[0071] S120 , forming a two-dimensional conductive layer on the sidewall of the gate trench.

[0072] like Figure 6 As shown, a two-dimensional conductive layer 300 is formed on the first surface 101 and in the gate trench T1 by an epitaxial process. Figure 7 As shown, a two-dimensional conductive layer 300 is formed on the sidewall of the gate trench T1 by an etching process.

[0073] The first surface 101 is then planarized by a chemical mechanical polishing (CMP) process.

[0074] S130 , forming a first insulating layer on the sidewall of the gate trench, wherein the two-dimensional conductive layer is at least located between the well region and the first insulating layer.

[0075] like Figure 8 As shown, a first insulating layer 200 with a high dielectric constant is formed on the sidewall of the gate trench T1 by thermal oxidation or deposition process. The two-dimensional conductive layer 300 is at least located between the well region 103 and the first insulating layer 200 .

[0076] It should be noted that for Figure 2 and Figure 3 For the double-trench MOSFET shown, while forming the first insulating layer 200 , the second insulating layer 403 is also prepared.

[0077] S140 , forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench.

[0078] like Figure 8 As shown, a first insulating layer 200 is formed in the gate trench T1 through a deposition process. A trench gate 201 is formed on a side away from the semiconductor body 100 . The trench gate 201 may be a polysilicon gate.

[0079] It should be noted that for Figure 2 and Figure 3 For the double-trench MOSFET shown, a filling layer 402 needs to be formed on the side of the second insulating layer 403 in the source trench T2 away from the semiconductor body 100. The filling layer 402 can be made of filling materials such as polysilicon or silicon nitride.

[0080] S150 , forming a source electrode on the first surface.

[0081] like Figure 1 As shown, the source 400 is formed on the first surface 101 by a metal conductive layer deposition process. Figure 9 As shown, before forming the source 400 , an interlayer insulating layer 202 may be formed. The interlayer insulating layer 202 is used to insulate the trench gate 201 and the source 400 .

[0082] S160 , forming a drain on the second surface.

[0083] like Figure 1 As shown, a metal conductive layer deposition process is used to form a drain electrode 500 on the second surface 102. Optionally, before forming the drain electrode 500, the substrate 10 may be thinned to reduce the on-resistance of the device.

[0084] In the technical solution provided by the embodiments of the present invention, when the device is turned on, current flows through the source 400, the first region 104, the two-dimensional conductive layer 300 located on the sidewalls of the gate trench T1, and then through the drift region 105 to the drain 500. The two-dimensional conductive layer 300 is very thin, has high conductivity and electron mobility, and the mobility of carriers flowing through the two-dimensional conductive layer 300 is greatly improved. Without increasing the thickness of the device, the on-resistance of the device is reduced. The effects of semiconductor lattice damage caused by high-temperature, high-dose, and high-energy ion implantation, as well as possible defects in the isolation oxide layer during fabrication, which increase the on-resistance of the semiconductor device, can be completely ignored. Because the current flows through the two-dimensional conductive layer 300 and no longer through the well region 103 when the device is turned on, there is no need to provide a low-ion concentration well region 103 as an inversion layer. Instead, a heavily doped well region 103 can be provided, so that the well region 103 and the drift region 105 form a depletion layer, improving the electric field distribution at the bottom of the gate trench T1, increasing the breakdown voltage of the semiconductor device, and enhancing the withstand voltage performance of the semiconductor device. Furthermore, there is no need to provide a low-ion concentration well region 103 as an inversion layer. During the preparation of the well region 103, a second conductivity type and heavily doped well region 103 is directly used, allowing the source 400 to form a good ohmic contact with the semiconductor body 100. Compared to the prior art, in order to form a good ohmic contact between the source 400 and the semiconductor body 100, a region of the second conductivity type and high ion concentration is usually provided on one side of the first region 104. This structural arrangement can reduce the ion implantation process while improving the withstand voltage performance of the device.

[0085] Optionally, based on the above technical solution, the first conductivity type is N-type, and the two-dimensional conductive layer 300 includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

[0086] Specifically, depending on the conductivity type of the MOSFET semiconductor device, the two-dimensional conductive layer 300 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Since the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness and has a very high conductivity and carrier mobility, the mobility of the carriers flowing through the two-dimensional conductive layer 300 is greatly improved, thereby reducing the on-resistance of the device without increasing the thickness of the device.

[0087] It should be noted that the two-dimensional electron gas layer is typically a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperature conditions), due to differences in material properties at its heterojunction interface, a large concentration of two-dimensional electron gas is formed, achieving excellent electron mobility, which is far greater than the electron mobility of silicon, silicon carbide, and gallium nitride, far exceeding the carrier requirements of the device and significantly improving the carrier mobility of the device. Moreover, the movement of electrons in the two-dimensional electron gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent electron mobility on the two-dimensional surface where the heterojunction interface is located. Correspondingly, the movement of holes in the two-dimensional hole gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent hole mobility on the two-dimensional surface where the heterojunction interface is located.

[0088] Optionally, based on the above technical solution, Figure 10 As shown, Figure 10 yes Figure 4 The process diagram of S110 includes: S110 provides a semiconductor body including:

[0089] S1101 , provide a semiconductor body, wherein the semiconductor body includes a first surface and a second surface arranged opposite to each other.

[0090] like Figure 11 As shown, a substrate 10 is prepared, and an epitaxial layer 20 is formed on the surface of the substrate 10 by an epitaxial process to provide a semiconductor body 100 . The semiconductor body 100 includes a first surface 101 and a second surface 102 that are opposite to each other.

[0091] S1102 , forming a well region on the first surface, wherein the well region is set to a second conductivity type.

[0092] like Figure 12 The well region 103 is formed on the first surface 101 by an ion doping process. The well region 103 is set to the second conductivity type, wherein the semiconductor body 100 is the first conductivity type. The ion doping process includes ion implantation, ion diffusion or vapor deposition.

[0093] S1103, forming a first region on the first surface, wherein the first region is set to a first conductivity type; the well region is located on a side of the first region away from the first surface and extends along an edge of the first region to the first surface; the well region is heavily doped.

[0094] like Figure 12As shown, a first region 104 of a first conductivity type is formed on the first surface through an ion doping process, and a well region 103 extends along the edge of the first region 104 to the first surface 101. The well region 103 is heavily doped. For example, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type dopant ions in the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P+ well region, and the P-type dopant ions in the P+ well region can be aluminum (Al) ions or boron (B) ions.

[0095] S1104 , forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body.

[0096] like Figure 5 As shown, a gate trench T1 is formed on the first surface 101 by a trench etching process, and the gate trench T1 extends from the first surface 101 into the semiconductor body 100 .

[0097] It should be noted that in the above technical solution, the first region 104 and the well region 103 are first formed on the first surface 101 by an ion doping process, and then the gate trench T1 is formed by a trench etching process. In the double-trench MOSFET device, the source trench T2 is also formed on the first surface 101.

[0098] In other optional embodiments, the gate trench T1 and the source trench T2 may be formed on the first surface 101 first, and then an ion doping process may be performed to form the first region 104 and the well region 103 .

[0099] Optionally, based on the above technical solution, for an N-type MOSFET device, the first conductivity type is N-type, the first region 104 is an N+ region, and the well region 103 is a P+ region; or, for a P-type MOSFET device, the first conductivity type is P-type, the first region 104 is a P+ region, and the well region 103 is an N+ region.

[0100] It should be noted that in existing semiconductor devices, for N-type MOSFET devices, the first conductivity type is N-type, the first region 104 is an N+ region, and the well region 103 is a P-type region; alternatively, for P-type MOSFET devices, the first conductivity type is P-type, the first region 104 is a P+ region, and the well region is an N-type region. The well region 103 is not a heavily doped region. Because in existing semiconductor devices, when the device is turned on, current flows through the well region 103, it is necessary to provide a well region 103 with a low ion concentration as an inversion layer.

[0101] Therefore, for an N-type MOSFET device, the first conductivity type is N-type, the first region 104 is an N+ region, and the well region 103 is a heavily doped well region 103 of a P+ region, which increases the ion concentration of the well region 103, so that the well region 103 and the drift region 105 form a depletion layer, improve the electric field distribution at the bottom of the gate trench T1, increase the breakdown voltage of the semiconductor body device, and improve the voltage resistance performance of the semiconductor device. There is no need to set a well region 103 with a low ion concentration as an inversion layer. In the process of preparing the well region 103, ion implantation with a P+ ion concentration is directly used. Compared to forming a P+ region on one side of the first region 104 in order to form a good ohmic contact between the source 400 and the semiconductor body 100, the above-mentioned structural setting can reduce the ion implantation process and improve the voltage resistance performance of the device.

[0102] For a P-type MOSFET device, the first conductivity type is P-type, the first region 104 is a P+ region, and the well region 103 is a heavily doped well region 103 of an N+ region, which increases the ion concentration of the well region 103, so that the well region 103 and the drift region 105 form a depletion layer, improve the electric field distribution at the bottom of the gate trench T1, increase the breakdown voltage of the semiconductor body device, and improve the voltage resistance performance of the semiconductor device. There is no need to set a well region 103 with a low ion concentration as an inversion layer. In the process of preparing the well region 103, ion implantation with an N+ ion concentration is directly used. Compared with the N+ region usually set on one side of the first region 104 in order to form a good ohmic contact between the source 400 and the semiconductor body 100, the above-mentioned structural setting can reduce the ion implantation process and improve the voltage resistance performance of the device.

[0103] Optionally, based on the above technical solution, S1104 forming a gate trench on the first surface includes:

[0104] A gate trench is formed on the first surface, passing through the first region, the well region, and extending to a side of the well region away from the first region; the two-dimensional conductive layer includes a first conductive portion and a second conductive portion located on and connected to the sidewall of the gate trench, the second conductive portion being located on a side of the first conductive portion away from the first surface; the first conductive portion is located between the well region and the first insulating layer; and the second conductive portion is located extending to a side of the well region away from the first region.

[0105] like Figure 5 As shown, a gate trench T1 is formed on the first surface 101, passing through the first region 104 and the well region 103 and extending to a side of the well region 103 away from the first region 104. Figure 6As shown, the two-dimensional conductive layer 300 includes a first conductive portion 301 and a second conductive portion 302 located on and connected to the side wall of the gate trench T1, the second conductive portion 302 is located on the side of the first conductive portion 301 away from the first surface 101; the first conductive portion 301 is located between the well region 103 and the first insulating layer 200; the second conductive portion 302 is located on the side of the well region 103 away from the first region 104.

[0106] The two-dimensional conductive layer 300 is located on the sidewall of the gate trench T1. The longer the length of the two-dimensional conductive layer 300 from the first surface 101 to the second surface 102 is, the more significant the effect of the two-dimensional conductive layer 300 on improving the carrier mobility and reducing the on-resistance of the device is. The two-dimensional conductive layer 300 is at least located between the well region 103 and the first insulating layer 200, and includes Figure 1 In addition to the structure shown, the following two structures are also included:

[0107] The two-dimensional conductive layer 300 is located between the well region 103 and the first insulating layer 200 .

[0108] Or, as Figure 3 In the structure shown, the two-dimensional conductive layer 300 is located between the first region 104 and the first insulating layer 200 , between the well region 103 and the first insulating layer 200 , and between the drift region 105 and the first insulating layer 200 .

[0109] Alternatively, as Figure 13 As shown, Figure 13 4 is a schematic diagram of the process included in S120, characterized in that S120 forms a two-dimensional conductive layer on the sidewall of the gate trench, including:

[0110] S1201 , forming a first gallium nitride layer on a sidewall of the gate trench, wherein the first gallium nitride layer at least contacts the well region.

[0111] like Figure 6 and Figure 7 As shown, a first gallium nitride layer is formed on the sidewall of the gate trench T1 by an epitaxial process. The first gallium nitride layer includes undoped gallium nitride material.

[0112] S1202. Form a second gallium nitride layer on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0113] like Figure 6 and Figure 7As shown, a second gallium nitride layer is formed on a side of the first gallium nitride layer away from the well region 103 through an epitaxial process. The second gallium nitride layer is a doped gallium nitride material. Two-dimensional electron gas or two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0114] The two-dimensional conductive layer 300 includes a first gallium nitride layer and a second gallium nitride layer. The first gallium nitride layer comprises an undoped gallium nitride material, and the second gallium nitride layer comprises magnesium gallium nitride or aluminum gallium nitride. The first and second gallium nitride layers are stacked to form a heterojunction semiconductor layer. Under specific conditions (e.g., a specific electric field and a specific temperature), due to differences in material properties, a high concentration of a two-dimensional electron gas or a two-dimensional hole gas is formed at the heterojunction interface. This two-dimensional electron gas or a two-dimensional hole gas has carrier mobility far exceeding that of silicon, silicon carbide, and gallium nitride, far exceeding the carrier mobility requirements of the device. This significantly improves the device's carrier mobility and reduces its on-resistance. For example, in an N-type MOSFET device, magnesium gallium nitride or aluminum gallium nitride forms a P-type doped second gallium nitride layer, forming a space charge region between it and the first conductivity type semiconductor body 100. This prevents current from flowing from the source 400 to the drain 500 when the device is in the off state.

[0115] Optionally, based on the above technical solution, semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device; or, semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0116] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device provided by any of the embodiments of the present invention, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of the power module including any of the semiconductor devices provided by the embodiments of the present invention are not further described here.

[0117] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device provided by any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0118] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device provided by the embodiments of the present invention will not be repeated here.

[0119] An embodiment of the present invention further provides a vehicle, including a load and a power conversion circuit as provided in any embodiment of the present invention. The power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. Therefore, the beneficial effects of including any power conversion circuit provided in any embodiment of the present invention in the vehicle are not further elaborated here.

[0120] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0121] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and being located on the first surface; the well region being configured as a second conductivity type, being located on a side of the first region away from the first surface and extending along an edge of the first region to the first surface; the well region being heavily doped; a gate trench being further provided on the first surface, the gate trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on sidewalls of the gate trench; the semiconductor body further comprising a two-dimensional conductive layer, the two-dimensional conductive layer being located on sidewalls of the gate trench; the two-dimensional conductive layer being located at least between the well region and the first insulating layer; a trench gate, the trench gate being located in the gate trench on a side of the first insulating layer away from the semiconductor body; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

3. The semiconductor device according to claim 1, wherein The first conductivity type is N type, the first region is an N+ region, and the well region is a P+ region; Alternatively, the first conductivity type is P type, the first region is a P+ region, and the well region is an N+ region.

4. The semiconductor device according to claim 1, wherein The gate trench extends from the first surface through the first region and the well region to a side of the well region away from the first region; The two-dimensional conductive layer includes a first conductive portion and a second conductive portion located on and connected to the sidewall of the gate trench, wherein the second conductive portion is located on a side of the first conductive portion away from the first surface; The first conductive portion is located between the well region and the first insulating layer; The second conductive portion is located on a side of the well region away from the first region.

5. The semiconductor device according to claim 4, wherein The two-dimensional conductive layer further includes a third conductive portion located on a sidewall of the gate trench and connected to the first conductive portion, wherein the third conductive portion is located between the first region and the first insulating layer. The semiconductor device according to claim 1 , wherein: The two-dimensional conductive layer includes a first gallium nitride layer and a second gallium nitride layer; The first gallium nitride layer is in contact with at least the well region; The second gallium nitride layer is located on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

7. The semiconductor device according to claim 1 or 6, characterized in that The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride body.

8. The semiconductor device according to claim 6, wherein: The second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

9. The semiconductor device according to claim 1, wherein The first surface is provided with a plurality of gate trenches, and the plurality of gate trenches are located on the first surface and are arranged at intervals.

10. The semiconductor device according to claim 1, wherein The first surface is further provided with a source trench, wherein the source trench extends from the first surface into the semiconductor body; The semiconductor device further includes a source trench structure, wherein the source trench structure includes a filling layer and a second insulating layer; The second insulating layer is located on the bottom surface and sidewalls of the source trench; the filling layer is located on a side of the source trench away from the second insulating layer and away from the semiconductor body.

11. The semiconductor device according to claim 10, wherein: The semiconductor body also includes a second region, which is set to a second conductivity type and surrounds the bottom surface and sidewalls of the source trench. The ion concentration of the second region is greater than or equal to the ion concentration of the first region; the second region is connected to the well region.

12. The semiconductor device according to claim 1, wherein An ohmic contact layer is also included, located between the source electrode and the first surface.

13. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, the well region being of a second conductivity type and located on a side of the first region away from the first surface and extending along an edge of the first region to the first surface; the well region being heavily doped; and a gate trench being further disposed on the first surface, the gate trench extending from the first surface into the semiconductor body. forming a two-dimensional conductive layer on the sidewall of the gate trench; forming a first insulating layer on the sidewall of the gate trench, wherein the two-dimensional conductive layer is at least located between the well region and the first insulating layer; forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; forming a well region on the first surface, wherein the well region is set to a second conductivity type; A first region is formed on the first surface, the first region being of a first conductivity type; the well region is located on a side of the first region away from the first surface and extends along an edge of the first region to the first surface; the well region is heavily doped; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; Alternatively, providing the semiconductor body comprises: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; forming a well region on the first surface, wherein the well region is set to a second conductivity type; A first region is formed on the first surface, and the first region is set to a first conductivity type; the well region is located on a side of the first region away from the first surface and extends along an edge of the first region to the first surface, and the well region is heavily doped.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The first conductivity type is N-type, and forming a well region on the first surface includes: forming a well region including a P+ region on the first surface; Forming a first region on the first surface includes: forming a first region including an N+ region on the first surface; Alternatively, the first conductivity type is P-type, and forming a well region on the first surface includes: forming a well region including an N+ region on the first surface; Forming a first region on the first surface includes: A first region including a P+ region is formed on the first surface.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: Forming a gate trench on the first surface includes: forming a gate trench on the first surface, the gate trench extending from the first surface through the first region and the well region to a side of the well region away from the first region; The two-dimensional conductive layer includes a first conductive part and a second conductive part located on and connected to the sidewall of the gate trench, the second conductive part is located on the side of the first conductive part away from the first surface; the first conductive part is located between the well region and the first insulating layer; the second conductive part is located on the side of the well region away from the first region.

18. The method for manufacturing a semiconductor device according to claim 13, wherein: Forming a two-dimensional conductive layer on the sidewall of the gate trench includes: forming a first gallium nitride layer on a sidewall of the gate trench, wherein the first gallium nitride layer at least contacts the well region; A second gallium nitride layer is formed on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

19. The method for manufacturing a semiconductor device according to claim 13 or 18, wherein: The semiconductor body provided includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride body.

20. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 12, wherein the substrate is used to support the semiconductor device.

21. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device is electrically connected to the circuit board.

22. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 21, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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