Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, the semiconductor body comprises a first surface, a second surface, a well region and a first region, and the well region is located on the side, away from the first surface, of the first region, extends to the first surface along the surface of the first region and comprises a fourth surface and a fifth surface; the two-dimensional conductive layer is located on the fifth surface; the voltage-withstanding layer is located on the first surface and located on the side, away from the well region, of the two-dimensional conductive layer; the first insulating layer is located on the first surface; the gate is located at one side of the first insulating layer away from the first surface; the source is located on the first surface; the drain is located on the second surface. The two-dimensional conductive layer and the voltage-withstanding layer are arranged, so that the carrier mobility of the semiconductor device is improved, the influence of built-in resistance is eliminated, the resistance between the source electrode and the drain electrode of the semiconductor device is reduced, the energy consumption is reduced, the working temperature of the device is reduced, and the size of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) have excellent high-temperature performance, electronic properties and chemical stability.

[0003] For a planar Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the semiconductor body on one side of the well region is a Junction Field-Effect Transistor (JFET) region.

[0004] For P-type SiC MOSFET, a positive voltage is applied to its source and a negative voltage is applied to the gate. When the threshold voltage is reached, an inversion layer is formed in the N-type well region. The current flows from the metal conductive layer through the doped region formed by P-type ion implantation to the inversion layer, and then through the JFET region and drift region, and then through the silicon carbide substrate to reach the drain.

[0005] However, due to the space charge region generated at the intersection of the N-type well region and the P-type SiC epitaxial region of the JFET region, the device generates built-in resistance, namely the JFET resistance. When the device is in the on state, the current flows from the inversion region of the well region through the JFET region to the drain, which will be affected by the space charge region, resulting in an increase in the resistance between the source and drain of the semiconductor device, and increased energy consumption, causing the temperature of the device to rise during operation. Summary of the Invention

[0006] The present invention provides a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle to solve the problems of increased resistance between the source and drain of MOSFET devices, increased energy consumption and increased temperature during device operation.

[0007] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0008] A semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, wherein the first region is configured to be of a first conductivity type and is located on the first surface; the well region is configured to be of a second conductivity type and is located on a side of the first region away from the first surface and extends along a surface of the first region to the first surface; the well region comprises a fourth surface away from the first surface and a fifth surface connecting the fourth surface and the first surface;

[0009] a two-dimensional conductive layer located on the fifth surface; a preset distance is set between an end of the two-dimensional conductive layer close to the first surface and the first surface;

[0010] a voltage-resistant layer, located on the first surface and on a side of the two-dimensional conductive layer away from the well region;

[0011] a first insulating layer, located on the first surface;

[0012] a gate, located on a side of the first insulating layer away from the first surface;

[0013] a source electrode, located on the first surface;

[0014] The drain is located on the second surface.

[0015] Optionally, the semiconductor body includes a first semiconductor body and a second semiconductor body;

[0016] The second semiconductor body is located on the first surface, and the first semiconductor body is located on the second surface;

[0017] The first semiconductor body is provided with a groove, the groove is located on the third surface of the first semiconductor body and extends into the first semiconductor body, and the third surface and the second surface are arranged opposite to each other;

[0018] The two-dimensional conductive layer is located on the sidewalls of the groove;

[0019] The voltage-resistant layer is located in the groove, and the surface of the voltage-resistant layer is away from the first semiconductor body and is flush with the first surface;

[0020] The first region and the well region are located in the second semiconductor body and the first semiconductor body.

[0021] Optionally, the two-dimensional conductive layer includes a first gallium nitride layer and a second gallium nitride layer;

[0022] The first gallium nitride layer is located on the fifth surface;

[0023] The second gallium nitride layer is located on a side of the fifth surface away from the well region;

[0024] The second gallium nitride layer is a doped gallium nitride material, and two-dimensional electron gas or two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0025] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a silicon nitride semiconductor body.

[0026] Optionally, the second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

[0027] Optionally, the dielectric constant of the material of the voltage-resistant layer is greater than or equal to the dielectric constant of silicon oxide.

[0028] Optionally, the voltage-resistant layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and zirconium oxide.

[0029] Optionally, the semiconductor body further includes a second region, which is set to the second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0030] Optionally, the first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

[0031] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:

[0032] A semiconductor body is provided, comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, wherein the first region is configured as a first conductivity type and is located on the first surface; the well region is configured as a second conductivity type and is located on a side of the first region away from the first surface and extends along the surface of the first region to the first surface; the well region comprises a fourth surface away from the first surface and a fifth surface connecting the fourth surface and the first surface; a two-dimensional conductive layer is formed on the fifth surface; a preset distance is provided between an end of the two-dimensional conductive layer close to the first surface and the first surface; and a voltage-resistant layer is formed on the first surface.

[0033] forming a first insulating layer on the first surface;

[0034] forming a gate on a side of the first insulating layer away from the first surface;

[0035] forming a source electrode on the first surface;

[0036] A drain electrode is formed on the second surface.

[0037] Optionally, providing a semiconductor body includes:

[0038] providing a first semiconductor body;

[0039] forming a groove in the first semiconductor body, the groove being located on the third surface of the first semiconductor body and extending into the first semiconductor body, the third surface being arranged opposite to the second surface;

[0040] forming a two-dimensional conductive layer on the sidewalls of the groove;

[0041] forming a second semiconductor body on one side of the first semiconductor body, the second semiconductor body covering the two-dimensional conductive layer, the surface of the second semiconductor body away from the first semiconductor body being a first surface, and the surface of the first semiconductor body away from the second semiconductor body being a second surface;

[0042] forming a voltage-resistant layer in the groove, wherein the voltage-resistant layer is away from a surface of the first semiconductor body and is flush with the first surface;

[0043] A first region and a well region are formed in the second semiconductor body and the first semiconductor body.

[0044] Optionally, forming a two-dimensional conductive layer on the sidewall of the groove includes:

[0045] forming a two-dimensional conductive layer on the third surface and the sidewalls of the groove;

[0046] The two-dimensional conductive layer on the third surface is removed.

[0047] Optionally, before the second semiconductor body and the first semiconductor body form the first region and the well region, the method further includes:

[0048] A planarization process is performed on a surface of the second semiconductor body away from the first semiconductor body.

[0049] Optionally, forming a two-dimensional conductive layer on the sidewall of the groove includes:

[0050] forming a first gallium nitride layer on a sidewall of the groove;

[0051] A second gallium nitride layer is formed on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0052] Optionally, forming a pressure-resistant layer in the groove includes:

[0053] A voltage-resistant layer including at least one of silicon oxide, silicon nitride, aluminum oxide and zirconium oxide is formed in the groove; the voltage-resistant layer is away from a surface of the first semiconductor body and flush with the first surface.

[0054] Optionally, providing the semiconductor body further includes:

[0055] A semiconductor body is provided which includes a silicon carbide semiconductor body or a silicon nitride semiconductor body.

[0056] Optionally, providing the semiconductor body further includes:

[0057] A semiconductor body including a second region is provided; the second region is set to a second conductivity type and is located on the first surface; the second region contacts the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0058] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0059] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0060] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0061] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0062] According to the technical solution of the embodiment of the present invention, when the first conductivity type is N-type, the two-dimensional conductive layer includes a two-dimensional electron gas layer; when the first conductivity type is P-type, the two-dimensional conductive layer includes a two-dimensional hole gas layer. When the device is turned on, the carriers pass through the source, the first region, the well region, and then through the two-dimensional conductive layer, and then through the drift region to reach the drain, without passing through the JFET region on the side of the well region. Since the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very high carrier mobility, a low-resistance conductive channel can be provided between the first surface and the drift region. Carriers can flow through this channel without being affected by the narrowing of the effective conductive area caused by the expansion of the depletion layer in the JFET structure. This solves the problems of increased resistance between the source and drain in MOSFET devices, increased energy consumption, and temperature rise during device operation, thereby reducing the on-resistance of the device. The two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness. Due to its high conductivity and carrier mobility, it replaces the JFET region as the current channel. There is no need to provide a JFET region of sufficient lateral dimensions on one side of the well region in the planar MOSFET device to ensure that the JFET region has a resistance that matches the on-current. In addition, a voltage-resistant layer 30 is provided between the drift region and the first surface. While ensuring the device's voltage resistance, the lateral dimensions of the semiconductor body on the well region side can be reduced, thereby reducing the lateral dimensions of the semiconductor device. It should be noted that in the embodiments of the present invention, the lateral dimension refers to the dimension in the direction perpendicular to the first surface and pointing to the second surface.

[0063] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0066] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0067] Figure 3-Figure 6 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided in accordance with an embodiment of the present invention;

[0068] Figure 7 According to an embodiment of the present invention, Figure 2 A schematic diagram of the process included in S110;

[0069] Figures 8-12 According to an embodiment of the present invention, Figure 7 Cross-sectional diagram corresponding to each step in . DETAILED DESCRIPTION

[0070] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0071] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0072] In order to solve the problems of increased resistance between the source and drain of MOSFET devices, increased energy consumption, and increased temperature during device operation, the embodiments of the present invention provide the following technical solutions:

[0073] Figure 1 FIG. 1 is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to a first conductivity type and is located on the first surface 101, the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101, and extends along the surface of the first region to the first surface 101, the well region 103 includes a fourth surface 1031 away from the first surface 101 and a fourth surface 1031 connecting the fourth surface 1031 and the first region 104. A fifth surface 1032 of a surface 101; a two-dimensional conductive layer 200, located on the fifth surface 1032; a preset distance is set between the end of the two-dimensional conductive layer 200 close to the first surface 101 and the first surface 101; a voltage-resistant layer 30, located on the first surface 101, and located on the side of the two-dimensional conductive layer 200 away from the well region 103; a first insulating layer 201, located on the first surface 101; a gate 300, located on the side of the first insulating layer 201 away from the first surface 101; a source 400, located on the first surface 101; and a drain 500, located on the second surface 102.

[0074] In the embodiment of the present invention, Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through one or more epitaxial processes, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0075] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0076] The gate 300 may be made of polysilicon. The first insulating layer 201 is used to insulate the semiconductor body 100 from the gate 300. The first insulating layer 201 may be a gate oxide layer.

[0077] In an optional embodiment of the present invention, the dielectric constant of the material of the voltage-resistant layer 30 is greater than or equal to the dielectric constant of silicon oxide.

[0078] The voltage-withstanding layer 30 may be formed by depositing a high-dielectric-constant material between the drift region and the first surface 101. The high-dielectric-constant material includes, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide.

[0079] In an optional embodiment of the present invention, the voltage-resistant layer 30 includes at least one of silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide.

[0080] In an embodiment of the present invention, the semiconductor device further includes an interlayer dielectric layer 301. Interlayer dielectric layer 301 provides electrical isolation between gate 300 and source 400, preventing electron migration between different metal layers and preventing diffusion or penetration between substances. Interlayer dielectric layer 301 can be made of silicon dioxide. Interlayer dielectric layer 301 can be formed by plasma-enhanced chemical vapor deposition.

[0081] According to the technical solution of the embodiment of the present invention, when the first conductivity type is N-type, the two-dimensional conductive layer 200 includes a two-dimensional electron gas layer; when the first conductivity type is P-type, the two-dimensional conductive layer 200 includes a two-dimensional hole gas layer. When the device is turned on, carriers pass through the source 400, the first region 104, the well region 104, and then through the two-dimensional conductive layer 200, and then through the drift region to reach the drain 500, without passing through the JFET region on the side of the well region 104. Because the two-dimensional electron gas layer or the two-dimensional hole gas layer has a high carrier mobility, a low-resistance conductive channel can be provided between the first surface 101 and the drift region. Carriers can flow through this channel without being affected by the narrowing of the effective conductive area caused by the expansion of the depletion layer in the JFET structure. This solves the problems of increased resistance between the source and drain, increased energy consumption, and increased temperature during device operation in MOSFET devices, thereby reducing the on-resistance of the device. Furthermore, the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness. Due to its high conductivity and carrier mobility, it replaces the JFET region as the current channel. This eliminates the need to provide a JFET region with a sufficient lateral dimension X on one side of the well region 104 in the planar MOSFET device to ensure that the JFET region has a resistance that matches the on-current. Furthermore, by providing a voltage-resistant layer 30 between the drift region and the first surface, while ensuring the device's voltage resistance, the lateral dimension X of the semiconductor body on the side of the well region 104 can be reduced, thereby reducing the lateral dimension X of the semiconductor device. It should be noted that in this embodiment, the lateral dimension X refers to the dimension in a direction perpendicular to the first surface 101 and pointing toward the second surface 102.

[0082] It should be noted that the two-dimensional electron gas layer is typically a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperature conditions), due to differences in material properties at its heterojunction interface, a large concentration of two-dimensional electron gas is formed, achieving excellent electron mobility, which is far greater than the electron mobility of silicon, silicon carbide, and gallium nitride, far exceeding the carrier requirements of the device and significantly improving the carrier mobility of the device. In addition, the movement of electrons in the two-dimensional electron gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent electron mobility on the two-dimensional surface where the heterojunction interface is located. Correspondingly, the movement of holes in the two-dimensional hole gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent hole mobility on the two-dimensional surface where the heterojunction interface is located.

[0083] In an optional embodiment of the present invention, reference Figure 1The semiconductor body 100 includes a first semiconductor body 106 and a second semiconductor body 107; the second semiconductor body 107 is located on the first surface 101, and the first semiconductor body 106 is located on the second surface 102; the first semiconductor body 106 is provided with a groove 108, the groove 108 is located on the third surface 109 of the first semiconductor body 106 and extends into the first semiconductor body 106, and the third surface 109 and the second surface 102 are arranged opposite to each other; the two-dimensional conductive layer 200 is located on the sidewall of the groove 108; the voltage-resistant layer 30 is located in the groove 108, and the surface of the voltage-resistant layer 30 away from the first semiconductor body 106 is flush with the first surface 101; the first region 104 and the well region 103 are located in the second semiconductor body 107 and the first semiconductor body 106.

[0084] In the embodiment of the present invention, Figure 1 As shown, the first semiconductor body 106 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the first semiconductor body 106 may also include only the epitaxial layer 20. In other embodiments of the present invention, the first semiconductor body 106 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed by one or more epitaxial processes on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE). The second semiconductor body 107 can be formed by an epitaxial process. The groove 108 can be formed by photolithography and etching processes.

[0085] In an optional embodiment of the present invention, the second semiconductor body 107 can be formed by epitaxial growth on one side of the first semiconductor body 106, and then the second semiconductor body 107 in the groove 108 is removed, and finally a high dielectric constant material is deposited in the groove 108 to form a voltage-resistant layer 30.

[0086] In other optional embodiments of the present invention, an epitaxial growth process may be performed on one side of the first semiconductor body 106 and on the portion excluding the recess 108 to form the second semiconductor body 107. Subsequently, a high-k dielectric constant material may be deposited in the recess 108 to form the voltage-withstand layer 30. The high-k dielectric constant material includes, but is not limited to, silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide.

[0087] After forming the voltage-resistant layer 30, the first surface 101 can be subjected to chemical mechanical polishing (CMP) to remove silicon carbide surface defects, thereby reducing leakage caused by interface states, altering device capacitance, and increasing on-resistance. CMP can precisely control the polishing thickness of the film layer, avoiding the effects of instability caused by sacrificial oxidation processes.

[0088] In an optional embodiment of the present invention, reference Figure 1The two-dimensional conductive layer 200 includes a first gallium nitride layer 202 and a second gallium nitride layer 203; the first gallium nitride layer 202 is located on the fifth surface 1032; the second gallium nitride layer 203 is located on the side of the fifth surface 1032 away from the well region 103; the second gallium nitride layer 203 is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer 202 and the second gallium nitride layer 203.

[0089] The first gallium nitride layer 202 and the second gallium nitride layer 203 form a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperatures), differences in material properties form a high concentration of a two-dimensional electron gas or a two-dimensional hole gas at the heterojunction interface. This carrier mobility is significantly greater than that of silicon, silicon carbide, and gallium nitride, far exceeding the carrier mobility of the device. This significantly improves the device's carrier mobility and reduces its on-resistance. Taking an N-type MOSFET device as an example, the second gallium nitride layer 1032, made of magnesium gallium nitride or aluminum gallium nitride, is P-type doped. A space charge region is formed between it and the first conductivity type semiconductor body 100, preventing current from flowing from the source to the drain when the device is in the off state.

[0090] In an optional embodiment of the present invention, reference Figure 1 , the semiconductor body 100 includes a silicon carbide semiconductor body or a silicon nitride semiconductor body.

[0091] In an embodiment of the present invention, the semiconductor body 100 is made of silicon carbide. The semiconductor device is a silicon carbide MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of the semiconductor device. The semiconductor body 100 is also made of silicon nitride. The semiconductor device is a silicon nitride MOSFET semiconductor device. Silicon nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of the semiconductor device.

[0092] In an embodiment of the present invention, when the two-dimensional conductive layer 200 is a gallium nitride epitaxial layer and a doped gallium nitride epitaxial layer, the lattice matching between the gallium nitride epitaxial layer and the doped gallium nitride epitaxial layer is high when grown on silicon carbide via an epitaxial process. This reduces the difficulty of forming the first gallium nitride layer 202 via the epitaxial process, and also reduces the difficulty of forming the second semiconductor body 107 via the epitaxial process on the side of the second gallium nitride layer 203 away from the first gallium nitride layer 202. The second gallium nitride layer 203 is a gallium nitride layer of the second conductivity type and can form a space charge region with the first semiconductor body 106 of the first conductivity type, preventing leakage current from the source 400 to the drain 500, thereby reducing losses in the semiconductor device.

[0093] In an optional embodiment of the present invention, reference Figure 1 The second gallium nitride layer 203 includes magnesium gallium nitride or aluminum gallium nitride.

[0094] In an embodiment of the present invention, a gallium nitride epitaxial layer and a gallium nitride epitaxial layer doped with magnesium ions or aluminum ions can be sequentially grown in the groove 108 and the third surface 109 of the first semiconductor body 106, and then the formed gallium nitride epitaxial layer is etched, and a silicon carbide epitaxial layer is secondarily grown on the gallium nitride epitaxial layer to form a two-dimensional electron gas layer or a two-dimensional hole gas layer. Two-dimensional conductive layer 200.

[0095] In nanoelectronics and optoelectronics, in order to achieve specific quantum effects, the thickness of the heterojunction needs to be controlled within a relatively thin range. For example, in the heterojunction composed of a GaN epitaxial layer and a GaN magnesium epitaxial layer or a GaN aluminum epitaxial layer, when the thickness of the GaN magnesium epitaxial layer or the GaN aluminum epitaxial layer is between a few nanometers and tens of nanometers, electrons and holes will be confined to this very thin spatial region, thereby more effectively controlling the behavior of carriers. Therefore, the heterojunction composed of the GaN epitaxial layer and the GaN magnesium epitaxial layer or the GaN aluminum epitaxial layer has a relatively thin thickness and high conductivity.

[0096] In an optional embodiment of the present invention, reference Figure 1 The semiconductor body 100 further includes a second region 105 , which is set to the second conductivity type and is located on the first surface 101 ; the second region 105 contacts the first region 104 , and the ion concentration of the second region 105 is greater than the ion concentration of the well region 103 .

[0097] In the embodiment of the present invention, the conductivity type of the second region 105 is the same as that of the well region 103, and both are set to the second conductivity type. For an N-type MOSFET, the second region 105 can be a P+ doped region, whose ion concentration is greater than that of the well region 103. The second region 105 can form a good ohmic contact with the source 400.

[0098] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0099] S110. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other; the semiconductor body also includes a well region and a first area, the first area is set to a first conductive type and is located on the first surface, the well region is set to a second conductive type and is located on a side of the first area away from the first surface, and extends along the surface of the first area to the first surface, the well region includes a fourth surface away from the first surface and a fifth surface connecting the fourth surface and the first surface; a two-dimensional conductive layer is formed on the fifth surface; a preset distance is set between an end of the two-dimensional conductive layer close to the first surface and the first surface; a voltage-resistant layer is formed on the first surface.

[0100] refer to Figure 3 , providing a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to a first conductive type and is located on the first surface 101, the well region 103 is set to a second conductive type and is located on a side of the first region 104 away from the first surface 101, and extends along the surface of the first region to the first surface 101, the well region 103 includes a fourth surface 1031 away from the first surface 101 and a fifth surface 1032 connecting the fourth surface 1031 and the first surface 101; a two-dimensional conductive layer 200 is formed on the fifth surface 1032; a preset distance is set between the end of the two-dimensional conductive layer 200 close to the first surface 101 and the first surface 101; a voltage-resistant layer 30 is formed on the first surface 101.

[0101] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0102] like Figure 3As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through one or more epitaxial processes, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0103] In an optional embodiment of the present invention, S110, providing a semiconductor body also includes: providing a semiconductor body including a second region; the second region is set to a second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0104] refer to Figure 3 , providing a semiconductor body 100 including a second region 105; the second region 105 is set to a second conductivity type and is located on the first surface 101; the second region 105 is in contact with the first region 104, and the ion concentration of the second region 105 is greater than the ion concentration of the well region 103.

[0105] In the embodiment of the present invention, the conductivity type of the second region 105 is the same as that of the well region 103, and both are set to the second conductivity type. For an N-type MOSFET, the second region 105 can be a P+ doped region, whose ion concentration is greater than that of the well region 103. The second region 105 can form a good ohmic contact with the source.

[0106] S120 , forming a first insulating layer on the first surface.

[0107] refer to Figure 4 A first insulating layer 201 is formed on the first surface 101 by a high temperature oxidation or deposition process. The first insulating layer 201 may be a gate oxide layer.

[0108] S130 , forming a gate on a side of the first insulating layer away from the first surface.

[0109] refer to Figure 5 A gate 300 is formed on a side of the first insulating layer 201 away from the first surface 101. The gate 300 may be made of polysilicon. The first insulating layer 201 is used to insulate the semiconductor body 100 from the gate 300.

[0110] S140 , forming a source electrode on the first surface.

[0111] refer to Figure 6, metal is deposited on the first surface 101 to form the source electrode 400. Before forming the source electrode 400, an interlayer dielectric layer 301 is formed on the side of the gate 300 away from the semiconductor body 100. The interlayer dielectric layer 301 electrically isolates the gate 300 from the source electrode 400, preventing electron migration between different metal layers and diffusion or penetration between substances. The material of the interlayer dielectric layer 301 can be silicon dioxide. The interlayer dielectric layer 301 can be formed by plasma-enhanced chemical vapor deposition.

[0112] S150 , forming a drain on the second surface.

[0113] refer to Figure 1 , metal is deposited on the second surface 102 to form a drain 500. The deposited metal may be titanium (Ti), nickel (Ni) or silver (Ag).

[0114] Before forming the drain 500 on the second surface 102, the second surface 102 is thinned. Specifically, thinning the second surface 102 before forming the drain 500 can reduce the on-resistance of the semiconductor device and improve the quality of the formed drain 500.

[0115] According to the technical solution of the embodiment of the present invention, when the first conductivity type is N-type, the formed two-dimensional conductive layer 200 includes a two-dimensional electron gas layer; when the first conductivity type is P-type, the formed two-dimensional conductive layer 200 includes a two-dimensional hole gas layer. When the device is turned on, carriers pass through the source 400, the first region 104, the well region 104, and then through the two-dimensional conductive layer 200, and then through the drift region to reach the drain 500, without passing through the JFET region on the side of the well region 104. Because the two-dimensional electron gas layer or the two-dimensional hole gas layer has a high carrier mobility, a low-resistance conductive channel can be provided between the first surface 101 and the drift region. Carriers can flow through this channel without being affected by the narrowing of the effective conductive area caused by the expansion of the depletion layer in the JFET structure. This solves the problems of increased resistance between the source and drain in MOSFET devices, increased energy consumption, and increased temperature during device operation, thereby reducing the on-resistance of the device. Furthermore, the two-dimensional electron gas layer or the two-dimensional hole gas layer has a very thin thickness. Due to its high conductivity and carrier mobility, it replaces the JFET region as the current channel. This eliminates the need to provide a JFET region with a sufficient lateral dimension X on one side of the well region 104 in the planar MOSFET device to ensure that the JFET region has a resistance that matches the on-current. Furthermore, by providing a voltage-resistant layer 30 between the drift region and the first surface, while ensuring the device's voltage resistance, the lateral dimension X of the semiconductor body on the side of the well region 104 can be reduced, thereby reducing the lateral dimension X of the formed semiconductor device. It should be noted that in this embodiment, the lateral dimension X refers to the dimension in a direction perpendicular to the first surface 101 and pointing toward the second surface 102.

[0116] It should be noted that the two-dimensional electron gas layer is typically a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperature conditions), due to differences in material properties at its heterojunction interface, a large concentration of two-dimensional electron gas is formed, achieving excellent electron mobility, which is far greater than the electron mobility of silicon, silicon carbide, and gallium nitride, far exceeding the carrier requirements of the device and significantly improving the carrier mobility of the device. In addition, the movement of electrons in the two-dimensional electron gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent electron mobility on the two-dimensional surface where the heterojunction interface is located. Correspondingly, the movement of holes in the two-dimensional hole gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent hole mobility on the two-dimensional surface where the heterojunction interface is located.

[0117] Figure 7 According to an embodiment of the present invention, Figure 2 The flow chart of S110 is shown in FIG. Figure 7 As shown, in an optional embodiment of the present invention, S110, providing a semiconductor body includes:

[0118] S1101. Provide a first semiconductor body.

[0119] refer to Figure 8 , providing a first semiconductor body 106. The first semiconductor body 106 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the first semiconductor body 106 may also include only the epitaxial layer 20. In other embodiments of the present invention, the first semiconductor body 106 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed by one or more epitaxial processes on the basis of the substrate 10, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes. The first semiconductor body 106 also includes a third surface 109 and a second surface 102. The second surface 102 serves as the second surface 102 of the semiconductor body 100.

[0120] S1102 , forming a groove in the first semiconductor body, where the groove is located on the third surface of the first semiconductor body and extends into the first semiconductor body, and the third surface and the second surface are arranged opposite to each other.

[0121] refer to Figure 9 A groove 108 is formed in the first semiconductor body 106. The groove 108 is located on the third surface 109 of the first semiconductor body 106 and extends into the first semiconductor body 106. The third surface 109 is opposite to the second surface 102. The groove 108 can be formed by photolithography and etching processes.

[0122] S1103 , forming a two-dimensional conductive layer on the sidewall of the groove.

[0123] refer to Figure 1 , a two-dimensional conductive layer 200 is formed on the sidewall of the groove 108 .

[0124] In an optional embodiment of the present invention, S1103, forming a two-dimensional conductive layer on the sidewall of the groove includes: forming a two-dimensional conductive layer on the third surface and the sidewall of the groove; and removing the two-dimensional conductive layer on the third surface.

[0125] refer to Figure 10 A two-dimensional conductive layer 200 is formed on the third surface 109 and the sidewalls of the groove 108. When the first conductivity type is N-type, the two-dimensional conductive layer 200 includes a two-dimensional electron gas layer; when the first conductivity type is P-type, the two-dimensional conductive layer 200 includes a two-dimensional hole gas layer.

[0126] refer to Figure 11 , the two-dimensional conductive layer 200 located on the third surface 109 is removed through an etching process.

[0127] In an optional embodiment of the present invention, S1103, forming a two-dimensional conductive layer on the sidewall of the groove also includes: forming a first gallium nitride layer on the sidewall of the groove; forming a second gallium nitride layer on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

[0128] refer to Figure 1 and Figure 11 A first gallium nitride layer 202 is formed on the sidewalls of the recess 108; a second gallium nitride layer 203 is formed on the side of the first gallium nitride layer 202 away from the well region 103. The second gallium nitride layer 203 is a doped gallium nitride material. A two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer 202 and the second gallium nitride layer 203. Because the two-dimensional electron gas or the two-dimensional hole gas has high carrier mobility, it can provide a low-resistance conductive channel between the first surface 101 and the drift region. Carriers can flow through this channel without being affected by the narrowing of the effective conductive area caused by the expansion of the depletion layer in the JFET structure. The formation of the two-dimensional conductive layer 200 including the two-dimensional electron gas layer or the two-dimensional hole gas layer can increase the area for current flow, allowing current to flow more smoothly from the source 400 to the drain 500, further reducing the resistance between the source 400 and the drain 500.

[0129] The first gallium nitride layer 202 and the second gallium nitride layer 203 form a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperatures), differences in material properties form a high concentration of a two-dimensional electron gas or a two-dimensional hole gas at the heterojunction interface. This carrier mobility is significantly greater than that of silicon, silicon carbide, and gallium nitride, far exceeding the carrier mobility of the device. This significantly improves the device's carrier mobility and reduces its on-resistance. Taking an N-type MOSFET device as an example, the second gallium nitride layer 1032, made of magnesium gallium nitride or aluminum gallium nitride, is P-type doped. A space charge region is formed between it and the first conductivity type semiconductor body 100, preventing current from flowing from the source to the drain when the device is in the off state.

[0130] S1104. Form a second semiconductor body on one side of the first semiconductor body, the second semiconductor body covering the two-dimensional conductive layer, the surface of the second semiconductor body away from the first semiconductor body being the first surface, and the surface of the first semiconductor body away from the second semiconductor body being the second surface.

[0131] refer to Figure 1 A second semiconductor body 107 is formed on one side of the first semiconductor body 106 , and the second semiconductor body 107 covers the two-dimensional conductive layer 200 . The surface of the second semiconductor body 107 away from the first semiconductor body 106 is the first surface 101 , and the surface of the first semiconductor body 106 away from the second semiconductor body 107 is the second surface 102 .

[0132] S1105 , forming a voltage-resistant layer in the groove, wherein the voltage-resistant layer is away from a surface of the first semiconductor body and flush with the first surface.

[0133] refer to Figure 1 and Figure 12 A voltage-resistant layer 30 is formed in the groove 108 . The surface of the voltage-resistant layer 30 away from the first semiconductor body 106 is flush with the first surface 101 .

[0134] In an optional embodiment of the present invention, S1105, forming a voltage-resistant layer in the groove, includes: forming a voltage-resistant layer including at least one of silicon oxide, silicon nitride, aluminum oxide and zirconium oxide in the groove; the voltage-resistant layer is away from the surface of the first semiconductor body and is flush with the first surface.

[0135] A voltage-resistant layer 30 is formed by depositing at least one high-dielectric-constant material selected from silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide. Forming the voltage-resistant layer 30 within the recess 108 allows the size of the semiconductor body on one side of the well region to be reduced while ensuring the device's voltage resistance, thereby reducing the size of the semiconductor device.

[0136] S1106 , forming a first region and a well region in the second semiconductor body and the first semiconductor body.

[0137] refer to Figure 1 、 Figure 12 and Figure 3 A first region 104 and a well region 103 are formed in the second semiconductor body 107 and the first semiconductor body 106. The first region 104 and the well region 103 are formed by ion implantation followed by high temperature annealing.

[0138] Optionally, before the second semiconductor body and the first semiconductor body form the first region and the well region, the method further includes: performing a planarization process on a surface of the second semiconductor body away from the first semiconductor body.

[0139] refer to Figure 12 , the surface of the second semiconductor body 107 facing away from the first semiconductor body 106 is planarized. For example, chemical mechanical polishing (CMP) can replace the sacrificial oxidation process to remove silicon carbide surface defects, reducing leakage caused by interface states, changes in device capacitance, and increased on-resistance. CMP can precisely control the polishing thickness of the film layer, avoiding the effects of instability caused by the sacrificial oxidation process.

[0140] Optionally, S110, providing a semiconductor body further includes:

[0141] A semiconductor body is provided which includes a silicon carbide semiconductor body or a silicon nitride semiconductor body.

[0142] Specifically, refer to Figure 1 The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a silicon nitride semiconductor body, and the MOSFET semiconductor device is a silicon nitride MOSFET semiconductor device.

[0143] Silicon carbide MOSFET semiconductor devices or silicon nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0144] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0145] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0146] Therefore, the power conversion circuit includes the beneficial effects of the semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0147] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0148] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0149] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0150] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, the well region being configured as a second conductivity type and located on a side of the first region away from the first surface and extending along a surface of the first region to the first surface, the well region comprising a fourth surface away from the first surface and a fifth surface connecting the fourth surface and the first surface; a two-dimensional conductive layer, located on the fifth surface; a preset distance is set between an end of the two-dimensional conductive layer close to the first surface and the first surface; a voltage-resistant layer, located on the first surface and on a side of the two-dimensional conductive layer away from the well region; a first insulating layer, located on the first surface; a gate, located on a side of the first insulating layer away from the first surface; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The semiconductor body includes a first semiconductor body and a second semiconductor body; The second semiconductor body is located on the first surface, and the first semiconductor body is located on the second surface; The first semiconductor body is provided with a groove, the groove is located on the third surface of the first semiconductor body and extends into the first semiconductor body, and the third surface and the second surface are arranged opposite to each other; The two-dimensional conductive layer is located on the sidewall of the groove; The voltage-resistant layer is located in the groove, and the surface of the voltage-resistant layer is away from the first semiconductor body and is flush with the first surface; The first region and the well region are located in the second semiconductor body and the first semiconductor body.

3. The semiconductor device according to claim 1, wherein The two-dimensional conductive layer includes a first gallium nitride layer and a second gallium nitride layer; The first gallium nitride layer is located on the fifth surface; The second gallium nitride layer is located on a side of the fifth surface away from the well region; The second gallium nitride layer is a doped gallium nitride material, and two-dimensional electron gas or two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

4. The semiconductor device according to claim 3, wherein The semiconductor body includes a silicon carbide semiconductor body or a silicon nitride semiconductor body.

5. The semiconductor device according to claim 3, wherein The second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride. The semiconductor device according to claim 1 , wherein: The dielectric constant of the material of the voltage-resistant layer is greater than or equal to the dielectric constant of silicon oxide.

7. The semiconductor device according to claim 6, wherein: The voltage-resistant layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and zirconium oxide.

8. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region, which is set to a second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

9. The semiconductor device according to claim 1, wherein The first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

10. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface; the well region being configured as a second conductivity type and located on a side of the first region away from the first surface, and extending along a surface of the first region to the first surface; the well region comprising a fourth surface away from the first surface and a fifth surface connecting the fourth surface and the first surface; a two-dimensional conductive layer being formed on the fifth surface; a preset distance being provided between an end of the two-dimensional conductive layer close to the first surface and the first surface; and a voltage-resistant layer being formed on the first surface. forming a first insulating layer on the first surface; forming a gate on a side of the first insulating layer away from the first surface; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The semiconductor body provided includes: providing a first semiconductor body; forming a groove in the first semiconductor body, the groove being located on a third surface of the first semiconductor body and extending into the first semiconductor body, the third surface being arranged opposite to the second surface; forming a two-dimensional conductive layer on the sidewall of the groove; forming a second semiconductor body on one side of the first semiconductor body, the second semiconductor body covering the two-dimensional conductive layer, the surface of the second semiconductor body away from the first semiconductor body being the first surface, and the surface of the first semiconductor body away from the second semiconductor body being the second surface; forming a voltage-resistant layer in the groove, wherein the voltage-resistant layer is away from a surface of the first semiconductor body and is flush with the first surface; A first region and a well region are formed in the second semiconductor body and the first semiconductor body.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: Forming a two-dimensional conductive layer on the sidewall of the groove includes: forming a two-dimensional conductive layer on the third surface and the sidewalls of the groove; The two-dimensional conductive layer located on the third surface is removed.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: Before the second semiconductor body and the first semiconductor body form the first region and the well region, the method further includes: A planarization process is performed on a surface of the second semiconductor body away from the first semiconductor body.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: Forming a two-dimensional conductive layer on the sidewall of the groove includes: forming a first gallium nitride layer on a sidewall of the groove; A second gallium nitride layer is formed on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer.

15. The method for manufacturing a semiconductor device according to claim 11, wherein: forming a pressure-resistant layer in the groove, comprising: A voltage-resistant layer comprising at least one of silicon oxide, silicon nitride, aluminum oxide and zirconium oxide is formed in the groove; the voltage-resistant layer is away from a surface of the first semiconductor body and flush with the first surface.

16. The method for manufacturing a semiconductor device according to claim 10, wherein: Providing a semiconductor body also includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a silicon nitride semiconductor body.

17. The method for manufacturing a semiconductor device according to claim 10, wherein: Providing a semiconductor body also includes: A semiconductor body is provided, comprising a second region; the second region is set to a second conductivity type and is located on the first surface; the second region contacts the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

18. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 9, wherein the substrate is used to support the semiconductor device.

19. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is electrically connected to the circuit board.

20. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 19, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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