Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body further comprises a well region and a first region; the first surface is provided with a groove, and the groove extends from the first surface to the well region; the groove comprises a first sub-groove and a second sub-groove which are communicated with each other, and the first sub-groove is located between the well region and the first surface; the two-dimensional conductive layer is located in the first sub-groove; the insulating layer comprises a first sub-insulating part and a second sub-insulating part which are connected, the first sub-insulating part is located in the second sub-groove, and the second sub-insulating part is located on the first surface; the grid electrode is located on the side, away from the semiconductor body, of the second sub-insulating part, and the insulating layer is used for insulating the semiconductor body and the grid electrode. According to the embodiment of the invention, the channel carrier mobility of the device can be improved, and the on-resistance can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based on third-generation wide-bandgap semiconductors such as silicon carbide or gallium nitride has the characteristics of large critical breakdown electric field strength, high thermal conductivity, large bandgap width and high electron saturation drift velocity, making third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride a research hotspot for power semiconductor devices. In high-power applications such as high-speed railways, hybrid vehicles, and intelligent high-voltage direct current transmission, silicon carbide devices are given high expectations.

[0003] Currently, MOSFET semiconductor devices including planar gate structures often suffer from low channel carrier mobility, resulting in a large on-resistance of the semiconductor device. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to improve the channel carrier mobility of the semiconductor device and reduce the on-resistance.

[0005] In a first aspect, a semiconductor device is provided, comprising:

[0006] A semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, the well region being of a second conductivity type and located on a side of the first region away from the first surface; a groove being provided on the first surface, the groove extending from the first surface to the well region; the groove comprising a first sub-groove and a second sub-groove connected to each other, the first sub-groove being located on a side of the second sub-groove away from the first surface;

[0007] a two-dimensional conductive layer, located in the first sub-groove;

[0008] The insulating layer includes a first sub-insulating portion and a second sub-insulating portion connected to each other, wherein the first sub-insulating portion is located in the second sub-groove, and the second sub-insulating portion is located on the first surface;

[0009] a gate, located on a side of the second sub-insulating portion away from the semiconductor body, wherein the insulating layer is used to insulate the semiconductor body from the gate;

[0010] a source electrode, located on the first surface;

[0011] The drain is located on the second surface.

[0012] Optionally, the two-dimensional conductive layer includes a first gallium nitride layer and a second gallium nitride layer;

[0013] The first gallium nitride layer is located in the first sub-groove;

[0014] The second gallium nitride layer is located on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer;

[0015] Wherein, the first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

[0016] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride body.

[0017] Optionally, the second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

[0018] Optionally, the semiconductor body further includes a second region, which is set to a second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0019] In a second aspect, a method for manufacturing a semiconductor device is provided, comprising:

[0020] A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the first surface is provided with a groove, the groove extending from the first surface into the semiconductor body; the groove includes a first sub-groove and a second sub-groove connected to each other, the first sub-groove being located between a well region and the first surface; a two-dimensional conductive layer is provided in the first sub-groove;

[0021] forming a well region and a first region in the semiconductor body, wherein the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region away from the first surface;

[0022] forming a first sub-insulating portion in the second sub-groove;

[0023] forming a second sub-insulating portion on the first surface, wherein the first sub-insulating portion and the second sub-insulating portion are connected to form an insulating layer;

[0024] forming a gate on a side of the second sub-insulating portion away from the semiconductor body, wherein the insulating layer is used to insulate the semiconductor body from the gate;

[0025] forming a source electrode on the first surface;

[0026] A drain electrode is formed on the second surface.

[0027] Optionally, providing the semiconductor body includes:

[0028] Providing a semiconductor body; the semiconductor body comprising a first transition surface and a second transition surface disposed opposite to each other;

[0029] A groove is formed on the transition first surface; the groove extends from the transition first surface into the semiconductor body; the groove includes a first sub-groove and a second sub-groove that are connected, and the first sub-groove is located between the semiconductor body and the transition first surface;

[0030] forming a two-dimensional conductive layer in the first sub-groove and on the transition first surface;

[0031] The transition first surface is planarized, wherein the surface opposite to the second surface of the semiconductor body is the first surface, and after a first sub-insulating portion is formed in the second sub-groove, the surface of the first sub-insulating portion away from the two-dimensional conductive layer is flush with the first surface.

[0032] Optionally, performing a planarization process on the transition first surface includes:

[0033] removing the two-dimensional conductive layer located on the transition first surface;

[0034] The transition first surface is planarized.

[0035] Optionally, the two-dimensional conductive layer includes a first gallium nitride layer and a second gallium nitride layer; and forming the two-dimensional conductive layer in the first sub-groove and on the transition first surface includes:

[0036] forming a first gallium nitride layer in the first sub-recess and on the transition first surface;

[0037] forming a second gallium nitride layer on a side of the first gallium nitride layer away from the semiconductor body; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer;

[0038] Wherein, the first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

[0039] Optionally, providing the semiconductor body includes:

[0040] A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride body.

[0041] Optionally, forming a second gallium nitride layer on a side of the first gallium nitride layer away from the semiconductor body includes:

[0042] A second gallium nitride layer including magnesium gallium nitride or aluminum gallium nitride is formed on a side of the first gallium nitride layer away from the semiconductor body.

[0043] Optionally, when the semiconductor body forms the well region and the first region, the method further includes:

[0044] A second region is formed in the semiconductor body. The second region is set to a second conductivity type and is located on the first surface. The second region contacts the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0045] In a third aspect, a power module is provided, comprising a substrate and the semiconductor device according to any embodiment of the first aspect, wherein the substrate is used to support the semiconductor device.

[0046] In a fourth aspect, a power conversion circuit is provided, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0047] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the first aspect, and the semiconductor device is electrically connected to the circuit board.

[0048] In a fifth aspect, a vehicle is provided, comprising a load and a power conversion circuit as described in the embodiment of the fourth aspect, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0049] In a semiconductor device provided by an embodiment of the present invention, a first surface of a semiconductor body is provided with a groove extending from the first surface to a well region. The groove includes a first sub-groove and a second sub-groove arranged in communication, wherein a two-dimensional conductive layer is provided in the first sub-groove and contacts the first region. Depending on the conductivity type of the MOSFET semiconductor device, the two-dimensional conductive layer includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Because the two-dimensional electron gas layer or the two-dimensional hole gas layer is very thin and has high conductivity and carrier mobility, the carrier mobility of the carriers in the two-dimensional conductive layer is greatly improved as the carriers pass through the source electrode, the first region, enter the two-dimensional conductive layer, and then pass through the semiconductor body to the drain electrode, thereby reducing the on-resistance of the device without increasing the thickness of the device. In addition, a first sub-insulating portion is provided in the second sub-groove, which is connected to the second sub-insulating portion provided on the first surface to form an insulating layer to insulate the gate from the semiconductor body. The first sub-insulating portion extending into the well region increases the thickness of the insulating layer between the gate and the channel region of the device, which is beneficial for increasing the threshold voltage of the semiconductor device, thereby improving the device's withstand voltage performance and enhancing product competitiveness.

[0050] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;

[0053] Figure 2 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0054] Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0055] Figures 4 to 6 for Figure 3 Schematic diagram of the structure corresponding to the relevant steps in the figure;

[0056] Figure 7 yes Figure 3 The flowchart included in S110;

[0057] Figures 8 and 9 yes Figure 7 Structural diagram corresponding to each relevant step in;

[0058] Figure 10 yes Figure 7 The flowchart of step S113 is included in the following;

[0059] Figure 11 yes Figure 7 The flowchart of step S114 is included in the following;

[0060] Figure 12 yes Figure 7 Schematic diagram of the structure corresponding to step S1141. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0063] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided by the prior art. Figure 1As shown, the semiconductor device includes a semiconductor body 100 having a first surface 101 and a second surface 102 disposed opposite each other. The semiconductor body 100 further includes a well region 103, a first region 104, and a second region 105. The conductivity type of the first region 104 is opposite to that of the well region 103, and the conductivity type of the second region 105 is the same as that of the well region 103. The ion concentration of the second region 105 is greater than that of the well region 103. An insulating layer 106 and a gate 107 are disposed on a side of the first surface 101 away from the semiconductor body 100. The insulating layer 106 is used to insulate the gate 107 from the semiconductor body 100. A spacer insulating layer 108 and a source electrode 109 are also disposed on a side of the first surface 101 away from the semiconductor body 100. A drain electrode 110 is disposed on the second surface 102 of the semiconductor body 100. The spacer insulating layer 108 is used to insulate the gate 107 from the source electrode 109.

[0064] for Figure 1 The planar MOSFET semiconductor device structure shown, taking N-type MOSFET as an example, has an operating principle of applying a positive voltage to the source 109 and a negative voltage to the gate 107; when the threshold voltage is reached, an inversion layer is formed in the portion of the well region 103 near the first surface 101, so that the on-current can flow through the source 109, through the first region 104, the inversion layer in the well region 103, and the drift layer of the semiconductor body 100, and finally flow to the drain 110. At this time, the semiconductor device is in the on state. However, due to the high temperature, high dose, and high energy ion implantation performed in the preparation of the well region 103, the first region 104, etc., the lattice damage to the semiconductor body 100 is caused, and the prepared insulating layer 106 may also have defects. Therefore, the semiconductor device often has a large interface state and low channel carrier mobility, resulting in a large on-resistance of the semiconductor device.

[0065] In order to improve the channel carrier mobility of semiconductor devices and reduce the on-resistance, the embodiments of the present invention provide the following technical solutions:

[0066] Figure 2 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention. Figure 2 As shown, the semiconductor device includes:

[0067] A semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite each other. The semiconductor body 100 further includes a well region 104 and a first region 105. The first region 105 is configured as a first conductivity type and is located on the first surface 101. The well region 104 is configured as a second conductivity type and is located on a side of the first region 105 away from the first surface 101. A groove T1 is provided on the first surface 101. The groove T1 extends from the first surface 101 to the well region 104. The groove T1 includes a first sub-groove T11 and a second sub-groove T12 that are connected to each other. The first sub-groove T11 is located on a side of the second sub-groove T12 away from the first surface 101.

[0068] The two-dimensional conductive layer 103 is located in the first sub-groove T11;

[0069] The insulating layer 106 includes a first sub-insulating portion 1061 and a second sub-insulating portion 1062 connected to each other, wherein the first sub-insulating portion 1061 is located in the second sub-groove T12 and the second sub-insulating portion 1062 is located on the first surface 101 ;

[0070] The gate 107 is located on a side of the second sub-insulating portion 1062 away from the semiconductor body 100 . The insulating layer 106 is used to insulate the semiconductor body 100 from the gate 107 .

[0071] a source electrode 108 , located on the first surface 101 ;

[0072] The drain 110 is located on the second surface 102 .

[0073] For example, see Figure 2 The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0074] Specifically, a groove T1 extending from the first surface 101 to the well region 104 is provided at a position on the first surface 101 of the semiconductor body 100 corresponding to the well region 104. The groove T1 includes a first sub-groove T11 and a second sub-groove T12 that are connected to each other. The first sub-groove T11 is located on a side of the well region 104 close to the first surface 101, and the second sub-groove T12 is located on a side of the first sub-groove T11 close to the first surface 101. A two-dimensional conductive layer 103 is provided in the first sub-groove T11, and the two-dimensional conductive layer 103 is away from the surface of the semiconductor body 100 and is flush with the interface surface between the first sub-groove T11 and the second sub-groove T12, that is, the two-dimensional conductive layer 103 completely fills the first sub-groove T11. Because the two-dimensional conductive layer 103 is very thin and has high conductivity and carrier mobility, the carrier mobility in the two-dimensional conductive layer 103 is greatly improved as the carriers pass through the source 108 and the first region 105 into the two-dimensional conductive layer 103, and then through the semiconductor body 100 to the drain 110. This reduces the on-resistance of the device without increasing the thickness of the semiconductor device. A spacer insulating layer 109 is also provided between the source 108 and the gate 107 to insulate the source 108 and the gate 107.

[0075] A first sub-insulating portion 1061 is provided in the second sub-recess T12, and the first sub-insulating portion 1061 completely fills the second sub-recess T12. The surface of the first sub-insulating portion 1061 away from the semiconductor body 100 is flush with the first surface 101. A second sub-insulating portion 1062 is provided on the first surface 101 and connected to the first sub-insulating portion 1061 to form an insulating layer 106, thereby insulating the gate 107 from the semiconductor body 100. Compared to the related art in which the insulating layer is provided only on the side away from the semiconductor body from the first surface, the embodiment of the present invention provides an additional first sub-insulating portion 1061 in the well region 104, which is connected to the second sub-insulating portion 1062 provided on the first surface 101 to form an insulating layer 106. This increases the thickness of the insulating layer between the gates in the channel region of the MOSFET semiconductor device, which is beneficial for increasing the threshold voltage of the semiconductor device, thereby improving the device's withstand voltage performance and enhancing product competitiveness.

[0076] In a semiconductor device provided by an embodiment of the present invention, a first surface 101 of a semiconductor body 100 is provided with a groove T1, which extends from the first surface 101 to the well region 104. The groove T1 includes a first sub-groove T11 and a second sub-groove T12, which are connected to each other. The first sub-groove T11 contains a two-dimensional conductive layer 103, which contacts the first region 105. Because the two-dimensional conductive layer 103 is very thin and has high conductivity and carrier mobility, the carrier mobility of the carriers in the two-dimensional conductive layer 103 is greatly improved as the carriers pass through the source 108 and the first region 105 to enter the two-dimensional conductive layer 103, and then pass through the semiconductor body 100 to reach the drain 110. This reduces the on-resistance of the device without increasing the thickness of the device. In addition, a first sub-insulating portion 1061 is provided in the second sub-groove T12, which connects to the second sub-insulating portion 1062 provided on the first surface 101 to form an insulating layer 106, thereby insulating the gate 107 from the semiconductor body 100. The first sub-insulating portion 1061 is extended into the well region 104 , thereby increasing the thickness of the insulating layer between the gates in the device channel region, which is beneficial to increasing the threshold voltage of the semiconductor device, thereby improving the device's withstand voltage performance and enhancing product competitiveness.

[0077] Optionally, based on the above embodiment, continue to refer to Figure 2 The two-dimensional conductive layer 103 includes a first gallium nitride layer 1031 and a second gallium nitride layer 1032 .

[0078] The first gallium nitride layer 1031 is located in the first sub-recess T11;

[0079] The second gallium nitride layer 1032 is located on a side of the first gallium nitride layer 1031 away from the well region 104. The second gallium nitride layer 1032 is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer 1031 and the second gallium nitride layer 1032. Wherein, the first conductivity type is N-type, and the two-dimensional conductive layer 103 includes a two-dimensional electron gas layer; alternatively, the first conductivity type is P-type, and the two-dimensional conductive layer 103 includes a two-dimensional hole gas layer.

[0080] Optionally, semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device; alternatively, semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0081] The two-dimensional conductive layer 103 includes a first gallium nitride layer 1031 and a second gallium nitride layer 1032. The first gallium nitride layer 1031 includes intrinsic gallium nitride, and the second gallium nitride layer 1032 includes magnesium gallium nitride or aluminum gallium nitride. The first gallium nitride layer 1031 and the second gallium nitride layer 1032 are stacked to form a heterojunction semiconductor layer. Under specific conditions (such as a specific electric field and a specific temperature), due to the difference in material properties, a large concentration of two-dimensional electron gas or two-dimensional hole gas is formed at the heterojunction interface. The carrier mobility of these two-dimensional electron gas or two-dimensional hole gas is much greater than that of silicon, silicon carbide, and gallium nitride, far exceeding the carrier mobility requirements of the device, significantly improving the device's carrier mobility and reducing the device's on-resistance. Depending on the conductivity type of the MOSFET device, the two-dimensional conductive layer 103 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. For example, for an N-type MOSFET semiconductor device, the first conductivity type is N-type, the carriers are electrons, and the two-dimensional conductive layer 103 formed includes a two-dimensional electron gas layer. For a P-type MOSFET semiconductor device, the first conductivity type is P-type, the carriers are holes, and the two-dimensional conductive layer 103 formed includes a two-dimensional hole gas layer. For example, in an N-type MOSFET device, the second gallium nitride layer 1032, which is P-type doped with magnesium gallium nitride or aluminum gallium nitride, can form a space charge region between it and the semiconductor body 100 of the first conductivity type. When the device is in the non-conducting state, it can prevent current from flowing from the source to the drain.

[0082] It should be noted that the two-dimensional electron gas layer is typically a heterojunction semiconductor layer. Under specific conditions (such as specific electric fields and specific temperature conditions), due to differences in material properties at its heterojunction interface, a large concentration of two-dimensional electron gas is formed, achieving excellent electron mobility, which is far greater than the electron mobility of silicon, silicon carbide, and gallium nitride, far exceeding the carrier requirements of the device and significantly improving the carrier mobility of the device. Moreover, the movement of electrons in the two-dimensional electron gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent electron mobility on the two-dimensional surface where the heterojunction interface is located. Correspondingly, the movement of holes in the two-dimensional hole gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent hole mobility on the two-dimensional surface where the heterojunction interface is located.

[0083] Optionally, based on the above embodiments, continue to refer to Figure 2 The semiconductor body 100 further includes a second region 112 , which is set to the second conductivity type and is located on the first surface 101 ; the second region 112 contacts the first region 105 , and the ion concentration of the second region 112 is greater than the ion concentration of the well region 104 .

[0084] Specifically, the conductivity type of the second region 112 is opposite to that of the first region 105. For example, taking an N-type MOSFET semiconductor device as an example, if the first conductivity type is N-type, the second conductivity type is P-type, and the second region 112 includes a P+ doped region. The ion concentration of the second region 112 is greater than the ion concentration of the well region 104. The second region 112 is provided to form a better ohmic contact with the source 108.

[0085] An embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 3 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figures 4 to 6 for Figure 3 The structural diagram corresponding to the relevant steps in Figures 2 to 6 The method for manufacturing the semiconductor device specifically comprises the following steps:

[0086] S110. Provide a semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other; the first surface is provided with a groove, and the groove extends from the first surface into the semiconductor body; the groove includes a first sub-groove and a second sub-groove that are connected, and the first sub-groove is located between the well region and the first surface; a two-dimensional conductive layer is provided in the first sub-groove.

[0087] Specifically, see Figure 4 The semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; a groove T1 is provided on the first surface 101, and the groove T1 extends from the first surface 101 to the semiconductor body 100; the groove T1 includes a first sub-groove T11 and a second sub-groove T12 that are connected, and the first sub-groove T11 is located between the well region 104 and the first surface 101; a two-dimensional conductive layer 103 is provided in the first sub-groove T11.

[0088] For example, the semiconductor body 100 may include a substrate 10 and an epitaxial layer 20. A recess T1 is formed by etching from the first surface 101 into the interior of the semiconductor body 100, wherein the recess T1 includes a first sub-recess T11 and a second sub-recess T12, the second sub-recess T12 being located between the first sub-recess T11 and the first surface 101, and the first sub-recess T11 and the second sub-recess T12 being connected. A two-dimensional conductive layer 103 is epitaxially grown in the first sub-recess T11, so that the two-dimensional conductive layer 103 completely fills the recess T1, i.e., the two-dimensional conductive layer 103 is away from the surface of the semiconductor device 100 and is flush with the interface surface between the first sub-recess T11 and the second sub-recess T12.

[0089] S120 , forming a well region and a first region in the semiconductor body, wherein the first region is set to be of the first conductivity type and is located on the first surface, and the well region is set to be of the second conductivity type and is located on a side of the first region away from the first surface.

[0090] Specifically, see Figure 5 A well region 104 and a first region 105 are formed in the semiconductor body 100 . The first region 105 is set to a first conductivity type and is located on the first surface 101 . The well region 104 is set to a second conductivity type and is located on a side of the first region 105 away from the first surface 101 .

[0091] For example, the MOSFET semiconductor device may include an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. In the embodiment of the present invention, an N-type MOSFET semiconductor device is used as an example for description. If the first conductivity type is N-type, the semiconductor body 100 is an N-type semiconductor body, the well region 104 is a P-well region, and the first region 105 is an N+ doped region.

[0092] Depending on the conductivity type of the MOSFET semiconductor device, the first conductivity type can be N-type or P-type, and the two-dimensional conductive layer 103 formed at the bottom of the first sub-groove T11 can be a two-dimensional electron gas layer or a two-dimensional hole gas layer; that is, when the MOSFET semiconductor device is in the on state, that is, when the voltage reaches the rated turn-on voltage of the two-dimensional conductive layer 103, the carriers form a conduction current, flowing through the two-dimensional conductive layer 103, providing a channel for accelerated transmission of the carriers, thereby facilitating the improvement of the channel carrier mobility of the MOSFET semiconductor device and the reduction of the on-resistance of the device.

[0093] S130 , forming a first sub-insulating portion in the second sub-groove; the first sub-insulating portion is away from a surface of the two-dimensional conductive layer and flush with the first surface.

[0094] Specifically, see Figure 6 A first sub-insulating portion 1061 is formed in the second sub-recess T12. The first sub-insulating portion 1061 is away from the surface of the two-dimensional conductive layer 103 and is flush with the first surface 101. The first sub-insulating portion 1061 extends from the first surface 101 to the interior of the well region 104, completely filling the second sub-recess T12.

[0095] S140, forming a second sub-insulating portion on the first surface, wherein the first sub-insulating portion and the second sub-insulating portion are connected to form an insulating layer.

[0096] Specifically, see Figure 6, a second sub-insulating portion 1062 is formed on the first surface 101, and the first sub-insulating portion 1061 and the second sub-insulating portion 1062 are connected to form an insulating layer 106. The second sub-insulating portion 1062 is formed by epitaxial growth on the first surface 101, covering the first sub-insulating portion 1061 and connected to the first sub-insulating portion 1061, together forming the insulating layer 106, thereby achieving insulation between the gate and the semiconductor body 100. Compared with the related art in which the insulating layer is only formed on the first surface, the embodiment of the present invention forms the first sub-recess T11 by etching, and adds the first sub-insulating portion 1061 to the portion extending from the first surface 101 to the well region 104, thereby increasing the thickness of the insulating layer between the gate of the channel region of the MOSFET semiconductor device, which is beneficial to increasing the threshold voltage of the semiconductor device, thereby improving the voltage resistance performance of the device.

[0097] It should be noted that the second sub-insulating portion 1062 serves as a gate oxide layer, which is formed by depositing silicon dioxide. The first sub-insulating portion 1061 can be formed by depositing any insulating material and is not limited here. For example, if the first sub-insulating portion 1061 and the second sub-insulating portion 1062 use different insulating materials, it is necessary to first deposit the first sub-insulating portion 1061 in the second sub-groove T12, and then deposit the second sub-insulating portion 1062 on the first surface 101 to form the insulating layer 106; if the first sub-insulating portion 1061 and the second sub-insulating portion 1062 use the same insulating material, the first sub-insulating portion 1061 and the second sub-insulating portion 1062 can be deposited in a one-step deposition process, and the first sub-insulating portion 1061 is formed in the second sub-groove T12 at the same time, and the second sub-insulating portion 1062 is formed on the first surface 101, thereby forming the insulating layer 106, which is conducive to simplifying the manufacturing process of the semiconductor device.

[0098] S150 , forming a gate on a side of the second sub-insulating portion away from the semiconductor body, wherein the insulating layer is used to insulate the semiconductor body and the gate.

[0099] Specifically, see Figure 6 A gate 107 is formed on a side of the second sub-insulating portion 1062 away from the semiconductor body 100, and the insulating layer 106 is used to insulate the semiconductor body 100 from the gate 107. The gate 107 may be a polysilicon gate.

[0100] S160 , forming a source electrode on the first surface.

[0101] Specifically, see Figure 2 A source electrode 108 is formed on the first surface 101. A spacer insulating layer 109 is formed between the source electrode 108 and the gate electrode 107 by a deposition process. The spacer insulating layer 109 covers and wraps the gate electrode 107 and the insulating layer 106. The spacer insulating layer 109 is used to insulate the source electrode 108 from the gate electrode 107.

[0102] S170 , forming a drain on the second surface.

[0103] Specifically, see Figure 2 A drain electrode 110 is formed on the second surface 102. The drain electrode 110 may include a stack of metal Ti, metal Ni, and metal Ag.

[0104] In a method for manufacturing a semiconductor device provided by an embodiment of the present invention, a two-dimensional conductive layer 103 is formed in a first sub-recess T11 of a recess T1 provided on a first surface 101. A well region 104 and a first region 105 are then formed on the first surface 101. The two-dimensional conductive layer 103 is located in the well region 104 near the first surface 101 and in contact with the first region 105. A first sub-insulating portion 1061 is formed in the second sub-recess T12. A second sub-insulating portion 1062 is then formed on the first surface 101. The second sub-insulating portion 1062 and the first sub-insulating portion 1061 form an insulating layer 106 to insulate the gate 107 from the semiconductor body 100. Depending on the conductivity type of the MOSFET device, the two-dimensional conductive layer 103 includes a two-dimensional electron gas layer or a two-dimensional hole gas layer. Because the two-dimensional electron gas layer or the two-dimensional hole gas layer is very thin and has high conductivity and carrier mobility, the carrier mobility of the carriers in the two-dimensional conductive layer 103 is greatly improved as they pass through the source 108 and the first region 105 into the two-dimensional conductive layer 103, and then through the semiconductor body 100 to the drain 110. This reduces the on-resistance of the device without increasing the thickness of the device. In addition, by forming a second sub-recess T12 and providing a first sub-insulating portion 1061 within the second sub-recess T12, that is, by extending the insulating layer 106 into the well region 104, the thickness of the insulating layer between the gates in the device channel region is increased, which helps to increase the threshold voltage of the semiconductor device, thereby improving the device's withstand voltage performance and enhancing product competitiveness.

[0105] Optionally, based on the above embodiment, Figure 7 yes Figure 3 The flowchart included in S110, Figures 8 and 9 yes Figure 7 The structural diagram corresponding to each relevant step in the Figures 7 to 9 The providing of the semiconductor body in step S110 includes:

[0106] S111. Provide a semiconductor body; the semiconductor body includes a transitional first surface and a second surface that are oppositely arranged.

[0107] Specifically, see Figure 8 The semiconductor body 100 includes a transitional first surface 111 and a second surface 102 that are opposite to each other. The transitional first surface 111 is an initial surface of the semiconductor body 100 that has not been processed.

[0108] Exemplarily, providing the semiconductor body 100 may include providing a semiconductor body that is a silicon carbide semiconductor body or a gallium nitride body.

[0109] Semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. Semiconductor body 100 also includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high withstand voltage, low on-resistance, and high frequency, which can further improve the performance of semiconductor devices.

[0110] S112. Form a groove on the transition first surface; the groove extends from the transition first surface into the semiconductor body; the groove includes a first sub-groove and a second sub-groove that are connected, and the first sub-groove is located between the semiconductor body and the transition first surface.

[0111] Specifically, see Figure 8 , a groove T1 is formed on the transition first surface 111; the groove T1 extends from the transition first surface 111 into the semiconductor body 100; the groove T1 includes a first sub-groove T11 and a second sub-groove T12 that are connected, and the first sub-groove T11 is located between the semiconductor body 100 and the transition first surface 111.

[0112] S113 , forming a two-dimensional conductive layer in the first sub-groove and on the transition first surface.

[0113] Specifically, see Figure 9 A two-dimensional conductive layer 103 is formed in the first sub-groove T11 and on the transition first surface 111 .

[0114] Figure 10 yes Figure 7 The flowchart included in step S113 is shown in FIG. Figure 10 The two-dimensional conductive layer 103 includes a first gallium nitride layer 1031 and a second gallium nitride layer 1032 . Step S113 of forming a two-dimensional conductive layer in the first sub-groove and on the transition first surface includes the following steps:

[0115] S1131 , forming a first gallium nitride layer in the first sub-recess and on the transition first surface.

[0116] S1132. Form a second gallium nitride layer on a side of the first gallium nitride layer away from the semiconductor body; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at the interface of the heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer; wherein the first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

[0117] Specifically, see Figure 9 To prepare the two-dimensional conductive layer 103, a first gallium nitride layer 1031 is first epitaxially grown at the bottom of the first sub-recess T11 and on the first transition surface 111. A second gallium nitride layer 1032 is then epitaxially grown on the surface of the first gallium nitride layer 1031 located at the bottom of the first sub-recess T11 and on the first transition surface 111. Exemplarily, in step S1132, the second gallium nitride layer 1032 may be formed on a side of the first gallium nitride layer away from the semiconductor body. The stacked first and second gallium nitride layers 1031 and 1032 form a heterojunction structure. Under specific conditions (e.g., a specific electric field and temperature), a high concentration of two-dimensional electron gas or two-dimensional hole gas is formed at the heterojunction interface, which more than meets the device's carrier requirements, significantly improving the device's carrier mobility and reducing its on-resistance. Exemplarily, the first conductivity type is N-type, and the two-dimensional conductive layer 103 includes a two-dimensional electron gas layer; alternatively, the first conductivity type is P-type, and the two-dimensional conductive layer 103 includes a two-dimensional hole gas layer. Taking an N-type MOSFET device as an example, a second gallium nitride layer 1032 of P-type doping, magnesium gallium nitride or aluminum gallium nitride, can form a space charge region between it and the semiconductor body 100 of the first conductivity type, which can prevent current from flowing from the source to the drain when the device is in the non-conducting state. It should be noted that the two-dimensional electron gas layer is usually a heterojunction semiconductor layer. Under specific conditions (such as specific electric field and specific temperature conditions), due to the difference in material properties at its heterojunction interface, a large concentration of two-dimensional electron gas is formed, achieving excellent electron mobility, which is far greater than the electron mobility of silicon, silicon carbide and gallium nitride, far more than meeting the carrier requirements of the device, and can significantly improve the carrier mobility of the device. Moreover, the movement of electrons in the two-dimensional electron gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent electron mobility on the two-dimensional surface where the heterojunction interface is located. Accordingly, the movement of holes in the two-dimensional hole gas layer is confined to the two-dimensional interface at the heterojunction interface, and has excellent hole mobility on the two-dimensional surface where the heterojunction interface is located.

[0118] S114. Flatten the transition first surface, wherein the surface opposite to the second surface of the semiconductor body is the first surface, and after the first sub-insulating portion is formed in the second sub-groove, the surface of the first sub-insulating portion away from the two-dimensional conductive layer is flush with the first surface.

[0119] Specifically, see Figure 4 The transitional first surface 111 can be planarized using a chemical mechanical polishing (CMP) process. The surface of the semiconductor body 100 facing the second surface 102 is the first surface 101. After the first sub-insulating portion 1061 is formed in the second sub-recess T12, the surface of the first sub-insulating portion 1061 away from the two-dimensional conductive layer 103 is flush with the first surface 101. The first surface 101 is a planarized surface, which improves surface quality, thereby facilitating improved formation quality of the first region 105, the well region 104, and other doped regions.

[0120] Figure 11 yes Figure 7 The flowchart of step S114 includes: Figure 12 yes Figure 7 Schematic diagram of the structure corresponding to step S1141 in FIG. Figure 11 In step S114, the first transition surface is flattened, including the following steps:

[0121] S1141. Remove the two-dimensional conductive layer located on the transition first surface.

[0122] S1142, performing a planarization process on the transition first surface.

[0123] Specifically, see Figure 12 and Figure 4 The two-dimensional conductive layer 103 on the transition first surface 111 is removed by etching. The transition first surface 111 is ground by CMP to obtain a new ground first surface 101. Figure 12 shows a schematic structural diagram of the transition first surface 111 before being flattened. Figure 4A schematic diagram of the structure of the first surface 101 obtained after planarizing the transitional first surface 111 is shown. A second sub-recess T12 is further provided between the two-dimensional conductive layer 103 and the plane of the first surface 101, for forming the first sub-insulating portion 1061 through a subsequent deposition process. Using a CMP process for planarization allows for precise control of the polishing thickness of the film layer, replacing the sacrificial oxidation process of the two-dimensional conductive layer 103 located on the transitional first surface 111. This avoids the effects of the unstable sacrificial oxidation process and removes defects on the transitional first surface 111, reducing issues such as leakage caused by interface states, changes in device capacitance, and increases in device on-resistance.

[0124] Optionally, based on the above embodiments, when forming the well region and the first region in the semiconductor body in step S120, the following steps are further included:

[0125] A second region is formed in the semiconductor body. The second region is configured as a second conductivity type and is located on the first surface. The second region contacts the first region.

[0126] Specifically, see Figure 5 or Figure 6 A second region 112 is formed in the semiconductor body 100 . The second region 112 is configured to be of the second conductivity type and is located on the first surface 101 . The second region 112 contacts the first region 105 .

[0127] The conductivity type of the second region 112 is opposite to that of the first region 105. For example, in an N-type MOSFET semiconductor device, the first conductivity type is N-type, while the second conductivity type is P-type. The second region 112 includes a P+ doped region. The ion concentration of the second region 112 is greater than the ion concentration of the well region 104. The second region 112 is provided to form a better ohmic contact with the source 108.

[0128] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device provided by any of the embodiments of the present invention, wherein the substrate is used to support the semiconductor device. Therefore, the beneficial effects of the power module including any of the semiconductor devices provided by the embodiments of the present invention are not further described here.

[0129] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device provided by any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0130] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device provided by the embodiments of the present invention will not be repeated here.

[0131] An embodiment of the present invention further provides a vehicle, including a load and a power conversion circuit as provided in any embodiment of the present invention. The power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. Therefore, the beneficial effects of including any power conversion circuit provided in any embodiment of the present invention in the vehicle are not further elaborated here.

[0132] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, the well region being of a second conductivity type and located on a side of the first region away from the first surface; a groove being provided on the first surface, the groove extending from the first surface to the well region; the groove comprising a first sub-groove and a second sub-groove connected to each other, the first sub-groove being located on a side of the second sub-groove away from the first surface; a two-dimensional conductive layer, located in the first sub-groove; The insulating layer includes a first sub-insulating portion and a second sub-insulating portion connected to each other, wherein the first sub-insulating portion is located in the second sub-groove, and the second sub-insulating portion is located on the first surface; a gate, located on a side of the second sub-insulating portion away from the semiconductor body, wherein the insulating layer is used to insulate the semiconductor body from the gate; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The two-dimensional conductive layer includes a first gallium nitride layer and a second gallium nitride layer; The first gallium nitride layer is located in the first sub-groove; The second gallium nitride layer is located on a side of the first gallium nitride layer away from the well region; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer; Wherein, the first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

3. The semiconductor device according to claim 1 or 2, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride body.

4. The semiconductor device according to claim 2, wherein The second gallium nitride layer includes magnesium gallium nitride or aluminum gallium nitride.

5. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region, which is set to a second conductivity type and is located on the first surface; the second region is in contact with the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

6. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the first surface is provided with a groove, the groove extending from the first surface into the semiconductor body; the groove includes a first sub-groove and a second sub-groove connected to each other, the first sub-groove being located between a well region and the first surface; a two-dimensional conductive layer is provided in the first sub-groove; forming a well region and a first region in the semiconductor body, wherein the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; forming a first sub-insulating portion in the second sub-groove; forming a second sub-insulating portion on the first surface, wherein the first sub-insulating portion and the second sub-insulating portion are connected to form an insulating layer; forming a gate on a side of the second sub-insulating portion away from the semiconductor body, wherein the insulating layer is used to insulate the semiconductor body from the gate; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The semiconductor body provided includes: Providing a semiconductor body; the semiconductor body comprising a first transition surface and a second transition surface disposed opposite to each other; A groove is formed on the transition first surface; the groove extends from the transition first surface into the semiconductor body; the groove includes a first sub-groove and a second sub-groove that are connected, and the first sub-groove is located between the semiconductor body and the transition first surface; forming a two-dimensional conductive layer in the first sub-groove and on the transition first surface; The transition first surface is planarized, wherein the surface opposite to the second surface of the semiconductor body is the first surface, and after a first sub-insulating portion is formed in the second sub-groove, the surface of the first sub-insulating portion away from the two-dimensional conductive layer is flush with the first surface.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The planarizing process of the transition first surface comprises: removing the two-dimensional conductive layer located on the transition first surface; The transition first surface is planarized.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The two-dimensional conductive layer includes a first gallium nitride layer and a second gallium nitride layer; forming the two-dimensional conductive layer in the first sub-groove and on the transition first surface includes: forming a first gallium nitride layer in the first sub-recess and on the transition first surface; forming a second gallium nitride layer on a side of the first gallium nitride layer away from the semiconductor body; the second gallium nitride layer is a doped gallium nitride material, and a two-dimensional electron gas or a two-dimensional hole gas exists at an interface of a heterojunction structure formed by the first gallium nitride layer and the second gallium nitride layer; Wherein, the first conductivity type is N-type, and the two-dimensional conductive layer includes a two-dimensional electron gas layer; or, the first conductivity type is P-type, and the two-dimensional conductive layer includes a two-dimensional hole gas layer.

10. The method for manufacturing a semiconductor device according to claim 6 or 7, wherein: The semiconductor body provided includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride body.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a second gallium nitride layer on a side of the first gallium nitride layer away from the semiconductor body includes: A second gallium nitride layer including magnesium gallium nitride or aluminum gallium nitride is formed on a side of the first gallium nitride layer away from the semiconductor body.

12. The method for manufacturing a semiconductor device according to claim 6, wherein: When the semiconductor body forms the well region and the first region, the method further includes: A second region is formed in the semiconductor body. The second region is set to a second conductivity type and is located on the first surface. The second region contacts the first region, and the ion concentration of the second region is greater than the ion concentration of the well region.

13. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 5, wherein the substrate is used for supporting the semiconductor device.

14. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

15. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 14, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

Images