Heterojunction cell, heterojunction cell preparation method and photovoltaic module

Abstract

The invention provides a heterojunction cell, a heterojunction cell preparation method and a photovoltaic module, and relates to the technical field of solar cells. The heterojunction cell comprises a silicon substrate layer, the silicon substrate layer is provided with a first surface and a second surface which are oppositely arranged, the first surface is a suede surface, the second surface is a polished surface, the suede surface and the polished surface are each provided with an intrinsic amorphous silicon layer, a doped layer and a transparent conductive layer in a stacked mode in sequence, and the doped layer is a transparent conductive layer. Impurity Fe element and Al element exist in the suede surface and the polished surface, and the concentration of Fe element / Al element in the suede surface is higher than that of Fe element / Al element in the polished surface. During use, the surface of a polished surface is smoother, subsequent deposition of an amorphous silicon film is facilitated, impurities Fe and Al exist in the suede and the polished surface, and the content of the impurity elements of the polished surface is far lower than that of the impurity elements of the suede, so that the overall minority carrier lifetime is prolonged, and the passivation effect of the polished surface is better.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a heterojunction cell, a method for preparing a heterojunction cell, and a photovoltaic module. Background Art

[0002] The photovoltaic industry is currently developing rapidly. With the continuous improvement of traditional technologies and the continuous development of new technologies, the conversion efficiency of solar cells is gradually increasing. Heterojunction cell technology has an iterative advantage over PERC cell technology. The current mainstream heterojunction cell preparation process is to texturize the original silicon wafer on both sides, then undergo CVD amorphous silicon thin film deposition, then TCO film deposition, and finally screen printing into cells. Although the process steps are simple and the cell bifaciality is high, it is still far from reaching the theoretical conversion efficiency of heterojunction cells. Due to its structure, the core part of the heterojunction cell technology is CVD amorphous silicon thin film deposition. The quality of the back passivation directly determines the Voc level of the cell. The higher the Voc, the easier it is to improve the conversion efficiency. Having an ultra-high Voc is the biggest advantage of heterojunction cells compared to other battery technologies.

[0003] The heterojunction battery in the prior art has a technical problem of poor back passivation effect, which leads to poor conversion efficiency of the battery cell. Summary of the Invention

[0004] The present invention provides a heterojunction battery, a method for preparing a heterojunction battery, and a photovoltaic module, which can improve the back passivation effect of a battery cell, thereby improving the conversion efficiency of the battery cell.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] An embodiment of the present invention provides a heterojunction battery, including a silicon base layer, wherein the silicon base layer has a first surface and a second surface arranged opposite to each other, wherein the first surface is a velvet surface and the second surface is a polished surface, and both the velvet surface and the polished surface are sequentially stacked with an intrinsic amorphous silicon layer, a doped layer and a transparent conductive layer, and impurities Fe and Al elements exist in both the velvet surface and the polished surface, and the Fe / Al concentration in the velvet surface is higher than that in the polished surface.

[0007] Optionally, the concentration of Fe in the suede surface is 10 to 100 times higher than that in the polished surface, and the concentration of Al in the suede surface is 10 to 100 times higher than that in the polished surface.

[0008] Optionally, the concentration of Fe element / Al element in the suede is 0.1ppb-1ppb.

[0009] Optionally, the concentration of Fe element / Al element in the polishing surface is not greater than 0.1 ppb.

[0010] Optionally, the difference between the reflectivity of the suede surface and the reflectivity of the polished surface is 7%-17%.

[0011] Optionally, a metal grid line is provided on a surface of the transparent conductive layer away from the doping layer.

[0012] An embodiment of the present invention further provides a method for preparing a heterojunction battery, which is used to prepare a heterojunction battery. The method for preparing a heterojunction battery comprises:

[0013] Perform double-sided texturing on the silicon base layer;

[0014] preparing a mask layer on the first surface of the silicon base layer;

[0015] polishing the second surface of the silicon base layer;

[0016] The silicon base layer is subjected to multiple gettering processes.

[0017] Optionally, the step of polishing the second surface of the silicon base layer further includes:

[0018] The polishing and etching thickness of the second surface is 2um-6um.

[0019] Optionally, the step of preparing a mask layer on the first surface of the silicon base layer includes:

[0020] A mask layer with a thickness of 50 nm to 100 nm is prepared on the first surface of the silicon base layer by using PECVD equipment.

[0021] Optionally, before the step of performing double-sided texturing on the silicon base layer, the heterojunction battery preparation method further comprises:

[0022] The silicon base layer is polished on both sides and subjected to gettering treatment.

[0023] Optionally, the step of performing double-sided texturing on the silicon base layer includes:

[0024] The first surface and the second surface of the silicon base layer are formed with a textured surface having a pyramid structure with a width of 0.05 μm to 5 μm.

[0025] An embodiment of the present invention further provides a photovoltaic module, comprising the above-mentioned heterojunction battery, or comprising a heterojunction battery manufactured by the heterojunction battery manufacturing method.

[0026] The beneficial effects of the heterojunction battery, heterojunction battery preparation method, and photovoltaic module according to the embodiments of the present invention include, for example:

[0027] The heterojunction cell includes a silicon substrate layer having a first surface and a second surface disposed opposite each other, wherein the first surface is a velvet surface and the second surface is a polished surface. Both the velvet surface and the polished surface are sequentially stacked with an intrinsic amorphous silicon layer, a doped layer, and a transparent conductive layer. Both the velvet surface and the polished surface contain impurities of Fe and Al, and the Fe / Al concentration in the velvet surface is higher than that in the polished surface. During use, the polished surface is smoother, facilitating the subsequent deposition of an amorphous silicon thin film. Both the velvet surface and the polished surface contain impurities of Fe and Al, and the impurity content of the polished surface is much lower than that of the velvet surface, thereby improving the overall minority carrier lifetime and enhancing the passivation effect of the polished surface.

[0028] The heterojunction battery preparation method includes performing a double-sided texturing treatment on a silicon base layer; preparing a mask layer on the first surface of the silicon base layer; polishing the second surface of the silicon base layer; and performing multiple gettering on the silicon base layer. During use, after performing the double-sided texturing treatment on the silicon base layer, a mask layer is prepared on the first surface of the silicon base layer, and the second surface of the silicon base layer is polished to make the second surface of the silicon base layer more flat, which is conducive to the subsequent deposition of an amorphous silicon thin film. The flat surface can make the thin film grow more uniformly, thereby improving the quality of the thin film and battery performance; the first and second surfaces of the silicon base layer are subjected to multiple gettering. Multiple gettering can more effectively remove impurities on the first and second surfaces of the silicon base layer, further reducing the impurity concentration on the second surface of the silicon base layer, so that the impurity concentration on the second surface of the silicon base layer is lower than the impurity concentration on the first surface, thereby improving the overall minority carrier lifetime and making the passivation effect of the second surface of the silicon base layer better.

[0029] The photovoltaic module includes the above-mentioned heterojunction battery, or includes a heterojunction battery prepared by the heterojunction battery preparation method, and has all the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 A flow chart of the heterojunction battery preparation method provided in this embodiment;

[0032] Figure 2 This is a comparison diagram of the concentration of metal impurities on the front side of the silicon base layer before and after multiple repeated gettering processes;

[0033] Figure 3 This is a comparison diagram of the concentration of metal impurities on the back side of the silicon base layer before and after multiple repeated gettering processes;

[0034] Figure 4 This is a schematic structural diagram of the heterojunction battery provided in this embodiment.

[0035] Icon: 10-silicon base layer; 11-velvet surface; 12-polished surface; 20-intrinsic amorphous silicon layer; 30-doped layer; 40-transparent conductive layer; 50-metal grid line. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0039] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0040] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0041] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0042] The photovoltaic industry is currently developing rapidly. With the continuous improvement of traditional technologies and the continuous development of new technologies, the conversion efficiency of solar cells is gradually increasing. Heterojunction cell technology has an iterative advantage over PERC cell technology. The current mainstream heterojunction cell preparation process is to texturize the original silicon wafer on both sides, then undergo CVD amorphous silicon thin film deposition, then TCO film deposition, and finally screen printing into cells. Although the process steps are simple and the cell bifaciality is high, it is still far from reaching the theoretical conversion efficiency of heterojunction cells. Due to its structure, the core part of the heterojunction cell technology is CVD amorphous silicon thin film deposition. The quality of the back passivation directly determines the Voc level of the cell. The higher the Voc, the easier it is to improve the conversion efficiency. Having an ultra-high Voc is the biggest advantage of heterojunction cells compared to other battery technologies.

[0043] The heterojunction battery in the related art has a technical problem of poor back passivation effect, which leads to poor conversion efficiency of the battery cell.

[0044] Please refer to Figure 1-Figure 2 This embodiment provides a heterojunction battery, a method for preparing a heterojunction battery, and a photovoltaic module, which can effectively improve the technical problems mentioned above, improve the back passivation effect of the battery cell, and thus improve the conversion efficiency of the battery cell.

[0045] The heterojunction battery preparation method includes:

[0046] S1: polishing both sides of the silicon base layer 10.

[0047] Specifically, a pre-cleaning solution is used to clean and polish both sides of the silicon substrate layer 10 to remove organic matter and metallic impurities from the surface of the silicon substrate layer 10. The pre-cleaning solution comprises a 10%-18% concentration of hydrogen peroxide and a 10%-15% concentration of alkaline solution. During the pre-cleaning process, the thickness of the etching on both sides of the silicon substrate layer 10 is 3µm-6µm.

[0048] In this embodiment, the concentration of hydrogen peroxide can be 10%, 12%, 15%, or 18%, and the concentration of alkali solution can be 10%, 12%, or 15%, without specific limitation.

[0049] In this embodiment, the double-sided etching thickness of the silicon base layer 10 during the pre-cleaning process may be 3 um, 5 um, or 6 um, which is not specifically limited here.

[0050] S2: Perform phosphorus gettering treatment on both sides of the silicon base layer 10 .

[0051] Specifically, a layer of phosphorus slurry is applied to the surface of the silicon substrate layer 10. The silicon substrate layer 10 is then driven by rollers at a constant speed of 3m / min-6m / min through multiple high-temperature chambers at temperatures ranging from 700°C to 1000°C. At this high temperature, the phosphorus slurry forms a layer of phosphosilicate glass (PSG) on the surface of the silicon substrate layer 10, which condenses and separates out metal impurities within the silicon substrate layer 10. The phosphorus compound concentration in the phosphorus slurry is 2%-12%. Two rollers are positioned opposite each other, each coated with phosphorus slurry. The silicon substrate 10 is passed between the two rollers, thereby coating the surface of the silicon substrate layer 10 with phosphorus slurry. The phosphorus-coated silicon substrate 10 is then passed through the multiple high-temperature chambers at a constant speed, causing the phosphorus slurry to form a layer of phosphosilicate glass (PSG) on the surface of the silicon substrate layer 10, which condenses and separates out metal impurities within the silicon substrate layer 10, thereby reducing the amount of metal impurities on the surface of the silicon substrate layer 10.

[0052] S3: removing the phosphosilicate glass (PSG) layer.

[0053] Specifically, the silicon base layer 10 is etched with a hydrofluoric acid solution having a concentration of 10% to 15% to remove the phosphosilicate glass (PSG) layer, wherein the etching thickness of the silicon base layer 10 is 0.02 μm to 0.05 μm, for example, 0.02 μm, 0.03 μm or 0.05 μm, which is not specifically limited here.

[0054] S4: performing double-sided texturing treatment on the silicon base layer 10 .

[0055] Specifically, a pyramid-structured velvet surface with a width of 0.05um-5um is formed on the first surface and the second surface of the silicon base layer 10. The width of the pyramid-structured velvet surface can be 0.05um, 1um, 3um or 5um, which is not specifically limited here.

[0056] It can be understood that the velvet surface of the pyramid structure can reduce optical reflectivity, improve electrical performance, and increase carrier collection efficiency.

[0057] It should be noted that, in this embodiment, the two opposite surfaces of the silicon base layer 10 are respectively a first surface and a second surface, wherein the first surface is the front surface and the second surface is the back surface.

[0058] S5 : preparing a mask layer on the first surface of the silicon base layer 10 .

[0059] Specifically, a PECVD device is used to prepare a mask layer with a thickness of 50 nm to 100 nm on the first surface of the silicon base layer 10, that is, the front surface of the silicon base layer 10. For example, the thickness of the mask layer can be 50 nm, 60 nm, 80 nm or 100 nm, which is not specifically limited here.

[0060] S6: polishing the second surface of the silicon base layer 10 .

[0061] Specifically, the second surface of the silicon base layer 10 , ie, the back side of the silicon base layer 10 , is single-sided polished using a mixture of an alkali solution with a concentration of 1.10%-1.40% and a polishing auxiliary additive with a concentration of 0.50%-0.80%.

[0062] It should be noted that, when preparing heterojunction cells in the prior art, the silicon base layer 10 is double-sided textured and then an amorphous silicon film is directly deposited. Since the surface of the silicon base layer 10 after textured will form a pyramid-shaped textured surface, that is, the surface of the silicon base layer 10 is not flat enough, and the surface of the silicon base layer 10 is uneven, the direct deposition of the amorphous silicon film will cause the local film thickness of the film to be uneven, thereby affecting the passivation effect, and the uneven surface of the silicon base layer 10 will also be unfavorable for intercepting long-wavelength light. Therefore, in order to solve this technical problem, after the silicon base layer 10 is double-sided textured, the second surface of the silicon base layer 10, that is, the back side of the silicon base layer 10, is polished again, so that the back side of the silicon base layer 10 is in a flat state, which is conducive to the subsequent deposition of the amorphous silicon film. The flat surface can make the film grow more uniformly, reduce defects and stress concentration in the film, thereby improving the quality of the film and the passivation effect, and thus improving the efficiency and stability of the battery.

[0063] In this embodiment, the polishing and etching thickness of the second surface is 2um-6um. Specifically, the polishing and etching thickness of the back side of the silicon base layer 10 can be 2um, 3um, 5um or 6um, which is not specifically limited here.

[0064] S7: removing the mask layer on the first surface.

[0065] Specifically, the mask layer is removed by using a hydrofluoric acid solution with a concentration of 9% to 11% at 18° C. to 30° C. for 200 s to 300 s.

[0066] Furthermore, after the double-sided texturing of the silicon base layer 10, single-sided polishing of the back side of the silicon base layer 10 is performed, the impurities on the surface of the silicon base layer 10 can be removed more effectively, and the impurities on the surface of the silicon base layer 10 can be fixed at a specific position. Compared with the existing technology, unnecessary impurity diffusion paths on the back side of the polished silicon base layer 10 are reduced, so that impurities can be more easily absorbed during subsequent impurity absorption treatment, thereby forming a difference between the impurity concentration on the back side of the silicon base layer 10 and the impurity concentration on the front side of the silicon base layer 10, thereby increasing the efficiency improvement brought by impurity absorption.

[0067] S8: Gettering is performed on the silicon base layer 10 multiple times.

[0068] Specifically, a phosphorus gettering machine is used to perform a phosphorus gettering treatment on the silicon base layer 10. The phosphorus gettering process is consistent with step S2, namely, a phosphorus slurry is applied to both sides of the silicon base layer 10. The silicon base layer 10 is then passed through multiple high-temperature chambers at a constant speed of 3m / min-6m / min using rollers at temperatures ranging from 700°C to 1000°C. At this high temperature, the phosphorus slurry forms a PSG layer on the surface of the silicon base layer 10, which precipitates metallic impurities within the silicon base layer 10. The concentration of phosphorus compounds in the phosphorus slurry is 2%-12%.

[0069] It can be understood that the specific temperatures of multiple high-temperature chambers need to be set according to the different segregation coefficients of each metal, so that after the silicon base layer 10 passes through multiple high-temperature chambers in sequence, the metal impurities such as aluminum, iron, zinc and copper inside the silicon base layer 10 can be precipitated into the phosphosilicate glass layer.

[0070] It should be noted that step S8 is repeated 2 to 5 times. In other words, the gettering is repeated 2 to 5 times on the front and back surfaces of the silicon base layer 10 .

[0071] Furthermore, although a gettering process has been performed before the double-sided texturing of the silicon base layer 10, that is, step S2 in this embodiment, due to the quality of the silicon base layer 10, the metal impurity content inside it is relatively high and there are many defects. The gettering process before the double-sided texturing of the silicon base layer 10 cannot effectively solve the defect problem existing in the silicon base layer 10. Therefore, the heterojunction preparation process provided in this embodiment performs another and repeated gettering process on both sides of the silicon base layer 10 after the double-sided texturing of the silicon base layer 10, so as to further reduce the metal impurity concentration of the silicon base layer 10.

[0072] In addition, during the phosphorus gettering process, the polished back side of the silicon base layer 10 can more accurately control the diffusion of phosphorus atoms, allowing them to better interact with impurities on the surface of the silicon base layer 10, thereby improving the gettering effect.

[0073] Please refer to Figure 2-Figure 3 , Figure 2 The graph shows a comparison of the concentration of metal impurities on the front surface of the silicon base layer 10 before and after the front surface of the silicon base layer 10 is subjected to multiple repeated gettering treatments. Figure 3 The figure shows the concentration comparison of metal impurities on the back of the silicon base layer 10 before and after repeated gettering. Figure 2 and Figure 3It can be seen from the figure that after repeated gettering treatments on the front and back sides of the silicon base layer 10, the metal impurity concentrations on both the front and back sides of the silicon base layer 10 have been significantly reduced. Furthermore, by comparing the concentrations of various metal impurities on the front side of the silicon base layer 10 with the concentrations of various metal impurities on the back side of the silicon base layer 10, Table 1 can be obtained, as follows:

[0074] Table 1

[0075]

[0076] As can be seen from Table 1, the Fe element concentration on the back side of the silicon base layer 10 is 14.24% lower than the Fe element concentration on the front side of the silicon base layer 10, and the Al element concentration on the back side of the silicon base layer 10 is 17.37% lower than the Al element concentration on the front side of the silicon base layer 10. There is a large difference between the element concentration on the back side of the silicon base layer 10 and the element concentration on the front side of the silicon base layer 10. The concentration difference can make the electric field distribution more reasonable, improve the carrier collection efficiency, and improve the overall minority carrier lifetime, so that the passivation effect of the back side of the polished silicon base layer 10 is better, thereby achieving the purpose of improving the conversion efficiency of the battery cell.

[0077] Furthermore, the lower Fe concentration on the back side of the polished silicon base layer 10 can reduce recombination and increase minority carrier lifetime, while the appropriate Fe concentration on the front side of the silicon base layer 10 facilitates other steps such as gettering and optimizes overall performance.

[0078] S9: removing the phosphosilicate glass (PSG) layer.

[0079] Specifically, the silicon base layer 10 is etched with a hydrofluoric acid solution having a concentration of 10% to 15% to remove the phosphosilicate glass (PSG) layer, wherein the etching thickness of the silicon base layer 10 is 0.02 μm to 0.05 μm, for example, 0.02 μm, 0.03 μm or 0.05 μm, which is not specifically limited here.

[0080] S10: performing a rounding treatment on the silicon base layer 10 .

[0081] S11 : cleaning the silicon base layer 10 .

[0082] S12 : forming an intrinsic amorphous silicon layer 20 on both sides of the silicon base layer 10 .

[0083] Specifically, the intrinsic amorphous silicon thin film is deposited on the front and back sides of the silicon base layer 10 using chemical vapor deposition technology.

[0084] S13 : forming a P-type doping layer 30 on the front surface of the silicon base layer 10 , and forming an N-type doping layer 30 on the back surface of the silicon base layer 10 .

[0085] S14 : forming a transparent conductive layer 40 on both sides of the silicon base layer 10 .

[0086] Specifically, physical vapor deposition technology is used to prepare TCO thin films on both sides of the silicon base layer 10. The TCO thin films can be indium tin oxide thin films or fluorine-doped tin oxide thin films.

[0087] S15: Screen printing.

[0088] Please refer to Figure 4 The embodiments of the present invention further provide a heterojunction battery, which is prepared by the above-mentioned heterojunction battery preparation method. The heterojunction battery includes a silicon substrate layer 10, which has a first surface and a second surface disposed opposite each other. The first surface is a velvet surface 11, and the second surface is a polished surface 12. The velvet surface 11 and the polished surface 12 are each sequentially stacked with an intrinsic amorphous silicon layer 20, a doped layer 30, a transparent conductive layer 40, and a metal grid line 50. The metal grid line 50 is disposed on a surface of the transparent conductive layer 40 away from the doped layer 30. Among them, the silicon base layer 10 has a first surface and a second surface arranged opposite to each other, the first surface is a suede surface 11, and the second surface is a polished surface 12. Impurities Fe and Al elements exist in both the suede surface 11 and the polished surface 12. The concentration of Fe elements in the suede surface 11 is 10 times to 100 times higher than that in the polished surface 12, and the concentration of Al elements in the suede surface 11 is 10 times to 100 times higher than that in the polished surface 12. The difference in reflectivity between the suede surface 11 and the polished surface 12 is 7% to 17%.

[0089] Specifically, the concentration of Fe in the suede surface 11 is 0.1 ppb to 1 ppb, the concentration of Al in the suede surface 11 is 0.1 ppb to 1 ppb, and the concentration of Fe and Al in the polished surface 12 is no greater than 0.1 ppb.

[0090] In this embodiment, the doping layer 30 may be made of amorphous silicon material, such as boron-doped amorphous silicon oxide or phosphorus-doped amorphous silicon oxide. The doping layer 30 may also be made of microcrystalline silicon material, which is not specifically limited here.

[0091] In this embodiment, the heterojunction battery prepared by the heterojunction battery preparation method provided in this embodiment will eventually form a battery structure with a velvet surface on the front and a polished surface 12 on the back. From the appearance, the polished surface 12 has a mirror-like effect, which is brighter and smoother than the unpolished surface. From the perspective of electrical performance characteristics, carrier transport is improved, the open circuit voltage is increased, and the fill factor is optimized. From the perspective of optical performance characteristics, since the mirror reflectivity is higher than the rough surface reflectivity, the reflectivity Ref of the polished surface 12 is significantly higher than the reflectivity of the velvet surface 11, and the best effect is achieved when the difference is 7%-17%. The polishing effect within this range can slightly increase the opening voltage of the battery cell, increase the short current by more than 20mA, and increase the fill factor by more than 0.30%. At the same time, the bifaciality of the battery cell decreases by ≤5%, reaching the optimal balance node of the efficiency and bifaciality of the battery cell.

[0092] An embodiment of the present invention further provides a photovoltaic module comprising the above-mentioned heterojunction cell.

[0093] In summary, the embodiments of the present invention provide a method for preparing a heterojunction battery, a heterojunction battery and a photovoltaic module. The method for preparing a heterojunction battery includes performing double-sided texturing treatment on a silicon base layer 10; preparing a mask layer on a first surface of the silicon base layer 10; polishing the second surface of the silicon base layer 10; and performing multiple impurity removal on the silicon base layer 10. During use, the silicon base layer 10 is subjected to double-sided texturing treatment, and a mask layer is prepared on the first surface of the silicon base layer 10. The second surface of the silicon base layer 10 is polished to make the second surface of the silicon base layer 10 more flat, which is beneficial to the subsequent deposition of amorphous silicon thin film. The flat surface can make the thin film grow more uniformly, thereby improving the quality of the thin film and battery performance; the first surface and the second surface of the silicon base layer 10 are subjected to multiple impurity gettering. Multiple impurity gettering can make the impurities on the first surface and the second surface of the silicon base layer 10 more effectively removed, further reducing the impurity concentration of the second surface of the silicon base layer 10, so that the impurity concentration of the second surface of the silicon base layer 10 is lower than the impurity concentration of the first surface, thereby improving the overall minority carrier lifetime, and making the passivation effect of the second surface of the silicon base layer 10 better.

[0094] The heterojunction cell includes a transparent conductive layer 40, a doping layer 30, an intrinsic amorphous silicon layer 20 and a silicon base layer 10 stacked in sequence, wherein the first surface is a velvet surface 11 and the second surface is a polished surface 12. The concentration of the Fe element in the velvet surface 11 is 10 times to 100 times higher than the concentration of the Fe element in the polished surface 12, and the concentration of the Al element in the velvet surface 11 is 10 times to 100 times higher than the concentration of the Al element in the polished surface 12. The difference in reflectivity between the velvet surface 11 and the polished surface 12 is 7% to 17%. When in use, the surface of the polishing surface 12 is smoother, which is conducive to the subsequent deposition of amorphous silicon thin films. The concentration of Fe elements in the velvet surface 11 of the silicon base layer 10 is 10 times to 100 times higher than the concentration of Fe elements in the polishing surface 12, and the concentration of Al elements in the velvet surface 11 is 10 times to 100 times higher than the concentration of Al elements in the polishing surface 12, that is, the content of impurity elements in the polishing surface 12 is much lower than the content of impurity elements in the velvet surface 11, thereby improving the overall minority carrier lifetime and making the passivation effect of the polishing surface 12 better; and the difference in reflectivity between the velvet surface 11 and the polishing surface 12 is 7% to 17%, that is, the reflectivity of the polishing surface 12 is much higher than the reflectivity of the velvet surface 11, which enhances the light trapping effect of the polishing surface 12 and improves the light absorption efficiency.

[0095] The photovoltaic module includes the above-mentioned heterojunction battery and has all the above-mentioned beneficial effects.

[0096] Example 1

[0097] This embodiment provides a method for preparing a heterojunction battery, comprising:

[0098] S1: polishing both sides of the silicon base layer 10.

[0099] S2: Perform phosphorus gettering treatment on both sides of the silicon base layer 10 .

[0100] S3: removing the phosphosilicate glass (PSG) layer.

[0101] S4: performing double-sided texturing treatment on the silicon base layer 10 .

[0102] S5 : preparing a mask layer on the first surface of the silicon base layer 10 .

[0103] S6: polishing the second surface of the silicon base layer 10 .

[0104] S7: removing the mask layer on the first surface.

[0105] S8: Gettering is performed on the silicon base layer 10 multiple times.

[0106] Specifically, the silicon substrate 10 was subjected to two phosphorus gettering treatments using a phosphorus gettering machine. A phosphorus slurry was applied to both sides of the silicon substrate 10. The silicon substrate 10 was then passed through multiple high-temperature chambers at a constant speed of 4 m / min using rollers at temperatures ranging from 700°C to 1000°C. At this high temperature, the phosphorus slurry formed a PSG layer on the surface of the silicon substrate 10, which precipitated metallic impurities within the silicon substrate 10. The phosphorus compound concentration in the phosphorus slurry was 6%.

[0107] S9: removing the phosphosilicate glass (PSG) layer.

[0108] S10: performing a rounding treatment on the silicon base layer 10 .

[0109] S11 : cleaning the silicon base layer 10 .

[0110] S12 : forming an intrinsic amorphous silicon layer 20 on both sides of the silicon base layer 10 .

[0111] S13 : forming a P-type doping layer 30 on the front surface of the silicon base layer 10 , and forming an N-type doping layer 30 on the back surface of the silicon base layer 10 .

[0112] S14 : forming TCO thin film layers on both sides of the silicon base layer 10 .

[0113] S15: Screen printing.

[0114] Example 2

[0115] The method is carried out with reference to Example 1. However, the difference from Example 1 is that step S8 of the heterojunction battery preparation method in this embodiment includes: performing multiple gettering on the silicon base layer 10 .

[0116] Specifically, the silicon substrate 10 was subjected to five phosphorus gettering treatments using a phosphorus gettering machine. A phosphorus slurry was applied to both sides of the silicon substrate 10. The silicon substrate 10 was then passed through multiple high-temperature chambers at a constant speed of 6 m / min using rollers at temperatures ranging from 700°C to 1000°C. At this high temperature, the phosphorus slurry formed a PSG layer on the surface of the silicon substrate 10, which precipitated metallic impurities within the silicon substrate 10. The phosphorus compound concentration in the phosphorus slurry was 10%.

[0117] Comparative Example 1

[0118] The method is carried out with reference to Example 1. The difference from Example 1 is that this comparative example provides a method for preparing a heterojunction battery. When in use, in step S8, only one gettering is performed on the silicon base layer 10.

[0119] Comparative Example 2

[0120] The method is carried out with reference to Example 1. Unlike Example 1, this comparative example provides a method for preparing a heterojunction battery, and steps S8 and S9 are removed during use.

[0121] Comparative Example 3

[0122] The method is carried out with reference to Example 1. Unlike Example 1, this comparative example provides a method for preparing a heterojunction battery, and step S6 is removed during use.

[0123] Test Case

[0124] The minority carrier lifetime, short-circuit current, open-circuit voltage, conversion efficiency and fill factor of the cells prepared by the heterojunction battery preparation methods of Example 1, Example 2 and Comparative Examples 1 to Comparative Examples 3 were tested. The results are shown in Table 2.

[0125] Table 2

[0126]

[0127] From the above results, it can be seen that the solar cell produced by the method for producing a solar cell provided in Example 1 of the present invention has the longest minority carrier lifetime, the best conversion efficiency and the best fill factor.

[0128] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A heterojunction battery, characterized in that: The invention comprises a silicon base layer (10), wherein the silicon base layer (10) has a first surface and a second surface arranged opposite to each other, wherein the first surface is a velvet surface (11), and the second surface is a polished surface (12), wherein the velvet surface and the polished surface are both sequentially stacked with an intrinsic amorphous silicon layer (20), a doping layer (30), and a transparent conductive layer (40), and impurities Fe and Al elements exist in both the velvet surface (11) and the polished surface (12), and the Fe element / Al element concentration in the velvet surface (11) is higher than that in the polished surface (12).

2. The heterojunction battery according to claim 1, characterized in that The concentration of the Fe element in the velvet surface (11) is 10 to 100 times higher than the concentration of the Fe element in the polished surface (12), and the concentration of the Al element in the velvet surface (11) is 10 to 100 times higher than the concentration of the Al element in the polished surface (12).

3. The heterojunction battery according to claim 1, characterized in that The concentration of Fe element / Al element in the velvet surface (11) is 0.1ppb-1ppb.

4. The heterojunction battery according to claim 1, characterized in that The concentration of Fe element / Al element in the polishing surface (12) is not greater than 0.1 ppb.

5. The heterojunction battery according to claim 1, characterized in that: The difference between the reflectivity of the velvet surface (11) and the reflectivity of the polished surface (12) is 7%-17%.

6. The heterojunction battery according to claim 1, characterized in that: A metal grid line (50) is provided on a surface of the transparent conductive layer (40) that is away from the doping layer (30).

7. A method for preparing a heterojunction battery, characterized in that: For preparing the heterojunction battery according to any one of claims 1 to 6, the heterojunction battery preparation method comprises: Performing double-sided texturing on the silicon base layer (10); preparing a mask layer on a first surface of the silicon base layer (10); Polishing the second surface of the silicon base layer (10); The silicon base layer (10) is subjected to multiple gettering.

8. The method for preparing a heterojunction battery according to claim 7, wherein: The step of polishing the second surface of the silicon base layer (10) further comprises: The polishing and etching thickness of the second surface is 2um-6um.

9. The method for preparing a heterojunction battery according to claim 7, wherein: The step of preparing a mask layer on the first surface of the silicon base layer (10) comprises: A PECVD device is used to prepare a mask layer with a thickness of 50 nm to 100 nm on the first surface of the silicon base layer (10).

10. The method for preparing a heterojunction battery according to claim 7, wherein: Before the step of performing double-sided texturing on the silicon base layer (10), the heterojunction battery preparation method further comprises: The silicon base layer (10) is polished on both sides and subjected to a gettering process.

11. The method for preparing a heterojunction battery according to claim 7, wherein: The step of performing double-sided texturing on the silicon base layer (10) comprises: The first surface and the second surface of the silicon base layer (10) are formed with a velvet surface having a pyramid structure with a width of 0.05um-5um.

12. A photovoltaic module, characterized in that: A heterojunction battery comprising the heterojunction battery according to any one of claims 1 to 6, or a heterojunction battery prepared by the heterojunction battery preparation method according to any one of claims 7 to 11.

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