Display method, display device and electronic equipment

Abstract

The invention provides a display method, a display device and electronic equipment, and belongs to the technical field of display. The display method is applied to the display device, and the display device comprises a main control board, a time schedule controller, a gate drive circuit, a source drive circuit and a sub-pixel array. The sub-pixel array comprises a plurality of grid lines, a plurality of data lines, and a plurality of sub-pixels defined by the crossed arrangement of the grid lines and the data lines; the display method comprises the steps that the main control board receives an initial data frame and divides the initial data frame into a first target data frame and a second target data frame; the first target data frame comprises odd-numbered line data of the initial data frame, and the second target data frame comprises even-numbered line data of the initial data frame; the time schedule controller applies a frame start signal and a plurality of clock signals to the gate drive circuit and applies a source control signal to the source drive circuit; the gate drive circuit provides gate drive signals for the multiple rows of gate lines based on the frame start signal and the multiple clock signals.

Description

Display method, display device, and electronic equipment Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display method, a display device, and an electronic device. Background Art

[0002] With technological advancements, display devices are moving towards larger sizes and higher resolutions. However, as the size of display devices increases and the resolution improves, the charging time provided to each row of pixels becomes shorter and shorter, making it impossible to meet the required pixel charging rate, thus affecting the display. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a display method, a display device and an electronic device.

[0004] An embodiment of the present disclosure provides a display method, which is applied to a display device. The display device includes a main control board, a timing controller, a gate drive circuit, a source drive circuit, and a sub-pixel array. The sub-pixel array includes a plurality of gate lines and a plurality of data lines, and a plurality of sub-pixels defined by the intersection of the gate lines and the data lines. The display method includes:

[0005] The main control board receives an initial data frame and divides the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered row data of the initial data frame, and the second target data frame includes even-numbered row data of the initial data frame;

[0006] The timing controller applies a frame start signal and a plurality of clock signals to the gate driving circuit, and applies a source control signal to the source driving circuit;

[0007] The gate driving circuit provides a gate driving signal for the plurality of rows of gate lines based on the frame start signal and the plurality of clock signals;

[0008] The source driving circuit controls the start time of writing the data signal of each row of sub-pixels based on the source control signal, and the phase difference between the start time of writing the effective level of the gate driving signal of the gate line connected to the row of sub-pixels is 2H; H is half of the phase difference between the start time of writing the effective level of the gate driving signal of the k-th row gate line and the k+2-th row gate line in the scanning order; k is a positive integer; wherein,

[0009] Based on the source control signal and the gate drive signal, the source drive circuit writes the data signal of the first target data frame into the odd-numbered rows of sub-pixels row by row; and the source control signal and the gate drive signal satisfy: a start time of writing data to the sub-pixels in the 2kth row is no later than an end time of writing data to the sub-pixels in the 2k-1th row, and an end time of writing data to the sub-pixels in the 2kth row is no earlier than a start time of writing data to the sub-pixels in the 2k+1th row;

[0010] Based on the source control signal and the gate drive signal, the source drive circuit writes the data signal of the second target data frame into the sub-pixels in the even rows row by row; and the source control signal and the gate drive signal satisfy: the starting time of data writing of the sub-pixels in the 2k+1th row is not later than the ending time of data writing of the sub-pixels in the 2kth row, and the ending time of data writing of the sub-pixels in the 2k+1th row is not earlier than the starting time of data writing of the sub-pixels in the 2k+2th row.

[0011] The gate drive signals written into two adjacent rows of sub-pixels are simultaneously at the effective level for a period of not less than 2 hours.

[0012] Wherein, the gate driving circuit includes a plurality of shift register units; one shift register unit is connected to one gate line, and different shift register units are connected to different gate lines;

[0013] The plurality of clock signals include a first clock signal for controlling a first-stage shift register unit in the gate driving circuit to output a gate driving signal;

[0014] Among them, the starting time of the effective level of the frame start signal output by the timing controller is earlier than the starting time of the effective level of the first clock signal; the phase difference between the ending time of the effective level of the frame start signal and the ending time of the effective level of the first clock signal is greater than or equal to 0.2H and less than or equal to 0.6H.

[0015] In which, the gate drive circuit includes N levels of shift register units; the first-level shift register unit to the P-th level shift register unit are connected to the frame start signal; the multiple clock signals also include a P-th clock signal for controlling the P-th level shift register unit to output a gate drive signal; the duty cycle of each of the clock signals is less than or equal to 50%, N is greater than P; and P is an integer greater than 1.

[0016] Among them, the phase difference between the starting time of the effective level of each two adjacent clock signals in the multiple clock signals is 1H, the ending time of the effective level of the frame start signal is not later than the ending time of the effective level of the first clock signal, and the duty cycle of each of the clock signals is greater than or equal to 40% and less than or equal to 45%.

[0017] The duty cycle of each clock signal is 40%, the duration of the effective level of the gate drive signal is 3.2 hours, and the phase difference between the termination time of the effective level of the frame start signal and the termination time of the effective level of the first clock signal is 0.2 hours.

[0018] The multiple clock signals include 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group receive the 8 clock signals respectively;

[0019] The timing controller writes the frame start signal into the first stage shift register unit to the fourth stage shift register unit among the N shift register units.

[0020] Among them, the end time of the effective level of the frame start signal is later than the end time of the effective level of the first clock signal; the phase difference between the start time of the effective level of the gate drive signal applied to the k-th gate line and the K+1-th gate line is 1H; every two adjacent clock signals are a group, and for adjacent groups of clock signals, the timing controller controls the phase difference of the start time of the effective level of one group of clock signals to be less than 1H, and the phase difference of the start time of the effective level of the other group of clock signals to be greater than 1H.

[0021] The duty cycle of each clock signal is 33%, and the duration of the effective level of the gate drive signal is 2.66 hours. For adjacent groups of clock signals, the timing controller controls the phase difference between the starting time of the effective level of one group of clock signals to be 0.76 hours, and the phase difference between the starting time of the effective level of the other group of clock signals to be 1.24 hours.

[0022] The multiple clock signals include 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group receive the 8 clock signals respectively;

[0023] The timing controller writes the frame start signal into the first stage shift register unit to the fourth stage shift register unit among the N shift register units.

[0024] The plurality of clock signals include a first clock signal for controlling a first-stage shift register unit in the gate driving unit to output a gate driving signal;

[0025] The plurality of clock signals include a first clock signal for controlling a first-stage shift register unit in the gate driving circuit to output a gate driving signal;

[0026] Among them, the starting time of the effective level of the frame start signal output by the timing controller is earlier than the starting time of the effective level of the first clock signal; the ending time of the effective level of the frame start signal is the same as the ending time of the effective level of the first clock signal.

[0027] The gate drive circuit includes N stages of shift register units; the first to P-th stages of shift register units are connected to the frame start signal; the multiple clock signals also include a P-th clock signal for controlling the P-th stage of shift register units to output a gate drive signal;

[0028] The first-stage shift register unit to the P-th stage shift register unit are connected to the frame start signal; the multiple clock signals also include a P-th clock signal for controlling the P-th stage shift register unit to output a gate drive signal; the duty cycle of each of the clock signals is greater than or equal to 40% and less than or equal to 45%, N is greater than P; and P is an integer greater than 1.

[0029] The phase difference between the starting times of the effective levels of every two adjacent clock signals in the multiple clock signals is 1H, and the duty cycle of each clock signal is 41.6%.

[0030] The effective level duration of the gate drive signal is 5 hours, and the pre-charge period is 3 hours.

[0031] The multiple clock signals include 12 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group includes 12 shift register units, and the 12 shift register units in each group receive the 12 clock signals respectively;

[0032] The timing controller writes the frame start signal into the first stage shift register unit to the sixth stage shift register unit among the N shift register units.

[0033] Among them, when the sub-pixel is selected by the effective level of the gate drive signal, this period is divided into a pre-charging period and a charging period; the charging period is a period for writing data signals to the sub-pixel, and the duration of the pre-charging period is greater than 1H.

[0034] The display of the kth initial data frame and the k+1th initial data frame includes:

[0035] The timing controller controls the source driving circuit and the gate driving circuit to control the sub-pixel array to display frame by frame in the following order:

[0036] a first target data frame of the kth initial data frame;

[0037] a second target data frame of the kth initial data frame;

[0038] the first target data frame of the k+1th initial data frame;

[0039] The second target data frame of the k+1th initial data frame.

[0040] The display of the kth initial data frame and the k+1th initial data frame includes:

[0041] The timing controller controls the source driving circuit and the gate driving circuit to control the sub-pixel array to display frame by frame in the following order:

[0042] a second target data frame of the kth initial data frame;

[0043] a first target data frame of the kth initial data frame;

[0044] a second target data frame of the k+1th initial data frame;

[0045] The first target data frame of the k+1th initial data frame.

[0046] The present disclosure provides a display device including a main control board, a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; the sub-pixel array includes a plurality of gate lines and a plurality of data lines, and a plurality of sub-pixels defined by the intersection of the gate lines and the data lines; wherein,

[0047] The main control board is configured to receive an initial data frame and divide the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered rows of data of the initial data frame, and the second target data frame includes even-numbered rows of data of the initial data frame;

[0048] The timing controller is configured to apply a frame start signal and a plurality of clock signals to the gate driving circuit, and apply a source control signal to the source driving circuit;

[0049] The gate driving circuit provides a gate driving signal for the plurality of rows of gate lines based on the frame start signal and the plurality of clock signals;

[0050] The source driving circuit controls the start time of writing the data signal of each row of sub-pixels based on the source control signal, and the phase difference between the start time of writing the effective level of the gate driving signal of the gate line connected to the row of sub-pixels is 2H; H is half of the phase difference between the start time of writing the effective level of the gate driving signal of the k-th row gate line and the k+2-th row gate line in the scanning order; k is a positive integer; wherein,

[0051] The source control signal and the gate drive signal generated by the timing controller satisfy, when the source drive circuit writes the data signal of the first target data frame into the sub-pixels in odd rows row by row, that the start time of writing data to the sub-pixels in the 2kth row is no later than the end time of writing data to the sub-pixels in the 2k-1th row, and the end time of writing data to the sub-pixels in the 2kth row is no earlier than the start time of writing data to the sub-pixels in the 2k+1th row;

[0052] The source control signal and the gate drive signal generated by the timing controller write the data signal of the second target data frame into the sub-pixels in the even rows row by row in the source drive circuit; and the source control signal and the gate drive signal satisfy: the starting time of the data writing of the sub-pixels in the 2k+1th row is not later than the ending time of the data writing of the sub-pixels in the 2kth row, and the ending time of the data writing of the sub-pixels in the 2k+1th row is not earlier than the starting time of the data writing of the sub-pixels in the 2k+2th row.

[0053] An embodiment of the present disclosure provides an electronic device including the above-mentioned display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG1 shows a schematic diagram of a display device provided by an embodiment of the present disclosure.

[0055] 2A and 2B show example structural diagrams of a gate driving circuit provided by an embodiment of the present disclosure.

[0056] FIG. 3A shows a signal timing diagram of a display method.

[0057] FIG. 3B shows a signal timing diagram of another display method.

[0058] FIG4 shows a flowchart of a display method according to an embodiment of the present disclosure.

[0059] FIG5 shows a timing diagram of a display method according to an embodiment of the present disclosure.

[0060] FIG6 shows a timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure.

[0061] FIG7 shows a schematic diagram of a frame start signal line and a clock signal line according to an embodiment of the present disclosure.

[0062] FIG8A is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to an embodiment of the present disclosure.

[0063] FIG8B is a schematic diagram of extracting odd-numbered rows of data from an initial data frame according to an embodiment of the present disclosure.

[0064] FIG9 is a schematic diagram of extracting even-numbered rows of data from an initial data frame according to an embodiment of the present disclosure.

[0065] FIG. 10 shows a signal timing diagram of odd-numbered frame display according to an embodiment of the present disclosure.

[0066] FIG. 11 shows a signal timing diagram of odd-numbered frame display according to an embodiment of the present disclosure.

[0067] FIG. 12 shows a signal timing diagram of a display method according to an embodiment of the present disclosure.

[0068] 13A and 13B show example structural diagrams of another gate driving circuit provided by an embodiment of the present disclosure.

[0069] FIG14 shows another timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure.

[0070] FIG. 15 shows a signal timing diagram of odd-numbered frame display according to an embodiment of the present disclosure.

[0071] FIG. 16 shows a signal timing diagram of an even-numbered frame display according to an embodiment of the present disclosure.

[0072] FIG17 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0073] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0074] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0075] Figure 1 shows a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in Figure 1 , the display device 100 includes a sub-pixel array, which includes a plurality of sub-pixels P arranged in an N×M array, where N and M are both integers greater than 1.

[0076] The display device 100 may further include a gate driver circuit 10, which is connected to a plurality of sub-pixels P. The gate driver circuit 10 may be connected to N rows of sub-pixels via a plurality of gate signal lines extending along a first direction (the x direction in FIG1 ), respectively. For example, the gate driver circuit 10 may be connected to the first row of sub-pixels via a first gate signal line to provide a first gate driver signal G1 to the first row of sub-pixels, and then connected to the second row of sub-pixels via a second gate signal line to provide a second gate driver signal G2 to the second row of sub-pixels, and so on. The first row of sub-pixels turns on in response to receiving the first gate driver signal G1, the second row of sub-pixels turns on in response to receiving the second gate driver signal G2, and so on.

[0077] In some embodiments, the gate drive circuit 10 can scan N rows of sub-pixels one by one or more rows. For example, the gate drive circuit 10 can scan one row of sub-pixels at a time, for example, generating N gate drive signals G1, G2, ... GN in sequence to turn on the first row of sub-pixels, the second row of sub-pixels P ... the Nth row of sub-pixels P in sequence. The gate drive circuit 10 can also scan two or more rows of sub-pixels P at a time. For example, the gate drive circuit 10 can simultaneously generate the first gate drive signal G1 and the second gate drive signal G2 to turn on the first row of sub-pixels and the second row of sub-pixels at the same time, then the gate drive circuit 10 can simultaneously generate the third gate drive signal G3 and the fourth gate drive signal G4 to turn on the third row of sub-pixels and the fourth row of sub-pixels at the same time, and so on. In some embodiments, the gate drive circuit 10 can scan the N rows of sub-pixels with at least one row interval to turn on the sub-pixels of some rows in sequence. For example, the gate driving circuit 10 can turn on the odd-numbered rows of sub-pixels P in sequence (for example, turn on the first row of sub-pixels, the third row of sub-pixels, the fifth row of sub-pixels, and so on), or turn on the even-numbered rows of sub-pixels in sequence (for example, turn on the second row of sub-pixels, the fourth row of sub-pixels, the sixth row of sub-pixels, and so on).

[0078] The display device 100 may further include a source driver circuit 20, which is connected to a plurality of sub-pixels P. For example, the source driver circuit 20 may be connected to M columns of sub-pixels P via a plurality of data lines extending along a second direction (the y direction in FIG. 1 ). For example, the source driver circuit 20 may be connected to a first column of sub-pixels via a first data line to provide a first data signal D1 to the first column of sub-pixels, and may be connected to a second column of sub-pixels via a second data line to provide a second data signal D2 to the second column of sub-pixels, and so on.

[0079] For example, when the first row of sub-pixels is turned on, the source driver circuit 20 can provide M data signals D11, D12, ..., D1M for the first row of sub-pixels via M data lines; when the second row of sub-pixels is turned on, the source driver circuit 20 can provide M data signals D21, D22, ..., D2M for the second row of sub-pixels via multiple data lines, and so on. Of course, the embodiments of the present disclosure are not limited to this, and this will be further described below.

[0080] In some embodiments, the display device 100 may further include a main control board 40 and a timing controller 30. The main control board 40 is connected to the timing controller 30 for transmitting the initial data frame to the timing controller 30. The timing controller 30 is connected to the gate drive circuit 10 and the source drive circuit 20 and can provide relevant control signals to the gate drive circuit 10 and the source drive circuit 20. For example, the timing controller 30 can provide a data control signal TP to the source drive circuit 20, and the source drive circuit 20 can output a data signal for each row under the control of the data control signal TP. The timing controller 30 can also provide other control signals to the source drive circuit 20, including but not limited to a row data start signal, a data synchronization signal, a data inversion signal, etc. The timing controller 30 can also provide various control signals to the gate drive circuit 10, including but not limited to a frame start signal, a clock signal, etc. required by the gate drive circuit 10.

[0081] Figures 2A and 2B show example structural diagrams of a gate drive circuit according to an embodiment of the present disclosure. As shown in Figures 2A and 2B, the gate drive circuit includes multiple stages of cascaded shift register units GOA1, GOA2, ..., GOAN. For example, for a 4K2K (resolution 3840×2160) display panel, the number of horizontal pixels is 3840 and the number of vertical pixels is 2160. If each pixel contains multiple sub-pixels arranged horizontally, the display panel includes 2160 rows of sub-pixels. If the display panel contains 2160 rows of sub-pixels and each shift register unit corresponds to a row of sub-pixels, the number of shift register units included in the gate drive circuit can be 2160.

[0082] Figure 2A shows the first through ninth shift register units GOA1 through GOA9. As shown in Figure 2A, STV1 is a frame start signal. When the gate drive circuit is connected to 8 CLKs, the input terminals "Input" of the first through fourth shift register units GOA1 through GOA4 can be connected to the frame start signal terminal STV1. Following the fourth shift register unit GOA4, the input terminal "Input" of the nth shift register unit GOAn is connected to the output terminal of the n-4th shift register unit GOA(n-4), where 5 ≤ n ≤ N. For example, the output of GOA1 is connected to the input of GOA5, the output of GOA2 is connected to the input of GOA6, the output of G3 is connected to the input of GOA7, the output of G4 is connected to the input of GOA8, the output of G5 is connected to the input of GOA9, and so on. The reset terminal RST of the nth shift register unit GOAn is connected to the output terminal OUT of the n+4th shift register unit GOA(n+4), where 1 ≤ n ≤ N-4. Figure 2B shows the final shift register unit, GOA2160, and the dummy GOA unit (Dummy GOA). As shown in Figure 2B, the last four rows of GOAs can be reset using four rows of Dummy GOAs. For example, Dummy GOA1 (Dum1) resets GOA2157, Dummy GOA2 (Dum2) resets GOA2158, and so on. Each Dummy GOA can be reset using STV1. STV0 is the total reset signal, connected to GOA9 and subsequent units. The waveforms of STV0 and STV1 are identical, so they can be connected together externally.

[0083] The gate drive circuit shown in Figures 2A and 2B uses eight clock signals CLK1 to CLK8, wherein the clock signal terminal CLK of the first-stage shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second-stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the eighth-stage shift register unit GOA8 is connected to receive the eighth clock signal CLK8. In a similar manner, the ninth to sixteenth-stage shift register units GOA9 to GOA16 are connected to receive the first to eighth clock signals CLK1 to CLK8, respectively.

[0084] Each stage of shift register units GOA1, GOA2, ..., GOAN can generate an output signal at its output terminal OUT as a gate drive signal (or gate scan signal) under the control of its clock signal terminal CLK and the signal at its input terminal. For example, the first stage of shift register unit GOA1 generates a first gate drive signal G1, the second stage of shift register unit GOA2 generates a second gate drive signal G2, and so on. By cascading, the gate drive signal generated by one stage of shift register unit can be shifted relative to the gate drive signal generated by another stage of shift register unit.

[0085] The above is merely an example of a display device according to an embodiment of the present disclosure. The structure of the display device according to the embodiment of the present disclosure is not limited thereto and may have other structures as needed. For example, the display device may be a display device based on liquid crystal display (LCD) technology or a display device based on organic light emitting diode (OLED) display technology. The gate drive circuit of the display device may adopt a cascade method different from that shown in Figures 2A and 2B. For example, 10 or 12 clock signals may be cascaded in a different manner.

[0086] FIG3A shows a signal timing diagram for a display method. The signal timing of FIG3A is described below using the display device of FIG1 , FIG2A , and FIG2B as an example. As shown in FIG3A , when each frame of an image is displayed, the gate drive circuit 10 sequentially generates a first gate drive signal G1, a second gate drive signal G2, a third gate drive signal G3, a fourth gate drive signal G4, and so on, at preset time intervals. The phase difference between the start time at which data signals are written to sub-pixels in two adjacent rows is H. In FIG3A , the effective level duration of each gate drive signal is, for example, 4 hours.

[0087] For the first row of sub-pixels, during periods T1 to T4, the first gate drive signal G1 is at a high level, causing the first row of sub-pixels to be in the on state. The lengths of periods T1 to T4 are all H, meaning the first sub-pixels are on for 4 hours. During period T4, the first high-level pulse of the data control signal TP arrives, thereby controlling the source driver circuit 20 to apply the data signal DATA1 for the first row of sub-pixels (also referred to as the first row data signal) to the first row of sub-pixels in the on state. The first row data signal DATA1 may include M data signals D11, D12, ..., D1M, respectively, for the M sub-pixels in the first row, where data signal D11 is provided to the first row, first column sub-pixel, data signal D12 is provided to the second row, ..., and data signal D1M is provided to the Mth column sub-pixel in the first row.

[0088] Similarly, for the second row of sub-pixels, during periods T2 to T5, the second gate drive signal G2 is at a high level, turning on the second row of sub-pixels. During period T5, a second high-level pulse of the data control signal TP arrives, thereby controlling the source driver circuit 20 to apply data signals (also referred to as second-row data signals) DATA2 for the second row of sub-pixels to the turned-on second row of sub-pixels. The second-row data signals DATA2 may include M data signals D21, D22, ..., D2M for the M sub-pixels in the second row, respectively. Data signal D21 is provided to the sub-pixel in the first column of the second row, data signal D22 is provided to the sub-pixel in the second column of the second row, ..., and data signal D2M is provided to the sub-pixel in the Mth column of the second row. The same applies to the sub-pixels in other rows.

[0089] FIG3B shows a signal timing diagram for another display method. As shown in FIG3B , the effective level duration of each gate drive signal is, for example, 3.2 hours, so that each row of sub-pixels is in the on state for 3.2 hours, but the time for writing the data signal to each row of sub-pixels is 1 hour, that is, the actual charging time is 1 hour. In addition, in the embodiment of the present disclosure, both the frame start signal and the gate drive signal are taken as an example of an effective level of high level. In this case, the starting time of the effective level is the rising edge of the gate drive signal, and the ending time of the effective level is the falling edge of the gate drive signal.

[0090] From the above two examples, it can be seen that for each row of sub-pixels, although the turn-on time of each row of sub-pixels is multiple times the unit scan time, the length of time that the data signal is written to each row of sub-pixels (also called the actual charging time) is only one time the unit scan time H, that is, the phase difference between the rising edges of the gate drive signals of the two rows of gate lines. Taking an 8K display device with a resolution of 7680×4320 as an example, when the refresh rate is 60Hz, the scan time for 1 frame is 1 / 60 second, that is, the time spent scanning 4320 rows of sub-pixels is 1 / 60 second, then the time spent scanning each row of sub-pixels (that is, the unit scan time) H=1 / 60÷4320≈3.7us. When the refresh rate is 120Hz, the unit scan time H is 1.85us, which is too short to fully charge the sub-pixels, thereby affecting the display.

[0091] In addition, in some embodiments, the frame start signal line STV1, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5 and the sixth clock signal line CLK6 are arranged in sequence in a first direction (e.g., horizontally). Due to the long distance between these signal lines, capacitance may be formed between adjacent signal lines. A capacitance may be formed between the start pulse signal line STV1 and the first clock signal line CLK1; similarly, a capacitance may be formed between the first clock signal line CLK1 and the second clock signal line CLK2, and a capacitance may be formed between the second clock signal line CLK2 and the third clock signal line CLK3, and so on. A CLK signal may cause adjacent CLK signals to be disturbed during the process of pulling up or pulling down. For example, the falling edge of the clock signal CLK1 may cause a pull-down disturbance to the clock signal CLK2. Accordingly, the gate drive signal G2 corresponding to the clock signal CLK2 is also subjected to a pull-down disturbance during the charging cycle, resulting in the charging time of the second row of sub-pixels being affected.

[0092] When the falling edge of the frame start signal STV1 is aligned with the falling edge of the clock signal CLK1, or when the falling edge of the frame start signal STV1 is earlier than the falling edge of the clock signal CLK1 and the phase difference between the two falling edges is large, the output signal (gate drive signal) corresponding to the first clock signal line CLK1 will not be disturbed by the frame start signal line STV1 during the charging cycle, or the disturbance is very small. In addition, the falling edges of other clock signals are later than the falling edge of the clock signal CLK1. Therefore, the output signal corresponding to the first clock signal line CLK1 will not be disturbed by other clock signals during the charging cycle. Since the output signal corresponding to the first clock signal line CLK1 is not disturbed by other signals during the charging cycle, the charging rate of the pixels in the corresponding row is normal. However, the output signals corresponding to the second clock signal line CLK2 to the eighth clock signal line CLK8 are disturbed during the charging cycle, so the charging rate of the pixels in the corresponding row is low. The waveforms of the gate drive signals corresponding to clock signal CLK1 and clock signals CLK2-CLK8 differ. From a macroscopic perspective, this can cause periodic horizontal fine lines to appear on the display panel, with eight rows of sub-pixels forming one cycle. Consequently, the display screen exhibits horizontal lines. Therefore, balancing the disturbances experienced by each clock signal is a critical issue.

[0093] The present disclosure provides a display method for a display device, comprising: applying a frame start signal and a plurality of clock signals to a gate drive circuit 10, so that the gate drive circuit 10 outputs a plurality of gate drive signals to a sub-pixel array based on the frame start signal and the plurality of clock signals, wherein the sub-pixel array comprises N rows of gate lines and M columns of data lines, the N rows of gate lines and the M columns of data lines being cross-arranged to define a plurality of sub-pixels in an N×M array; scanning the sub-pixel array one by one or more rows by using a plurality of gate drive signals, so as to turn on each scanned row of sub-pixels, so that the time length during which two adjacent rows of sub-pixels are simultaneously in an on state is greater than or equal to 2 times of a unit scan time, where the unit scan time is the time required to scan a row of sub-pixels, wherein N and M are both integers greater than 1; and scanning the sub-pixel array by at least one of the plurality of gate drive signals that are simultaneously in an on state. Two rows of sub-pixels are applied with data signals, so that the duration for which the data signals are applied to at least some rows of sub-pixels is greater than the unit scanning time; wherein, the gate drive circuit 10 includes N shift register units respectively connected to the N rows of sub-pixels in the sub-pixel array, and the first shift register unit among the N shift register units is connected to the first row of sub-pixels in the sub-pixel array; the multiple clock signals include a first clock signal for driving the first shift register unit to output a gate drive signal; wherein, the rising edge of the frame start signal is earlier than the rising edge of the first clock signal, the falling edge of the frame start signal is no later than the falling edge of the first clock signal, and the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is greater than or equal to 0.2 times the unit scanning time and less than or equal to 0.6 times H.

[0094] The display method provided by the embodiments of the present disclosure applies data signals to at least two rows of sub-pixels that are simultaneously in the on state, ensuring that the duration of the data signal applied to each row of sub-pixels is greater than the unit scan time. Furthermore, this method can balance the interference experienced by the clock signal CLK1 and subsequent clock signals, improve the phenomenon of horizontal stripes, and achieve better display effects.

[0095] The embodiments of the present disclosure and some examples thereof are described in detail below with reference to the accompanying drawings.

[0096] Fig. 4 shows a flow chart of a display method of a display device according to an embodiment of the present disclosure. As shown in Fig. 4 , the display method includes steps S401 to S403.

[0097] Step S401 : the timing controller 30 applies a frame start signal and a plurality of clock signals to the gate driving circuit 10 .

[0098] Step S402: The gate drive circuit 10 outputs multiple gate drive signals to the subpixel array based on the frame start signal and multiple clock signals. The gate drive circuit 10 uses the multiple gate drive signals to scan the subpixel array row by row or multiple rows, turning on the subpixels in each scanned row, so that the duration for which the subpixels in two adjacent rows are simultaneously turned on is greater than or equal to 2 hours. The subpixel array includes multiple subpixels arranged in an N×M array, where N and M are both integers greater than 1.

[0099] Step S403 : the source driving circuit 20 applies data signals to at least two rows of sub-pixels that are simultaneously in the on state, so that the duration for which the data signals are applied to at least some rows of sub-pixels is greater than the unit scanning time.

[0100] For example, the multiple clock signals may include 8 clock signals. The N shift register units are divided into multiple groups according to the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group receive 8 clock signals respectively. For example, the gate drive circuit 10, the frame start signal, the clock signal, the gate drive signal, the data signal, etc. can be referred to Figures 1, 2A and 2B for the above-mentioned related description, and will not be repeated here.

[0101] For example, in the first time period, the nth row of sub-pixels and the n+1th row of sub-pixels are turned on in sequence, where n is an integer and 1≤n≤N-3; in the second time period, the n+2th row of sub-pixels and the n+3th row of sub-pixels are turned on in sequence, and one of the nth row of data signals and the n+1th row of data signals is applied to the nth row of sub-pixels and the n+1th row of sub-pixels, and the length of the second time period is greater than or equal to 2 times the unit scanning time; in the third time period, the nth row of sub-pixels is turned off, and one of the n+2th row of data signals and the n+3th row of data signals is applied to the n+1th row of sub-pixels, the n+2th row of sub-pixels and the n+3th row of sub-pixels.

[0102] FIG5 shows a timing diagram of a display method according to an embodiment of the present disclosure.

[0103] As shown in FIG5 , during period T1 (the first period), the first row of sub-pixels and the second row of sub-pixels are sequentially turned on. For example, during the first sub-period T11 of the first period T1, the first gate drive signal G1 is at a high level, thereby turning on the first row of sub-pixels; and during the second sub-period T12 of the first period T1, the second gate drive signal G2 is at a high level, thereby turning on the second row of sub-pixels.

[0104] In period T2 (second period), the third row of sub-pixels and the fourth row of sub-pixels are sequentially turned on, and data signals are applied to the first row of sub-pixels and the second row of sub-pixels. For example, upon the arrival of the first high-level pulse of the data control signal TP, the source driver circuit 20 applies one of the first row of data signals DATA1 and the second row of data signals DATA2 (in this embodiment, the first row of data signals DATA1) to the first row of sub-pixels and the second row of sub-pixels.

[0105] In period T3 (third period), the first row of sub-pixels is turned off, and data signals are applied to the second row of sub-pixels, the third row of sub-pixels, and the fourth row of sub-pixels. For example, upon the arrival of the second high-level pulse of the data control signal TP, one of the third row of data signal DATA3 and the fourth row of data signal DATA4 is applied to the second row of sub-pixels, the third row of sub-pixels, and the fourth row of sub-pixels that are in the turned-on state.

[0106] Similarly, for the third and fourth rows of sub-pixels, the first period is period T2 in FIG. 5 , the second period is periods T3 and T4 in FIG. 5 , and the third period is period T5 in FIG. During period T2, the third and fourth rows of sub-pixels are sequentially turned on. For example, during the first sub-period T21 of period T2, the third gate drive signal G3 is at a high level, thereby turning on the third row of sub-pixels. During the second sub-period T22 of period T2, the fourth gate drive signal G4 is at a high level, thereby turning on the fourth row of sub-pixels. During periods T3 and T4, the fifth and sixth rows of sub-pixels are sequentially turned on, and one of the third row data signal DATA3 and the fourth row data signal DATA4 is applied to the third and fourth rows of sub-pixels. During period T5, the third row of sub-pixels is turned off, and one of the fifth row data signal DATA5 and the sixth row data signal DATA6 is applied to the fourth, fifth, and sixth rows of sub-pixels.

[0107] The length of the second time period can be set to be greater than or equal to 2H, so that the length of time that the data signal is applied to each row of sub-pixels is greater than or equal to 2H. For example, in the example of Figure 5, the time period in which the data signal is applied to the sub-pixels in the first row is time period T2, and the time period in which the data signal is applied to the sub-pixels in the second row is time periods T2 and T3. The lengths of time periods T1 and T2 can be set to 2H, and the length of time period T3 can be set to H. In this case, the actual charging time of the sub-pixels in the first row is 2H (the length of time period T2), and the actual charging time of the sub-pixels in the second row is 3H (the sum of the lengths of time periods T2 and T3). Similarly, the actual charging time of the sub-pixels in the third row is 2H, and the actual charging time of the sub-pixels in the fourth row is 3H.

[0108] In the embodiments of the present disclosure, by sequentially turning on two rows of sub-pixels and applying data signals to the two rows of sub-pixels that are simultaneously turned on, the actual charging time of some sub-pixels (e.g., the sub-pixels in the odd rows) can be 2 hours or longer, while the actual charging time of another portion of sub-pixels (e.g., the sub-pixels in the even rows) can be 3 hours or longer. For example, the data written to the sub-pixels in the even rows may be the data of the two adjacent pixels in the odd rows.

[0109] For example, the gate drive circuit 10 includes N shift register units respectively connected to N rows of sub-pixels in the sub-pixel array, wherein the N shift register units include a first-stage shift register unit (e.g., GOA1) connected to the first row of sub-pixels in the sub-pixel array. The multiple clock signals include a first clock signal (e.g., CLK1) for driving the first-stage shift register unit to output a gate drive signal. For example, in the disclosed embodiment, the shift register unit connected to the first row of sub-pixels is referred to as the first-stage shift register unit.

[0110] FIG6 shows a timing diagram of a frame start signal and a clock signal according to an embodiment of the present disclosure.

[0111] As shown in Figure 6, the high level duration of the frame start signal STV does not exceed the number of corresponding clock signals. For example, the high level time of the frame start signal STV does not exceed the number of corresponding clock signals CLK, that is, 8CLK, then the high level time of STV does not exceed 8H, which can be 8H or 7H or 6H. In this example, the effective level time of STV is 6H. The rising edge of the frame start signal STV is earlier than the rising edge of the first clock signal CLK1, and the falling edge of the frame start signal STV is not later than the falling edge of the first clock signal CLK1. The phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is greater than or equal to 0.2H and less than or equal to 0.6H. Based on this setting, poor display can be improved to achieve better display effects. Figure 7 shows a schematic diagram of the frame start signal line and the clock signal line according to an embodiment of the present disclosure.

[0112] As shown in Figures 6 and 7, if the falling edge of the frame start signal line STV is aligned with the falling edge of the clock signal line CLK1, then the frame start signal line STV will not cause pull-down interference to the clock signal CLK1 when it is pulled down. The width of the frame start signal line STV is greater than the width of the clock signal line CLK, so the resistance of the frame start signal line STV is greater than the resistance of the clock signal line CLK. When the falling edge of the frame start signal line STV is earlier than the falling edge of the first clock signal line CLK1, and the phase difference between the falling edge of the frame start signal line STV and the falling edge of the first clock signal line CLK1 is, for example, 1 hour or greater, the falling edge of the frame start signal STV when pulled down is relatively slow, thereby having a smaller impact on the first clock signal line CLK1 and not being balanced with the interference to the second clock signal CLK2 and subsequent clock signals. In the embodiment of the present disclosure, the phase difference between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is set to 0.2H~0.6H. In this way, the frame start signal STV can have a greater pull-down effect on the first clock signal CLK1, thereby balancing the interference of the first clock signal CLK1 and the clock signals thereafter, improving the phenomenon of poor horizontal stripes, and achieving a better display effect.

[0113] For example, the first-stage shift register unit to the P-th-stage shift register unit in the N shift register units are connected to the frame start signal; the multiple clock signals CLK also include the P-th clock signal CLK for driving the P-th-stage shift register unit to output a gate drive signal; the duty cycle of each clock signal CLK is greater than or equal to 40% and less than or equal to 45%, and the phase difference and duty cycle are configured so that the falling edge of the frame start signal STV is aligned with the rising edge of the P-th clock signal, and P is an integer greater than 1.

[0114] For example, the value of P is related to the number of clock signals connected to the gate drive circuit 10. When the gate drive circuit 10 is connected to an 8CLK signal, P is 4; when the gate drive circuit 10 is connected to a 12CLK signal, P is 6.

[0115] For example, if the frame revelation signal STV is connected to the first through fourth stage shift register units, the P-th stage shift register unit is the fourth stage shift register unit. Setting the phase difference between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 to 0.2H to 0.6H, setting the duty cycle of the clock signal to 40% to 45%, and coordinating the phase difference and duty cycle so that the falling edge of the frame start signal is aligned with the rising edge of the fourth clock signal CLK4 can further improve display defects and achieve a good display effect.

[0116] For example, in some embodiments, the phase difference between the rising edges of each two adjacent clock signals in the plurality of clock signals is 1 hour, the phase difference between the falling edge of the frame start signal and the falling edge of the first clock signal is 0.2 times the unit scan time, and the duty cycle of each clock signal is 40%. For example, as shown in FIG6 , the high-level duration t1 of the frame start signal STV is 6 hours, the high-level duration t3 of each clock signal CLK is 3.2 hours, and the cycle time t4 of the clock signal CLK is 8 hours, so the duty cycle of the clock signal is 3.2 / 8 = 40%. The phase difference t2 between the rising edge of the frame start signal STV and the rising edge of the first clock signal CLK1 is 5 hours, the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is 0.2 hours, and the start and end times of the clock signals CLK differ by t5 by 1 hour. The rising edge of the fourth clock signal CLK4 is aligned with the falling edge of the frame start signal STV. That is to say, when the phase difference between the clock signals CLK is 1H, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the first clock signal CLK1 is 0.2H and the duty cycle of the clock signal is 40%, the rising edge of the fourth clock signal CLK4 can be aligned with the falling edge of the frame start signal STV.

[0117] For example, in some other embodiments, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.3H, the duty cycle of the clock signal is set to 3.3 / 8=41.25%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. For another example, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.4H, the duty cycle of the clock signal is set to 3.4 / 8=42.5%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV. For another example, when the phase difference t6 between the falling edge of the frame start signal STV and the falling edge of the clock signal CLK1 is 0.6H, the duty cycle of the clock signal is set to 3.6 / 8=45%, so that the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV.

[0118] For example, when the rising edge of the clock signal CLK4 is aligned with the falling edge of the frame start signal STV, when the frame start signal STV ends, the clock signal CLK4 immediately starts to rise, generating a second-order PU, fully controlling the GOA output, and avoiding leakage of the PU point in the shift register unit, so that each sub-pixel can achieve a better charging effect.

[0119] For example, setting the clock signal's duty cycle to 40% to 45% can also improve poor display in some situations. The clock signal's duty cycle is typically 50%, but when the duty cycle is 50%, poor display may occur due to in-plane coupling and other factors. The disclosed embodiments set the duty cycle to 40% to 45%, which can address poor display in this situation.

[0120] The embodiment of the present disclosure further provides a display method for a display device. The display device has the same structure as the above, and also includes a main control board 40, a timing controller 30, a source driving circuit 20, a gate driving circuit 10, and a sub-pixel array.

[0121] The display method of the embodiment of the present disclosure mainly improves the problem of insufficient sub-pixel charging time caused by high refresh rate by designing the timing of the clock signal CLK and the frame start signal STV. The display method of the embodiment of the present disclosure specifically includes the following steps:

[0122] The main control board 40 receives the initial data frame and divides the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered row data of the initial data frame, and the second target data frame includes even-numbered row data of the initial data frame.

[0123] The timing controller 30 applies a frame start signal STV and a plurality of clock signals CLK to the gate driving circuit 10 , and applies a source control signal to the source driving circuit 20 .

[0124] The gate drive circuit 10 provides gate drive signals for multiple rows of gate lines based on the frame start signal and multiple clock signals CLK, and for the k-th row of gate lines and the k+2-th row of gate lines in the scanning order, the starting moment of the effective level of the gate drive signal written into the k+2-th row of gate lines and the starting moment of the effective level of the gate drive signal written into the k-th row of gate lines have a phase difference of 2H; H is half of the phase difference of the rising edge of the gate drive signal written into the k-th row of gate lines and the k+2-th row of gate lines in the scanning order; k is a positive integer.

[0125] Based on the source control signal and the gate drive signal, the source drive circuit 20 writes the data signal of the first target data frame into the odd-row sub-pixels row by row; and the source control signal and the gate drive signal satisfy: the start time of data writing of the 2kth row sub-pixels is not later than the end time of data writing of the 2k-1th row sub-pixels, and the end time of data writing of the 2kth row sub-pixels is not earlier than the start time of data writing of the 2k+1th row sub-pixels.

[0126] Based on the source control signal and the gate drive signal, the source drive circuit 20 writes the data signal of the second target data frame into the even-row sub-pixels row by row; and the source control signal and the gate drive signal satisfy: the start time of the data writing of the 2k+1th row sub-pixel is not later than the end time of the data writing of the 2kth row sub-pixel, and the end time of the data writing of the 2k+1th row sub-pixel is not earlier than the start time of the data writing of the 2k+2th row sub-pixel. In the embodiment of the present disclosure, mainly for the display of a display device whose refresh frequency is doubled compared with the previous refresh frequency (for example, 60Hz is increased to 120Hz), first, the main control board 40 splits the received initial data frame into two frames according to the odd-row data and the even-row data. The two frames of data formed by the split are respectively referred to as the first target frame data and the second target frame data. The resolution of these two frames of data is halved compared with the initial data frame. In this way, the data amount remains unchanged and the refresh rate is doubled compared with the previous one. In this case, the gate drive circuit 10 provides gate drive signals for multiple rows of gate lines based on the frame start signal and multiple clock signals CLK in the above manner, and the source drive circuit 20 writes the data signal row by row in the above manner. In this way, when the display device displays the first target data frame, the sub-pixels in the odd rows are all written with real data, and the sub-pixels in the even rows are written with the data interpolation of the two odd rows above and below the even row. Similarly, when the display device displays the second target data frame, the sub-pixels in the even rows are all written with real data, and the sub-pixels in the odd rows are written with the data interpolation of the two even rows above and below the odd row. In this way, the charging rate of each sub-pixel is guaranteed when the refresh rate is doubled.

[0127] In some examples, the timing controller 30 may apply a single or multiple frame start signals STV to the gate driver circuit 10, such as one, two, or three. When multiple frame start signals STV are provided, one of the frame start signals STV is a global reset signal having the same waveform as the first frame start signal STV. The number of clock signals CLK applied by the timing controller 30 to the gate driver circuit 10 is generally a multiple of four, such as 4, 8, 12, or 16 clock signals CLK. In this embodiment, only 8 and 12 clock signals CLK are used as examples.

[0128] Among them, the multiple clock signals CLK include a first clock signal CLK1 for controlling the first-stage shift register unit in the gate drive circuit 10 to output the gate drive signal; the starting time of the effective level of the frame start signal STV output by the timing controller 30 is earlier than the starting time of the effective level of the first clock signal CLK1, and the ending time of the effective level of the frame start signal STV is no later than the ending time of the effective level of the first clock signal CLK1; the phase difference between the ending time of the effective level of the frame start signal STV and the ending time of the effective level of the first clock signal CLK1 is greater than or equal to 0.2H and less than or equal to 0.6H.

[0129] Among them, when there are multiple frame start signals STV, the high level time of the frame start signal STV is generally (2n~4n)H, and its falling edge does not exceed the rising edge of the 2nth clock signal CLK2n, and is generally not later than the falling edge of the first clock signal CLK1. The period of the clock signal CLK is 4nH, and its high level time is less than or equal to 2nH. For example, when n is 3, that is, 12CLK, the period is 12H, and the high level time of the clock signal CLK is 5H. The phase difference of CLK1~CLK4n is 1H respectively. G1~Gs are gate drive signals that are turned on row by row. The total number of rows s is related to the display resolution. For example, for UHD, s is 2160 rows, for 8K, s is 4320 rows, and so on. The phase difference of G1~Gs is 1H time respectively. Data is the data signal of the source drive circuit, and the maintenance time of each data signal is 2H. When the first target data frame is displayed, the end of each data signal can be aligned with the falling edge of the gate drive signal of 2k-1 rows (odd rows). When the second target data frame is displayed, the end of each data signal can be aligned with the falling edge of the gate drive signal of 2k rows (even rows).

[0130] Figure 8A is a schematic diagram of an embodiment of the present disclosure for extracting even-numbered rows of data from an initial data frame. Figure 8B is a schematic diagram of an embodiment of the present disclosure for extracting odd-numbered rows of data from an initial data frame. As shown in Figures 8A and 8B, the main control board 40 extracts odd-numbered rows of data from an initial data frame to form a first target data frame, and extracts even-numbered rows of data from the initial data frame to form a second target data frame. Alternatively, the odd-numbered rows of data from an initial data frame can be extracted to form a second target data frame, and the even-numbered rows of data from the initial data frame can be extracted to form a first target data frame. By decomposing an initial data frame into odd frames and even frames, and using the time originally used to display one frame of data to display two frames of data, the refresh rate of the display panel can be increased, thereby improving the display effect. For ease of description, in some of the following embodiments, odd frames and even frames are used to represent the first target data frame and the second target data frame.

[0131] For example, the display of the kth initial data frame and the k+1th initial data frame includes: the timing controller 30 controls the source driving circuit 20 and the gate driving circuit 10, and controls the sub-pixel array to display frame by frame in the following order: the first target data frame of the kth initial data frame, the second target data frame of the kth initial data frame, the first target data frame of the k+1th initial data frame; the second target data frame of the k+1th initial data frame; or controls the sub-pixel array to display frame by frame in the following order: the second target data frame of the kth initial data frame, the first target data frame of the kth initial data frame, the second target data frame of the k+1th initial data frame, and the first target data frame of the k+1th initial data frame. In this way, the first target data frame and the second target data frame of the initial data frame are displayed alternately. Figure 9 is a schematic diagram of extracting even-numbered row data of the initial data frame according to an embodiment of the present disclosure. As shown in Figure 9, in mode 1 and mode 2, the first target data frame and the second target data frame are displayed alternately. The first initial data frame is an odd frame b1 and an even frame c1, the second initial data frame is an odd frame b2 and an even frame c2, the third initial data frame is an odd frame b3 and an even frame c3, and so on. In mode 1, the odd frame b can be displayed first, and then the even frame c can be displayed, for example, in the order of b1 ~ c1 ~ b2 ~ c2 ~ b3 ~ c3... In mode 2, the even frame c can be displayed first, and then the odd frame b can be displayed, for example, in the order of c1 ~ b1 ~ c2 ~ b2 ~ c3 ~ b3...

[0132] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the second frame, data of the second target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the third frame, data of the second target data frame corresponding to the second initial data frame is applied to the sub-pixel array; in the fourth frame, data of the first target data frame corresponding to the second initial data frame is applied to the sub-pixel array.

[0133] For example, as shown in FIG9 , in modes 3 and 4, the odd and even frames corresponding to each initial data frame are displayed continuously, and two adjacent odd frames are displayed continuously, and two adjacent even frames are displayed continuously. In mode 3, they are displayed in the order of b1 to c1 to c2 to b2 to b3 to c3… In mode 4, they are displayed in the order of c1 to b1 to b2 to c2 to c3 to b3… The driving mode of the odd frames can be the same, and the driving mode of the even frames can be the same. By displaying adjacent odd frames continuously and adjacent even frames continuously, repeated switching of the driving mode can be avoided, efficiency can be improved, and power consumption can be saved.

[0134] For example, in other embodiments, in the first frame, data of the first target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the second frame, data of the first target data frame corresponding to the second initial data frame is applied to the sub-pixel array; in the third frame, data of the second target data frame corresponding to the first initial data frame is applied to the sub-pixel array; in the fourth frame, data of the second target data frame corresponding to the second initial data frame is applied to the sub-pixel array.

[0135] For example, as shown in FIG9 , in modes 5 and 6, the odd frames of two adjacent initial data frames are displayed continuously, and the even frames of two adjacent initial data frames are displayed continuously, and the odd and even frames corresponding to each initial data frame are separated. In mode 5, the sequence of b1 to b2 to c1 to c2 to b3 to b4… is displayed. In mode 6, the sequence of c1 to c2 to b1 to b2 to c3 to c4… is displayed. The driving mode of the odd frames can be the same, and the driving mode of the even frames can be the same. By displaying adjacent odd frames continuously and adjacent even frames continuously, repeated switching of the driving mode can be avoided, efficiency can be improved, and power consumption can be saved.

[0136] Next, a display method in which the timing controller 30 applies 8 clock signals (8CLK) and 12 clock signals (10CLK) to the gate driving circuit 10 will be described.

[0137] The cascade relationship of the 8CLK gate drive circuit 10 is the same as that of Figures 2A and 2B, so it will not be repeated here. Figure 10 is a signal timing diagram showing an odd frame according to an embodiment of the present disclosure; Figure 11 is a signal timing diagram showing an even frame according to an embodiment of the present disclosure; as shown in Figures 10 and 11, 1H=1.85μs; the high level time of the frame start signal STV does not exceed the corresponding clock signal CLK number, that is, 8CLK, then the high level time of STV does not exceed 8H, it can be 8H or 7H or 6H, and the effective level time of STV in this example is 8H. CLK1~CLK8 are periodic waveforms, and the cycle time is fixed to the CLK number, that is, 8H. The high level duty cycle is less than or equal to 50%, such as 4H or 3H or a non-integer. In this example, the high level is 3.2H and the duty cycle is 40%. The high level phase difference of CLK1 to CLK8 is offset by 1H time in sequence.

[0138] In each frame, the gate drive circuit 10 sequentially generates a first gate drive signal G1, a second gate drive signal G2, a third gate drive signal G3, a fourth gate drive signal G4, and so on, up to Gs, at a preset time interval. The high-level widths of G1-Gs are the same as the width of the clock signal CLK, and are sequentially offset by a time width of 1H, i.e., the preset time interval is 1H.

[0139] For each row of sub-pixels, the gate line is written to a high level, and the data line refreshes a row of data signals. Each row of sub-pixels requires 2 hours to write data signals, and the voltage corresponding to the data is charged into the sub-pixel capacitor to complete the data refresh.

[0140] Specifically, referring to Figure 10, the writing time of each row of data signals is 2H, and the termination time of the data signal writing is aligned with the falling edge of the gate drive signal of the 2k-1th row of gate lines in the sub-pixel array. At this time, the data signals written into the 2k-1 rows of sub-pixels in the odd frame are real data; the 2K rows of sub-pixels are in the last 2H of the high level of their corresponding gate drive signals, of which 1H is the data signal written into the 2k-1 sub-pixel, and the other 1H is the data signal written into the 2k+1 sub-pixel. In other words, the data signal actually written into the 2K rows of sub-pixels is the interpolation of the data signal of the 2k-1 sub-pixel and the data signal of the 2k+1 sub-pixel, which is an intermediate grayscale value.

[0141] Similarly, referring to Figure 11, the writing time of each row of data signals is 2H, and the termination time of the data signal writing is aligned with the falling edge of the gate drive signal of the 2k-th row of gate lines in the sub-pixel array. At this time, the data signals written into the 2k rows of sub-pixels in the even frame are real data; the 2K-1 rows of sub-pixels (except the first row of sub-pixels) are in the last 2H of the high level of their corresponding gate drive signals, of which 1H is the data signal written into the 2k-2 sub-pixels, and the other 1H is the data signal written into the 2k sub-pixels. In other words, the data signal actually written into the 2K rows of sub-pixels is the interpolation of the data signal of the 2k-2 sub-pixels and the data signal of the 2k sub-pixels, which is an intermediate grayscale value.

[0142] In the display method of the display device, the timings shown in FIG. 10 and FIG. 11 operate alternately to achieve interleaving of data between frames.

[0143] Figure 12 is a signal timing diagram of the display method of an embodiment of the present disclosure; as shown in Figure 12, this example is the same as the above example, and is also applied to the 8CLK gate drive circuit 10, wherein the connection method of the shift register is the same as the above example. Unlike the above example, in this example, the falling edge of the frame start signal STV is not earlier than the falling edge of the first clock signal.

[0144] Specifically, 1H=3.7μs; the data signal writing time for each row of sub-pixels is 2H, and the high level of the frame start signal STV is 4H-5H. In this example, the high level of the frame start signal STV is 4.5H. CLK1-CLK8 are periodic waveforms, and the cycle time is fixed to the number of CLKs, that is, 8H. The high level duty cycle is less than or equal to 50%, such as 4H or 3H or a non-integer. In this example, the high level is 2.66H, and the duty cycle is 33%. In this example, the first four rows of sub-pixels are not written with data signals. The fifth row of sub-pixels begins to be written with data signals, and the data signal writing time is 2H.

[0145] The clock signals CLK are grouped into groups of two adjacent CLKs, that is, CLK1 and CLK2 are in one group, CLK3 and CLK4 are in one group, CLK5 and CLK6 are in one group, and CLK7 and CLK8 are in one group. For two adjacent groups, the rising edge delay of the two CLKs in one group is less than 1H, and in the embodiment of the present disclosure, the delay is 0.76H; the rising edge delay of the two CLKs in one group is greater than 1H, and in the embodiment of the present disclosure, the delay is 1.24H. Similarly, the rising edge delay of the two clock signals in each group of CLK can be controlled to be greater than 1H, and the rising edge delay of the two clock signals in the other group of CLK can be controlled to be less than 1H. Alternatively, when the rising edge delay of the two clock signals in each group of CLK is 1H, the rising edge delay of the adjacent groups of CLK is also 1H, and the phase relationship of the CLK waveform is the same as the above example. In the embodiment of the present disclosure, the phase difference between the rising edge of the kth clock signal and the rising edge of the k+1th clock signal is 2H.

[0146] Specifically, referring to Figure 12, in this example, the duration T1 of the high level of the frame start signal STV is 4.5H, the durations of the high level and the low level in one cycle of the first clock signal CLK1 are T2 and T3, T2 = 2.66H, T3 = 5.34H; the phase difference between the rising edge of the frame start signal STV and the rising edge of the first clock signal CLK1 is T4, the phase difference between the rising edge of the frame start signal STV and the rising edge of the second clock signal CLK2 is T5, the phase difference between the rising edge of the frame start signal STV and the rising edge of the third clock signal CLK3 is T6, the rising edge of the frame start signal STV and the rising edge of the fourth clock signal CLK The phase difference between the rising edge of the frame start signal STV and the rising edge of the fifth clock signal CLK5 is T7, the phase difference between the rising edge of the frame start signal STV and the rising edge of the sixth clock signal CLK6 is T9, the phase difference between the rising edge of the frame start signal STV and the rising edge of the seventh clock signal CLK7 is T10, and the phase difference between the rising edge of the frame start signal STV and the rising edge of the eighth clock signal CLK8 is T11, T4=1.66; T5=2.42; T6=3.66; T7=4.42; T8=5.66; T9=6.42; T10=7.66; T11=8.42.

[0147] For the writing of a frame of data signals: there is no data signal for the first N / 2 rows of sub-pixels in the sub-pixel array (N is the total number of CLKs, which is 8 in this example), that is, there is no data signal written to the sub-pixels in rows 1 to 4, and the data signal is written starting from the sub-pixels in row 5, and the writing time of the data signal is 2H (T12), and the 1.08H of the first data signal is aligned with the last 1.08H (T13) of the high level of the gate line drive signal of the sub-pixels in row 5, so the writing of the data signal of the sub-pixels in row 5 is completed, and the sub-pixels in row 6 are written with 0.76H of the data signal of the sub-pixels in row 5, and the data signal of the sub-pixels in row 6 is charged in advance for 0.16H, so that the first and second data signals are mixed in row N / 2+2, forming an effect similar to data interpolation.

[0148] Similarly, according to the above timing design, the delay time of the two clock signals of each group of CLK, the delay time of the two clock signals of CLK, and the data interpolation effect in other situations can also be calculated.

[0149] In the above embodiments, the gate driving circuit 10 is described as being connected to 8 CLK signals. In other embodiments, the gate driving circuit 10 may be connected to 12 CLK signals. This case will be described below.

[0150] 13A and 13B show exemplary structural diagrams of another gate driving circuit 10 according to an embodiment of the present disclosure.

[0151] [Corrected 08.02.2025 in accordance with Rule 91] Figure 13A shows the first through thirteenth shift register units GOA1 through GOA13. As shown in Figure 13A, STV1 is a frame start signal. When the gate drive circuit 10 is connected to 12 CLKs, the input terminals "Input" of the first through sixth shift register units GOA1 through GOA6 can be connected to the frame start signal terminal STV1. Following the sixth shift register unit GOA4, the input terminal "Input" of the nth shift register unit GOAn is connected to the output terminal of the n-6th shift register unit GOA(n-4), where 7 ≤ n ≤ N. For example, the output of GOA1 is connected to the input of GOA7, the output of GOA2 is connected to the input of GOA8, the output of GOA3 is connected to the input of GOA9, the output of GOA4 is connected to the input of GOA10, the output of G5 is connected to the input of GOA11, and so on. The reset terminal RST of the nth stage shift register unit GOAn is connected to the output terminal OUT of the n+6th stage shift register unit GOA(n+6), where 1≤n≤N-6. FIG13B shows the last stage shift register unit GOA4320 and the dummy shift register unit (Dummy GOA). As shown in FIG13B, the last six rows of GOAs can be reset by six rows of Dummy GOAs, for example, Dummy GOA1 (Dum1) resets GOA4315, Dummy GOA2 (Dum2) resets GOA4316, and so on, and each Dummy GOA can be reset by STV1.

[0152] The gate drive circuit 10 shown in Figures 13A and 13B uses 12 clock signals CLK1 to CLK12, wherein the clock signal terminal CLK of the first-stage shift register unit GOA1 is connected to receive the first clock signal CLK1, the clock signal terminal CLK of the second-stage shift register unit GOA2 is connected to receive the second clock signal CLK2, and so on. The clock signal terminal CLK of the 12th-stage shift register unit GOA12 is connected to receive the 12th clock signal CLK12. In a similar manner, the 13th to 24th-stage shift register units GOA13 to GOA24 are connected to receive the first to twelfth clock signals CLK1 to CLK12, respectively.

[0153] Each stage of shift register units GOA1, GOA2, ..., GOAN can generate an output signal at its output terminal OUT as a gate drive signal (or gate scan signal) under the control of its clock signal terminal CLK and the signal at its input terminal. For example, the first stage of shift register unit GOA1 generates a first gate drive signal G1, the second stage of shift register unit GOA2 generates a second gate drive signal G2, and so on. By cascading, the gate drive signal generated by one stage of shift register unit can be shifted relative to the gate drive signal generated by another stage of shift register unit.

[0154] For example, the GOA cascade relationship with a period of 12CLK can be applied to 8K4K products, referred to as 8K.

[0155] Figure 14 is a signal timing diagram showing an odd-numbered frame according to an embodiment of the present disclosure; Figure 15 is a signal timing diagram showing an even-numbered frame according to an embodiment of the present disclosure; as shown in Figures 14 and 15, 1H = 1.85μs; the high-level duration of the frame start signal STV does not exceed the corresponding number of clock signals CLK, that is, 12CLK, so the high-level duration of the frame start signal STV does not exceed 12H, and can be 6H to 12H. In this example, the high-level duration of STV is 9H. CLK1 to CLK12 are periodic waveforms, and the cycle time is fixed to the number of CLKs, that is, 12H. The high-level duty cycle is less than or equal to 50%, such as 6H or 5H or a non-integer. In this example, the high level is 5H and the duty cycle is 40%. The high-level phase difference of CLK1 to CLK12 is offset by 1H time respectively. The falling edge of the frame start signal STV is aligned with the falling edge of the first clock signal CLK1.

[0156] In each frame, the gate drive circuit 10 sequentially generates a first gate drive signal G1, a second gate drive signal G2, a third gate drive signal G3, a fourth gate drive signal G4, and so on, up to Gs, at a preset time interval. The high-level widths of G1-Gs are the same as the width of the clock signal CLK, and are sequentially offset by a time width of 1H, i.e., the preset time interval is 1H.

[0157] For each row of sub-pixels, the gate line is written to a high level, and the data line refreshes a row of data signals. Each row of sub-pixels requires 2 hours to write data signals, and the voltage corresponding to the data is charged into the sub-pixel capacitor to complete the data refresh.

[0158] Specifically, referring to Figure 14, the writing time of each row of data signals is 2H, and the termination time of the data signal writing is aligned with the falling edge of the gate drive signal of the 2k-1th row of gate lines in the sub-pixel array. At this time, the data signals written into the 2k-1 rows of sub-pixels in the odd frame are real data; the 2K rows of sub-pixels are in the last 2H of the high level of their corresponding gate drive signals, of which 1H is the data signal written into the 2k-1 sub-pixel, and the other 1H is the data signal written into the 2k+1 sub-pixel. In other words, the data signal actually written into the 2K rows of sub-pixels is the interpolation of the data signal of the 2k-1 sub-pixel and the data signal of the 2k+1 sub-pixel, which is an intermediate grayscale value.

[0159] Similarly, referring to Figure 15, the writing time of each row of data signals is 2H, and the termination time of the data signal writing is aligned with the falling edge of the gate drive signal of the 2k-th row of gate lines in the sub-pixel array. At this time, the data signals written into the 2k rows of sub-pixels in the even frame are real data; the 2K-1 rows of sub-pixels (except the first row of sub-pixels) are in the last 2H of the high level of their corresponding gate drive signals, of which 1H is the data signal written into the 2k-2 sub-pixels, and the other 1H is the data signal written into the 2k sub-pixels. In other words, the data signal actually written into the 2K rows of sub-pixels is the interpolation of the data signal of the 2k-2 sub-pixels and the data signal of the 2k sub-pixels, which is an intermediate grayscale value.

[0160] In the display method of the display device, the timings shown in FIG. 14 and FIG. 15 operate alternately to achieve interleaving of data between frames.

[0161] 1 , the embodiment of the present disclosure provides a display device, including a main control board 40, a timing controller 30, a gate drive circuit 10, a source drive circuit 20, and a sub-pixel array; the sub-pixel array includes a plurality of gate lines and a plurality of data lines, and a plurality of sub-pixels defined by the intersection of the gate lines and the data lines; wherein the main control board 40 is configured to receive an initial data frame and divide the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered row data of the initial data frame, and the second target data frame includes even-numbered row data of the initial data frame. The timing controller 30 is configured to apply a frame start signal STV and a plurality of clock signals CLK to the gate drive circuit 10, and to apply a source control signal TP to the source drive circuit 20; the gate drive circuit 10 provides a gate drive signal for a plurality of rows of gate lines based on the frame start signal STV and the plurality of clock signals CLK; the source drive circuit 20 controls the start time of writing the data signal of each row of sub-pixels based on the source control signal TP, and the phase difference between the start time of writing the effective level of the gate drive signal written to the gate line connected to the row of sub-pixels is 2H; H is half of the starting time phase difference of the effective level of the gate drive signal written into the kth row gate line and the k+2th row gate line in the scanning order; k is a positive integer; wherein, the source control signal and the gate drive signal generated by the timing controller 30, when the source drive circuit 20 writes the data signal of the first target data frame into the odd-numbered rows of sub-pixels row by row, the source control signal and the gate drive signal satisfy: the starting time of the data writing into the 2kth row sub-pixel is not later than the ending time of the data writing into the 2k-1th row sub-pixel, and the number of the 2kth row sub-pixel is The end time of data writing is no earlier than the start time of data writing of the 2k+1th row of sub-pixels; the source control signal and gate drive signal generated by the timing controller 30 write the data signal of the second target data frame into the even-row sub-pixels row by row in the source drive circuit 20; and the source control signal and the gate drive signal satisfy: the start time of data writing of the 2k+1th row of sub-pixels is no later than the end time of data writing of the 2kth row of sub-pixels, and the end time of data writing of the 2k+1th row of sub-pixels is no earlier than the start time of data writing of the 2k+2th row of sub-pixels.

[0162] The present disclosure also provides an electronic device. Figure 17 shows a schematic diagram of an electronic device according to an embodiment of the present disclosure. As shown in Figure 17, the electronic device 1 may include a display device 100. Furthermore, the electronic device 1 may also include components such as a processor. The display device 100 can be referred to as the display device in the above embodiment and will not be described in detail here.

[0163] For example, the electronic device 1 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, etc., or a combination of any electronic device and hardware, which is not limited in the embodiments of the present disclosure.

[0164] It should be noted that for the sake of clarity and brevity, the embodiments of the present disclosure do not provide all components of the electronic device 1. To achieve the necessary functions of the electronic device, those skilled in the art may provide and configure other components not shown according to specific needs, and the embodiments of the present disclosure are not limited thereto.

[0165] For the relevant description and technical effects of the electronic device 1 , reference may be made to the relevant description and technical effects of the frequency divider provided in the embodiments of the present disclosure, which will not be repeated here.

[0166] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display method, which is applied to a display device, wherein the display device includes a main control board, a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; The sub-pixel array includes a plurality of gate lines and a plurality of data lines, and a plurality of sub-pixels defined by the intersection of the gate lines and the data lines; wherein, The display method comprises: The main control board receives an initial data frame, and divides the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered row data of the initial data frame, and the second target data frame includes even-numbered row data of the initial data frame; The timing controller applies a frame start signal and a plurality of clock signals to the gate driving circuit, and applies a source control signal to the source driving circuit; The gate driving circuit provides a gate driving signal for the plurality of rows of gate lines based on the frame start signal and the plurality of clock signals; The source driving circuit controls the start time of writing the data signal of each row of sub-pixels based on the source control signal, and the phase difference between the start time of writing the effective level of the gate driving signal written into the gate line connected to the row of sub-pixels is 2H; H is half of the start time phase difference of the effective level of the gate driving signal written into the kth row of gate lines and the k+2th row of gate lines in the scanning order; k is a positive integer; wherein, Based on the source control signal and the gate drive signal, the source drive circuit writes the data signal of the first target data frame into the odd-numbered rows of sub-pixels row by row; and the source control signal and the gate drive signal satisfy: the start time of data writing into the 2kth row of sub-pixels is not later than the end time of data writing into the 2k-1th row of sub-pixels, and the end time of data writing into the 2kth row of sub-pixels is not earlier than the start time of data writing into the 2k+1th row of sub-pixels; Based on the source control signal and the gate drive signal, the source drive circuit writes the data signal of the second target data frame into the sub-pixels of the even rows row by row; and the source control signal and the gate drive signal satisfy: the start time of the data writing of the sub-pixels in the 2k+1th row is not later than the end time of the data writing of the sub-pixels in the 2kth row, and the end time of the data writing of the sub-pixels in the 2k+1th row is not earlier than the start time of the data writing of the sub-pixels in the 2k+2th row.

2. The display method according to claim 1, wherein: The duration during which the gate drive signals written into two adjacent rows of sub-pixels are simultaneously at an effective level is not less than 2H.

3. The display method according to claim 1, wherein: The gate driving circuit comprises a plurality of shift register units; one shift register unit is connected to one gate line, and different shift register units are connected to different gate lines; The plurality of clock signals include a first clock signal for controlling a first stage shift register unit in the gate driving circuit to output a gate driving signal; Among them, the starting time of the effective level of the frame start signal output by the timing controller is earlier than the starting time of the effective level of the first clock signal; the phase difference between the ending time of the effective level of the frame start signal and the ending time of the effective level of the first clock signal is greater than or equal to 0.2H and less than or equal to 0.6H.

4. The display method according to claim 3, wherein: The gate driving circuit includes N stages of shift register units; the first stage shift register unit to the P stage shift register unit are connected to the frame start signal; the multiple clock signals also include a Pth clock signal for controlling the Pth stage shift register unit to output a gate driving signal; the duty cycle of each of the clock signals is less than or equal to 50%, and N is greater than P; And P is an integer greater than 1.

5. The display method according to claim 4, wherein: The phase difference between the starting time of the effective level of each two adjacent clock signals among the multiple clock signals is 1H, the ending time of the effective level of the frame start signal is not later than the ending time of the effective level of the first clock signal, and the duty cycle of each of the clock signals is greater than or equal to 40% and less than or equal to 45%.

6. The display method according to claim 5, wherein: The duty cycle of each of the clock signals is 40%, the duration of the effective level of the gate drive signal is 3.2H; the phase difference between the termination time of the effective level of the frame start signal and the termination time of the effective level of the first clock signal is 0.2H; The multiple clock signals include 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group receive the 8 clock signals respectively; The timing controller writes the frame start signal into the first-stage shift register unit to the fourth-stage shift register unit among the N shift register units.

7. The display method according to claim 4, wherein: The termination time of the effective level of the frame start signal is later than the termination time of the effective level of the first clock signal; the phase difference between the starting time of the effective level of the gate drive signal applied to the k-th gate line and the K+1-th gate line is 1H; every two adjacent clock signals form a group, and for adjacent groups of clock signals, the timing controller controls the phase difference of the starting time of the effective level of one group of clock signals to be less than 1H, and the phase difference of the starting time of the effective level of the other group of clock signals to be greater than 1H.

8. The display method according to claim 7, wherein: The duty cycle of each of the clock signals is 33%, and the duration of the effective level of the gate drive signal is 2.66H; for adjacent groups of clock signals, the timing controller controls the phase difference of the starting time of the effective level of one group of clock signals to be 0.76H, and the phase difference of the starting time of the effective level of the other group of clock signals to be 1.24H; The multiple clock signals include 8 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group includes 8 shift register units, and the 8 shift register units in each group receive the 8 clock signals respectively; The timing controller writes the frame start signal into the first-stage shift register unit to the fourth-stage shift register unit among the N shift register units.

9. The display method according to claim 1, wherein: The plurality of clock signals include a first clock signal for controlling a first stage shift register unit in the gate driving unit to output a gate driving signal; The plurality of clock signals include a first clock signal for controlling a first stage shift register unit in the gate driving circuit to output a gate driving signal; Among them, the starting time of the effective level of the frame start signal output by the timing controller is earlier than the starting time of the effective level of the first clock signal; the ending time of the effective level of the frame start signal is the same as the ending time of the effective level of the first clock signal.

10. The display method according to claim 9, wherein: The gate driving circuit includes N stages of shift register units; the first stage shift register unit to the P-th stage shift register unit are connected to the frame start signal; the multiple clock signals also include a P-th clock signal for controlling the P-th stage shift register unit to output a gate driving signal; The first-stage shift register unit to the P-stage shift register unit are connected to the frame start signal; The plurality of clock signals further include a Pth clock signal for controlling the Pth stage shift register unit to output a gate drive signal; the duty cycle of each of the clock signals is greater than or equal to 40% and less than or equal to 45%, and N is greater than P; And P is an integer greater than 1.

11. The display method according to claim 10, wherein: The phase difference between the starting times of the effective levels of every two adjacent clock signals in the multiple clock signals is 1H, and the duty cycle of each of the clock signals is 41.6%.

12. The display method according to claim 11, wherein: The duration of the effective level of the gate drive signal is 5H, and the duration of the pre-charging period is 3H; The multiple clock signals include 12 clock signals; the N shift register units are divided into multiple groups according to the arrangement order, each group includes 12 shift register units, and the 12 shift register units in each group receive the 12 clock signals respectively; The timing controller writes the frame start signal into the first-stage shift register unit to the sixth-stage shift register unit among the N shift register units.

13. The display method according to any one of claims 1 to 12, wherein: When the sub-pixel is gated by the effective level of the gate drive signal, the period is divided into a pre-charging period and a charging period; The charging period is a period for writing data signals of the sub-pixels, and the duration of the pre-charging period is greater than 1H.

14. The display method according to any one of claims 1 to 12, wherein: The display of the kth initial data frame and the k+1th initial data frame includes: The timing controller controls the source driving circuit and the gate driving circuit to control the sub-pixel array to display frame by frame in the following order: The first target data frame of the kth initial data frame; a second target data frame of the kth initial data frame; The first target data frame of the k+1th initial data frame; The second target data frame of the k+1th initial data frame.

15. The display method according to any one of claims 1 to 12, wherein: The display of the kth initial data frame and the k+1th initial data frame includes: The timing controller controls the source driving circuit and the gate driving circuit to control the sub-pixel array to display frame by frame in the following order: a second target data frame of the kth initial data frame; The first target data frame of the kth initial data frame; a second target data frame of the k+1th initial data frame; The first target data frame of the k+1th initial data frame.

16. A display device comprising a main control board, a timing controller, a gate driving circuit, a source driving circuit, and a sub-pixel array; the sub-pixel array comprises a plurality of gate lines and a plurality of data lines, and a plurality of sub-pixels defined by the intersection of the gate lines and the data lines; wherein: The main control board is configured to receive an initial data frame and divide the initial data frame into a first target data frame and a second target data frame; the first target data frame includes odd-numbered row data of the initial data frame, and the second target data frame includes even-numbered row data of the initial data frame; The timing controller is configured to apply a frame start signal and a plurality of clock signals to the gate driving circuit, and to apply a source control signal to the source driving circuit; The gate driving circuit provides a gate driving signal for the plurality of rows of gate lines based on the frame start signal and the plurality of clock signals; The source driving circuit controls the start time of writing the data signal of each row of sub-pixels based on the source control signal, and the phase difference between the start time of writing the effective level of the gate driving signal written into the gate line connected to the row of sub-pixels is 2H; H is half of the start time phase difference of the effective level of the gate driving signal written into the kth row of gate lines and the k+2th row of gate lines in the scanning order; k is a positive integer; wherein, The source control signal and the gate drive signal generated by the timing controller satisfy the following conditions when the source drive circuit writes the data signal of the first target data frame into the sub-pixels in odd rows row by row: the start time of writing the data of the sub-pixels in the 2kth row is not later than the end time of writing the data of the sub-pixels in the 2k-1th row, and the end time of writing the data of the sub-pixels in the 2kth row is not earlier than the start time of writing the data of the sub-pixels in the 2k+1th row; The source control signal and the gate drive signal generated by the timing controller write the data signal of the second target data frame into the sub-pixels in the even rows row by row in the source drive circuit; and the source control signal and the gate drive signal satisfy: the starting time of the data writing of the sub-pixels in the 2k+1th row is not later than the ending time of the data writing of the sub-pixels in the 2kth row, and the ending time of the data writing of the sub-pixels in the 2k+1th row is not earlier than the starting time of the data writing of the sub-pixels in the 2k+2th row.

17. An electronic device comprising the display device according to claim 16.

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