Package die including vertical interconnects for signal and power distribution in three-dimensional (3D) integrated circuit (IC) packages

Abstract

The 3D IC package includes a first package die having a first side coupled to a package substrate and a second side coupled to a second package die. The first package die includes a vertical interconnect to provide an interconnect between the second package die and the package substrate. The vertical interconnects each extend vertically between a first die contact on a first side of the first package die and a second die contact on a second side of the first package die. The second package die is coupled to the second die contact of the first package die to form a power and / or signal interconnect between the package substrate and the second package die. Horizontal interconnects in a distribution layer on a first side of the first package die horizontally distribute power and signals between the first die contacts and the vertical interconnects.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 18 / 171,428, filed on February 20, 2023, entitled “PACKAGE DIES INCLUDING VERTICAL INTERCONNECTS FOR SIGNAL AND POWER DISTRIBUTION IN A THREE-DIMENSIONAL (3D) INTEGRATED CIRCUIT (IC) PACKAGE,” which is incorporated herein by reference in its entirety. Background Art

[0003] I. Technical Field

[0004] The technology of the present disclosure relates generally to integrated circuit (IC) packages, and more particularly to interconnecting dies in three-dimensional (3D) IC packages.

[0005] II. Background Technology

[0006] Integrated circuits (ICs) provide functionality for many types of electronic devices, which often include multiple ICs designed to work together. These ICs can be arranged horizontally adjacent to each other on a two-dimensional (2D) surface of a substrate or circuit board, with horizontal metal interconnects running on or through the substrate or circuit board between the ICs to provide die-to-die (D2D) connections. To save area and reduce the length of metal interconnects, device manufacturers also offer IC packages that include multiple ICs stacked vertically to provide three-dimensional (3D) packages.

[0007] One of the challenges of manufacturing 3D IC packages is the need for routing resources for power and signal connections to the lower die and for vertical connections to the upper die. The vertical connections to the upper die extend from the package interconnects on the bottom side of the lower die that connect to the package substrate to the contacts on the top side of the lower die that connect to the upper die. Incorporating these vertical connections into the lower die requires sacrificing resources, and this problem is exacerbated if the preferred location of the vertical connections conflicts with the densely packed logic area of ​​the lower die. Therefore, there is a trade-off between area efficiency of the lower die and having sufficient area through which to route the vertical connections to distribute power and logic signals to the upper die. Summary of the Invention

[0008] Aspects disclosed in the detailed description include a packaged die including vertical interconnects for signal and power distribution in a three-dimensional (3D) integrated circuit (IC) package. Related methods for manufacturing packaged dies including vertical interconnects are also disclosed. A 3D IC package includes a first packaged die having a first side coupled to a packaging substrate disposed vertically below the first packaged die and a second side opposite the first side and coupled to a second packaged die disposed vertically above and adjacent to the first packaged die. The first packaged die includes a first die contact disposed on the first side and coupled to the packaging substrate, and a second die contact disposed on the second side and coupled to the second packaged die. The first packaged die, disposed vertically between the second packaged die and the packaging substrate, includes vertical interconnects to provide interconnection between the second packaged die and the packaging substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first packaged die and a second die contact on the second side of the first packaged die. A third die contact on a third side of the second packaged die is coupled to the second die contact of the first packaged die to provide power and / or signal interconnects between the package substrate and the second packaged die. In an exemplary aspect, the horizontal interconnect distributes power and signals horizontally between the first die contact and the vertical interconnect. The horizontal interconnect may be disposed in a distribution layer to provide a low resistance path and avoid an increase in congestion that would be caused by routing power and signals through a metallization layer on the first packaged die. In some examples, the position of the vertical interconnect is selected to avoid interfering with circuit blocks on the first packaged die and to distribute power between the second die contacts, which may be coupled to a power distribution network in the second packaged die.

[0009] In this regard, in one aspect, a 3D IC package is disclosed. The 3D IC package includes a first packaged die. The first packaged die includes a plurality of vertical interconnects extending through the first packaged die in a first direction between a first side of the first packaged die and a second side of the first packaged die. The first packaged die also includes a distribution layer including horizontal interconnects extending in a second direction orthogonal to the first direction. The distribution layer is disposed on a metallization layer on the first side of the first packaged die and coupled to the plurality of vertical interconnects. The first packaged die also includes a first die contact disposed on the first side of the first packaged die and coupled to the horizontal interconnects. The first packaged die also includes a second die contact disposed on the second side of the first packaged die, coupled to the plurality of vertical interconnects, and configured to couple to the second packaged die.

[0010] In another aspect, a method for manufacturing a 3D IC package is disclosed. The method includes forming a plurality of vertical interconnects extending through a first packaged die in a first direction between a first side of the first packaged die and a second side of the first packaged die. The method also includes forming a distribution layer including horizontal interconnects extending in a second direction orthogonal to the first direction. The distribution layer is disposed on a metallization layer on the first side of the first packaged die and coupled to the plurality of vertical interconnects. The method also includes forming a first die contact disposed on the first side of the first packaged die and coupled to the horizontal interconnect. The method also includes forming a second die contact disposed on the second side of the first packaged die, coupled to the plurality of vertical interconnects, and configured to couple to a second packaged die. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a perspective view of a three-dimensional (3D) integrated circuit (IC) package including an exemplary first packaged die disposed between a packaging substrate and a second packaged die and including vertical interconnects for power and signal distribution and reduced metal layer congestion;

[0012] Figure 2 yes Figure 1 a cross-sectional side view of a 3D IC package in , showing a vertical interconnect extending through a first packaged die and interconnecting a first die contact to a second die contact;

[0013] Figure 3 It is used to manufacture Figure 1 and Figure 2 A flow chart of a method for packaging a first die in a 3D IC package is shown;

[0014] Figure 4 yes Figure 2 a plan view of an example of a first packaged die in FIG. 1 , the first packaged die including vertical interconnects disposed in separation channels between circuit blocks in an active circuit layer and first die contacts disposed in non-overlapping regions of the first packaged die;

[0015] Figure 5 yes Figure 1 、 Figure 2 and Figure 4 a plan view of one example of a first packaged die comprising circuit blocks of memory blocks of a memory array interconnected in hierarchical levels and separated by separation channels;

[0016] Figure 6is a plan view of a primary circuit block including memory arrays arranged in columns on either side of a separation channel and array interconnects directed primarily toward control circuitry in a central portion of the separation channel, thereby allowing edge-centered vertical interconnects to pass through each end portion of the separation channel without obstructing the primary circuit block;

[0017] Figure 7 yes Figure 5 a plan view of an example of a first packaged die in which the secondary circuit blocks are separated by separation channels through which vertical interconnects including a number of vias may extend;

[0018] Figure 8A and Figure 8B Examples of regions of power distribution networks, circuit blocks, and vertical interconnects with coarse and fine pitches are illustrated, respectively;

[0019] Figure 9 is a block diagram of an exemplary processor-based system that may include a 3D IC package including an exemplary packaged die including vertical interconnects through a first packaged die and horizontal interconnects in a distribution layer to provide a low resistance path without increasing Figure 1 、 Figure 2 and Figures 4 to 7 congestion in the metallization layers, and based on, but not limited to Figure 3 any of the exemplary manufacturing processes in the exemplary manufacturing process; and

[0020] Figure 10 is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component that may include a 3D IC package including an exemplary packaged die including vertical interconnects passing through a first packaged die and horizontal interconnects located in a distribution layer to provide a low resistance path without increasing Figure 1 、 Figure 2 and Figures 4 to 7 congestion in the metallization layers, and based on, but not limited to Figure 3 Any exemplary manufacturing process in the exemplary manufacturing process. DETAILED DESCRIPTION

[0021] With reference now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0022] Aspects disclosed in the detailed description include a packaged die including vertical interconnects for signal and power distribution in a three-dimensional (3D) integrated circuit (IC) package. Related methods for manufacturing packaged dies including vertical interconnects are also disclosed. A 3D IC package includes a first packaged die having a first side coupled to a packaging substrate disposed vertically below the first packaged die and a second side opposite the first side and coupled to a second packaged die disposed vertically above and adjacent to the first packaged die. The first packaged die includes a first die contact disposed on the first side and coupled to the packaging substrate, and a second die contact disposed on the second side and coupled to the second packaged die. The first packaged die, disposed vertically between the second packaged die and the packaging substrate, includes vertical interconnects to provide interconnection between the second packaged die and the packaging substrate. The vertical interconnects each extend vertically between a first die contact on the first side of the first packaged die and a second die contact on the second side of the first packaged die. A third die contact on a third side of the second packaged die is coupled to the second die contact of the first packaged die to provide power and / or signal interconnects between the package substrate and the second packaged die. In an exemplary aspect, the horizontal interconnect distributes power and signals horizontally between the first die contact and the vertical interconnect. The horizontal interconnect may be disposed in a distribution layer to provide a low resistance path and avoid an increase in congestion that would be caused by routing power and signals through a metallization layer on the first packaged die. In some examples, the position of the vertical interconnect is selected to avoid interfering with circuit blocks on the first packaged die and to distribute power between the second die contacts, which may be coupled to a power distribution network in the second packaged die.

[0023] In this regard, Figure 1 The present invention is a three-dimensional (3D) integrated circuit (IC) package 100 that includes an exemplary first packaged die 102 coupled to a package substrate 104 on a first side S1 and coupled to a second packaged die 106 on a second side S2. The first packaged die 102 includes vertical interconnects (see Figure 2), each of these vertical interconnects includes a via extending between the package substrate 104 and the second packaged die 106 for improving power distribution and reducing metal layer congestion. The first packaged die 102 includes a first active circuit layer 108, in which circuit blocks (not shown) including transistor circuits provide functions such as data and instruction processing and / or data storage. The term "circuit block" indicates a circuit that is interconnected to provide a function, for example, where the circuits can be densely arranged. The term "block" is not intended to indicate any particular shape (i.e., not necessarily square or rectangular). The first packaged die 102 can be coupled to an external circuit (not shown) via the package substrate 104. In some examples, as shown below, the first die contacts are distributed (e.g., in one or more arrays) on a first side surface 110 on a first side S1 of the first packaged die 102 and can be coupled to the package substrate 104 via solder balls or solder bumps (not shown) or other suitable components known in the art.

[0024] Second packaged die 106 includes a second active circuit layer 112 that can provide functionality that closely interacts with functionality provided in first active circuit layer 108 of first packaged die 102. Thus, stacking second packaged die 106 vertically (e.g., three-dimensionally) on first packaged die 102, rather than positioning first and second packaged dies 102, 106 in a laterally adjacent relationship (e.g., side-by-side) on packaging substrate 104, reduces the area of ​​packaging substrate 104 occupied by first and second packaged dies 102, 106, and also reduces the propagation distance of signals and power transmitted between first active circuit layer 108 of first packaged die 102 and second active circuit layer 112 of second packaged die 106. In some examples, first and second active circuit layers 108, 112 can include circuit blocks that include logic circuitry (e.g., digital logic circuitry) for data processing and memory array circuitry for data storage, respectively. Storing data in memory array circuitry close to the processing circuitry that processes the data reduces data access latency, which can improve processing performance.

[0025] exist Figure 1In the embodiment of the present invention, second packaged die 106 is stacked on first packaged die 102 such that second packaged die 106 is above first packaged die 102 in the vertical direction (e.g., Z-axis). In this regard, second packaged die 106 may also be referred to as upper packaged die 106, while first packaged die 102 may be referred to as lower packaged die 102. As noted, first (lower) packaged die 102 is coupled to packaging substrate 104 via first die contacts (not shown) disposed on first side surface 110 on first side S1. First active circuit layer 108 may be coupled to second packaged die 106 via second die contacts (not shown) on second side S2 of first packaged die 102. Second packaged die 106 may also transmit control and / or data signals to and / or receive control and / or data signals from circuitry external to first packaged die 102. Power must also be provided from packaging substrate 104 to both second packaged die 106 and first packaged die 102. In some examples, the second packaged die 106 can have greater power requirements than the first packaged die 102 . Therefore, a problem for designers of the 3D IC package 100 is to provide sufficient power from the package substrate 104 to the upper packaged die 106 .

[0026] In a 3D IC package that includes a memory die and a processor die, the number of vertical interconnects between the package substrate 104 and the upper package die 106 can be minimized by placing the processing circuitry in the lower package die 102 closer to the package substrate 104, because the processing circuitry typically consumes more power than the memory array circuitry. In this regard, the memory array circuitry would be located in the upper package die 106. However, such a configuration makes it difficult to efficiently dissipate the heat generated in the processing circuitry. An alternative configuration is one in which the upper package die 106 contains the processing circuitry and the lower package die 102 contains the memory array circuitry. However, there remains the problem of providing sufficient vias for the signals and high power requirements of the processing circuitry in the upper package die 106 without significantly negatively impacting the lower package die 102. Figure 2 Exemplary aspects of a first packaged die 102 in a 3D IC package are illustrated in FIG.

[0027] Figure 2 is a cross-sectional side view of a 3D IC package 200, which may be Figure 13D IC package 100 in FIG. Features of 3D IC package 200 include those corresponding to those of 3D IC package 100 discussed above, and additionally include exemplary vertical interconnects 202 in first packaged die 204 for vertically coupling package substrate 206 to second packaged die 208. First packaged die 204 includes a first active circuit layer 210 that includes circuit blocks (not shown), such as transistor circuits, which may include, for example, processing circuitry (logic circuitry), memory array circuitry, and analog circuitry. First active circuit layer 210 is disposed on substrate layer 212 and on first side S1 of first packaged die 204. Substrate layer 212 may be a semiconductor substrate, such as silicon, although other types of semiconductor substrates are possible. As another example, substrate layer 212 may include at least one other layer of material in addition to semiconductor. Vertical interconnects 202, exemplified in more detail below, include one or more vias (not shown). For this reason, vertical interconnects 202 may be referred to as “clustered through silicon vias” (“clustered TSVs”). Vertical interconnects 202 extend through first packaged die 204 from first side S1 to second side S2 in a direction orthogonal to first active circuit layer 210 (eg, the Z-axis direction).

[0028] The 3D IC package 200 includes a package substrate 206 located on a first side S1 of a first packaged die 204. The package substrate 206 may be, for example, a laminate, a printed circuit board (PCB), an interposer, a module substrate, or a semiconductor substrate. The first packaged die 204 includes first die contacts 214 (A)-214 (C) coupled to the package substrate 206. Figure 2 Only the first die contacts 214(A)-214(C) are shown in the cross-sectional view of FIG. , but it should be understood that the first die contacts 214(A)-214(C) are merely examples of the plurality of first die contacts 214. In this example, the plurality of first die contacts 214 are coupled to the package substrate 206 via solder balls or solder bumps 216, although another type of package interconnect may be employed. The plurality of first die contacts 214 may be arranged in one or more contact arrays on the first side surface 218 on the first side S1 of the first packaged die 204. In this manner, the first packaged die 204 is arranged in a face-down orientation, with the first active circuit layer 210 opposite (e.g., facing) the package substrate 206 and interconnected to the package substrate 206 via the plurality of first die contacts 214. This may be referred to as a flip-chip bonding technique.

[0029] The second packaged die 208 is coupled to a second die contact 220 on the second side S2 of the first packaged die 204. The second die contact 220 is coupled to the vertical interconnect 202. The vertical interconnect 202 extends through the first packaged die 204 between the first side S1 and the second side S2 in a direction orthogonal to the first active circuit layer 210 (e.g., the Z-axis direction). Figure 2 The second die contacts 220 on the first packaged die 204 are coupled to a second active circuit layer 226 of the second packaged die 208 via additional solder bumps or solder balls 222 or another type of interconnect disposed between the second die contacts 220 on the first packaged die 204. The solder bumps 222 are connected to third die contacts 224 on the second packaged die 208, and the third die contacts 224 are coupled to the second active circuit layer 226, which may include, for example, transistor circuitry that provides logic, processing, or memory functions. In some examples, the first active circuit layer 210 of the first packaged die 204 includes a circuit block that includes memory array circuitry, and the second active circuit layer 226 of the second packaged die 208 includes logic circuitry, such as processing circuitry of a processor. Placing the first packaged die 204, which includes the memory array circuitry, below the second packaged die 208 rather than on top of it allows for better heat dissipation from the high-power consuming processing circuitry.

[0030] Signals and power are provided to the second packaged die 208 via the vertical interconnects 202 through the second die contacts 220. More specifically, the second die contacts 220 are coupled to vias (not shown) included within the vertical interconnects 202. Some of the vertical interconnects 202 (e.g., vias) are electrically coupled to the packaging substrate 206 through the plurality of first die contacts 214, while other vertical interconnects 202 may instead be coupled to the first active circuit layer 210 in the first packaged die 204. In this way, control signals and data signals, for example, can be passed directly between processing circuitry in the second packaged die 208 and memory array circuitry in the first packaged die 204, rather than also passing through the first die contacts 214 and down to the packaging substrate 206. Power and other signals can be passed directly between the packaging substrate 206 and the second packaged die 208, rather than also being coupled to the first active circuit layer 210 on the first packaged die 204. The vias in the vertical interconnects 202 may couple the second active circuit layer 226 only to the first active circuit layer 210 , only to the packaging substrate 206 , or to both the first active circuit layer 210 and the packaging substrate 206 .

[0031] The vertical interconnects 202 extend through a metallization layer 227 disposed on the first active circuit layer 210. The metallization layer 227 may be disposed on the first active circuit layer 210 in a back-end-of-line (BEOL) process. Each of the vertical interconnects 202 includes at least one and up to several (e.g., seven or more) vias, which are electrical conductors extending through the vertical interconnects 202. The vertical interconnects 202 are insulated from the first active circuit layer 210, the substrate layer 212, and each other. The vertical interconnects 202 are further coupled to a plurality of first die contacts 214. However, as Figure 1 and Figure 2 As shown in the example of FIG, the first packaged die 204 and the second packaged die 208 can have different sizes in the horizontal direction (e.g., in a plane extending parallel to the X-axis and Y-axis directions of the packaging substrate 206). For at least this reason, the plurality of first die contacts 214 coupled to the packaging substrate 206 can have a different pattern, a different pitch, and / or be distributed over different sized areas than the vertical interconnects 202 coupled to the second die contacts 220.

[0032] Because the plurality of first die contacts 214 are horizontally offset from the second die contacts 220, the vertical interconnect 202 may be aligned with the second die contacts 220 but not with the plurality of first die contacts 214. On the first side S1 of the first packaged die 204, a plurality of vias are present in the vertical interconnect 202, and each of the vias is coupled to a different one of the plurality of first die contacts 214 that are horizontally offset (e.g., in the X-axis direction and / or the Y-axis direction) from the vertical interconnect 202 through which the vias extend.

[0033] supply Figure 2 To illustrate, in a first exemplary aspect, a horizontal interconnect 230 horizontally couples a plurality of first die contacts 214 to vias in a vertical interconnect 202. The horizontal interconnect 230 is formed in a distribution layer 232 of a metallization layer 227 on a first active circuit layer 210. In some examples, the distribution layer 232 may also be referred to as a redistribution layer (RDL). The distribution layer 232 is disposed in the metallization layer 227 on the first active circuit layer 210, and the horizontal interconnect 230 is coupled to the vertical interconnect 202. A plurality of first die contacts 214 are also disposed on the first active circuit layer 210 and coupled to the horizontal interconnect 230. The plurality of first die contacts 214 may be part of the horizontal interconnect 230 in the distribution layer 232. Alternatively, for example, the plurality of first die contacts 214 may be contact pads (not shown) formed separately from the horizontal interconnect 230 but coupled to the horizontal interconnect 230.

[0034] In some examples, the distribution layer 232 is the outermost metal layer in the metallization layers 227 formed on the first active circuit layer 210. In other words, the distribution layer 232 is further away from the first active circuit layer 210 than the other metallization layers 227. The horizontal interconnects 230 formed in the distribution layer 232 can have a large cross-section that provides a low resistance path for power and signal transmission. For power transmission, the horizontal interconnects 230 can be coupled to the vertical interconnects 202 through metal traces 234 (e.g., wires) formed in the first metallization layer 235 (in the metallization layer 227), which also provide a low resistance path. The first metallization layer 235 is adjacent to the distribution layer 232. The distribution layer 232 and the first metallization layer 235 are located adjacent to each other. Figure 2 2 is shown on the bottom side (in the Z-axis direction) of the first packaged die 204 because the first packaged die 204 is inverted for flip-chip bonding to the packaging substrate 206 .

[0035] In some examples, the vertical interconnects 202 extend in a first direction (e.g., the Z-axis direction), the horizontal interconnects 230 extend in a second direction (e.g., the X-axis direction) orthogonal to the vertical interconnects 202, and the metal traces 234 extend in a third direction (e.g., the Y-axis direction) orthogonal to the horizontal interconnects 230 and the vertical interconnects 202. The horizontal interconnects 230 and the metal traces 234 together provide a low-resistance horizontal bias between the plurality of first die contacts 214 and the vertical interconnects 202. Utilizing the horizontal interconnects 230 and the metal traces 234 of the metallization layer 227 in the distribution layer 232 rather than a lower layer of the metallization layer 227 avoids increasing congestion in the metallization layer 227 used for interconnecting circuits in the first active circuit layer 210.

[0036] Because the transmission of data and control signals generally does not involve the higher current levels required for power transmission, the horizontal interconnects 230 used to transmit such control and data signals can be coupled to smaller metal traces 236 in the metallization layers 227, such as those between the first metallization layer 235 and the first active circuit layer 210. Thus, the smaller metal traces 236 can be used for communications directed to the first packaged die 204, or for data and control signals directed to the vertical interconnects 202 destined for the second packaged die 208. In some examples, the vertical interconnects 202 extend between the second die contacts 220 and another metallization layer that is located between the first metallization layer 235 and the first active circuit layer 210.

[0037] A manufacturing process may be employed to manufacture a 3D IC package including a first packaged die 204 having a vertical interconnect 202 coupled between a first die contact 214 on a first side S1 and a second die contact 220 on a second side S2 and configured to route power and / or logic signals with low resistance and minimal impact on metallization congestion of the first packaged die 204, as shown. Figure 2 As shown and based on but not limited to Figure 3 In this regard, Figure 3 is a flow chart illustrating an exemplary manufacturing process 300 for manufacturing a 3D IC package 200 including a first packaged die 204 including a Figure 2 In this regard, the exemplary method includes forming a plurality of vertical interconnects 202 extending through the first packaged die 204 in a first direction between the first side S1 of the first packaged die 204 and the second side S2 of the first packaged die 204 (block 302). The method also includes forming a distribution layer 232 including horizontal interconnects 230 extending in a second direction orthogonal to the first direction and disposed in the metallization layer 227 on the first side S1 of the first packaged die 204 and coupled to the plurality of vertical interconnects 202 (block 304). The method also includes forming a first die contact 214 on the first side S1 of the first packaged die 204 and coupled to the horizontal interconnect 230 (block 306 ), and forming a second die contact 220 on the second side S2 of the first packaged die 204 coupled to the plurality of vertical interconnects 202 and configured to couple to a second packaged die (block 308 ).

[0038] Figure 4 corresponds to Figure 1 and Figure 2 A plan view of an example of a first packaged die 400 of the first packaged die 102, 204 is provided. Figure 4 To facilitate description (see Figure 5 )like Figure 2Detail of an exemplary placement of vertical interconnects is shown. In this example, a first packaged die 400 includes a plurality of primary circuit blocks 402, which in this example are memory array circuits, and more specifically, may be static random access memory (SRAM) array circuits and / or dynamic random access memory (DRAM) array circuits. Primary circuit blocks 402 (memory arrays) may be logically grouped and coupled together to form a plurality of secondary circuit blocks 404, which function as a memory array having a larger capacity of contiguous memory. In this regard, primary circuit blocks 402 may be organized in a hierarchy. Primary circuit blocks 402 are the smallest memory arrays formed as an array of memory circuits in rows and columns (e.g., a rectangular array). Addressing and data control circuitry may be arranged to control the plurality of primary circuit blocks 402 so that each secondary circuit block 404 operates as a single, larger array.

[0039] In the layout of the first packaged die 400, the primary circuit blocks 402 are arranged into rows 406 and columns 408 within each of the secondary circuit blocks 404, and the secondary circuit blocks 404 are also arranged into rows 410 and columns 412. The secondary circuit blocks 404 include the primary circuit blocks 402 in rows 406 and columns 408, which are separated by primary separation channels 414. Therefore, the primary separation channels 414 can extend in both the Y-axis direction and the X-axis direction. Similarly, the first packaged die 400 includes secondary separation channels 416 located between the rows 410 and columns 412 of the secondary circuit blocks 404. The secondary separation channels 416 also extend in both the Y-axis direction and the X-axis direction. The primary separation channels 414 are narrower in width than the secondary separation channels 416.

[0040] Primary separation channel 414 and secondary separation channel 416 provide space through which array interconnects (not shown) can be routed and multiplexing circuits can be placed. Primary separation channel 414 and secondary separation channel 416 occupy less space (e.g., have more unused space) than primary circuit block 402 and secondary circuit block 404, and for this reason, provide a desired location for vertical interconnects (not shown) to extend vertically through the active circuit layer, as described with reference to FIG. Figure 5 Described in more detail.

[0041] In the example of the first packaged die 400, the primary circuit block 402 is a memory array circuit, but it should be understood that the primary circuit block 402 can also be a logic circuit, such as a processing circuit, or other circuit. Regardless of the circuit type, the primary circuit blocks 402 can be separated by primary separation channels 414 and can be organized in layers such that the secondary circuit blocks 404 can be arranged and separated by wider secondary separation channels 416.

[0042] Figure 5 is a top plan view of a first packaged die 500, which may be Figure 1 、 Figure 2 and Figure 4 Any first packaged die in the first packaged die 102, 204, 400. Figure 5 The vertical interconnects (including the primary vertical interconnect 502 and the secondary vertical interconnect 504) extending vertically (e.g., in the Z-axis direction) through the first packaged die 500 are arranged in a manner illustratively to avoid obstructing the circuit blocks and to avoid causing a significant increase in routing congestion. The first packaged die 500 includes a secondary circuit block 506 corresponding to Figure 4 In the secondary circuit block 404. To reduce clutter, Figure 5 Only the secondary circuit block 506 is shown in FIG, but it should be appreciated that each of the secondary circuit blocks 506 represents a Figure 4 One of the columns 412 extending in the Y-axis direction. Figure 5 Secondary separation channels 508 are shown extending in the Y-axis direction between the secondary circuit blocks 506. Figure 5 The primary circuit blocks are not shown in FIG, but some examples of the primary separation channels 510 extending in the Y-axis direction are shown. Figure 4 It should be appreciated that the primary separation channel 510 and the secondary separation channel 508 extend in both the Y-axis direction and the X-axis direction, even if Figure 5 Only an example extending in the Y-axis direction is shown.

[0043] It should also be appreciated that the primary separation channel 510 and the secondary separation channel 508 are Figure 5 In the embodiment, the secondary separation channel 508 is wider than the primary separation channel 510 (e.g., in the X-axis or Y-axis direction), as shown in FIG. Figure 4 As shown. Consequently, secondary separation channel 508 has more space where vertical interconnects 502, 504 can be added without obstructing secondary circuit blocks 506 on either side. On the other hand, primary separation channel 510, while narrower, is provided in greater numbers and closer together than secondary separation channel 508. Consequently, there are more locations for primary vertical interconnects 502 to extend through primary separation channel 510 and they are more evenly distributed than secondary vertical interconnects 504 in secondary separation channel 508. In some examples, primary vertical interconnects 502 may also extend through secondary separation channel 508.

[0044] As noted above, the primary vertical interconnect 502 and the secondary vertical interconnect 504 can be cluster TSVs that each include a plurality of vias 512. In some examples, the primary vertical interconnect 502 can include fewer than four vias 512, and the secondary vertical interconnect 504 can include at least four (4) (and up to seven or more) vias 512. In this regard, the secondary vertical interconnect 504 extending through the secondary separation channel 508 can provide a larger number of vias 512, but at a coarser granularity (larger pitch), while the primary vertical interconnect 502 extending through the primary separation channel 510 can provide a smaller number of vias 512, but at a finer granularity (e.g., smaller pitch).

[0045] exist Figure 5 , perimeter 514 extends around an overlap region 516 in which the corresponding Figure 2 The second packaged die 208 in the second packaged die (not shown) overlaps the first packaged die 500 because the area of ​​the second packaged die 208 may be smaller than the area of ​​the first packaged die 500. The overlap region 516 is where the second packaged die may be positioned opposite (e.g., overlapping) the first packaged die 500 in the Z-axis direction. Figure 2 , the second die contact 220 on the second side S2 (e.g., top side) of the first packaged die 204, 500 is disposed within the overlap region 516 so as to couple to the corresponding third die contact 224 on the second active circuit layer 226 of the second packaged die 208. The primary vertical interconnect 502 and the secondary vertical interconnect 504 are each connected to the second die contact ( Figure 5 516 ). In the embodiment of the present invention, the primary vertical interconnects 502 and the secondary vertical interconnects 504 are vertically aligned with one of the second die contacts 518 in the first packaged die 500 (not shown), and therefore they must be located in the overlap region 516. Because the primary vertical interconnects 502 and the secondary vertical interconnects 504 do not need to be vertically aligned with the first die contacts 518, some of the first die contacts 518 can be disposed in a non-overlap region 520 of the first packaged die 500, which is outside of the overlap region 516. In this regard, a row 522 of the primary vertical interconnects 502 can be disposed in the overlap region 516 along the perimeter 514, and horizontal interconnects 524 (and / or metal traces 526) couple the primary vertical interconnects 502 to the first die contacts 518 in the non-overlap region 520.

[0046] Figure 5Also shown are examples of horizontal interconnects 524 and metal traces 526 that extend from the primary vertical interconnects 502 and the secondary vertical interconnects 504 in the overlap region 516 to the first die contacts 518. The horizontal interconnects 524 can extend in the X-axis direction or the Y-axis direction, with the metal traces 526 extending orthogonal to the horizontal interconnects 524. The distribution and number of each of the primary vertical interconnects 502 and the secondary vertical interconnects 504 can depend on several factors, including the organization of circuit blocks (e.g., a memory array) in the first packaged die 500, the total amount of power consumed by the second packaged die, and the distribution of power consumption in the second packaged die.

[0047] Figure 6 are respectively corresponding to Figure 4 and Figure 5 6, which includes a primary circuit block 602 disposed on either side of a primary separation channel 604. Figure 6In the example shown, primary circuit blocks 602 are interconnected to form secondary circuit blocks 600 (memory array circuitry) having the combined storage capacity of primary circuit blocks 602. Secondary circuit blocks 600 include array interconnects 606, which can carry data, address, clock, and control signals. Furthermore, secondary circuit blocks 600 include control circuitry 608 (e.g., address and data multiplexing circuitry) for selecting one or more of primary circuit blocks 602 for access (e.g., reading or writing) based on a memory address and directing data to / from the selected primary circuit blocks 602. Control circuitry 608 is located in a central region 610 of a primary separation channel 604 of secondary circuit block 600 to optimize timing to the corresponding primary circuit block 602. Central region 610 is centered in the primary separation channel 604 along the Y-axis. The array interconnects 606 also extend between the control circuitry 608 in the center region 610 (e.g., in the Y-axis direction) and the end regions 612 of the primary separation channels 604. Thus, the end regions 612 have a much lower density of control circuitry 608 and array interconnects 606 than the center region 610. Because these end regions are relatively unoccupied spaces, there is room for the primary vertical interconnects 614 to pass vertically (e.g., in the Z-axis direction) between the primary circuit blocks 602 and through the secondary circuit blocks 600 without affecting the placement of the primary circuit blocks 602, the control circuitry 608, and / or the array interconnects 606. The primary vertical interconnects 614 extend through the end regions 612, but do not extend through the center region 610 between the end regions 612. Positioning the primary vertical interconnects 614 in the end regions 612 of the primary separation channels 604 can be referred to as an "edge-centered" placement of the primary vertical interconnects 614. According to Figure 4 Primary vertical interconnects 614 can be distributed across the first packaged die according to the number and placement of primary separation channels 414 in FIG. 4 (which correspond to primary separation channels 604 ).

[0048] Figure 7 corresponds to Figure 4 700 of the first packaged die 400 in a plan view, wherein secondary circuit blocks 702 are arranged in columns 704 separated by secondary separation channels 706, and secondary vertical interconnects 708 extend through the secondary separation channels 706. Figure 7 To illustrate that each of the secondary vertical interconnects 708 includes a plurality of vias 710. Since the secondary vertical interconnects 708 occupy more area, they only fit in the secondary separation channels 706. Some examples of primary separation channels 712 within the secondary circuit block 702 are shown for comparison. Although Figure 7It is not drawn to scale, but it clearly illustrates that the secondary vertical interconnects 708 can provide a greater number of vias 710, but are arranged at a much lower density and in a much smaller total number than the primary vertical interconnects 714. It should be understood that while the first packaged die 700 includes both the primary vertical interconnects 714 and the secondary vertical interconnects 708, a first packaged die according to the present disclosure may alternatively include only the primary vertical interconnects 714, or only the secondary vertical interconnects 708.

[0049] Figure 8A is a plan view of an area 800A of a 3D IC, wherein a second packaged die (not shown) (eg, Figure 2 Superimposed on the secondary circuit block 804 and the secondary vertical interconnect 806 is a power distribution network (PDN) 802A in the second packaged die 208 in FIG. Figure 8B is a plan view of another example area 800B of a 3D IC, where a PDN 802B of a second packaged die is overlaid on a primary circuit block 808 and a primary vertical interconnect 810 . Figure 8A and Figure 8B Comparative options for supplying current to the PDNs 802A, 802B in the second packaged die are provided. Figure 8A As shown, the secondary vertical interconnect 806 provides a greater number of vias (see Figure 7 ), but are more coarsely distributed than the primary vertical interconnects 810. Figure 8B It is shown that the primary vertical interconnects 810 are more abundant and evenly distributed, although there are fewer vias (not shown) in each primary vertical interconnect 810. The type of PDN 802A, 802B used in the second packaged die, or even within the area of ​​the second packaged die, can be adjusted based on the space available in the first packaged die, the need for even power distribution in the second packaged die (such as due to hot spots), and / or the total amount of power required.

[0050] An electronic device including a 3D IC package having a first packaged die including vertical interconnects providing vias extending between a package substrate and a second packaged die for improved power distribution and reduced metal layer congestion can be provided in or integrated into any processor-based device, such as Figure 2 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A and Figure 8B As shown and based on but not limited to Figure 3Examples of the exemplary manufacturing processes of the present invention and according to any aspect disclosed herein include, but are not limited to, a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a Session Initiation Protocol (SIP) phone, a tablet computer, a phablet, a server, a computer, a portable computer, a mobile computing device, a laptop computer, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multirotor aircraft.

[0051] Figure 9 An exemplary wireless communication device 900 is illustrated that includes a radio frequency (RF) assembly formed of one or more ICs 902, wherein any of the ICs 902 may be included in a 3D IC package 903. The 3D IC package 903 may include a first packaged die that includes vertical interconnects that provide vias extending between a package substrate and a second packaged die for improving power distribution and reducing metal layer congestion, such as Figure 2 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A and Figure 8B As shown and in accordance with any exemplary aspects disclosed herein. As an example, the wireless communication device 900 may include or be arranged in any of the above-mentioned devices. Figure 9 As shown, wireless communication device 900 includes a transceiver 904 and a data processor 906. Data processor 906 may include memory for storing data and program codes. Transceiver 904 includes a transmitter 908 and a receiver 910 that support bidirectional communication. In general, wireless communication device 900 may include any number of transmitters 908 and / or receivers 910 for any number of communication systems and frequency bands. All or a portion of transceiver 904 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0052] The transmitter 908 or receiver 910 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and baseband in multiple stages, for example, in the case of the receiver 910, from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Figure 9 In the wireless communication device 900 in FIG. 1 , the transmitter 908 and the receiver 910 are implemented using a direct conversion architecture.

[0053] In the transmit path, the data processor 906 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 908. In the exemplary wireless communication device 900, the data processor 906 includes digital-to-analog converters (DACs) 912(1), 912(2) to convert the digital signals generated by the data processor 906 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0054] Within the transmitter 908, low-pass filters 914(1), 914(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 916(1), 916(2) amplify the signals from the low-pass filters 914(1), 914(2), respectively, and provide I and Q baseband signals. An upconverter 918 upconverts the I and Q baseband signals using I and Q TX local oscillator (LO) signals from a transmit (TX) local oscillator (LO) signal generator 922 via mixers 920(1), 920(2) to provide upconverted signals 924. A filter 926 filters the upconverted signals 924 to remove undesired signals caused by the upconversion and noise in the receive band. A power amplifier (PA) 928 amplifies the upconverted signals 924 from the filter 926 to obtain a desired output power level and provide a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 930 and transmitted via an antenna 932 .

[0055] In the receive path, antenna 932 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 930 and provided to a low noise amplifier (LNA) 934. The duplexer or switch 930 is designed to operate with specific receive (RX) and TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 934 and filtered by filter 936 to obtain the desired RF input signal. Down-conversion mixers 938 (1), 938 (2) mix the output of filter 936 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 940 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 942(1), 942(2) and further filtered by low-pass filters 944(1), 944(2) to obtain I and Q analog input signals, which are provided to the data processor 906. In this example, the data processor 906 includes analog-to-digital converters (ADCs) 946(1), 946(2) to convert the analog input signals into digital signals to be further processed by the data processor 906.

[0056] exist Figure 9 In wireless communication device 900, TX LO signal generator 922 generates I and Q TX LO signals for upconversion, while RX LO signal generator 940 generates I and Q RX LO signals for downconversion. Each LO signal is a periodic signal with a specific fundamental frequency. TX phase-locked loop (PLL) circuit 948 receives timing information from data processor 906 and generates control signals for adjusting the frequency and / or phase of the TX LO signal from TX LO signal generator 922. Similarly, RX PLL circuit 950 receives timing information from data processor 906 and generates control signals for adjusting the frequency and / or phase of the RX LO signal from RX LO signal generator 940.

[0057] In this regard, Figure 10 An example of a processor-based system 1000 is illustrated that may include a 3D IC package having a first packaged die including vertical interconnects that provide vias extending between a package substrate and a second packaged die for improving power distribution and reducing metal layer congestion, such as Figure 2 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8A and Figure 8BAs shown and in accordance with any exemplary aspects disclosed herein. The processor-based system 1000 includes a central processing unit (CPU) 1008 that includes one or more processors 1010, which may also be referred to as CPU cores or processor cores. The CPU 1008 may have a cache memory 1012 coupled to the CPU 1008 for fast access to temporarily stored data. The CPU 1008 is coupled to a system bus 1014 and may couple master devices and slave devices included in the processor-based system 1000 to each other. As is well known, the CPU 1008 communicates with these other devices by exchanging address, control, and data information via the system bus 1014. For example, the CPU 1008 may communicate a bus transaction request to a memory controller 1016, which is an example of a slave device. Although in Figure 10 Although not illustrated in the figure, multiple system buses 1014 may be provided, each system bus 1014 forming a different structure.

[0058] Other master devices and slave devices may be connected to the system bus 1014. Figure 10 As illustrated, as an example, these devices may include a memory system 1020 including a memory controller 1016 and a memory array 1018, one or more input devices 1022, one or more output devices 1024, one or more network interface devices 1026, and one or more display controllers 1028. Input devices 1022 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1024 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 1026 may be any device configured to allow data exchange to and from network 1030. Network 1030 may be any type of network, including but not limited to a wired or wireless network, private or public network, local area network (LAN), wireless local area network (WLAN), wide area network (WAN), Bluetooth ™ Network and Internet. The network interface device 1026 may be configured to support any type of communication protocol desired.

[0059] The CPU 1008 may also be configured to access a display controller 1028 via the system bus 1014 to control information transmitted to one or more displays 1032. The display controller 1028 transmits information to be displayed to the display 1032 via one or more video processors 1034, which process the information to be displayed into a format suitable for the display 1032. The display 1032 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, and the like.

[0060] Those skilled in the art will further understand that the various illustrative logical blocks, modules, circuits, and algorithms described in conjunction with the various aspects disclosed herein can be implemented as electronic hardware, instructions stored in a memory or another computer-readable medium, with any such instructions being executed by a processor or other processing device, or a combination of the two. By way of example, the devices and components described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be any type and size of memory and can be configured to store any desired type of information. To clearly illustrate this interchangeability, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing a departure from the scope of this disclosure.

[0061] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0062] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware and may reside, for example, in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. In an alternative embodiment, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative embodiment, the processor and storage medium may reside as discrete components in a remote station, a base station, or a server.

[0063] As also noted, the operational steps described in any of the exemplary aspects herein are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in a plurality of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, numerous different modifications may be made to the operational steps illustrated in the flow charts. Those skilled in the art will also understand that any of a variety of different technologies and techniques may be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0064] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0065] Specific implementation examples are described in the following numbered clauses:

[0066] 1. A three-dimensional (3D) integrated circuit (IC) package, comprising:

[0067] A first packaged die, the first packaged die comprising:

[0068] a plurality of vertical interconnects extending through the first packaged die in a first direction between a first side of the first packaged die and a second side of the first packaged die;

[0069] a distribution layer comprising horizontal interconnects extending in a second direction orthogonal to the first direction, the distribution layer disposed on the metallization layer on the first side of the first packaged die and coupled to the plurality of vertical interconnects;

[0070] a first die contact disposed on the first side of the first packaged die and coupled to the horizontal interconnect; and

[0071] A second die contact is disposed on the second side of the first packaged die, coupled to the plurality of vertical interconnects, and configured to be coupled to a second packaged die.

[0072] 2. The 3D IC package of clause 1, wherein the first packaged die further comprises:

[0073] a first semiconductor substrate, wherein the first side of the first packaged die comprises the first side of the first semiconductor substrate; and

[0074] A first active circuit layer is located on the first side of the first semiconductor substrate, wherein the metallization layer is disposed on the first active circuit layer.

[0075] 3. The 3D IC package of clause 2, wherein:

[0076] each of the horizontal interconnects in the distribution layer is coupled to a corresponding metal trace in a first of the metallization layers on the first side of the first packaged die; and

[0077] Each of the metal traces extends in a third direction orthogonal to the second direction and is coupled to one of the plurality of vertical interconnects.

[0078] 4. The 3D IC package of clause 3, wherein at least one vertical interconnect of the plurality of vertical interconnects extends between one of the second die contacts and one of the metal traces in the first metallization layer.

[0079] 5. The 3D IC package of one of clauses 3 and 4, wherein at least one vertical interconnect of the plurality of vertical interconnects extends between one of the second die contacts and another metallization layer, the other metallization layer being located between the first metallization layer and the first active circuit layer.

[0080] 6. The 3D IC package of any one of clauses 1 to 5, wherein the first die contacts each comprise a portion of a horizontal interconnect in the distribution layer.

[0081] 7. The 3D IC package of any one of clauses 1 to 5, wherein each of the first die contacts comprises a contact coupled to a horizontal interconnect.

[0082] 8. The 3D IC package of any one of clauses 2 to 5, further comprising the second packaged die comprising a second active circuit layer coupled to the second die contacts on the second side of the first packaged die.

[0083] 9. The 3D IC package of clause 8, wherein the first active circuit layer comprises:

[0084] secondary circuit blocks, each secondary circuit block comprising a primary circuit block, wherein each of the primary circuit blocks comprises memory array circuitry;

[0085] a primary separation channel disposed between the primary circuit blocks within each of the secondary circuit blocks; and

[0086] A secondary separation channel is provided between the secondary circuit blocks,

[0087] The secondary separation channel is wider than the primary separation channel.

[0088] 10. The 3D IC package of clause 9, wherein the primary circuit blocks include static random access memory (SRAM) circuits and / or dynamic random access memory (DRAM) circuits.

[0089] 11. The 3D IC package of one of clauses 9 and 10, wherein the second active circuit layer is configured to receive power through a power distribution network (PDN) coupled to the second die contact.

[0090] 12. The 3D IC package of any one of clauses 9 to 11, wherein the second active circuit layer comprises digital logic circuitry configured to access the primary circuit blocks in the first active circuit layer.

[0091] 13. The 3D IC package of any one of clauses 9 to 12, wherein each vertical interconnect of the plurality of vertical interconnects comprises at least one through silicon via (TSV).

[0092] 14. The 3D IC package of clause 13, the plurality of vertical interconnects comprising primary vertical interconnects extending through the primary separation channel in the first packaged die, wherein the at least one TSV in the primary vertical interconnect comprises less than four (4) TSVs.

[0093] 15. The 3D IC package of one of clauses 13 and 14, the plurality of vertical interconnects comprising secondary vertical interconnects extending through the secondary separation channel in the first packaged die, wherein the at least one TSV in the secondary vertical interconnect comprises four (4) or more TSVs.

[0094] 16. The 3D IC package of any one of clauses 8 to 15, wherein:

[0095] The area of ​​the second packaged die is smaller than the area of ​​the first packaged die;

[0096] The first packaged die comprises:

[0097] an overlap region in which the second packaged die overlaps the second side of the first packaged die; and

[0098] a non-overlapping area, the non-overlapping area being located outside the overlapping area;

[0099] the second die contact being disposed in the overlap region;

[0100] One of the first die contacts is disposed in the non-overlap region of the first packaged die; and

[0101] A horizontal interconnect couples the primary vertical interconnect in the overlap region to the one of the first die contacts in the non-overlap region.

[0102] 17. The 3D IC package of any one of clauses 8 to 15, wherein:

[0103] The area of ​​the second packaged die is smaller than the area of ​​the first packaged die;

[0104] The first packaged die comprises:

[0105] an overlap region in which the second packaged die overlaps the second side of the first packaged die; and

[0106] a non-overlapping area, the non-overlapping area being located outside the overlapping area;

[0107] the second die contact being disposed in the overlap region;

[0108] the first packaged die comprising a row of primary vertical interconnects disposed in the overlap region parallel to a perimeter of the overlap region; and

[0109] The horizontal interconnect couples the row of primary vertical interconnects to the first die contacts in the non-overlap region.

[0110] 18. The 3D IC package of clause 14, wherein:

[0111] The primary circuit blocks in one of the secondary circuit blocks are arranged in columns separated by one of the primary separation channels;

[0112] Each of the primary separation channels comprises end regions and a central region disposed between the end regions; and

[0113] The primary vertical interconnect extending through the primary separation channel in one of the secondary circuit blocks extends through the end regions and not through the central region.

[0114] 19. A 3D IC package according to any one of clauses 1 to 18, wherein the 3D IC package is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multirotor aircraft.

[0115] 20. A method of manufacturing a three-dimensional (3D) integrated circuit (IC) package, the method comprising forming a first packaged die, the method comprising:

[0116] forming a plurality of vertical interconnects extending through the first packaged die in a first direction between a first side of the first packaged die and a second side of the first packaged die;

[0117] forming a distribution layer comprising horizontal interconnects extending in a second direction orthogonal to the first direction, the distribution layer disposed on a metallization layer on the first side of the first packaged die and coupled to the plurality of vertical interconnects;

[0118] forming a first die contact disposed on the first side of the first packaged die and coupled to the horizontal interconnect; and

[0119] A second die contact is formed, disposed on the second side of the first packaged die, coupled to the plurality of vertical interconnects, and configured to be coupled to a second packaged die.

[0120] 21. The method of clause 20, wherein forming the plurality of vertical interconnects further comprises forming vias coupled to a first one of the first die contacts and a second one of the second die contacts.

[0121] 22. The method of clause 21, wherein forming the first packaged die further comprises:

[0122] forming a first active circuit layer;

[0123] forming the metallization layer on the first active circuit layer; and

[0124] forming a metal trace in a first metallization layer of the metallization layers,

[0125] Wherein the metal trace couples the horizontal interconnect to the via.

[0126] 23. The method of clause 22, wherein forming the plurality of vertical interconnects further comprises forming the plurality of vertical interconnects between circuit blocks in the first active circuit layer.

Claims

1. A three-dimensional (3D) integrated circuit (IC) package, comprising: A first packaged die, the first packaged die comprising: a plurality of vertical interconnects extending through the first packaged die in a first direction between a first side of the first packaged die and a second side of the first packaged die; a distribution layer comprising horizontal interconnects extending in a second direction orthogonal to the first direction, the distribution layer disposed on the metallization layer on the first side of the first packaged die and coupled to the plurality of vertical interconnects; a first die contact disposed on the first side of the first packaged die and coupled to the horizontal interconnect; and A second die contact is disposed on the second side of the first packaged die, coupled to the plurality of vertical interconnects, and configured to be coupled to a second packaged die.

2. The 3D IC package of claim 1 , wherein the first packaged die further comprises: a first semiconductor substrate, wherein the first side of the first packaged die comprises the first side of the first semiconductor substrate; and A first active circuit layer is located on the first side of the first semiconductor substrate, wherein the metallization layer is disposed on the first active circuit layer.

3. The 3D IC package according to claim 2, wherein: each of the horizontal interconnects in the distribution layer is coupled to a corresponding metal trace in a first of the metallization layers on the first side of the first packaged die; and Each of the metal traces extends in a third direction orthogonal to the second direction and is coupled to one of the plurality of vertical interconnects. 4 . The 3D IC package of claim 3 , wherein at least one vertical interconnect of the plurality of vertical interconnects extends between one of the second die contacts and one of the metal traces in the first metallization layer.

5. The 3D IC package of claim 3 , wherein at least one vertical interconnect of the plurality of vertical interconnects extends between one of the second die contacts and another metallization layer, the another metallization layer being located between the first metallization layer and the first active circuit layer. 6 . The 3D IC package of claim 1 , wherein the first die contacts each comprise a portion of a horizontal interconnect in the distribution layer. 7 . The 3D IC package of claim 1 , wherein each of the first die contacts comprises a contact coupled to a horizontal interconnect. 8 . The 3D IC package of claim 2 , further comprising the second packaged die comprising a second active circuit layer coupled to the second die contacts on the second side of the first packaged die.

9. The 3D IC package according to claim 8, wherein the first active circuit layer comprises: secondary circuit blocks, each secondary circuit block comprising a primary circuit block, wherein each of the primary circuit blocks comprises memory array circuitry; a primary separation channel disposed between the primary circuit blocks within each of the secondary circuit blocks; and A secondary separation channel is provided between the secondary circuit blocks, The secondary separation channel is wider than the primary separation channel. 10 . The 3D IC package of claim 9 , wherein the primary circuit block comprises a static random access memory (SRAM) circuit and / or a dynamic random access memory (DRAM) circuit. 11 . The 3D IC package of claim 9 , wherein the second active circuit layer is configured to receive power through a power distribution network (PDN) coupled to the second die contact. 12 . The 3D IC package of claim 9 , wherein the second active circuit layer comprises digital logic circuits configured to access the primary circuit blocks in the first active circuit layer. 13 . The 3D IC package of claim 9 , wherein each vertical interconnect of the plurality of vertical interconnects comprises at least one through silicon via (TSV).

14. The 3D IC package of claim 13, the plurality of vertical interconnects comprising primary vertical interconnects extending through the primary separation channel in the first packaged die, wherein the at least one TSV in the primary vertical interconnect comprises less than four (4) TSVs.

15. The 3D IC package of claim 13, the plurality of vertical interconnects comprising secondary vertical interconnects extending through the secondary separation channel in the first packaged die, wherein the at least one TSV in the secondary vertical interconnect comprises four (4) or more TSVs.

16. The 3D IC package according to claim 8, wherein: The area of ​​the second packaged die is smaller than the area of ​​the first packaged die; The first packaged die comprises: an overlap region in which the second packaged die overlaps the second side of the first packaged die; and a non-overlapping area, the non-overlapping area being located outside the overlapping area; the second die contact being disposed in the overlap region; One of the first die contacts is disposed in the non-overlap region of the first packaged die; and A horizontal interconnect couples the primary vertical interconnect in the overlap region to the one of the first die contacts in the non-overlap region.

17. The 3D IC package according to claim 8, wherein: The area of ​​the second packaged die is smaller than the area of ​​the first packaged die; The first packaged die comprises: an overlap region in which the second packaged die overlaps the second side of the first packaged die; and a non-overlapping area, the non-overlapping area being located outside the overlapping area; the second die contact being disposed in the overlap region; the first packaged die comprising a row of primary vertical interconnects disposed in the overlap region parallel to a perimeter of the overlap region; and The horizontal interconnect couples the row of primary vertical interconnects to the first die contacts in the non-overlap region.

18. The 3D IC package of claim 14, wherein: The primary circuit blocks in one of the secondary circuit blocks are arranged in columns separated by one of the primary separation channels; Each of the primary separation channels comprises end regions and a central region disposed between the end regions; and The primary vertical interconnect extending through the primary separation channel in one of the secondary circuit blocks extends through the end regions and not through the central region.

19. The 3D IC package of claim 1 , wherein the 3D IC package is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multirotor aircraft.

20. A method of manufacturing a three-dimensional (3D) integrated circuit (IC) package, the method comprising forming a first packaged die, the method comprising: forming a plurality of vertical interconnects extending through the first packaged die in a first direction between a first side of the first packaged die and a second side of the first packaged die; forming a distribution layer comprising horizontal interconnects extending in a second direction orthogonal to the first direction, the distribution layer disposed on a metallization layer on the first side of the first packaged die and coupled to the plurality of vertical interconnects; forming a first die contact disposed on the first side of the first packaged die and coupled to the horizontal interconnect; as well as A second die contact is formed, disposed on the second side of the first packaged die, coupled to the plurality of vertical interconnects, and configured to be coupled to a second packaged die. 21 . The method of claim 20 , wherein forming the plurality of vertical interconnects further comprises forming vias coupled to a first one of the first die contacts and a second one of the second die contacts.

22. The method of claim 21, wherein forming the first packaged die further comprises: forming a first active circuit layer; forming the metallization layer on the first active circuit layer; as well as forming a metal trace in a first metallization layer of the metallization layers, Wherein the metal trace couples the horizontal interconnect to the via. 23 . The method of claim 22 , wherein forming the plurality of vertical interconnects further comprises forming the plurality of vertical interconnects between circuit blocks in the first active circuit layer.

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