Solid-state imaging element, light detection device, and method for manufacturing solid-state imaging element

Abstract

The present invention suppresses a current change in a solid-state imaging element in which a transistor serving as a current source is provided in each pixel. A current source transistor, a capacitance element, and a sample-and-hold switch are provided in each of a plurality of pixels. The current source transistor has a source connected to a ground node, and supplies a predetermined drain-source current. The capacitive element is interposed between a gate of the current source transistor and the ground node. The sample-and-hold switch samples and holds a predetermined bias voltage in the capacitive element during a period in which the drain-source current is not supplied.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element. More specifically, the present technology relates to a solid-state imaging element provided with a transistor as a current source, a light detection device, and a method for manufacturing the solid-state imaging element. Background Art

[0002] Conventionally, CMOS image sensors (CIS) use a global shutter method that exposes all pixels simultaneously to suppress rolling shutter distortion. For example, solid-state imaging devices have been proposed that use a capacitor element for each pixel and sample and hold a voltage in the capacitor element (see, for example, Non-Patent Document 1). In these solid-state imaging devices, an n-channel metal oxide semiconductor (nMOS) transistor with a grounded source and a gate bias voltage is provided for each pixel as a current source. Citation list Patent Literature

[0003] Patent Document 1: Geunsook Park, et al., A 2.2μm stacked back side illuminated voltage domain global shutter CMOS image sensor, IEDM 2019. Summary of the Invention Technical Problems to be Solved by the Invention

[0004] In the conventional technology described above, a global shutter method is implemented by providing a capacitor element for each pixel to sample and hold the voltage. However, in these solid-state imaging elements, the gate-source voltage of the nMOS transistor, which serves as a current source, varies for each pixel due to factors such as ground bounce when driving the pixels. As a result, there is a problem in which the current flowing through the nMOS transistor, which serves as a current source, varies for each pixel.

[0005] The present technology has been made in view of such circumstances, and an object of the present technology is to suppress current variation in a solid-state imaging element in which a transistor as a current source is provided for each pixel. Solutions to technical problems

[0006] The present technology is designed to address the aforementioned issues. A first aspect of the present technology is a solid-state imaging element and a method for controlling the same. The solid-state imaging element includes a plurality of pixels, each of which is provided with: a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current; a capacitor inserted between the gate of the current source transistor and the ground node; and a sample-and-hold switch configured to sample and hold a predetermined bias voltage in the capacitor during a period in which the drain-source current is not supplied. This effectively suppresses current variations.

[0007] Furthermore, in the first aspect, the device may further include: an amplifier transistor that amplifies the voltage of the floating diffusion layer and outputs the amplified voltage from its source; and a switch circuit that opens and closes the path between the amplifier transistor and the current source transistor, wherein the sample-and-hold switch can sample and hold the bias voltage in the capacitor while the switch circuit is in the off state. This achieves the effect of holding the bias voltage.

[0008] Furthermore, in the first aspect, a sample-and-hold circuit may be further included that holds each of a signal level corresponding to the exposure amount and a predetermined reset level. This results in an effect of realizing a global shutter.

[0009] Furthermore, in the first aspect, the switching circuit may include at least one of: a switching transistor that opens and closes a path between the source of the amplifier transistor and a preceding node connected to the sample-and-hold circuit; and a precharge transistor that opens and closes a path between the preceding node and the drain of the current source transistor. This provides the effect of cutting off current by controlling the transistor.

[0010] Furthermore, in the first aspect, the device may further include a mirror source transistor through which a predetermined reference current flows, wherein the sample-and-hold switch can open and close a path between the gate and drain of the mirror source transistor and the gate of the current source transistor. This provides an effect of supplying a current corresponding to the reference current.

[0011] Furthermore, in the first aspect, the current source transistor, the capacitive element, and the sample-and-hold switch may be arranged on any one of a plurality of stacked semiconductor chips. This facilitates miniaturization of the pixel.

[0012] Furthermore, in the first aspect, each of the plurality of pixels can detect the presence or absence of an address event. This has the effect of suppressing current variation in the pixel that detects the address event.

[0013] In addition, a second aspect of the present technology is a light detection device comprising: a pixel among a plurality of pixels, each pixel being provided with: a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current; a capacitor element interposed between the gate of the current source transistor and the ground node; a sample-and-hold switch configured to sample and hold a predetermined bias voltage in the capacitor element during a period in which the drain-source current is not supplied; and a signal processing circuit that processes a pixel signal from each of the plurality of pixels. This results in reduced power consumption by suppressing current variations. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 : is a block diagram showing a configuration example of an image pickup device according to a first embodiment of the present technology. Figure 2 : is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology. Figure 3 is a circuit diagram showing a configuration example of a pixel according to the first embodiment of the present technology. Figure 4 is a circuit diagram showing a configuration example of the accessory according to the first embodiment of the present technology. Figure 5 : is a block diagram showing a configuration example of a load metal oxide semiconductor (MOS) circuit block and a column signal processing circuit according to the first embodiment of the present technology. Figure 6 is a timing chart showing an operation example of the solid-state imaging element according to the first embodiment of the present technology. Figure 7 is a graph showing an example of characteristics of the current source transistor according to the first embodiment of the present technology. Figure 8 : is a circuit diagram showing an example of a state of a solid-state imaging element of a comparative example. Figure 9 : is a diagram showing an example of a state of the solid-state imaging element at the time of sample-hold according to the first embodiment of the present technology. Figure 10 : is a diagram showing an example of a state of the solid-state imaging element after sampling and holding of pixels according to the first embodiment of the present technology. Figure 11 : is a diagram showing a layout example of a sample-and-hold switch, a capacitance element, and a current source transistor according to the first embodiment of the present technology. Figure 12 is a flowchart illustrating an operation example of the solid-state imaging element according to the first embodiment of the present technology. Figure 13 is a circuit diagram showing a configuration example of a pixel according to a first modification example of the first embodiment of the present technology. Figure 14 is a circuit diagram illustrating another example of a pixel according to the first modification example of the first embodiment of the present technology. Figure 15 is a circuit diagram showing a configuration example of a pixel in which the number of transistors is reduced according to a first modification example of the first embodiment of the present technology. Figure 16 is a diagram illustrating an example of a stacked structure of a solid-state imaging element according to a second embodiment of the present technology. Figure 17 is a circuit diagram showing a configuration example of a pixel according to a second embodiment of the present technology. Figure 18 is a block diagram showing a configuration example of a solid-state imaging element according to a third embodiment of the present technology. Figure 19 is a circuit diagram showing a configuration example of a pixel according to a third embodiment of the present technology. Figure 20 is a block diagram showing a schematic configuration example of a vehicle control system. Figure 21 1 is an explanatory diagram showing an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0015] Modes for implementing the present technology (hereinafter, referred to as embodiments) will be described below. The description will be made in the following order. 1. First Embodiment (Example of Sampling and Holding in a Capacitive Element While Current is Stopped) 2. Second Embodiment (Example of Sampling and Holding in a Capacitive Element While Current is Stopped in a Stacked Structure) 3. Third Embodiment (Example of Sampling and Holding in a Capacitive Element While Current is Stopped and Detecting an Address Event) 4. Application Examples of Mobile Objects

[0016] <1. First Implementation Plan> [Configuration Example of Image Capture Device] Figure 1This is a block diagram illustrating an example configuration of an imaging device 100 according to the first embodiment of the present technology. The imaging device 100 captures image data and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. Assume that the imaging device 100 is a digital camera or an electronic device with an imaging function (such as a smartphone or personal computer). Note that the imaging device 100 is an example of the light detection device described in the claims.

[0017] The solid-state imaging element 200 captures image data under the control of the imaging control unit 130 . The solid-state imaging element 200 supplies the image data to the recording unit 120 via the signal line 209 .

[0018] The imaging lens 110 collects light and guides it to the solid-state imaging element 200. The imaging control unit 130 controls the solid-state imaging element 200 to capture image data. For example, the imaging control unit 130 supplies imaging control signals including the vertical synchronization signal VSYNC to the solid-state imaging element 200 via the signal line 139. The recording unit 120 records the image data.

[0019] Here, the vertical synchronization signal VSYNC is a signal indicating an imaging timing, and a periodic signal of a constant frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0020] Note that although the imaging device 100 records image data, the image data may be transmitted to an external portion of the imaging device 100. In this case, an external interface for transmitting image data is also provided. Alternatively, the imaging device 100 may also display image data. In this case, a display unit is also provided.

[0021] [Structure Example of Solid-State Imaging Element] Figure 2 This is a block diagram illustrating an example configuration of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 is a CIS and includes a vertical scanning circuit 211, an accessory 220, and a pixel array section 230. Furthermore, the solid-state imaging element 200 includes a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array section 230, a plurality of pixels 300 are arranged in a two-dimensional grid pattern. Furthermore, each circuit in the solid-state imaging element 200 is provided on, for example, a single semiconductor chip.

[0022] Hereinafter, a set of pixels 300 arranged in a horizontal direction is referred to as a “row”, and a set of pixels 300 arranged in a direction perpendicular to the row is referred to as a “column”.

[0023] The timing control circuit 212 controls the operation timing of each of the vertical scanning circuit 211 , the DAC 213 , and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control section 130 .

[0024] The DAC 213 generates a sawtooth ramp signal through digital-to-analog (DA) conversion and supplies the generated ramp signal to the column signal processing circuit 260 .

[0025] The vertical scanning circuit 211 sequentially selects and drives rows to output analog pixel signals. Each pixel 300 performs photoelectric conversion on incident light to generate an analog pixel signal. The pixel 300 supplies the pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250.

[0026] In the attachment 220, a mirror source transistor is arranged, which forms a current mirror circuit with a current source transistor (not shown) in the pixel.

[0027] In the load MOS circuit block 250 , a MOS transistor that supplies a constant current is provided for each column.

[0028] The column signal processing circuit 260 performs signal processing on the pixel signals for each column, such as analog-to-digital (AD) conversion and correlated double sampling (CDS). The column signal processing circuit 260 supplies image data including the processed signals to the recording unit 120. Note that the column signal processing circuit 260 is an example of the signal processing circuit described in the claims.

[0029] [Pixel Structure Example] Figure 3 is a circuit diagram showing an example of the construction of a pixel 300 according to the first embodiment of the present technology. The pixel 300 includes a front-stage circuit 310, a sampling and holding circuit 350, and a rear-stage circuit 360. The front-stage circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, a front-stage reset transistor 313, a floating diffusion (FD: floating diffusion) 314, and a front-stage amplifier transistor 315. In addition, the front-stage circuit 310 also includes a switching circuit 330, a current source transistor 317, a capacitor element 318, and a sampling and holding switch 319. The switching circuit 330 includes a switching transistor 331. In addition, the pixel 300 also includes a conversion efficiency control transistor 320, a capacitor element 321, and a pre-charge transistor 332. In addition, a selector 308 is added for each column. As a transistor in the front-stage circuit 310, for example, an nMOS transistor is used.

[0030] The photoelectric conversion element 311 photoelectrically converts incident light to generate charge. The transfer transistor 312 transfers the charge from the photoelectric conversion element 311 to the FD 314 according to the transfer signal TRG from the vertical scanning circuit 211. The pre-stage reset transistor 313 initializes the FD 314 according to the reset signal RST from the vertical scanning circuit 211.

[0031] The FD 314 accumulates charge and generates a voltage corresponding to the amount of charge. Hereinafter, the voltage when the FD 314 is initialized is referred to as a “reset level”, and the voltage when charge is transferred to the FD 314 is referred to as a “signal level”.

[0032] The pre-stage amplifier transistor 315 amplifies the voltage of the FD 314 and outputs the amplified voltage from the source. Note that the pre-stage amplifier transistor 315 is an example of an amplifier transistor described in the claims.

[0033] The switching transistor 331 opens and closes the path between the source of the preceding amplifier transistor 315 and the drain of the current source transistor 317 according to the control signal SW from the vertical scanning circuit 211. The connection node between the switching transistor 331 and the current source transistor 317 is referred to as a preceding node 316.

[0034] The current source transistor 317 supplies a constant drain-source current I according to the voltage applied to the gate. ds Furthermore, the source of the current source transistor 317 is connected to the ground node.

[0035] Capacitor 318 is inserted between the gate and source (in other words, the ground node) of current source transistor 317. Sample hold switch 319 opens and closes the path between accessory 220 and the gate of current source transistor 317 according to control signal SH from vertical scanning circuit 211.

[0036] Here, a configuration in which the capacitive element 318 and the sample-hold switch 319 are not provided is assumed as a comparative example.

[0037] In the comparative example, it is assumed that the vertical scanning circuit 211 turns on the switching transistors 331 of all pixels by the control signal SW at the end of exposure. As a result, the drain-source current I ds Flows through the current source transistor 317 of all pixels. At this time, the gate-source voltage V gs It varies for each pixel. Gate-source voltage V gs The change is caused by the following two factors.

[0038] The first factor is ground bounce on the pixel side caused by the IR drop caused by the DC current in the pixel itself. Although the ground grid resistance is minimized as much as possible through mesh wiring, bounce of about tens of millivolts (mV) is unavoidable.

[0039] The second factor is the change in bias voltage VB due to ground bounce on the accessory 220 side. However, regarding the second factor, since the accessory 220 is arranged outside the pixel array section 230, it is easy to take measures to prevent ground bounce. Therefore, the first factor has a greater impact.

[0040] Therefore, the capacitor 318 and the sample-hold switch 319 are arranged, and the vertical scanning circuit 211 switches the sample-hold switch 319 from the closed state to the open state by the control signal SH during the period when the switching transistor 331 is in the off state. As a result, the bias voltage VB is sampled and held in the capacitor 318.

[0041] Thereafter, when the switching transistor 331 turns on, ground bounce occurs; however, since the sample-hold switch 319 is in the off state, the charge on the voltage side of the capacitor 318 has nowhere to escape, and the voltage rises by the amount of ground bounce. As a result, the potential difference between the two ends of the capacitor 318 (i.e., the gate-source voltage V gs As a result, the drain-source current I ds fluctuations.

[0042] Assuming that the capacitance value of the parasitic capacitance is Cp and the capacitance value of the capacitor 318 is Cs, the gate-source voltage V gs Fluctuation ΔV relative to ground bounce gs It is represented by, for example, the following expression. ΔV gs ∝ Cs / (Cp + Cs) … Expression 1

[0043] For example, assuming Cp is approximately 1 femtofarad (fF), in order to gs To reduce by 90%, according to the above expression, Cs only needs to be about 10 femtofarads (fF). With this capacitance value, the area of ​​the capacitor 318 and the ability of the power supply side potential to follow the rebound can be properly balanced.

[0044] The sample-and-hold circuit 350 holds a signal level corresponding to the exposure amount and a predetermined reset level. The sample-and-hold circuit 350 includes capacitors 351 and 352, selection transistors 353 and 354, and a subsequent reset transistor 355. As transistors in the sample-and-hold circuit 350, for example, nMOS transistors are used.

[0045] Capacitors 351 and 352 hold the voltage (reset level or signal level) output from the preceding circuit 310. For example, capacitor 351 holds the reset level, while capacitor 352 holds the signal level. For example, a capacitor having a metal-insulator-metal (MIM) structure is used as such. Furthermore, one end of each of capacitors 351 and 352 is commonly connected to the preceding node 316.

[0046] The selection transistor 353 opens and closes the path between the other end of the capacitor element 351 and the subsequent node 356 in response to a selection signal S1 from the vertical scanning circuit 211. The selection transistor 354 opens and closes the path between the other end of the capacitor element 352 and the subsequent node 356 in response to a selection signal S2 from the vertical scanning circuit 211.

[0047] The subsequent reset transistor 355 initializes the voltage of the subsequent node 356 to a predetermined potential VREG according to a subsequent reset signal RB from the vertical scanning circuit 211. A potential different from the power supply voltage VDD (eg, a potential lower than VDD) is set as the potential VREG.

[0048] The subsequent-stage circuit 360 includes a subsequent-stage amplification transistor 361 and a subsequent-stage selection transistor 362. As these transistors, for example, nMOS transistors are used.

[0049] The post-stage amplifier transistor 361 amplifies the voltage of the post-stage node 356. The post-stage selection transistor 362 outputs the voltage signal amplified by the post-stage amplifier transistor 361 to the vertical signal line 309 as a pixel signal based on the selection signal SEL from the vertical scanning circuit 211.

[0050] The conversion efficiency control transistor 320 controls the conversion efficiency of converting charge into voltage based on the control signal FDG from the vertical scanning circuit 211. When the conversion efficiency control transistor 320 is in the on state, the capacitor element 321 is connected to the FD 314, and the conversion efficiency is reduced. On the other hand, when the conversion efficiency control transistor 320 is in the off state, the charge is converted into voltage only by the FD 314, so the conversion efficiency is improved. As the capacitor element 321, for example, an element with an MIM structure is used.

[0051] The selector 308 selects either the power supply voltage VDD or the voltage Vread based on the selection signal sel from the vertical scanning circuit 211, and supplies the selected voltage as the drain voltage VAMD to the drain of the pre-amplifier transistor 315. When the sample-and-hold circuit 350 samples and holds a voltage, the power supply voltage VDD is selected. On the other hand, when the sample-and-hold circuit 350 reads a voltage and performs AD conversion for each row, the voltage Vread is selected.

[0052] Here, the voltage Vread is set to a value shown in the following expression. Vread = VDD – Vgs – Vft … Expression 2 In the above expression, Vgs represents the gate-source voltage of the front-stage amplifying transistor 315 , and Vft is the amount of potential fluctuation of the FD 314 due to reset feedthrough of the front-stage reset transistor 313 .

[0053] By switching to the voltage Vread during reading, the pre-amplifier transistor 315 is turned off, thereby reducing noise generated in the transistor.

[0054] The precharge transistor 332 is arranged in the switch circuit 330 , and opens and closes a path between the previous stage node 316 and the current source transistor 317 according to the control signal PC from the vertical scanning circuit 211 .

[0055] Note that although both the switch transistor 331 and the precharge transistor 332 are arranged in the switch circuit 330 , only one of them may be arranged.

[0056] The sample-and-hold switch 319 samples and holds the bias voltage VB during a period in which at least one of the two transistors in the switch circuit 330 is in an off state.

[0057] In addition, in the sample-and-hold circuit 350 , p-channel metal oxide semiconductor (pMOS) transistors are used as the selection transistor 353 , the selection transistor 354 , and the subsequent-stage reset transistor 355 .

[0058] Furthermore, the vertical scanning circuit 211 can control the transfer signal TRG, reset signal RST, and control signal FDG to any of a high level, an intermediate level, and a low level. The high level is set to a value higher than "0" volts (V). The intermediate level is set to a value lower than the high level, for example, "0" volts (V). The low level is set to a value lower than the intermediate level, for example, "-1" volts (V). In other words, the transfer transistor 312, the previous reset transistor 313, and the conversion efficiency control transistor 320 are driven at three levels corresponding to these signals.

[0059] While holding the capacitor 351 at the reset level, the vertical scanning circuit 211 can softly reset the front-stage amplifier transistor 315 by changing the transfer signal TRG, the reset signal RST, and the control signal FDG from the intermediate level to the low level. As a result, kTC noise is reduced.

[0060] Furthermore, by using pMOS as the transistor in the sample-and-hold circuit 350 , the charge loss of the capacitor 351 can be reduced when the gate voltage of the previous-stage amplifier transistor 315 returns from a low level to an intermediate level.

[0061] Note that while all of the conversion efficiency control transistor 320, capacitor 321, selector 308, and precharge transistor 332 are provided, this configuration is not limited to this, and some of them may be reduced. Furthermore, while some transistors are driven by the vertical scanning circuit 211 at three values, these transistors may be driven at two values ​​if a soft reset is not required. Furthermore, while three pMOS transistors are provided in the sample-and-hold circuit 350, nMOS transistors may be used as some or all of these transistors.

[0062] [Example of attachment structure] Figure 4 This is a circuit diagram showing an example configuration of an accessory 220 according to the first embodiment of the present technology. The accessory 220 includes a reference current source 221 and a plurality of mirror transistors 222. When mirror transistors 222 are arranged for each row, and the number of rows is N (N is an integer), the number of mirror transistors 222 is N. For example, nMOS transistors are used as mirror transistors 222.

[0063] The reference current source 221 supplies a predetermined reference current I ref The gate and drain of each mirror source transistor 222 are connected to the reference current source 221, and the source is connected to the ground node. In addition, the sample-hold switch 319 opens and closes the path between the gate and drain of the mirror source transistor 222 of the corresponding row and the gate of the current source transistor 317. Note that in this figure, components other than the current source transistor 317, the capacitor 318, and the sample-hold switch 319 are omitted in each pixel 300.

[0064] Through the above circuit configuration, when the sample-hold switch 319 is in the closed state, the mirror source transistor 222 and the corresponding current source transistor 317 form a current mirror circuit. If the switch transistor 331 (not shown) is in the on state when the sample-hold switch 319 is in the closed state, the reference current I ref The drain-source current I ds flows through the current source transistor 317.

[0065] To suppress the effects of ground bounce, the vertical scanning circuit 211 switches the sample-and-hold switch 319 from on to off using the control signal SH during the period when the switching transistor 331 is off. As a result, the voltage at the gate of the mirror source transistor 222 is sampled and held in the capacitor 318 as the bias voltage VB.

[0066] After the sampling and holding, the vertical scanning circuit 211 turns on the switching transistor 331. At this time, since the bias voltage VB is held in the capacitor 318, the reference current I ref The drain-source current I ds flows through the current source transistor 317.

[0067] [Configuration Example of Column Signal Processing Circuit] Figure 5 : is a block diagram showing a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0068] In the load MOS circuit block 250 , a vertical signal line 309 is wired for each column. When the number of columns is 1 (I is an integer), one vertical signal line 309 is wired. Furthermore, a load MOS transistor 251 that supplies a constant current is connected to each vertical signal line 309 .

[0069] In the column signal processing circuit 260, a plurality of analog-to-digital converters (ADCs) 261 and a digital signal processing unit 262 are arranged. The ADC 261 is arranged for each column. When the number of columns is one, one ADC 261 is arranged.

[0070] The ADC 261 converts the analog pixel signal from the corresponding column into a digital signal using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signal to the digital signal processing section 262. For example, a single slope ADC including a comparator and a counter is arranged as the ADC 261.

[0071] The digital signal processing section 262 performs predetermined signal processing such as CDS processing on each digital signal of each column, and supplies image data including the processed digital signal to the recording section 120 .

[0072] [Operation Example of Solid-State Imaging Element] Figure 6 This is a timing diagram illustrating an example of the operation of the solid-state imaging element 200 according to the first embodiment of the present technology. The vertical scanning circuit 211 drives all pixels to simultaneously initiate exposure. In other words, exposure is performed using a global shutter method. During the sample-and-hold period from time T2 to time T20, at the end of the exposure period, the vertical scanning circuit 211 drives all pixels to maintain their voltages (reset and signal levels). Then, during the read period from time T20 to time T30, the vertical scanning circuit 211 sequentially drives rows to read voltages and perform analog-to-digital (AD) conversion.

[0073] In the period before time T2, the control signal SW is at a low level and the control signal SH is at a high level. At time T1 within this period, the vertical scanning circuit 211 changes the control signal SH from a high level to a low level. As a result, the bias voltage is sampled and held in the capacitor element 318 of the pixel.

[0074] At time T2, the vertical scanning circuit 211 sets the control signal FDG, the reset signal RST, the control signal SW, and the control signal PC to the high level. As a result, the FD 314 and the subsequent node are initialized.

[0075] At time T3, the vertical scanning circuit 211 sets the control signal FDG and the reset signal RST to the intermediate level. As a result, the reset level is determined, and the previous stage node is in the potential state buffered by the previous stage amplifying transistor 315.

[0076] The vertical scanning circuit 211 sets the selection signals S1 and S2 to the low level at time T4 and sets the selection signal S2 to the high level at time T5 immediately thereafter. As a result, the reset level is sampled in the capacitive element 351.

[0077] Then, at time T6, the vertical scanning circuit 211 changes the transfer signal TRG, the reset signal RST, and the control signal FDG from the intermediate level to the low level, and changes the control signal PC from the high level to the low level. As a result, the voltage of the FD 314 (the gate of the pre-amplifier transistor 315) drops, the pre-amplifier transistor 315 is softly reset, and the reset level is held in the capacitor 351.

[0078] At time T7, the vertical scanning circuit 211 sets the subsequent reset signal RB to a high level. As a result, the subsequent reset transistor 355 on the right side of the capacitor 351 is also turned off.

[0079] At time T8, the vertical scanning circuit 211 sets the selection signal S1 to a high level. As a result, the selection transistor 353 is also turned off.

[0080] At time T9, the vertical scanning circuit 211 returns the transfer signal TRG, the reset signal RST, and the control signal FDG to the intermediate level and returns the control signal PC to the high level. As a result, the charge lost at time T6 can be restored and the loss of reset level information can be prevented.

[0081] At time T10, the vertical scanning circuit 211 sets the transfer signal TRG to a high level and the selection signal S2 to a low level. As a result, the charge is transferred to the FD 314. At time T11, the vertical scanning circuit 211 sets the transfer signal TRG to an intermediate level. As a result, the signal level is sampled in the capacitor 352.

[0082] At time T12, the vertical scanning circuit 211 sets the subsequent-stage reset signal RB to a low level, and then immediately sets the transfer signal TRG, the reset signal RST, and the control signal FDG to a low level. At time T13, the vertical scanning circuit 211 returns the subsequent-stage reset signal RB to a high level. As a result, the subsequent-stage node is initialized.

[0083] At time T14 , the vertical scanning circuit 211 sets the selection signal S2 to high level and returns the transfer signal TRG, reset signal RST, and control signal FDG to intermediate levels. As a result, the selection transistor 354 is turned off, and the signal level is held in the capacitor 352 .

[0084] In the subsequent reading period, the control signal SW is controlled to an intermediate level. In addition, the selection signals S1 and S2 are sequentially controlled to a high level, and the reset level and the signal level are sequentially read.

[0085] Note that the vertical scanning circuit 211 keeps the switching transistor 331 on during the sampling and holding period, but control is not limited to this. For example, the vertical scanning circuit 211 may alternately turn on and off the switching transistor 331 and the precharge transistor 332 during the sampling and holding period. This can accelerate the settling of the previous node from a high level to a low level, improving responsiveness.

[0086] As shown in the figure, when the control signal SW is at a low level and no drain-source current I is supplied dsDuring the period of , the control signal SH is controlled from high level to low level. As a result, the bias voltage is sampled and held in the capacitor element 318 of the pixel.

[0087] Figure 7 : is a graph showing an example of the characteristics of the current source transistor 317 according to the first embodiment of the present technology. In this graph, the vertical axis represents the drain-source current I ds , and the horizontal axis represents the gate-source voltage V gs .

[0088] In the case where the current source transistor 317 is arranged for each pixel, from the viewpoint of suppressing power consumption, the current value of each pixel must be several nanoamperes (nA) and inevitably smaller than the threshold voltage V th The current in the weak inversion region (in other words, the subthreshold region) of the drain-source is ds It is represented by the following expression. I ds = I0•exp{(V gs -V th ) / ηV T} ... Expression 3 In the above expression, I0 and η are coefficients, and V T is the thermal voltage.

[0089] According to Expression 3, in the weak inversion region, the drain-source current I ds is the power of the natural logarithm, corresponding to the gate-source voltage V gs As mentioned above, the same degree of ΔV is generated in the strong inversion region. gs Compared with the case of gate-source voltage V gs Change of ΔV gs The drain-source current I ds Change in ΔI ds Very big.

[0090] Figure 8 3 is a circuit diagram showing an example of the state of the solid-state imaging element 200 of the comparative example. In the comparative example, the capacitor 318 and the sample-and-hold switch 319 are not provided in each pixel 300, and the gate and source of the mirror source transistor 222 are directly connected to the gate of the current source transistor 317 as the mirror destination.

[0091] In the comparative example, when all pixels are driven and the drain-source current I dsWhen current flows, ground bounce occurs due to the current, and the ground voltage varies for each pixel. For example, in the upper left pixel of this figure, the ground voltage is 80 millivolts (mV), but in the upper right pixel, the ground voltage is 100 millivolts (mV).

[0092] Note that although the bias voltage VB may vary due to ground bounce on the accessory side, for ease of explanation, it is assumed that the bias voltage VB does not vary.

[0093] In the comparative example, the gate-source voltage of the current source transistor 317 changes due to changes in the ground voltage of each pixel. For example, in the upper left pixel, since the bias voltage VB is 180 millivolts (mV) and the ground voltage is 80 millivolts (mB), the gate-source voltage is 100 millivolts (mV). On the other hand, in the upper right pixel, since the bias voltage VB is 180 millivolts (mV) and the ground voltage is 100 millivolts (mB), the gate-source voltage is 80 millivolts (mV). Due to the change in the gate-source voltage, the drain-source current I of the current source transistor 317 ds Varies for each pixel.

[0094] In the comparative example shown in the figure, it is necessary to supply a sufficiently large reference current I ref , so that even if the drain-source current I ds By changing the current, the current value required for driving can also be obtained in all pixels.

[0095] Figure 9 1 is a diagram illustrating an example of the state of the solid-state imaging element during pixel sample-holding according to the first embodiment of the present technology. A in the diagram illustrates the state of the solid-state imaging element during sampling using the sample-hold switch 319, and B in the diagram illustrates the state during holding.

[0096] As shown in a in the figure, assume that the supply of drain-source current Ids by current source transistor 317 is stopped in all pixels while switching transistor 331 (not shown) is in the off state. The dotted arrow indicates the cessation of supply of drain-source current Ids. During this period, ground bounce does not occur in any pixel, and the ground voltage of all pixels is, for example, 0 millivolts (mV).

[0097] Note that although the bias voltage VB may vary due to ground bounce on the accessory side, for ease of explanation, it is assumed that the bias voltage VB does not vary.

[0098] The vertical scanning circuit 211 closes the sample-hold switches 319 of all pixels. As a result, the bias voltage VB is sampled in the capacitor element 318.

[0099] Then, as shown in b in the figure, the vertical scanning circuit 211 closes the sample hold switches 319 of all pixels during the period in which the switching transistors 331 are in the off state. As a result, the bias voltage VB of the capacitor element 318 is held.

[0100] Then, if Figure 10 As shown, the vertical scanning circuit 211 turns on the switching transistors 331 (not shown) of all pixels and makes the drain-source current I ds This current causes ground bounce, and the ground voltage varies for each pixel. For example, in the upper left pixel of the figure, the ground voltage is 80 millivolts (mV), but in the upper right pixel, the ground voltage is 100 millivolts (mV).

[0101] At this time, since the sample-hold switch 319 is in the off state, the charge on the voltage side of the capacitor 318 has nowhere to escape. Therefore, according to the formula Q = CV, the voltage on the voltage side of the capacitor 318 rises by the amount of ground bounce. For example, in the upper left pixel, the power supply side voltage rises from 140 millivolts (mV) to 220 millivolts (mV), and in the upper right pixel, the power supply side voltage rises from 140 millivolts (mV) to 240 millivolts (mV). As a result, the gate-source voltages of the respective pixels are substantially the same, thereby suppressing the drain-source current I ds changes.

[0102] like Figure 9 and Figure 10 As shown, the variation of the drain-source current Ids can be suppressed by sampling and holding the bias voltage VB in the capacitor 318. Therefore, the current value of the reference current can be adjusted to the minimum value required for driving, and power consumption can be reduced compared to the comparative example.

[0103] Figure 11 This figure shows an example layout of a sample-and-hold switch 319, a capacitor 318, and a current source transistor 317 according to the first embodiment of the present technology. For example, a MOS transistor is used as the sample-and-hold switch 319. The gate of the transistor is connected to a signal line for supplying a control signal SH, and the source is connected to a signal line for supplying a bias voltage VB. In the figure, "G," "D," and "S" represent the gate, drain, and source of the MOS transistor.

[0104] In addition, for example, a gate capacitor of a MOS transistor is used as the capacitor element 318. The drain and source of this transistor are connected to a node of the ground voltage VSS, and the gate is connected to a signal line for supplying a bias voltage VB.

[0105] Furthermore, the current source transistor 317 has a gate connected to a connection node between the sample-and-hold switch 319 and the capacitance element 318 , and a source connected to a node of the ground voltage VSS.

[0106] Figure 12 1 is a flowchart showing an operation example of the solid-state imaging element 200 according to the first embodiment of the present technology. For example, when a predetermined application program for capturing image data is executed, the operation starts.

[0107] The vertical scanning circuit 211 starts exposure for all pixels by setting the control signal SW for all pixels to a low level (step S901). The vertical scanning circuit 211 then controls the sample-and-hold switches 319 for all pixels to sample and hold the bias voltage VB while holding the control signal SW at a low level (step S902). The vertical scanning circuit 211 then sets the control signal SW for all pixels to a high level, ending exposure for all pixels (step S903). Subsequently, the solid-state imaging element 200 sequentially reads all rows (step S904). After step S904, the solid-state imaging element 200 completes imaging operations.

[0108] As described above, according to the first embodiment of the present technology, since the sample-and-hold switch 319 samples and holds the bias voltage VB in the capacitor 318 while the drain-source current stops flowing, variations in the gate-source voltage can be suppressed. As a result, variations in the drain-source current of each pixel can be suppressed.

[0109] [Modification] In the first embodiment described above, a device having Figure 3 The circuit configuration of the pixel 300 is shown, but the circuit configuration of the pixel 300 is not limited to Figure 3 The solid-state imaging element 200 according to the modification of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that the same Figure 3 Different circuit configurations.

[0110] Figure 13 1 is a circuit diagram showing a configuration example of a pixel 300 according to a modification of the first embodiment of the present technology. The pixel 300 according to the modification of the first embodiment is different from the pixel 300 of the first embodiment in that there are two systems of subsequent stage circuits.

[0111] Pixel 300 includes subsequent circuits 360-1 and 360-2. Subsequent circuit 360-1 includes a subsequent amplifier transistor 361-1 and a subsequent selection transistor 362-1, and subsequent selection transistor 362-1 is connected to vertical signal line 309-1. Subsequent circuit 360-2 includes a subsequent amplifier transistor 361-2 and a subsequent selection transistor 362-2, and subsequent selection transistor 362-2 is connected to vertical signal line 309-2. The circuit configuration shown in this figure suppresses level fluctuations at subsequent nodes.

[0112] Note that Figure 14 As shown, the selection transistors 354 and 353 may be connected in series between the preceding circuit 310 and the succeeding circuit 360. In this case, the capacitor 351 is inserted between the succeeding node 356 and the ground node. The capacitor 352 is inserted between the connection node between the selection transistors 354 and 353 and the ground node.

[0113] Regarding the circuit shown in this figure, for example, reference can be made to the control described in “Chen Xu et al., A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single-Frame HDR and On-Chip Binarization Algorithm for SmartVision Applications, ISSCC2019.”

[0114] In addition, if Figure 15 As shown, a sampling transistor 357 can be arranged in the sample-and-hold circuit 350 instead of the selection transistors 353 and 354. In this case, the sampling transistor 357 and the capacitor 351 are connected in series between the preceding circuit 310 and the succeeding circuit 360. The capacitor 352 is inserted between the connection node between the sampling transistor 357 and the capacitor 351 and the ground node. The circuit configuration shown in this figure can reduce the number of transistors.

[0115] For the circuit shown in this figure, for example, see the control described in “Jae-kyu Lee, et al., A 2.1e-Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3 μm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020.”

[0116] As described above, according to the modification example of the first embodiment of the present technology, since there are two systems of subsequent-stage circuits, level fluctuations of subsequent-stage nodes can be suppressed.

[0117] <2. Second Implementation Plan> In the first embodiment described above, the circuits in the solid-state imaging element 200 are arranged on a single semiconductor chip. However, with this configuration, miniaturization of the pixels may be difficult. The solid-state imaging element 200 of the second embodiment differs from the first embodiment in that the solid-state imaging element 200 has a stacked structure.

[0118] exist Figure 16 In the embodiment shown in FIG. 2 , a solid-state imaging element 200 according to the second embodiment includes a lower chip 202 and an upper chip 201 stacked on the lower chip 202. These chips are electrically connected together by, for example, Cu-Cu bonding. Note that in addition to Cu-Cu bonding, vias or bumps can also be used for connection.

[0119] An upper pixel array section 231 is arranged on the upper chip 201. A lower pixel array section 232 and a column signal processing circuit 260 are arranged on the lower chip 202. For each pixel in the pixel array section 230, a portion of the pixels are arranged in the upper pixel array section 231, and the remaining pixels are arranged in the lower pixel array section 232. Note that the upper chip 201 and the lower chip 202 are examples of the plurality of semiconductor chips described in the claims.

[0120] Furthermore, in the lower chip 202, there are also arranged a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250. These circuits are not shown in the figure.

[0121] Figure 17is a circuit diagram showing an example of the configuration of a pixel 300 according to a second embodiment of the present technology. The components of the pre-stage circuit 310, excluding the pre-charge transistor 332, the current source transistor 317, the capacitor 318, and the sample-and-hold switch 319, are arranged on the upper chip 201. The circuits after the pre-charge transistor 332, the current source transistor 317, the capacitor 318, the sample-and-hold switch 319, and the sample-and-hold circuit 350 are arranged on the lower chip 202. As shown in this figure, by distributing the components of the pixel 300 across the stacked upper chip 201 and lower chip 202, the pixel area can be reduced, facilitating pixel miniaturization.

[0122] Note that the above-mentioned elements and circuits may be dispersedly arranged on three or more stacked semiconductor chips.

[0123] As described above, according to the second embodiment of the present technology, since the circuits and elements in the pixel 300 are dispersedly arranged on two semiconductor chips, miniaturization of the pixel is facilitated.

[0124] <3. Third Implementation Plan> In the first embodiment described above, the capacitor element 318 and the sample-and-hold switch 319 are arranged in a CIS, but these circuits can be arranged in a sensor other than a CIS. The third embodiment differs from the first embodiment in that the capacitor element 318 and the sample-and-hold switch 319 are arranged in an event-based vision sensor (EVS).

[0125] Figure 18 This is a block diagram illustrating an example configuration of a solid-state imaging element 200 according to a third embodiment of the present technology. The solid-state imaging element 200 is an EVS and includes a column arbiter 271, a column address event representation (AER) circuit 272, a column address encoder 273, a pixel array section 400, and a state machine 277. Furthermore, the solid-state imaging element 200 includes a row address encoder 274, a row AER circuit 275, and a row arbiter 276. The pixel array section 400 includes a plurality of pixels 410 arranged in a two-dimensional grid pattern.

[0126] Each pixel in the pixel array section 400 generates a differential signal indicating the amount of voltage change based on the photocurrent, and compares the level of the signal with a predetermined threshold. The result of this comparison represents the address event detection result. Here, the threshold used for comparison with the differential signal includes two different thresholds, the larger of which is defined as an upper threshold and the smaller one as a lower threshold. In addition, the address event includes an ON event and an OFF event, and the detection result includes a 1-bit ON event detection result and a 1-bit OFF event detection result. The ON event is detected when the differential signal exceeds the upper threshold, and the OFF event is detected when the differential signal falls below the lower threshold.

[0127] Furthermore, when an address event is detected, the pixel 410 sends and receives a request and a response (hereinafter referred to as “handshake”) with the row AER circuit 275 to output the address event detection result to the outside. Next, the pixel 410 performs handshake with the column AER circuit 272 .

[0128] The column arbiter 271 arbitrates requests from the column AER circuit 272 and sends a response to the column AER circuit 272 based on the arbitration result.

[0129] The column AER circuit 272 sends and receives (performs handshake) requests and responses for outputting the address event detection results to the outside with each column, the column arbiter 271 , and the state machine 277 .

[0130] Column address encoder 273 encodes the address of the column where the address event occurs and sends the address to state machine 277 .

[0131] The row address encoder 274 encodes the address of the row where the address event occurs and sends the address to the state machine 277.

[0132] The row arbiter 276 arbitrates requests from the row AER circuit 275 and sends a response to the row AER circuit 275 based on the arbitration result.

[0133] The row AER circuit 275 sends and receives (performs handshake) requests and responses for outputting the address event detection results to the outside with each row, the row arbiter 276 , and the state machine 277 .

[0134] The state machine 277 performs handshakes with the column AER circuit 272 and the row AER circuit 275. Upon receiving requests from the column AER circuit 272 and the row AER circuit 275, the state machine 277 decodes the data from the column address encoder 273 and the row address encoder 274 to indicate the address at which the address event was detected. Image data is generated by arranging the address event detection results of each pixel in a two-dimensional grid pattern. The state machine 277 supplies the image data to the recording unit 120.

[0135] Figure 19 4 is a circuit diagram showing a configuration example of a pixel 410 according to a third embodiment of the present technology. The pixel 410 includes a logarithmic response section 420 , a buffer 430 , a differentiation circuit 440 , a comparator 450 , and an AER logic circuit 460 .

[0136] The logarithmic response section 420 includes a photoelectric conversion element 421 , nMOS transistors 422 and 423 , and a pMOS transistor 424 .

[0137] The photoelectric conversion element 421 generates a photocurrent Ip as an electric signal by performing photoelectric conversion on incident light.

[0138] The pMOS transistor 424 and the nMOS transistor 423 are connected in series between the power supply and the ground terminal. Furthermore, the gate of the nMOS transistor 422 is connected to the connection node between the pMOS transistor 424 and the nMOS transistor 423, the source is connected to the photoelectric conversion element 421, and the drain is connected to the power supply. A bias voltage Vblog is then applied to the gate of the pMOS transistor 424. The gate of the nMOS transistor 423 is connected to the connection node between the nMOS transistor 422 and the photoelectric conversion element 421.

[0139] With the above-described circuit configuration, the logarithmic response section 420 performs current-voltage conversion on the photocurrent Ip to generate the pixel voltage Vp.

[0140] The solid-state imaging element 200 has a stacked structure of an upper chip 201 and a lower chip 202, and the photoelectric conversion element 421 and nMOS transistors 422 and 423 are arranged on the upper chip 201. On the other hand, circuits after the pMOS transistor 424 are arranged on the lower chip 202.

[0141] Note that although the solid-state imaging element 200 has a stacked structure, it may be formed as a single semiconductor chip without having a stacked structure.

[0142] Buffer 430 includes pMOS transistors 431 and 432 connected in series between a power supply and a ground node. The gate of pMOS transistor 432 on the ground side is connected to logarithmic response section 420, and a bias voltage Vbsf is applied to the gate of pMOS transistor 431 on the power supply side. Furthermore, the connection point between pMOS transistors 431 and 432 is connected to a differentiating circuit 440. This connection performs impedance conversion on pixel voltage Vp, and the converted voltage signal is output to differentiating circuit 440 as output signal Vp'.

[0143] The differentiating circuit 440 includes capacitive elements 318 , 441 , and 444 , pMOS transistors 442 , 443 , and 446 , an nMOS transistor 445 , and a sample-and-hold switch 319 .

[0144] One end of the capacitor 441 is connected to the buffer 430, and the other end is connected to one end of the capacitor 444 and the gate of the pMOS transistor 443. The gate of the pMOS transistor 442 is input with a reset signal xrst, and the source and drain are connected to the two ends of the capacitor 444. The pMOS transistor 443 and the nMOS transistor 445 are connected in series between the power supply and the ground terminal. In addition, the other end of the capacitor 444 is connected to the connection point between the pMOS transistor 443 and the nMOS transistor 445. The connection point is also connected to the comparator 450. Note that the nMOS transistor 445 is an example of a current source transistor described in the claims.

[0145] Capacitor 318 is inserted between the gate and source of nMOS transistor 445. PMOS transistor 446 supplies a power supply voltage to the gate of pMOS transistor 443 according to initialization signal INI, thereby turning off pMOS transistor 443. During the period when reset signal xrst is at a high level, pMOS transistor 446 is periodically controlled to an off state by initialization signal INI. For example, when pMOS transistor 446 is turned off by initialization signal INI and current is cut off, sample-and-hold switch 319 samples and holds bias voltage VB in capacitor 318.

[0146] Through this connection, a differential signal indicating the amount of change in the output signal Vp' is generated and output to the comparator 450. In addition, the differential signal is initialized by the reset signal xrst.

[0147] Comparator 450 includes pMOS transistors 451 and 453 and nMOS transistors 452 and 454. PMOS transistor 451 and nMOS transistor 452 are connected in series between a power supply and a ground terminal, and pMOS transistor 453 and nMOS transistor 454 are also connected in series between a power supply and a ground terminal. Furthermore, the gates of pMOS transistors 451 and 453 are connected to differentiating circuit 440. A predetermined upper threshold value Von is applied to the gate of nMOS transistor 452, and a predetermined lower threshold value Voff is applied to the gate of nMOS transistor 454.

[0148] The connection point between pMOS transistor 451 and nMOS transistor 452 is connected to AER logic circuit 460, and the voltage at this connection point is output as comparison result VCH. The connection point between pMOS transistor 453 and nMOS transistor 454 is also connected to AER logic circuit 460, and the voltage at this connection point is output as comparison result VCL. With this connection, comparator 450 outputs a high-level comparison result VCH when the differential signal exceeds upper threshold Von, and a low-level comparison result VCL when the differential signal falls below lower threshold Voff. Comparison result VCH indicates the result of detecting an on-state event, while comparison result VCL indicates the result of detecting an off-state event.

[0149] Note that the comparator 450 detects both the on and off events, but the comparator 450 may detect only one of the on and off events. For example, when only the on event is detected, only the corresponding pMOS transistor 451 and nMOS transistor 452 are arranged.

[0150] The AER logic circuit 460 performs handshake based on the comparison results VCH and VCL. When an address event occurs, the AER logic circuit 460 performs handshake with the column arbiter 271. Next, the AER logic circuit 460 performs handshake with the row arbiter 276 and resets the differentiating circuit 440 using the reset signal xrst.

[0151] Note that if the sensor includes a transistor serving as a current source for each pixel, the capacitor 318 and the sample-and-hold switch 319 can be disposed in a sensor other than an EVS or CIS. For example, the capacitor 318 and the sample-and-hold switch 319 can be disposed in a sensor that counts photons using a SPAD (single-photon avalanche diode).

[0152] As described above, according to the fourth embodiment of the present technology, since the capacitance element 318 and the sample-hold switch 319 are arranged in the EVS, current variation in the EVS can be suppressed.

[0153] <5. Application Examples for Mobile Objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile object, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, aircraft, drone, ship, or robot.

[0154] FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0155] Vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. In the example shown in FIG22 , vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, functional components of integrated control unit 12050 include a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0156] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various types of programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating vehicle drive force; a drive force transmission mechanism for transmitting drive force to wheels; a steering mechanism for adjusting the vehicle's steering angle; a braking device for generating vehicle braking force; and the like.

[0157] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, power windows, and various lights such as the headlights, backup lights, brake lights, turn signals, and fog lights. In this case, the body system control unit 12020 can receive radio waves or signals from various switches transmitted from a mobile device that replaces a key. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door locks, power windows, lights, and other functions.

[0158] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the vehicle exterior information detection unit 12030 can detect objects such as people, vehicles, obstacles, signs, and characters on the road surface, or can detect the distance to such objects.

[0159] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0160] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver status detection unit 12041 that detects the driver's condition. For example, the driver status detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver status detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0161] Microcomputer 12051 can calculate control target values ​​for the driving force generation device, steering mechanism, or braking device based on information about the vehicle's exterior or interior obtained by vehicle exterior information detection unit 12030 or vehicle interior information detection unit 12040, and output control commands to drive system control unit 12010. For example, microcomputer 12051 can perform coordinated control to implement advanced driver assistance system (ADAS) functions, including collision avoidance or impact mitigation, vehicle-to-vehicle distance-based follow-up driving, speed maintenance driving, vehicle collision warning, and vehicle lane departure warning.

[0162] In addition, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 is able to perform collaborative control aimed at achieving automatic driving, etc., wherein the automatic driving enables the vehicle to drive autonomously without relying on the driver's operation.

[0163] Furthermore, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam, for example, based on the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0164] The audio / video output unit 12052 transmits an output signal of at least one of audio and video to an output device capable of visually or aurally communicating information to vehicle occupants or the exterior of the vehicle. In the example of FIG22 , an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a heads-up display.

[0165] FIG. 23 is a diagram showing an example of the installation position of the imaging unit 12031 .

[0166] In FIG. 23 , imaging units 12101 , 12102 , 12103 , 12104 , and 12105 are included as an imaging unit 12031 .

[0167] Camera units 12101, 12102, 12103, 12104, and 12105 are located, for example, at locations such as the front nose, rearview mirror, rear bumper, rear door, and the upper portion of the windshield inside the vehicle 12100. Camera unit 12101 located at the front nose and camera unit 12105 located at the upper portion of the windshield inside the vehicle primarily capture images in front of vehicle 12100. Camera units 12102 and 12103 located at the rearview mirror primarily capture images from the sides of vehicle 12100. Camera unit 12104 located at the rear bumper or rear door primarily captures images from the rear of vehicle 12100. Camera unit 12105 located at the upper portion of the windshield inside the vehicle primarily detects vehicles ahead, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.

[0168] Note that FIG23 illustrates an example of the imaging ranges of imaging units 12101 through 12104. Imaging range 12111 represents the imaging range of imaging unit 12101 located at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 located at the rearview mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 located at the rear bumper or rear door. For example, by superimposing the image data captured by imaging units 12101 through 12104, a bird's-eye view image of vehicle 12100 can be obtained from above.

[0169] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0170] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114 and the temporal change in that distance (relative speed to vehicle 12100). It can then identify the closest three-dimensional object as the preceding vehicle. Specifically, this three-dimensional object is located on the travel path of vehicle 12100 and is traveling in the same direction as vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, microcomputer 12051 can pre-set the distance to be maintained between the vehicle and the preceding vehicle and execute automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and other related control mechanisms. This allows for coordinated control, such as automated driving, designed to enable the vehicle to travel autonomously without relying on driver input.

[0171] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can classify 3D object data of 3D objects into 3D object data of two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other 3D objects, extract the classified 3D object data, and use the extracted 3D object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as those that the driver of the vehicle 12100 can visually identify and those that are difficult for the driver of the vehicle 12100 to visually identify. The microcomputer 12051 then determines a collision risk, indicating the degree of risk of collision with each obstacle. If the collision risk is equal to or higher than a set value, indicating the possibility of a collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and executes forced deceleration or evasive steering via the drive system control unit 12010. Thus, the microcomputer 12051 can assist in driving to avoid collisions.

[0172] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can identify pedestrians, for example, by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. For example, this pedestrian identification is performed by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and performing pattern matching on a series of feature points representing the object's outline to determine whether the pedestrian is present. If the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and identifies the pedestrian, the audio / video output unit 12052 controls the display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. The audio / video output unit 12052 can also control the display unit 12062 to display an icon representing the pedestrian at a desired location.

[0173] In the above, an example of a vehicle control system to which the technology according to the present disclosure can be applied has been described. The technology according to the present disclosure can be applied to, for example, the camera unit 12031 in the above-mentioned components. Specifically, for example, Figure 1 The imaging device 100 in FIG. 1 can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, current variation can be suppressed and power consumption can be reduced.

[0174] Note that the above-described embodiments illustrate examples of the present technology, and that each item in the embodiments corresponds to each invention-specific item in the claims. Similarly, each invention-specific item in the claims corresponds to each item with the same name in the embodiments of the present technology. However, the present technology is not limited to the above-described embodiments, and can be implemented by making various modifications to the embodiments without departing from the scope of the present technology.

[0175] Note that the effects described herein are merely illustrative and not limiting, and other effects may exist.

[0176] Note that the present technology can also have the following configurations. (1) A solid-state imaging element comprising a plurality of pixels, each of the pixels being provided with: a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current; a capacitance element inserted between the gate of the current source transistor and the ground node; and The sample-and-hold switch is configured to sample and hold a predetermined bias voltage in the capacitive element during a period in which the drain-source current is not supplied. (2) The solid-state imaging device according to (1), further comprising: an amplifying transistor that amplifies a voltage of the floating diffusion layer and outputs the amplified voltage from a source; and a switch circuit that opens and closes a path between the amplifying transistor and the current source transistor, wherein The sample-and-hold switch samples and holds the bias voltage in the capacitive element during a period when the switch circuit is in an off state. (3) The solid-state imaging device according to (2), further comprising: A sample-and-hold circuit holds each of a signal level corresponding to the exposure amount and a predetermined reset level. (4) The solid-state imaging element according to (3), wherein The switching circuit includes at least one of the following: a switching transistor that opens and closes a path between the source of the amplifying transistor and a previous-stage node connected to the sample-and-hold circuit; and A precharge transistor opens and closes a path between the previous stage node and the drain of the current source transistor. (5) The solid-state imaging element according to any one of (1) to (4), further including: a mirror source transistor through which a predetermined reference current flows, wherein The sample-and-hold switch opens and closes a path between the gate and drain of the mirror source transistor and the gate of the current source transistor. (6) The solid-state imaging element according to any one of (1) to (5), wherein the current source transistor, the capacitive element, and the sample-and-hold switch are arranged on any one semiconductor chip among a plurality of stacked semiconductor chips. (7) The solid-state imaging element according to any one of (1) to (6), wherein each of the plurality of pixels detects the presence or absence of an address event. (8) A light detection device comprising: A pixel of a plurality of pixels, each of the pixels being provided with: a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current, a capacitance element inserted between the gate of the current source transistor and the ground node, and a sample-and-hold switch configured to sample and hold a predetermined bias voltage in the capacitive element during a period in which the drain-source current is not supplied; and A signal processing circuit processes a pixel signal from each of the plurality of pixels. (9) A method for controlling a solid-state imaging element, the method comprising: a process in which a current source transistor supplies a predetermined drain-source current, the source of the current source transistor being connected to a ground node; and A sampling and holding process is performed in which a predetermined bias voltage is sampled and held in a capacitor element during a period in which the drain-source current does not flow. The capacitor element is inserted between the gate of the current source transistor and the ground node. Reference Signs List

[0177] 100 Camera 110 Camera Lens 120 Records Department 130 Camera Control Unit 200 solid-state imaging element 201 Chip 202 Chip 211 vertical scanning circuit 212 Timing Control Circuit 213 DAC 220 Attachments 221 Reference Current Source 222 Mirror Source Transistor 230, 400 pixel array unit 231 upper pixel array portion 232 lower pixel array portion 250 load MOS circuit block 251 Load MOS transistor 260 columns of signal processing circuits 261 ADC 262 Digital Signal Processing Department 271 Column Arbiter 272 AER circuits 273 Column Address Encoder 274 row address encoder 275 AER circuits 276 row arbiter 277 State Machine 300, 410 pixels 308 Selector 310 preamplifier circuit 311, 421 photoelectric conversion elements 312 pass transistor 313 Pre-stage reset transistor 314 FD 315 pre-amplifier transistor 316 previous node 317 Current Source Transistor 318, 321, 351, 352, 441, 444 capacitor elements 319 Sample and Hold Switch 320 Conversion Efficiency Control Transistor 330 Switching Circuit 331 Switching Transistor 332 Precharge transistor 350 Sample and Hold Circuit 353, 354 Select transistor 355 post-stage reset transistor 356 back-end nodes 357 sampling transistor 360, 360-1, 360-2 post-stage circuit 361, 361-1, 361-2 post-amplifier transistors 362, 362-1, 362-2 rear stage selection transistor 420 Logarithmic Response Unit 422, 423, 445, 452, 454 nMOS transistors 424, 431, 432, 442, 443, 451, 453 pMOS transistors 430 Buffer 440 Differential Circuits 450 Comparator 460 AER Logic Circuit 12031 Camera Department

Claims

1. A solid-state imaging element comprising a plurality of pixels, each of the pixels being provided with: a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current; a capacitor element inserted between the gate of the current source transistor and the ground node; as well as The sample-and-hold switch is configured to sample and hold a predetermined bias voltage in the capacitive element during a period in which the drain-source current is not supplied.

2. The solid-state imaging element according to claim 1 , further comprising: an amplifier transistor that amplifies a voltage of the floating diffusion layer and outputs the amplified voltage from a source; and a switch circuit that opens and closes a path between the amplifying transistor and the current source transistor, wherein The sample-and-hold switch samples and holds the bias voltage in the capacitive element during a period when the switch circuit is in an off state.

3. The solid-state imaging element according to claim 2, further comprising: A sample-and-hold circuit holds each of a signal level corresponding to the exposure amount and a predetermined reset level.

4. The solid-state imaging element according to claim 3, wherein The switching circuit includes at least one of the following: a switching transistor that opens and closes a path between the source of the amplifying transistor and a previous-stage node connected to the sample-and-hold circuit; and A precharge transistor opens and closes a path between the previous stage node and the drain of the current source transistor.

5. The solid-state imaging element according to claim 1 , further comprising: a mirror source transistor through which a predetermined reference current flows, wherein The sample-and-hold switch opens and closes a path between the gate and drain of the mirror source transistor and the gate of the current source transistor. 6 . The solid-state imaging element according to claim 1 , wherein the current source transistor, the capacitance element, and the sample-and-hold switch are arranged on any one semiconductor chip among a plurality of stacked semiconductor chips. 7 . The solid-state imaging element according to claim 1 , wherein each of the plurality of pixels detects the presence or absence of an address event.

8. A light detection device comprising: A pixel of a plurality of pixels, each of the pixels being provided with: a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current, a capacitance element inserted between the gate of the current source transistor and the ground node, and a sample-and-hold switch configured to sample and hold a predetermined bias voltage in the capacitive element during a period in which no current is supplied between the drain and the source; as well as A signal processing circuit processes a pixel signal from each of the plurality of pixels.

9. A method for controlling a solid-state imaging element, the method comprising: a process in which a current source transistor supplies a predetermined drain-source current, wherein the source of the current source transistor is connected to a ground node; and A sampling and holding process is performed in which a predetermined bias voltage is sampled and held in a capacitor element during a period in which the drain-source current does not flow. The capacitor element is inserted between the gate of the current source transistor and the ground node.

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