Chip testing equipment and method

Abstract

The invention discloses chip testing equipment and method, and relates to the technical field of chip testing, and the chip testing equipment comprises at least one power-on identification block and a plurality of testing bases, and the power-on identification block is connected with the testing bases in parallel; the power-on identification block is used for storing identification information of chip test equipment and test information of a to-be-tested chip; the test base is used for fixing and connecting the to-be-tested chip, and the energization identification block and the test base are arranged in parallel, so that the energization condition of the energization identification block and the test base can be independently controlled, the influence on the to-be-tested chip when identification information is read is reduced, and the test effect is improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to chip testing equipment and methods. Background Art

[0002] In existing test boards, each test board is equipped with a power-on identification block, which can be used to realize test traceability of the test chip dut (Device Under Test). The power-on identification block can be an integrated circuit chip that can be used to store test information of the test board.

[0003] By building a database on an internal server and storing the identification information collected from test boards, the company's test boards can be managed and maintained. Furthermore, the identification information on the test board can be associated with the production information of the test chip dut. This information, including information such as the source of raw materials, production process parameters, and production equipment numbers, can be bound to the chip's entire production process based on the identification information on the test board. The identification information on the test board can also be associated with test data, associating the test results, test time, and test personnel during the chip testing process with the identification information on the test board. In the event of a chip problem, the test chip dut can be traced back through the associated information on the test board.

[0004] During the test process, the test board needs to enter its test information into the traceability system after power is applied. The traceability system then uses the identification information detected after power is applied to trace the test chip duts. However, the identification content in each power-on identification block can only be retrieved after power is applied. When reading the information in the power-on identification block, the various test sockets on the test board are often affected. This results in low stability when power is applied to test boards with power-on identification blocks. Summary of the Invention

[0005] The main purpose of this application is to provide a chip testing device and method, aiming to solve the technical problem that the current chip testing equipment is unstable when powered on, resulting in poor testing results.

[0006] To achieve the above-mentioned object, the present application proposes a chip testing device, which includes at least one power-on identification block and a plurality of test bases, wherein the power-on identification block is connected in parallel with the test bases;

[0007] The power-on identification block is used to store identification information of the chip testing equipment and test information of the chip to be tested;

[0008] The test base is used to fix and connect the chip to be tested.

[0009] In one embodiment, the chip testing device further comprises: an isolation circuit, the isolation circuit being provided between the power-on identification block and the chip to be tested;

[0010] The isolation circuit is used to electrically isolate the power-on identification block from the chip to be tested.

[0011] In one embodiment, the chip testing device further includes: a switch control module and a power supply module, wherein the switch control module is respectively provided on the power supply lines of the test base and the power identification block, and the power supply module is respectively connected to the power identification block and the test base;

[0012] The switch control module is used to control the power status of the test base and the power identification block;

[0013] The power supply module is used to supply power to the power-on identification block and the test base.

[0014] To achieve the above objectives, the present application proposes a chip testing method, which is applied to the chip testing device described above and includes:

[0015] In response to a read instruction, analyzing the read instruction to determine a read requirement;

[0016] When the reading requirement is to read identification information in the powered identification block, turning off the power supply of the test base and turning on the power supply of the powered identification block;

[0017] When the power supply of the power identification block is turned on, reading the identification information in the power identification block;

[0018] The test of the chip to be tested is completed according to the read identification information.

[0019] In one embodiment, when the reading requirement is to read identification information in a power-on identification block, the step of turning off the power supply of the test base and turning on the power supply of the power-on identification block includes:

[0020] When the reading requirement is to read identification information in the power-on identification block, turning off a first switch control module provided on a power supply line of the test base;

[0021] A second switch control module provided on the power supply line of the power-on identification block is turned on.

[0022] In one embodiment, the method further comprises:

[0023] Parsing the chip type parameter in the identification information;

[0024] Matching the chip type parameters with preset test conditions;

[0025] If the match is successful, a power supply instruction is generated, and the first switch control module is turned on based on the power supply instruction;

[0026] In case of matching failure, the first switch control module is kept closed.

[0027] In one embodiment, when the power supply of the power-on identification block is turned on, the step of reading the identification information in the power-on identification block includes:

[0028] When the power supply of the power identification block is turned on, obtaining the chip type and chip status of the chip to be tested;

[0029] determining a target reading strategy according to the chip type and the chip status;

[0030] The identification information in the power-on identification block is read using the target reading strategy.

[0031] In one embodiment, the step of determining a target read strategy according to the chip type and the chip status includes:

[0032] Matching corresponding reading parameters and reading timing according to the chip type;

[0033] determining a current read operation according to the chip state;

[0034] A target read strategy is generated according to the read parameter, the read timing, and the current read operation.

[0035] In one embodiment, the step of completing the test of the chip to be tested according to the read identification information includes:

[0036] Generate a check code of the read identification information using a cyclic redundancy check algorithm;

[0037] Comparing the generated verification code with a pre-stored standard verification code;

[0038] If the comparison is inconsistent, trigger an operation of re-reading the identification information;

[0039] If the comparison is consistent, the identification information is stored in the database to complete the test of the chip to be tested.

[0040] In one embodiment, before the step of analyzing the read instruction in response to the read instruction to determine the read requirement, the method further includes:

[0041] Obtain the clock signal of the chip to be tested;

[0042] Determining an idle time period of the chip to be tested according to the clock signal;

[0043] A read instruction is triggered during the idle time period.

[0044] One or more technical solutions proposed in the present application are that the chip testing equipment includes at least one power-on identification block and multiple test bases, and the power-on identification block is connected in parallel with the test base; the power-on identification block is used to store the identification information of the chip testing equipment and the test information of the chip to be tested; the test base is used to fix and connect the chip to be tested. By setting the power-on identification block and the test base in parallel, the power-on status of the power-on identification block and the test base can be independently controlled, thereby reducing the impact on the chip to be tested when reading the identification information and improving the test effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figure 1 A schematic diagram of the structure of the chip testing device provided in Example 1 of the present application;

[0048] Figure 2 A schematic diagram of the process flow provided in Example 1 of the chip testing method of this application;

[0049] Figure 3 A schematic diagram of the process flow provided for the second embodiment of the chip testing method of this application;

[0050] Figure 4 This is a flow chart of the third embodiment of the chip testing method of this application.

[0051] Description of Figure Numbers:

[0052] Power-on identification block 10, test base 20, chip to be tested 30, switch control module 40, power supply module 50;

[0053] A first switch control module 401 and a second switch control module 402 .

[0054] The purpose, features and advantages of this application will be further explained with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0055] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0056] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0057] The main solution of the embodiment of the present application is: the chip testing equipment includes at least one power-on identification block and multiple test bases, and the power-on identification block is connected in parallel with the test base; the power-on identification block is used to store the identification information of the chip testing equipment and the test information of the chip to be tested; the test base is used to fix and connect the chip to be tested.

[0058] Since the test base and the power-on identification block in the existing test board are connected in series, when the content in the power-on identification is read, the various test bases in the test board will often be affected, thereby causing the test board with the power-on identification to have low stability when powered on.

[0059] This application provides a solution that changes the connection between the test base and the powered identification block from series to parallel. In a series circuit, as long as the identification block is powered, the test base will also be powered. By switching to a parallel connection, the power supply of the powered identification block and the test base can be independently controlled.

[0060] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, mobile phone, etc., or an electronic device capable of performing the above functions, chip testing equipment, etc. The following uses chip testing equipment as an example to illustrate this embodiment and the following embodiments.

[0061] Based on this, the embodiment of the present application provides a chip testing device, referring to Figure 1 , Figure 1 This is a structural diagram of the first embodiment of the chip testing equipment of this application.

[0062] In this embodiment, the chip testing device includes: at least one power-on identification block 10 and a plurality of test bases 20, wherein the power-on identification block 10 is connected in parallel with the test bases 20;

[0063] The power-on identification block 10 is used to store identification information of the chip testing equipment and test information of the chip to be tested 30 ; the test base 20 is used to fix and connect the chip to be tested 30 .

[0064] It should be noted that the power-on identification block 10 can be an integrated circuit chip, which can be used to store test information of the chip to be tested 30. Therefore, the power-on identification block 10 can have a built-in non-volatile memory (such as EEPROM or Flash) to record the results of each test.

[0065] In this embodiment, the connection between the power-on identification block 10 and the test base 20 is changed from a series connection to a parallel connection, allowing for independent control of the power-on identification block 10 and the test base 20. The test base 20 is a hardware device used to support a device under test (DUT) or component under test, enabling various electrical, mechanical, or environmental tests. The test base 20 is typically equipped with a specific type of connector or socket that facilitates connecting the DUT to a test instrument, such as by using probes or sockets to achieve electrical connection.

[0066] In a specific implementation, when it is necessary to read the content in the power identification block 10, only the power identification block 10 can be powered on. After obtaining specific identification information, it is decided according to actual needs whether to power on the test base 20 to test the chip 30 to be tested.

[0067] In a feasible embodiment, in order to improve the control effect of the power-on identification block 10 and the test base 20, the chip testing device further includes: a switch control module 40 and a power supply module 50, wherein the switch control module 40 is respectively provided on the power supply lines of the test base 20 and the power-on identification block 10, and the power supply module 50 is respectively connected to the power-on identification block 10 and the test base 20;

[0068] It should be noted that the switch control module 40 can be a relay, a transistor or a mechanical switch, and the switch control module 40 includes a first switch control module 401 and a second switch control module 402 .

[0069] The first switch control module 401 is set on the power supply line between the power-on identification block 10 and the power supply module 50, and the second switch control module 402 is set on the power supply line between the test base 20 and the power supply module 50. The first switch control module 401 and the second switch control module 402 are independent switches. The power-on state of the power-on identification block 10 is controlled by the first switch control module 401, and the power-on state of the test base 20 is controlled by the second switch control module 402. Therefore, when reading the content in the power-on identification block 10, the power supply switch of the test base 20 is turned off, and only the power supply switch of the power-on identification block 10 is turned on. In this way, the test base 20 is prevented from being powered on when the identification information is read, thereby reducing the impact on the chip to be tested 30.

[0070] In a specific implementation, the power supply module 50 can be an external power source, such as a charging power source or a DC power source. The power supply module 50 can automatically adjust the power supply target according to the operation stage. For example, in the initial stage, only power is supplied to the power identification block 10. After the identification information is successfully read, it is determined based on the identification information whether power should be supplied to the test base 20. For example, if the identification information indicates that the chip type corresponding to the chip under test 30 does not need to be tested immediately, the test base 20 can be kept in a power-off state until power is supplied when there is an actual test demand.

[0071] In a feasible embodiment, the chip testing device also includes: an isolation circuit (not shown in the figure), which is arranged between the power-on identification block 10 and the chip to be tested 30; the isolation circuit is used to electrically isolate the power-on identification block and the chip to be tested.

[0072] It should be noted that the isolation circuit can be an optocoupler, a transformer, etc. The optocoupler can transmit data using optical signals as a medium to achieve electrical isolation and prevent the electrical signal when reading the identification information from directly affecting the electrical characteristics of the DUT.

[0073] In a specific implementation, the isolation circuit is arranged between the powered identification block 10 and the chip to be tested 30, so that when the chip to be tested 30 is tested, the use of optocoupler isolation can prevent voltage fluctuations, current shocks, etc. that may occur in the circuit that reads the identification information from affecting the normal operation of the chip to be tested 30.

[0074] This embodiment provides at least one power-on identification block 10 and multiple test bases 20 in a chip testing device. The power-on identification block 10 and the test bases 20 are connected in parallel. The power-on identification block 10 is used to store identification information of the chip testing device and test information of a chip to be tested 30. The test bases 20 are used to secure and connect the chip to be tested 30. By arranging the power-on identification block 10 and the test bases 20 in parallel, the power supply status of the power-on identification block 10 and the test bases 20 can be independently controlled, reducing the impact on the chip to be tested 30 when reading identification information, thereby improving testing performance.

[0075] The present application also proposes a chip testing method, which is applied to the chip testing device described above. Based on the first embodiment of the chip testing device described above, referring to Figure 2 , Figure 2 This is a flow chart of the first embodiment of the chip testing method of the present application.

[0076] In this embodiment, the chip testing method includes steps S10 to S40:

[0077] Step S10: In response to the read instruction, analyzing the read instruction to determine the read requirement.

[0078] It should be noted that after the system receives a read instruction, it first needs to analyze the instruction to determine the specific requirements of the read task. The read requirements may include the type of data to be read, the location of the device to be read, the time, etc.

[0079] Suppose a chip test system receives an instruction to read data from a certain identification block on the chip (such as the chip number). The system needs to analyze the instruction to confirm that the data to be read is from the identification block and not from other parts of the chip.

[0080] In a specific implementation, in order to synchronize the operation of reading the identification information ID with the working timing of the DUT and avoid timing conflicts, a trigger condition for the read instruction can be set. Therefore, before step S10, steps S01 to S03 are also included:

[0081] Step S01: obtaining the clock signal of the chip to be tested;

[0082] It should be noted that during chip testing, clock signals are the basis for synchronous operations. By obtaining the clock signal of the chip under test, the test system can determine the chip's operating rhythm (i.e., duty cycle). This signal is usually generated by the chip's internal clock and determines the operating timing of each module of the chip. Assume that the chip under test is a microprocessor that executes instructions within each clock cycle. The system will connect to the chip's clock output port and obtain this clock signal in real time to ensure that subsequent operations match the chip's timing.

[0083] Step S02: determining an idle time period of the chip to be tested according to the clock signal;

[0084] In practice, after acquiring the clock signal, the chip's operating cycle can be analyzed to identify idle periods. These periods are when the chip isn't performing any critical tasks or processing data, allowing it to accept other external operations, such as reading data or executing tests.

[0085] Step S03: triggering a read instruction within the idle time period.

[0086] It should be noted that read instructions can be triggered during idle time periods to retrieve data when the chip is not performing critical tasks. These triggered read instructions may read the chip's status, register values, or other important information without interfering with the chip's primary tasks. Specifically, these read instructions read the identification information in the power-on identification block.

[0087] In specific implementations, key control signals of the chip to be tested can also be obtained and used as a benchmark to trigger read instructions. For example, when testing high-speed digital chips, the identification ID is read based on the chip's system clock when the chip is idle or in a time period with low timing requirements, ensuring that the data transmission and processing process inside the chip will not be interfered with.

[0088] Step S20: When the reading requirement is to read identification information in the power-on identification block, turn off the power supply of the test base and turn on the power supply of the power-on identification block.

[0089] It should be understood that if the reading requirement is to obtain identification information from the identification block, then the power supply of the device needs to be regulated. In order to prevent unnecessary interference, the power supply of the test base is first turned off, and then the power supply to the powered identification block is turned on.

[0090] For example, a test system has a test base that supplies power to multiple chips for testing. However, when reading the identification information of the power-on identification block, to avoid affecting other test steps, the system turns off the power supply to the test base and only provides the required power to the power-on identification block.

[0091] Furthermore, in order to read the identification information in the powered identification block, the powered identification block needs to be powered on, so the power supply of the powered identification block can be turned on.

[0092] Step S30: when the power supply of the power identification block is turned on, reading the identification information in the power identification block.

[0093] It should be noted that after the powered identification block receives power, the system uses a reading device (such as a card reader or sensor) to obtain the identification information in the powered identification block, which is usually some pre-stored identifier, barcode, or other identification data. The identification information enables the traceability system to trace the test chip DUT.

[0094] Assume that the identification block contains a QR code containing the chip's unique number or other identification information. At this time, the test system will read the information in the QR code to identify the chip.

[0095] Step S40: completing the test of the chip to be tested according to the read identification information.

[0096] It should be noted that the system will further test the chip based on the identification information read from the power-on identification block. This identification information may indicate the chip model, batch, function or test conditions, etc., which all affect the test process.

[0097] If the identification information read is the chip model or production batch, the system can select a test program suitable for the chip based on this information and start detailed testing, such as functional testing or performance testing.

[0098] In a feasible implementation, to ensure that the read data is accurate, certain verification may be performed when reading the identification information. Therefore, step S40 may include steps A11 to A14:

[0099] Step A11: generating a check code of the read identification information by a cyclic redundancy check algorithm;

[0100] It should be noted that after reading the identification information, a cyclic redundancy check (CRC) algorithm can be used to generate a checksum. CRC is a common algorithm used to detect data transmission or storage errors. By performing specific calculations on the data, it generates a short checksum value that is used to verify the integrity of the data. This allows the read identification information to be verified to determine whether the read data has errors.

[0101] Assuming the identification information of the chip under test (such as a serial number or QR code) is read, a CRC algorithm is applied to the read identification information to generate a check code. This check code is used in subsequent verification steps to ensure that the identification information has not been tampered with or damaged.

[0102] Step A12: Compare the generated verification code with a pre-stored standard verification code;

[0103] It should be understood that the generated verification code is compared with a standard verification code pre-stored in the system. This standard verification code is generated based on the identification information under normal circumstances and represents correct and uncorrupted data. If the verification codes match, it means that the read information is accurate.

[0104] Step A13: triggering an operation of re-reading the identification information in the event of inconsistency in the comparison;

[0105] If the generated verification code is inconsistent with the standard verification code, it means that the read information may be incorrect or damaged. In this case, the operation of re-reading the identification information will be triggered to ensure that the correct data is obtained and the accuracy of the identification ID information is guaranteed.

[0106] In practice, if the CRC checksum of the identification information read by the system does not meet the standard, it may be due to signal interference, hardware failure or data transmission problem. The system will automatically re-trigger the read operation, obtain the identification information again, and recalculate the checksum for verification.

[0107] In a specific implementation, the inconsistent check codes may be restored and modified through an error correction algorithm, thereby forming correct identification information.

[0108] Step A14: If the comparison is consistent, the identification information is stored in the database to complete the test of the chip to be tested.

[0109] It should be noted that if the generated verification code matches the standard verification code, the read identification information is correct and can be stored in the database for subsequent processing. Once the identification information is stored in the database, the test process for the chip under test is complete. Assuming the identification information is the chip's unique number, after verification, the system stores this number and other relevant test data in the database. This information in the database can be subsequently queried and analyzed, completing a complete test record for the chip.

[0110] By verifying and correcting the identification information, the read data is guaranteed to be accurate. Even if there is some slight interference during the reading process, the correct identification ID information can be restored through verification and error correction, avoiding unnecessary operations on the DUT due to misreading.

[0111] This embodiment provides a chip testing method. In response to a read instruction, the read instruction is analyzed to determine a read requirement. When the read requirement is to read identification information in a power-on identification block, power to a test base is turned off and power to the power-on identification block is turned on. While the power-on identification block is on, identification information in the power-on identification block is read. Testing of the chip to be tested is completed based on the read identification information. By connecting the power-on identification block and the test base in parallel, the power supply of the power-on identification block and the test base can be independently controlled, reducing the impact on the chip to be tested when reading identification information and improving test effectiveness.

[0112] Based on the first embodiment of the chip testing method of this application, in the second embodiment of this application, the same or similar contents as those in the above embodiment 1 can be referred to the above introduction and will not be repeated hereafter. Figure 3 , step S20 includes steps S201 to S202:

[0113] Step S201: when the reading requirement is to read identification information in a power-on identification block, turning off a first switch control module provided on a power supply line of the test base.

[0114] Specifically, when the system receives a command to read the identification information in the powered identification block, it first analyzes the reading request and determines that the power supply to the test base needs to be shut down to avoid interference. At this point, it controls the first switch control module, located in the test base's power supply circuit, to switch it from a closed state to an open state, thereby shutting off power to the test base. This precise execution of this step ensures that the test base does not cause unnecessary interference when reading the identification information, improving the accuracy and reliability of the reading.

[0115] Step S202: Turn on a second switch control module provided on the power supply line of the power-on identification block.

[0116] In practice, while the power to the test base is turned off, it's also necessary to ensure a stable power supply to the powered identification block so the identification information can be accurately read. Therefore, a second switch control module, located in the power supply circuit for the powered identification block, is controlled to switch from an open state to a closed state, thereby providing a stable power supply to the powered identification block. This step enables the powered identification block to operate normally and output its stored identification information for the system to read.

[0117] In a feasible implementation, the power-on status of the test base will also be adjusted according to the specific situation. Therefore, the chip testing method also includes: parsing the chip type parameters in the identification information; matching the chip type parameters with preset test conditions; generating a power supply instruction when the match is successful, and turning on the first switch control module based on the power supply instruction; keeping the first switch control module closed when the match fails.

[0118] In specific implementations, while reading identification information, the chip type parameter can be extracted to improve intelligent control and automatically adjust the power supply target according to the operating phase. This parameter identifies the chip's specific model, version, or other information related to the chip's characteristics. The purpose of parsing this parameter is to obtain specific information related to the chip for subsequent testing and control.

[0119] Assume that the chip identification information contains a field indicating the chip model, such as "XYZ-1234" or "ABC-5678". The system parses this model from the identification information and determines which type of chip it is.

[0120] Preset test conditions are designed based on different chip types and typically include the operating environment and test requirements that each chip type should meet. The purpose of matching is to determine whether the chip meets the specified test requirements.

[0121] Therefore, the chip type parameters obtained by analysis can be compared with the preset test conditions to determine whether the match is successful. If the match is successful, it means that the test type of the chip to be tested corresponding to the identification information at this time is that it needs to be tested immediately. At this time, the test base needs to be powered normally for testing, so a power supply instruction can be generated, and the first switch control module is closed based on the power supply instruction, so that the power supply module supplies power to the test base to test the chip to be tested.

[0122] If the chip type doesn't match the preset test conditions, the system won't power the chip. To prevent incorrect operation or equipment damage, the first switch control module remains closed, ensuring no inappropriate power or test operations. This means that if the acquired identification information indicates that the chip type corresponding to the current chip under test doesn't require immediate testing, the test base can remain powered off until actual testing is required. Therefore, the first switch control module remains closed, preventing power from being supplied to the test base. By adjusting the power supply to the test base based on chip type parameters, test flexibility and accuracy are further improved.

[0123] This embodiment, when the read request is to read identification information from a power-on identification block, closes a first switch control module provided on the power supply circuit of the test base, and opens a second switch control module provided on the power supply circuit of the power-on identification block. This achieves independent control of the power supply status of the power-on identification block and the test base, thereby ensuring that the identification information reading does not unnecessarily affect the chip under test, thereby improving test accuracy and efficiency.

[0124] Based on the first embodiment of the chip testing method of this application, in the third embodiment of this application, the same or similar contents as those in the above embodiment 1 can be referred to the above introduction and will not be repeated hereafter. Figure 4 , step S30 includes steps S301 to S303:

[0125] Step S301: When the power supply of the power identification block is turned on, the chip type and chip status of the chip to be tested are obtained.

[0126] It should be noted that when the power supply of the power identification block is turned on, it means that the power identification block can provide normal reading operations. In order to improve the reading accuracy, different reading operations can be performed according to different chips. Therefore, the chip type and chip status of the chip to be tested can be obtained.

[0127] The chip type includes the chip model or category, which helps the system identify the chip's specific characteristics. Chips may have different operating states (such as normal, standby, abnormal, and faulty). Understanding their status is key to determining the subsequent test strategy, for example, if the chip is in an abnormal state. The chip type may also include the chip's memory type and operating mode.

[0128] Step S302: determining a target reading strategy according to the chip type and the chip status.

[0129] In a specific implementation, corresponding reading strategies can be determined for different chip types and chip states. For example, for some chips, it may be necessary to read identification information through a specific protocol (such as I2C or SPI); for different chip states (such as working state or sleep state), the reading strategy may be different.

[0130] In a feasible implementation, step S302 may include steps B11 to B13:

[0131] Step B11: matching corresponding reading parameters and reading timing according to the chip type;

[0132] It should be understood that the chip type determines the specific parameters and timing required for reading. For example, different chips may have different communication protocols (such as SPI, I2C, etc.), and their reading methods and timing requirements are also different.

[0133] Read parameters include the number of bits to be read, data format, access mode, etc. Read timing involves the time control of the read operation, including the start, duration, and interval of data transmission, which is crucial for reading chip memory or registers.

[0134] If the chip type is "Model A," a specific communication protocol, such as SPI, may be required, and specific clock frequency, transmission timing, and other parameters may need to be set. If it is "Model B," different read timings may be used, or even a different protocol (such as I2C). Each chip type requires different settings.

[0135] Step B12: determining a current read operation according to the chip status;

[0136] In a specific implementation, the current read operation can be determined according to the chip state. For example, if the chip state is abnormal, the current read operation is suspended to avoid further impact on the chip. If the chip state is normal, the current read operation is normal.

[0137] Step B13: generating a target read strategy according to the read parameters, the read timing, and the current read operation.

[0138] The target read strategy defines the detailed process of chip information reading and includes all necessary configurations (such as timing, parameters, operation steps, etc.) to ensure a smooth and accurate reading process.

[0139] For example, the SPI protocol and timing requirements are determined by reading parameters and reading timing. After confirming the "normal" state of the chip, the current read operation is a normal read. The system will generate a strategy including SPI read commands, timing settings and execution order, and prepare to execute this read operation.

[0140] Step S303: reading the identification information in the power-on identification block using the target reading strategy.

[0141] It should be noted that after determining the target read strategy, the system reads the identification information in the chip according to that strategy. The identification information read may include the chip model, version, production date, etc., or some internal chip status data. For example, it can also automatically adjust the ID reading parameters such as voltage and frequency based on the chip's storage type and operating mode, achieving efficient and secure reading.

[0142] In a feasible embodiment, when reading the identification information, the number of signal acquisitions read can also be adjusted to accurately control the electrical signal parameters when reading the identification information, ensuring that its voltage, current, frequency, etc. are within the tolerance range of the DUT. Therefore, the chip testing method also includes: adjusting the signal voltage when reading the identification information to a preset safety voltage threshold; limiting the signal current when reading the identification information to a preset safety current threshold; setting the signal reading frequency according to the operating frequency of the test chip; and controlling the reading timing of the identification information based on the signal reading frequency.

[0143] It should be noted that the preset safety voltage threshold and the preset safety current threshold are the tolerance values ​​of the chip to be tested. By limiting the signal voltage when reading the identification information to within the preset safety voltage threshold, and limiting the signal current when reading the identification information to within the preset safety current threshold, the read signal strength can be moderate and will not cause interference to the chip to be tested. The signal reading frequency is set according to the operating frequency of the chip to be tested, so as to control the reading timing and improve the accuracy and safety of the reading.

[0144] By calibrating and optimizing the test equipment's signal source, the signal strength for reading the ID is moderate, enabling accurate reading without causing electrical interference to the DUT. For example, for a chip operating at 1.2V, the signal voltage for reading the ID can be controlled within a safe low voltage range, such as around 0.5V, and the current is strictly limited to the chip's allowable leakage current.

[0145] This embodiment obtains the chip type and chip status of the chip under test when the power-on identification block is powered on; determines a target read strategy based on the chip type and chip status; and reads the identification information in the power-on identification block using the target read strategy. The strategy for reading the identification information ID is dynamically adjusted based on the type and status of the DUT, thereby achieving efficient and secure reading.

[0146] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the chip testing method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0147] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A chip testing device, characterized in that: The chip testing device comprises at least one power-on identification block and a plurality of test bases, wherein the power-on identification block is connected in parallel with the test bases; The power-on identification block is used to store identification information of the chip testing equipment and test information of the chip to be tested; The test base is used to fix and connect the chip to be tested.

2. The chip testing device according to claim 1, wherein: The chip testing device further includes: an isolation circuit, the isolation circuit being provided between the power-on identification block and the chip to be tested; The isolation circuit is used to electrically isolate the power-on identification block from the chip to be tested.

3. The chip testing device according to claim 1, wherein: The chip testing device further includes: a switch control module and a power supply module, wherein the switch control module is respectively provided on the power supply lines of the test base and the power identification block, and the power supply module is respectively connected to the power identification block and the test base; The switch control module is used to control the power status of the test base and the power identification block; The power supply module is used to supply power to the power-on identification block and the test base.

4. A chip testing method, characterized in that: The chip testing method is applied to the chip testing device described in any one of claims 1 to 3; The chip testing method comprises: In response to a read instruction, analyzing the read instruction to determine a read requirement; When the reading requirement is to read identification information in the powered identification block, turning off the power supply of the test base and turning on the power supply of the powered identification block; When the power supply of the power identification block is turned on, reading the identification information in the power identification block; The test of the chip to be tested is completed according to the read identification information.

5. The method according to claim 4, wherein When the reading requirement is to read identification information in the power-on identification block, the step of turning off the power supply of the test base and turning on the power supply of the power-on identification block includes: When the reading requirement is to read identification information in the power-on identification block, turning off a first switch control module provided on a power supply line of the test base; A second switch control module provided on the power supply line of the power-on identification block is turned on.

6. The method according to claim 5, wherein The method further comprises: Parsing the chip type parameter in the identification information; Matching the chip type parameters with preset test conditions; If the match is successful, a power supply instruction is generated, and the first switch control module is turned on based on the power supply instruction; In case of matching failure, the first switch control module is kept closed.

7. The method according to claim 4, wherein When the power supply of the power identification block is turned on, the step of reading the identification information in the power identification block includes: When the power supply of the power identification block is turned on, obtaining the chip type and chip status of the chip to be tested; determining a target reading strategy according to the chip type and the chip status; The identification information in the power-on identification block is read using the target reading strategy.

8. The method according to claim 7, wherein The step of determining a target read strategy according to the chip type and the chip status includes: Matching corresponding reading parameters and reading timing according to the chip type; determining a current read operation according to the chip state; A target read strategy is generated according to the read parameter, the read timing, and the current read operation.

9. The method according to claim 4, wherein The step of completing the test of the chip to be tested according to the read identification information includes: Generate a check code of the read identification information using a cyclic redundancy check algorithm; Comparing the generated verification code with a pre-stored standard verification code; If the comparison is inconsistent, trigger an operation of re-reading the identification information; If the comparison is consistent, the identification information is stored in the database to complete the test of the chip to be tested.

10. The method according to claim 4, wherein Before the step of analyzing the read instruction in response to the read instruction to determine the read requirement, the method further includes: Obtain the clock signal of the chip to be tested; Determining an idle time period of the chip to be tested according to the clock signal; A read instruction is triggered during the idle time period.

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