Power supply unit, mainboard and computing device

Abstract

The embodiment of the invention provides a power supply unit, a mainboard and computing equipment, and relates to the technical field of computing equipment. The power supply unit comprises a controller and an isolation module; the controller comprises at least one interface, and the interface is connected with the isolation module; when the input voltage of the isolation module is greater than the forward threshold voltage, the isolation module outputs a high level; when the input voltage of the isolation module is smaller than the negative threshold voltage, the isolation module outputs a low level. According to the technical scheme provided by the embodiment of the invention, the isolation module is additionally arranged, so that the situation that a signal sent to the mainboard by the power supply unit is greatly different from a signal sent to the power supply unit by the mainboard can be avoided, signal interference between the power supply unit and the mainboard is reduced, and the reliability of the mainboard is improved. And communication between the power supply unit and the mainboard is effectively prevented from being abnormal.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of computing devices, and in particular to a power supply unit, a motherboard, and a computing device. Background Art

[0002] The power supply unit (PSU) and the motherboard are key components in a computing device. The PSU provides the required power to all components in the computing device.

[0003] In related technologies, the PSU uses an input / output (I / O) interface to simulate IIC communication. However, the method of using the I / O interface to simulate IIC communication cannot pull the voltage of the I / O interface down to 0V. As a result, the voltage of the I / O interface is superimposed on the path impedance voltage divider, which further increases the voltage of the I / O interface, making the communication between the motherboard and the PSU prone to abnormalities. Summary of the Invention

[0004] The embodiments of the present application provide a power supply unit, a motherboard, and a computing device, which can reduce signal interference between the motherboard and the PSU and prevent abnormal communication between the motherboard and the PSU.

[0005] In a first aspect, the present application provides a power supply unit, comprising a controller and an isolation module;

[0006] The controller includes at least one interface connected to the isolation module;

[0007] When the input voltage of the isolation module is greater than the positive threshold voltage, the isolation module outputs a high level;

[0008] When the input voltage of the isolation module is less than the negative threshold voltage, the isolation module outputs a low level.

[0009] The power supply unit provided in the embodiment of the present application can avoid the situation where there is a large difference between the signal sent by the power supply unit to the mainboard and the signal sent by the mainboard to the power supply unit by adding an isolation module, thereby reducing the signal interference between the power supply unit and the mainboard, and effectively preventing abnormal communication between the power supply unit and the mainboard.

[0010] In a possible implementation, the isolation module includes at least one Schmitt trigger.

[0011] In the above embodiment, by adding a Schmitt trigger, the hysteresis function of the Schmitt trigger can be used to eliminate the low-level step of the signal, thereby avoiding false triggering.

[0012] In one possible embodiment, the at least one interface includes a first interface and a second interface, the first interface is used to output a serial data line (SDA) signal, and the second interface is used to output a serial clock line (SCL) signal; the isolation module includes a first isolation module and a second isolation module; the first isolation module includes at least one first Schmitt trigger; the second isolation module includes at least one second Schmitt trigger; the first interface is connected to the at least one first Schmitt trigger, and the second interface is connected to the at least one second Schmitt trigger.

[0013] In the above embodiment, the first Schmitt trigger and the second Schmitt trigger can be used to shape the SDA signal and the SCL signal respectively, and the voltage of the SDA signal and the SCL signal can be pulled down to 0V, thereby reducing the signal interference between the power supply unit and the mainboard, and effectively preventing abnormal communication between the power supply unit and the mainboard.

[0014] In one possible embodiment, the at least one interface includes a first interface and a second interface, the first interface is used to output an SDA signal, and the second interface is used to output an SCL signal; the isolation module includes a first input pin and a second input pin, the first interface is connected to the first input pin, and the second interface is connected to the second input pin.

[0015] In the above embodiment, the isolation module can be designed as an isolation integrated circuit, thereby reducing the space occupied by the circuit board and facilitating the miniaturization and portability of the computing device.

[0016] In a second aspect, the present application provides a mainboard, including a baseboard management controller and an isolation module;

[0017] The baseboard management controller includes at least one interface connected to the isolation module;

[0018] When the input voltage of the isolation module is greater than the positive threshold voltage, the isolation module outputs a high level;

[0019] When the input voltage of the isolation module is less than the negative threshold voltage, the isolation module outputs a low level.

[0020] The mainboard provided in the embodiment of the present application can avoid the situation where the signal sent by the mainboard to the power supply unit is significantly different from the signal sent by the power supply unit to the mainboard by adding an isolation module, thereby reducing signal interference between the mainboard and the power supply unit and effectively preventing abnormal communication between the mainboard and the power supply unit.

[0021] In a possible implementation, the isolation module includes at least one Schmitt trigger.

[0022] In the above embodiment, by adding a Schmitt trigger, the hysteresis function of the Schmitt trigger can be used to eliminate the low-level step of the signal, thereby avoiding false triggering.

[0023] In one possible embodiment, the at least one interface includes a third interface and a fourth interface, the third interface is used to output the SDA signal, and the fourth interface is used to output the SCL signal; the isolation module includes a third isolation module and a fourth isolation module; the third isolation module includes at least one first Schmitt trigger; the fourth isolation module includes at least one second Schmitt trigger; the third interface is connected to at least one third Schmitt trigger, and the fourth interface is connected to at least one fourth Schmitt trigger.

[0024] Through the above implementation, the first Schmitt trigger and the second Schmitt trigger can be used to shape the SDA signal and the SCL signal respectively, and the voltage of the SDA signal and the SCL signal can be pulled down to 0V, thereby reducing the signal interference between the mainboard and the power supply unit, and effectively preventing abnormal communication between the mainboard and the power supply unit.

[0025] In one possible embodiment, the at least one interface includes a third interface and a fourth interface, the third interface is used to output the SDA signal, and the fourth interface is used to output the SCL signal; the isolation module includes a third input pin and a fourth input pin, the third interface is connected to the third input pin, and the fourth interface is connected to the fourth input pin.

[0026] In the above embodiment, the isolation module can be designed as an isolation integrated circuit, thereby reducing the space occupied by the circuit board and facilitating the miniaturization and portability of the computing device.

[0027] In a third aspect, the present application provides a computing device comprising a power supply unit and / or a motherboard; the power supply unit is the power supply unit provided in the first aspect; and the motherboard is the motherboard provided in the second aspect.

[0028] In a possible implementation, the computing device further includes a backplane; the power supply unit is connected to the mainboard via the backplane.

[0029] The computing device provided in the embodiment of the present application can avoid the situation where the signal sent by the power supply unit to the mainboard is significantly different from the signal sent by the mainboard to the power supply unit by adding an isolation module, thereby reducing the signal interference between the power supply unit and the mainboard, and effectively preventing abnormal communication between the power supply unit and the mainboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0031] Figure 2 is a structural diagram of a power supply unit provided in an embodiment of the present application;

[0032] Figure 3 is a structural diagram of another power supply unit provided in an embodiment of the present application;

[0033] Figure 4 is a structural diagram of another isolation module provided in an embodiment of the present application;

[0034] Figure 5 This is a schematic structural diagram of a mainboard provided in an embodiment of the present application;

[0035] Figure 6 This is a structural diagram of another motherboard provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] Here, each exemplary embodiment of the present application will be described in detail. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with this application.

[0037] To facilitate a clear description of the technical solutions of the embodiments of this application, the words "exemplary," "for example," and the like are used in the embodiments of this application to indicate examples, illustrations, or explanations. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0038] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship.

[0039] In order to clearly describe the technical solutions in the embodiments of the present application, some of the terms and technologies involved in the embodiments of the present application are briefly introduced below:

[0040] 1. Power supply unit (PSU)

[0041] The PSU is used to convert standard alternating current (AC) into low-voltage stable direct current (DC) to meet the power requirements of various components inside the computer.

[0042] 2. Baseboard management controller (BMC)

[0043] BMC is a core component in server hardware management. It implements remote monitoring and management independent of the operating system based on the Intelligent Platform Management Interface (IPMI) protocol. The core functions of BMC include:

[0044] Hardware monitoring: BMC can monitor various hardware indicators of the server in real time, such as CPU temperature, voltage, fan speed, etc., to promptly detect hardware failures or abnormal conditions and take appropriate measures.

[0045] Remote control: Administrators can use the BMC to remotely control server power on / off, restart, start, and shut down.

[0046] Health check and diagnosis: The BMC provides hardware health check and diagnosis functions to help locate and resolve server hardware problems.

[0047] Equipment information management: Record detailed information about the server, including model, manufacturer, date, production and technical information of each component, chassis information, motherboard information, etc.

[0048] Maintenance management: including log management, user management, BIOS management, alarm management, etc.

[0049] 3. Schmitt trigger

[0050] A voltage comparator circuit with hysteresis characteristics, whose positive and negative thresholds are unequal, is used for signal shaping, interference rejection, and pulse processing. Key features include:

[0051] Dual-threshold characteristic: The Schmitt trigger has two threshold voltages: the positive-going threshold voltage (VT+) and the negative-going threshold voltage (VT-). When the input voltage is higher than VT+, the output is high; when the input voltage is lower than VT-, the output is low. When the input voltage is between VT+ and VT-, the output remains unchanged.

[0052] Hysteresis: Due to the difference between the positive and negative thresholds, the Schmitt trigger exhibits hysteresis, meaning that a change in the output state requires a sufficient change in the input voltage to trigger. This property enables the Schmitt trigger to effectively filter out noise superimposed on the signal.

[0053] Positive feedback mechanism: There is a positive feedback process inside the Schmitt trigger, which makes the output waveform edge steeper and helps to speed up the change of the signal edge.

[0054] The Schmitt trigger achieves hysteresis by applying positive feedback to the non-inverting input of a comparator or differential amplifier. When the input voltage rises and exceeds the positive-going threshold, the output flips to a high level; when the input voltage falls and falls below the negative-going threshold, the output flips to a low level. This dual-threshold characteristic and positive feedback mechanism make the Schmitt trigger robust against noisy signals.

[0055] 4. Microcontroller (MCU)

[0056] A microcomputer that integrates a microprocessor, memory, I / O interface, and other functional modules on a single chip.

[0057] 5. Interintegrated circuit (IIC or I2C)

[0058] A serial communication bus primarily used to connect low-speed peripheral devices.

[0059] 6. N-metal-oxide-semiconductor (NMOS)

[0060] An NMOS transistor consists of a source, drain, gate, and substrate (usually P-type silicon). An insulating layer of silicon dioxide (SiO2) is placed between the gate and the substrate. A voltage applied to the gate controls the current between the source and drain.

[0061] When the gate voltage is below the threshold voltage (Vth), the NMOS transistor is in the off state. At this point, almost no current flows between the source and drain because no effective N-type conductive channel is formed in the P-type substrate beneath the gate. When the gate voltage is above the threshold voltage, an N-type inversion layer (i.e., a conductive channel) forms in the P-type substrate beneath the gate, creating a current path between the source and drain. At this point, the NMOS transistor is in the on state, and current flows from the source to the drain.

[0062] 7. Serial data line (SDA)

[0063] The SDA signal is one of the key signal lines in the IIC (or I2C) bus, responsible for transmitting data between devices, including instructions, addresses, and data content.

[0064] 8. Serial clock line (SCL)

[0065] The SCL line is responsible for providing a clock signal for synchronizing data transmission between the host and the target device (such as a slave). It ensures the timing consistency of the data during transmission. In I2C communication, the clock pulse on the SCL line determines the rate and timing of data transmission. For example, data is transmitted on the rising or falling edge of the SCL signal (depending on the I2C 2 C protocol version and conventions) for transmission.

[0066] To ensure PSU performance and reliability, comprehensive PSU testing is crucial. In some testing scenarios, the PSU's MCU uses an I / O interface to simulate I / O communication. However, this method of simulating I / O communication cannot reduce the I / O interface voltage to 0V. As a result, the I / O interface voltage is superimposed on the path impedance voltage divider, further increasing the I / O interface voltage. The measured I / O interface voltage can reach approximately 0.8V, which can easily cause communication anomalies between the motherboard and the PSU.

[0067] Reference Figure 1 , Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application.

[0068] In some embodiments, the computing device may include a PSU 110 , a backplane 120 , and a motherboard 130 .

[0069] Among them, PSU110 includes MCU, resistors R1, R2, R3, and R4.

[0070] The MCU may be configured to output an SDA_PSU signal and an SCL_PSU signal, and the SDA_PSU signal and the SCL_PSU signal may be used to communicate with the mainboard 130 .

[0071] Optionally, the resistors R1, R2, R3, and R4 can be used for voltage division, current limiting, or signal conditioning, etc., which is not limited in the embodiments of the present application.

[0072] The backplane 120 includes resistors R5 and R6. Optionally, the resistors R5 and R6 can be used for impedance matching or voltage division on the signal transmission path to ensure stable signal transmission on the backplane.

[0073] The mainboard 130 includes resistors R7, R8, R9, R10, R11, R12, an NMOS1 transistor, an NMOS2 transistor, and a BMC.

[0074] Optionally, resistors R7, R8, R9, R10, R11, and R12 can be used for various purposes, such as voltage division, current limiting, signal conditioning, etc., which are not limited in the embodiments of the present application.

[0075] The NMOS1 transistor and the NMOS2 transistor can be used for switch control to control the on and off of the current according to the signal of the MCU or the BMC.

[0076] The BMC may be configured to output an SDA_BMC signal and an SCL_BMC signal, which may be used to communicate with the PSU 110 .

[0077] In some embodiments, taking the SDA_PSU signal as an example, when the PSU 110 sends the SDA_PSU signal to the motherboard 130, if the MCU uses an IIC transceiver, the voltage of the SDA_PSU signal output by the MCU is 0V, and after passing through the resistor R3 on the path and the voltage divider of the line path (assuming it is 0.23), the voltage of the SDA_BMC signal reaching the motherboard 130 is approximately 0.3V.

[0078] Similarly, when the motherboard 130 sends an SDA_BMC signal to the PSU 110, if the BMC uses an IIC transceiver, the voltage of the SDA_BMC signal output by the BMC is 0V. After passing through the resistor R7 on the path and the voltage divider of the line path (assuming it is 0.3V), the voltage of the SDA_BMC signal reaching the PSU 110 is 0.3V.

[0079] In the above embodiment, since the voltage of the SDA_BMC signal sent by PSU110 after reaching the motherboard 130 is substantially the same as the voltage of the SDA_BMC signal sent by the motherboard 130 after reaching the PSU110, the PSU110 and the motherboard 130 can communicate normally.

[0080] In other embodiments, still taking the SDA_PSU signal as an example, when the PSU110 sends the SDA_PSU signal to the motherboard 130, if the MCU uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SDA_PSU signal output by the MCU can only reach 0.4-0.5V, and cannot be pulled down to 0V. After passing through the resistor R3 on the path and the voltage divider of the line path (assuming it is 0.3V), the voltage of the SDA_BMC signal reaching the motherboard 130 is approximately 0.7-0.8V.

[0081] When the motherboard 130 sends the SDA_BMC signal to the PSU 110 , since the voltage of the SDA_BMC signal output by the BMC may be 0V, the voltage of the SDA_BMC signal reaching the PSU 110 is 0.3V after passing through the resistor R7 on the path and the voltage divider of the line path (assuming it is 0.3V).

[0082] In the above embodiment, since the voltage of the SDA_BMC signal sent by PSU110 after reaching the motherboard 130 is obviously different from the voltage of the SDA_BMC signal sent by the motherboard 130 after reaching PSU110, there are two different steps at the low level, and the low level upper limit of BMC is required to be 0.8V-0.9V, there is a risk of communication abnormality between PSU110 and the motherboard 130.

[0083] In response to the above technical problems, an embodiment of the present application provides a power supply unit, a motherboard and a computing device. By adding an isolation module to the power supply unit and / or the motherboard, it is possible to avoid a situation where the signal sent from the power supply unit to the motherboard is significantly different from the signal sent from the motherboard to the power supply unit, thereby reducing signal interference between the power supply unit and the motherboard and preventing abnormal communication between the power supply unit and the motherboard.

[0084] The power supply unit, motherboard, and computing device provided in the embodiments of the present application are described in detail below through specific implementation methods. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be repeated in different embodiments.

[0085] Reference Figure 2 , Figure 2 2 is a schematic diagram of a power supply unit according to an embodiment of the present invention. In some embodiments, the PSU 210 includes a controller 211, an isolation module 212, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R12, and a resistor R14.

[0086] The controller 211 includes at least one interface (such as a first interface a and a second interface b), which is connected to the isolation module 212 .

[0087] When the input voltage of the isolation module 212 is greater than the positive threshold voltage, the isolation module 212 outputs a high level; when the input voltage of the isolation module 212 is less than the negative threshold voltage, the isolation module 212 outputs a low level.

[0088] Optionally, the controller 211 may be an MCU.

[0089] In some embodiments, the first interface a may be used to output an SDA_PSU signal, and the second interface b may be used to output an SCL_PSU signal. The SDA_PSU signal and the SCL_PSU signal may be used to communicate with a mainboard.

[0090] Taking the SDA_PSU signal as an example, when PSU210 sends the SDA_PSU signal to the motherboard, if the MCU uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SDA_PSU signal output by the MCU can only reach 0.4-0.5V, and cannot be pulled down to 0V. After the SDA_PSU signal passes through the isolation module 212, the voltage will become 0V, and then pass through the resistor R3 on the path and the voltage divider of the line path (assuming it is 0.3V), and the voltage of the SDA_PSU signal reaching the motherboard is 0.3V.

[0091] When the motherboard sends the SDA_BMC signal to PSU 210, the voltage of the SDA_BMC signal output by the BMC can be 0V. Therefore, after passing through the resistors in the path and the voltage divider of the line path (assuming it is 0.3V), the voltage of the SDA_BMC signal reaching PSU 210 is 0.3V. As a result, the voltage of the SDA_PSU signal sent by PSU 210 after reaching the motherboard is basically the same as the voltage of the SDA_BMC signal sent by the motherboard after reaching PSU 210, preventing false triggering.

[0092] Similarly, when PSU210 sends the SCL_PSU signal to the motherboard, if the MCU uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SCL_PSU signal output by the MCU can only reach 0.4-0.5V and cannot be pulled down to 0V. After the SCL_PSU signal passes through the isolation module 212, the voltage will become 0V, and then pass through the resistor R4 on the path and the voltage divider of the line path (assuming it is 0.3V), and the voltage of the SCL_PSU signal reaching the motherboard is 0.3V.

[0093] When the motherboard sends an SCL_BMC signal to PSU 210, the voltage of the SCL_BMC signal output by the BMC can be 0V. Therefore, after passing through the resistors in the path and the voltage divider of the line path (assuming it is 0.3V), the voltage of the SCL_BMC signal reaching PSU 210 is 0.3V. As a result, the voltage of the SCL_BMC signal sent by PSU 210 after reaching the motherboard is basically the same as the voltage of the SCL_BMC signal sent by the motherboard after reaching PSU 210, preventing false triggering and ensuring normal communication between PSU 210 and the motherboard.

[0094] The power supply unit provided in the embodiment of the present application can avoid the situation where the signal sent by the power supply unit to the mainboard is significantly different from the signal sent by the mainboard to the power supply unit by adding an isolation module, thereby reducing the signal interference between the power supply unit and the mainboard, and effectively preventing abnormal communication between the power supply unit and the mainboard.

[0095] Based on the contents described in the above embodiments, in some embodiments, the isolation module 212 includes at least one Schmitt trigger.

[0096] It can be understood that when the input voltage of the Schmitt trigger is higher than the positive threshold voltage, the output voltage of the Schmitt trigger is a high level; when the input voltage of the Schmitt trigger is lower than the negative threshold voltage, the output voltage of the Schmitt trigger is a low level.

[0097] For example, when the power supply voltage is 3V (3.3V is generally used in the server field), when the input voltage of the Schmitt trigger is higher than 1.92V, the output voltage of the Schmitt trigger is a high level; when the input voltage of the Schmitt trigger is lower than 0.89V, the output voltage of the Schmitt trigger is 0V (low level).

[0098] Taking the SDA_PSU signal as an example, when PSU210 sends the SDA_PSU signal to the motherboard, if the MCU uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SDA_PSU signal output by the MCU can only reach 0.4-0.5V, and cannot be pulled down to 0V. After the SDA_PSU signal passes through the Schmitt trigger in the isolation module 212, the voltage will become 0V, and then pass through the resistor R3 on the path and the voltage divider of the line path (assuming it is 0.3V), and the voltage of the SDA_BMC signal reaching the motherboard is 0.3V.

[0099] The power supply unit provided in the embodiment of the present application, by adding a Schmitt trigger, can utilize the hysteresis function of the Schmitt trigger to eliminate the low-level steps of the signal and avoid false triggering.

[0100] In some possible implementations, the isolation module 212 includes a first isolation module and a second isolation module; the first isolation module includes at least one first Schmitt trigger; and the second isolation module includes at least one second Schmitt trigger.

[0101] The first interface a is connected to the at least one first Schmitt trigger, and the second interface b is connected to the at least one second Schmitt trigger.

[0102] For example, Figure 3 It is a structural diagram of another power supply unit provided in an embodiment of the present application.

[0103] Reference Figure 3 The isolation module 212 includes a first isolation module 2121 and a second isolation module 2122 ; the first isolation module 2121 includes two inverted first Schmitt triggers; the second isolation module 2122 also includes two inverted second Schmitt triggers.

[0104] The first interface a is connected to the two first Schmitt triggers in opposite directions, and the second interface b is connected to the two second Schmitt triggers in opposite directions.

[0105] Taking the SDA_PSU signal as an example, when PSU210 sends the SDA_PSU signal to the mainboard, if the MCU uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SDA_PSU signal output by the MCU can only reach 0.4-0.5V, and cannot be pulled down to 0V. After the SDA_PSU signal passes through the first Schmitt trigger in the first isolation module 2121, the voltage will become 0V, and then pass through the resistor R3 on the path and the voltage divider of the line path (assuming it is 0.3V), and the voltage of the SDA_PSU signal reaching the mainboard is 0.3V.

[0106] Similarly, when PSU210 sends the SCL_PSU signal to the motherboard, if the MCU uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SCL_PSU signal output by the MCU can only reach 0.4-0.5V and cannot be pulled down to 0V. After the SCL_PSU signal passes through the second Schmitt trigger in the second isolation module 2122, the voltage will become 0V, and then pass through the resistor R4 on the path and the voltage divider of the line path (assuming it is 0.3V), the voltage of the SCL_PSU signal reaching the motherboard is 0.3V.

[0107] In other possible embodiments, the isolation module 212 can adopt an I2C isolation integrated circuit (also referred to as an I2C isolation chip), which includes a first input pin SDA1 and a second input pin SCL1, and at least one Schmitt trigger; the first interface a is connected to the first input pin SDA1, and the second interface b is connected to the second input pin SCL1.

[0108] For example, Figure 4 It is a structural diagram of another isolation integrated circuit provided in an embodiment of the present application.

[0109] Reference Figure 4 The above-mentioned isolation integrated circuit includes multiple Schmitt triggers and inverters.

[0110] In addition, the above-mentioned isolation integrated circuit also includes multiple pins, for example, pins 1 and 8 are respectively used to connect power supplies VCC1 and VCC2; pins 2 and 7 are respectively used to connect SDA signal interfaces SDA1 and SDA2; pins 3 and 6 are respectively used to connect SCL signal interfaces SCL1 and SCL2; pins 4 and 5 are respectively connected to ground ports GND1 and GND2.

[0111] Taking the SDA_PSU signal as an example, when PSU210 sends the SDA_PSU signal to the motherboard, if the MCU uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SDA_PSU signal output by the MCU can only reach 0.4-0.5V and cannot be pulled down to 0V. After the SDA_PSU signal passes through the above-mentioned isolation integrated circuit, the voltage will become 0V. After that, it passes through the resistors on the path and the voltage divider of the line path (assuming it is 0.3V), and the voltage of the SDA_BMC signal reaching the motherboard is 0.3V.

[0112] Similarly, when PSU210 sends the SCL_PSU signal to the motherboard, if the MCU uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SCL_PSU signal output by the MCU can only reach 0.4-0.5V and cannot be pulled down to 0V. After the SCL_PSU signal passes through the above-mentioned isolation integrated circuit, the voltage will become 0V, and then pass through the resistors on the path and the voltage divider of the line path (assuming it is 0.3V), and the voltage of the SCL_BMC signal reaching the motherboard is 0.3V.

[0113] Some embodiments of the present application also provide a motherboard. Figure 5 , Figure 5 5 is a schematic diagram of a mainboard structure provided in an embodiment of the present application. In some embodiments, the mainboard 510 includes a BMC 511 and an isolation module 512.

[0114] The BMC 511 includes at least one interface (such as the third interface c and the fourth interface d), which is connected to the isolation module 512 .

[0115] When the input voltage of the isolation module 512 is greater than the positive threshold voltage, the isolation module 512 outputs a high level; when the input voltage of the isolation module 512 is less than the negative threshold voltage, the isolation module 512 outputs a low level.

[0116] In some embodiments, the third interface c may be used to output an SDA_BMC signal, and the fourth interface d may be used to output an SCL_BMC signal. The SDA_BMC signal and the SCL_BMC signal may be used to communicate with the PSU.

[0117] Taking the SDA_BMC signal as an example, when the motherboard 510 sends the SDA_BMC signal to the PSU, if the BMC uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SDA_BMC signal output by the BMC can only reach 0.4-0.5V and cannot be pulled down to 0V. After the SDA_BMC signal passes through the isolation module 512, the voltage will become 0V. Then, after passing through the resistor R7 on the path and the voltage divider of the line path (assuming it is 0.3V), the voltage of the SDA_BMC signal reaching the PSU is 0.3V.

[0118] When the PSU sends the SDA_PSU signal to the motherboard 510, the voltage of the SDA_PSU signal output by the MCU can be 0V. Therefore, after passing through the resistors in the path and the voltage division of the line path (assuming it is 0.3V), the voltage of the SDA_PSU signal reaching the motherboard 510 is 0.3V. As a result, the voltage of the SDA_PSU signal sent by the PSU after reaching the motherboard is basically the same as the voltage of the SDA_BMC signal sent by the motherboard 510 after reaching the PSU, preventing false triggering.

[0119] Similarly, when the motherboard 510 sends an SCL_BMC signal to the PSU, if the BMC uses an I / O interface to simulate an IIC transceiver, the minimum voltage of the SCL_BMC signal output by the BMC can only reach 0.4-0.5V and cannot be pulled down to 0V. After the SCL_BMC signal passes through the isolation module 512, the voltage will become 0V. Then, after passing through the resistor R8 on the path and the voltage divider of the line path (assuming it is 0.3V), the voltage of the SCL_BMC signal reaching the PSU is 0.3V.

[0120] When the PSU sends the SCL_PSU signal to the motherboard 510, the voltage of the SCL_PSU signal output by the MCU can be 0V. Therefore, after passing through the resistors in the path and the voltage division of the line path (assuming it is 0.3V), the voltage of the SCL_PSU signal reaching the motherboard 510 is 0.3V. As a result, the voltage of the SCL_PSU signal sent by the PSU after reaching the motherboard is basically the same as the voltage of the SCL_BMC signal sent by the motherboard after reaching the PSU, preventing false triggering and ensuring normal communication between the PSU and the motherboard.

[0121] The mainboard provided in the embodiment of the present application can avoid the situation where the signal sent by the mainboard to the power supply unit is significantly different from the signal sent by the power supply unit to the mainboard by adding an isolation module, thereby reducing signal interference between the mainboard and the power supply unit and effectively preventing abnormal communication between the mainboard and the power supply unit.

[0122] Based on the contents described in the above embodiments, in some embodiments, the isolation module 512 includes at least one Schmitt trigger.

[0123] In some possible embodiments, the isolation module 512 includes a third isolation module and a fourth isolation module; the third isolation module includes at least one third Schmitt trigger; the fourth isolation module includes at least one fourth Schmitt trigger; the above-mentioned third interface c is connected to at least one third Schmitt trigger, and the above-mentioned fourth interface d is connected to at least one fourth Schmitt trigger.

[0124] For example, Figure 6 This is a structural diagram of another motherboard provided in an embodiment of the present application.

[0125] Reference Figure 6 The isolation module 512 includes a third isolation module 5121 and a fourth isolation module 5122 ; the third isolation module 5121 includes two inverted third Schmitt triggers; and the fourth isolation module 5122 also includes two inverted fourth Schmitt triggers.

[0126] The third interface c is connected to the two third inverted Schmitt triggers, and the second interface d is connected to the two fourth inverted Schmitt triggers.

[0127] Taking the SDA_BMC signal as an example, when the motherboard sends the SDA_BMC signal to the PSU, if the BMC uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SDA_BMC signal output by the BMC can only reach 0.4-0.5V and cannot be pulled down to 0V. After the SDA_BMC signal passes through the third Schmitt trigger in the third isolation module 5121, the voltage will become 0V. After that, it passes through the resistor R7 on the path and the voltage divider of the line path (assuming it is 0.3V), and the voltage of the SDA_BMC signal reaching the PSU is 0.3V.

[0128] Similarly, when the motherboard sends the SCL_BMC signal to the PSU, if the BMC uses the I / O interface to simulate the IIC transceiver, the minimum voltage of the SCL_BMC signal output by the BMC can only reach 0.4-0.5V and cannot be pulled down to 0V. After the SCL_BMC signal passes through the fourth Schmitt trigger in the fourth isolation module 5122, the voltage will become 0V, and then pass through the resistor R8 on the path and the voltage divider of the line path (assuming it is 0.3V), the voltage of the SCL_BMC signal reaching the motherboard is 0.3V.

[0129] In other possible implementations, the isolation module 512 may employ an I2C isolation integrated circuit, which includes a third input pin and a fourth input pin; the third interface c is connected to the third input pin, and the fourth interface d is connected to the fourth input pin.

[0130] It is understandable that the structure of the above-mentioned isolation integrated circuit can refer to Figure 4 The isolation integrated circuit shown is not described in detail here.

[0131] Some embodiments of the present application also provide a computing device. The computing device may include Figure 2 or Figure 3 The power supply unit shown, and / or Figure 5 or Figure 6 The main board shown will not be described in detail in the embodiments of this application.

[0132] In some possible implementations, the computing device further includes a backplane; the power supply unit is connected to the mainboard via the backplane.

[0133] In some possible implementations, the computing device may be a server.

[0134] The computing device provided in the embodiment of the present application can avoid the situation where the signal sent by the motherboard to the power supply unit is significantly different from the signal sent by the power supply unit to the motherboard by adding an isolation module, thereby reducing signal interference between the motherboard and the power supply unit, and effectively preventing abnormal communication between the motherboard and the power supply unit.

[0135] In the description of the embodiments of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "coupled" and "connected" should be understood in a broad sense. For example, they may refer to a fixed connection, an indirect connection via an intermediate medium, internal communication between two components, or an interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the embodiments of this application based on specific circumstances.

[0136] It is understandable that the division of the modules in the above-mentioned computing device is merely a division of logical functions. Each function may correspond to a functional module, or two or more functions may be integrated into one functional module. In actual implementation, all or part of the modules may be integrated into one physical entity, or distributed across different physical entities. In addition, the above-mentioned functional modules may be implemented in the form of hardware, software, or a combination of hardware and software, depending on the actual situation. Whether a function is executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0137] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of this application in detail. It should be understood that the above are only specific implementation methods of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of this application should be included in the scope of protection of this application.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application have been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A power supply unit, characterized in that: Includes controller and isolation module; The controller includes at least one interface, and the interface is connected to the isolation module; When the input voltage of the isolation module is greater than the positive threshold voltage, the isolation module outputs a high level; When the input voltage of the isolation module is less than the negative threshold voltage, the isolation module outputs a low level.

2. The power supply unit according to claim 1, wherein: The isolation module includes at least one Schmitt trigger.

3. The power supply unit according to claim 2, wherein: The at least one interface includes a first interface and a second interface, the first interface is used to output a serial data line SDA signal, and the second interface is used to output a serial clock line SCL signal; The isolation module includes a first isolation module and a second isolation module; the first isolation module includes at least one first Schmitt trigger; the second isolation module includes at least one second Schmitt trigger; The first interface is connected to the at least one first Schmitt trigger, and the second interface is connected to the at least one second Schmitt trigger.

4. The power supply unit according to claim 2, wherein: The at least one interface includes a first interface and a second interface, the first interface is used to output an SDA signal, and the second interface is used to output an SCL signal; The isolation module includes a first input pin and a second input pin, the first interface is connected to the first input pin, and the second interface is connected to the second input pin.

5. A motherboard, characterized in that: Includes baseboard management controller and isolation module; The baseboard management controller includes at least one interface, and the interface is connected to the isolation module; When the input voltage of the isolation module is greater than the positive threshold voltage, the isolation module outputs a high level; When the input voltage of the isolation module is less than the negative threshold voltage, the isolation module outputs a low level.

6. The mainboard according to claim 5, characterized in that: The isolation module includes at least one Schmitt trigger.

7. The mainboard according to claim 6, wherein: The at least one interface includes a third interface and a fourth interface, the third interface is used to output an SDA signal, and the fourth interface is used to output an SCL signal; The isolation module includes a third isolation module and a fourth isolation module; the third isolation module includes at least one first Schmitt trigger; the fourth isolation module includes at least one second Schmitt trigger; The third interface is connected to the at least one third Schmitt trigger, and the fourth interface is connected to the at least one fourth Schmitt trigger.

8. The mainboard according to claim 6, wherein: The at least one interface includes a third interface and a fourth interface, the third interface is used to output an SDA signal, and the fourth interface is used to output an SCL signal; The isolation module includes a third input pin and a fourth input pin, the third interface is connected to the third input pin, and the fourth interface is connected to the fourth input pin.

9. A computing device, characterized in that The computing device includes a power supply unit and / or a mainboard; the power supply unit is the power supply unit according to any one of claims 1 to 4; and the mainboard is the mainboard according to any one of claims 5 to 8.

10. The computing device according to claim 9, wherein: The computing device further includes a backplane; the power supply unit is connected to the mainboard via the backplane.

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