Sparse matrix storage method and device, computer equipment and storage medium
By performing block transposition and storage optimization on sparse matrices, the problem of low parallel processing efficiency in sparse matrix calculations is solved, the efficiency of VLSI simulation is improved, and more efficient sparse matrix storage and computing performance is achieved.
Patent Information
- Application Number
- CN202510824268.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-19
- Publication Date
- 2025-09-16
AI Technical Summary
When processing large-scale sparse matrices, the existing technology has low SPMV computational efficiency and cannot fully utilize the parallel processing capabilities of hardware, resulting in limited improvement in VLSI simulation efficiency. The main problems include high cache miss rate, large memory access overhead, low branch prediction success rate and low utilization of parallel processing units.
The rows in the sparse matrix that meet the preset conditions are divided into multiple groups, and the blocks are transposed and stored. The SIMD parallel processing technology is used to optimize the storage format of the sparse matrix to improve computing performance.
By dividing and transposing the non-zero matrix elements within a row, the parallel processing efficiency of SPMV calculation is significantly improved, the frequency of zero-padding operations is reduced, the branch prediction hit rate and data reading efficiency are improved, and the computing performance is optimized.
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Figure CN120653206A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuits, and in particular to a sparse matrix storage method, apparatus, computer equipment, and storage medium. Background Art
[0002] With the rapid development of very large scale integrated circuit (VLSI) technology, the scale of chips continues to expand and the complexity is increasing. In the VLSI simulation process, such as in scenarios such as transient analysis and steady-state analysis of circuits, it is frequently necessary to solve large-scale linear equations. The coefficient matrices of these linear equations usually exhibit sparse characteristics, that is, non-zero matrix elements usually account for only a very small proportion (less than 1%). Sparse matrix-vector multiplication (SPMV) is usually used in the core operation link of solving such linear equations, and occupies a key position in the entire calculation process. The operation process of SPMV can be expressed as A·x=y, where is a sparse matrix, (called the source vector) and (called the target vector) is a dense vector.
[0003] The compressed row format (CSR) is the most commonly used sparse matrix representation method. Its data structure is compact and effectively avoids the storage of a large number of zero values. CSR encodes the sparse matrix into three arrays in a row-first manner: the nnz array, which stores the values of non-zero matrix elements; the colidx array, which stores the column indices of non-zero matrix elements; and the rowptr array, which stores the index of the first element of each row in the nnz and colidx arrays. Figure 1 As shown in the figure, in the SPMV calculation based on the CSR format, the colidx array is used to extract the elements of the corresponding index from the source vector x, perform multiplication and addition operations with the non-zero matrix elements of the corresponding row of the sparse matrix A, and then store them in the target vector y.
[0004] The computational efficiency of SPMV has a direct and decisive impact on the overall simulation speed of VLSI. Traditional serial SPMV algorithms, when faced with large-scale sparse matrices, take too long to compute, making it difficult to keep up with the ever-increasing scale and complexity of VLSI designs. Although some parallel computing technologies currently exist to accelerate SPMV, they present numerous problems when actually applied to VLSI simulation scenarios. SPMV suffers from poor locality in accessing source vectors, a high cache miss rate, and high memory access overhead; adjacent rows of sparse matrices have different and random lengths, reducing branch prediction success rates and pipeline efficiency; and low utilization of parallel processing units, which cannot fully utilize the parallel processing capabilities of the hardware. This results in parallel acceleration effects falling far short of expectations, severely hindering improvements in VLSI simulation efficiency. Summary of the Invention
[0005] To overcome the problems existing in the related art, the present disclosure provides a sparse matrix storage method, apparatus, computer equipment and storage medium.
[0006] According to a first aspect of an embodiment of the present disclosure, a sparse matrix storage method is provided, comprising:
[0007] Dividing a plurality of rows in the sparse matrix whose number of non-zero matrix elements in the rows meets a preset first condition into a first group;
[0008] Dividing the rows in the first group into a plurality of blocks;
[0009] Transposing each of the blocks in the sparse matrix to obtain a second sparse matrix;
[0010] The second sparse matrix is stored.
[0011] Furthermore, the first condition includes:
[0012] The number of rows that match the following expression is at least N:
[0013] The difference between the number of non-zero matrix elements in this row and the first threshold value;
[0014] Wherein, N is an integer greater than or equal to 1, and the first threshold is a preset value that is not greater than the number of columns of the sparse matrix.
[0015] Furthermore, the step of dividing the rows in the first group into a plurality of blocks includes:
[0016] Sort the rows in the first group in descending order according to the number of non-zero matrix elements;
[0017] According to the sorting result, every K rows are divided into a block, where K is the width of the Single Instruction Multiple Data (SIMD) register.
[0018] Furthermore, the step of storing the second sparse matrix includes:
[0019] The transposed blocks are stored one by one in a row-first mode.
[0020] Furthermore, before the step of storing the second sparse matrix, the method further includes:
[0021] The rows whose difference in the number of non-zero matrix elements from any other row in the sparse matrix reaches a preset first threshold are divided into the second group.
[0022] Furthermore, the step of storing the second sparse matrix further includes:
[0023] For each row in the second group, non-zero matrix elements are processed in parallel within the row according to the SIMD parallel processing quantity.
[0024] According to a second aspect of an embodiment of the present disclosure, a sparse matrix storage device is provided, characterized in that the device includes:
[0025] A first grouping module is configured to group a plurality of rows in the sparse matrix whose number of non-zero matrix elements in the rows meets a preset first condition into a first group;
[0026] A block processing module, configured to divide the rows in the first group into a plurality of blocks;
[0027] a matrix transposition module, configured to transpose each of the blocks in the sparse matrix to obtain a second sparse matrix;
[0028] A storage processing module is used to store the second sparse matrix.
[0029] Furthermore, the first condition includes:
[0030] The number of rows that match the following expression is at least N:
[0031] The difference between the number of non-zero matrix elements in this row and the first threshold value is less than the first threshold value, where N is an integer greater than or equal to 1, and the first threshold value is a preset value not greater than the number of columns of the sparse matrix.
[0032] The block processing module includes:
[0033] a sorting submodule, configured to sort the rows in the first group in descending order according to the number of non-zero matrix elements;
[0034] The block submodule is used to divide every K rows into a block according to the sorting results, where K is the number of SIMD parallel processing.
[0035] Furthermore, the device further comprises:
[0036] The second grouping module is configured to group rows whose difference in the number of non-zero matrix elements from any other row in the sparse matrix reaches a preset first threshold into a second group.
[0037] Furthermore, the storage processing module includes:
[0038] A first storage submodule is used to store each of the transposed blocks one by one in a row-first mode;
[0039] The second storage submodule is configured to perform parallel processing on non-zero matrix elements within each row of the second group according to the SIMD parallel processing quantity.
[0040] According to a third aspect of an embodiment of the present disclosure, a computer device is provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the sparse matrix storage method as described in the first aspect when executing the computer program.
[0041] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium stores a computer program thereon, wherein the computer program, when executed by a processor, implements the sparse matrix storage method as described in the first aspect.
[0042] The technical solution provided by the embodiments of the present disclosure may include the following beneficial effects: dividing a plurality of rows in a sparse matrix whose number of non-zero matrix elements in the rows meets a preset first condition into a first group, then dividing the rows in the first group into a plurality of blocks, and transposing each of the blocks in the sparse matrix to obtain a second sparse matrix, which is then stored. Based on the number of non-zero matrix elements, the plurality of rows are divided into a block, and SIMD processing is performed within the block, thereby solving the problem of low parallel processing efficiency caused by multiple zero-padding operations, optimizing computing performance, and significantly improving branch prediction hit rate.
[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0045] Figure 1 It is a schematic diagram showing the principle of SPMV calculation based on the CSR format according to an exemplary embodiment.
[0046] Figure 2 The figure is a flow chart of a sparse matrix storage method according to an exemplary embodiment.
[0047] Figure 3 is a diagram illustrating an example of a sparse matrix according to an exemplary embodiment.
[0048] Figure 4 The flowchart of another sparse matrix storage method is shown according to an exemplary embodiment.
[0049] Figure 5 FIG. 4 is a schematic diagram showing the sorting results of rows of a sparse matrix according to an exemplary embodiment.
[0050] Figure 6 FIG. 4 is a schematic diagram of block division after transposition according to an exemplary embodiment.
[0051] Figure 7 is a schematic diagram showing a SIMD processing result according to an exemplary embodiment.
[0052] Figure 8 The flowchart of another sparse matrix storage method is shown according to an exemplary embodiment.
[0053] Figure 9 The figure is a schematic structural diagram of a sparse matrix storage device according to an exemplary embodiment.
[0054] Figure 10 is a structural diagram of the block processing module 902 according to an exemplary embodiment.
[0055] Figure 11 is a structural diagram of yet another sparse matrix storage device according to an exemplary embodiment.
[0056] Figure 12 is a structural diagram of the storage processing module 904 according to an exemplary embodiment.
[0057] Figure 13 It is a block diagram of a computer device according to an exemplary embodiment.
[0058] In the picture:
[0059] 1300 - computer device; 1031 - computing unit; 1302 - ROM; 1303 - RAM; 1304 - bus; 1305 - input / output interface; 1306 - input unit; 1307 - output unit; 1308 - storage unit; 1309 - communication unit. DETAILED DESCRIPTION
[0060] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
[0061] In SPMV operations, the processing of each row of a sparse matrix follows the same logic, and there is no interdependence between rows. This feature enables SPMV to fully leverage the parallel processing capabilities of the CPU during calculations, effectively improving computational efficiency. SIMD technology, as an instruction-level parallel feature provided by the AVX instruction set, has the core advantage of being able to perform the same operation on multiple data elements in a vector register simultaneously through a single instruction. This mechanism greatly reduces the additional overhead associated with operations such as instruction fetch, decoding, renaming, and distribution, significantly improving the efficiency of instruction execution.
[0062] Although some parallel computing technologies exist for accelerating SPMV, they present numerous challenges when applied to VLSI simulation scenarios. SPMV suffers from poor locality in source vector access, resulting in high cache miss rates and high memory access overhead. Adjacent rows of sparse matrices have varying and random lengths, reducing branch prediction success rates and pipeline efficiency. Furthermore, the utilization of parallel processing units is low, hindering the full utilization of the hardware's parallel processing capabilities. Consequently, the parallel acceleration effect falls far short of expectations, severely hindering improvements in VLSI simulation efficiency.
[0063] To address the aforementioned issues, embodiments of the present disclosure provide a sparse matrix storage method, apparatus, computer device, and storage medium. By partitioning the matrix into blocks based on the number of nonzero elements per row and transposing the blocks before storage, high-speed and efficient parallel sparse matrix processing is achieved, addressing the inefficient parallel processing caused by multiple zero-padding operations.
[0064] An exemplary embodiment of the present disclosure provides a sparse matrix storage method. The process of preprocessing the sparse matrix in the SPMV calculation process using this method is as follows: Figure 2 As shown, including:
[0065] Step 201: Divide a plurality of rows in a sparse matrix whose number of non-zero matrix elements in the rows meets a preset first condition into a first group.
[0066] The first condition includes:
[0067] The number of rows that match the following expression is at least N:
[0068] The difference between the number of non-zero matrix elements in this row and the first threshold value;
[0069] Wherein, N is an integer greater than or equal to 1, and the first threshold is a preset value that is not greater than the number of columns of the sparse matrix.
[0070] According to an exemplary embodiment, N is set to 2, the value of the first threshold is set to the SIMD parallel processing number, and N rows of non-zero matrix elements whose difference does not exceed the SIMD parallel processing number constitute the first group. The SIMD parallel processing number is the number of data elements that can be processed simultaneously using SIMD instructions.
[0071] For example, if the number of SIMD parallel processing is 4, and the number of rows whose number of non-zero matrix elements differs from that of the current row by no more than 4 is greater than or equal to 2, the number of non-zero matrix elements in the current row is not significantly higher than that of other rows in the sparse matrix, and the current row can be divided into the first group together with multiple other rows.
[0072] Figure 3 The following example shows a sparse matrix with the number of nonzero matrix elements in each row being 2, 3, 2, 1, 7, 1, 3, and 1. The SIMD unit (i.e., the number of SIMD parallel processes) is set to 4, and N is set to 1. It can be seen that the number of nonzero matrix elements in row 5 is significantly higher than in other rows. Therefore, row 5 is divided into the second group, and the other rows are divided into the first group.
[0073] According to an exemplary embodiment, rows that do not meet the first condition may be divided into a second group.
[0074] Step 202: Divide the rows in the first group into multiple blocks.
[0075] In this step, the multiple rows in the first group are further divided into blocks, so as to adopt a parallel processing method such as SIMD, thereby realizing parallel processing of multiple blocks and improving data processing efficiency.
[0076] This step is as follows Figure 4 As shown, including:
[0077] Step 401: sort the rows in the first group in descending order according to the number of non-zero matrix elements.
[0078] In this step, the rows in the first group are sorted according to the number of non-zero matrix elements. According to an exemplary embodiment, the rows are sorted in descending order.
[0079] like Figure 5 As shown, for Figure 3 The sparse matrix shown is sorted in descending order by the number of nonzero elements.
[0080] Step 402: According to the sorting result, each K rows are divided into a block.
[0081] Where K is the number of SIMD parallel processing.
[0082] According to an exemplary embodiment, the K value is set to 4, and the corresponding SIMD unit includes four units.
[0083] In the SIMD-based SPMV calculation process, when the CPU executes an operation, it reads the i-th non-zero matrix element in K adjacent rows into a vector register at a time. Simultaneously, it reads the value at the corresponding index in the source vector x into another vector register. Subsequently, a multiplication-addition operation is performed on the data in these two vector registers. The K mentioned here is the number of SIMD processes, reflecting the SIMD parallelism. Its specific value is determined by the data type used and the actual length of the vector register.
[0084] The rows ranked 2-5 are divided into one block, and the rows ranked 6-8 are divided into one block.
[0085] Step 203: Transpose each of the blocks in the sparse matrix to obtain a second sparse matrix.
[0086] In this step, the rows and columns of each block are swapped to obtain the transposed matrix of each block. Figure 5 Take the sorting result shown in the figure as an example, where the rows ranked 2-5 are divided into a block, and the blocks obtained after transposing are as follows Figure 6 As shown, the third row is padded with zeros, and zero matrix elements are added to the third and fourth columns of the third row.
[0087] Step 204: Store the second sparse matrix.
[0088] In this step, each of the transposed blocks is stored one by one in a row-first mode. According to an exemplary embodiment, the storage result is as follows: Figure 7 As shown in the figure, by sorting, rows with the same or similar number of non-zero matrix elements are divided into a block. This greatly reduces the frequency of zero-padding operations when reading registers, better utilizes the data access mechanism of the SIMD algorithm, improves the efficiency of data reading, and thus improves the overall performance of the SPMV calculation process based on SIMD characteristics.
[0089] An exemplary embodiment of the present disclosure further provides a sparse matrix storage method. When the number of non-zero matrix elements in some rows in the sparse matrix is significantly higher than that in other rows, different storage methods are used for different rows. The specific process is as follows: Figure 8 As shown, including:
[0090] Step 801: Divide a plurality of rows in a sparse matrix whose number of non-zero matrix elements in the rows meets a preset first condition into a first group.
[0091] Step 802: Divide the rows whose difference in the number of non-zero matrix elements from any other row in the sparse matrix reaches a preset first threshold into a second group.
[0092] The first threshold is a positive integer. According to an exemplary embodiment, the first threshold is an integer multiple of the number of SIMD parallel processing.
[0093] Step 803: Divide the rows in the first group into multiple blocks.
[0094] Step 804: Transpose each of the blocks in the sparse matrix to obtain a second sparse matrix.
[0095] The implementation principle of step 801 is the same as that of step 201 , and the implementation principle of steps 803 to 804 is the same as that of steps 202 to 203 , and will not be repeated here.
[0096] Step 805: Store the second sparse matrix.
[0097] In this step, each of the transposed blocks in the first group is stored one by one in a row-first mode.
[0098] For each row in the second group, non-zero matrix elements are processed in parallel within the row according to the SIMD parallel processing quantity.
[0099] by Figure 3 Taking the sparse matrix shown in the figure as an example, when the SIMD parallel processing number K is set to 4, the number of non-zero matrix elements in the 5th row is significantly higher than that in other rows, so it is divided into the second group; the other rows all have at least one other row with the same or similar number of non-zero matrix elements, so these rows are divided into the second group, and the rows are sorted in descending order according to the number of non-zero matrix elements. The results are as follows Figure 5 shown.
[0100] For the 7th row divided into the second group, the non-zero matrix elements are processed in parallel within the row according to the SIMD parallel processing quantity. For each row in the first group, it is divided into two blocks, and after transposing each block, it is stored in a row-first mode. The storage result is as follows Figure 7 shown.
[0101] After the blocks are divided, a matrix transposition operation is performed on each block and the blocks are restored in row-major mode. This process better matches the memory access requirements of SIMD instructions in subsequent calculations, improving data reading efficiency and thus improving the overall performance of the SPMV calculation process based on SIMD characteristics.
[0102] For rows where the number of non-zero matrix elements is significantly higher than that of other rows, in order to avoid wasting parallel computing units, the intra-row SIMD method is used for calculation, that is, k non-zero matrix elements are read into the vector register in units of the row and multiplication and addition operations are performed, and finally the elements in the vector register are summed.
[0103] By making full use of the SIMD parallel features provided by the AVX512F instruction set, the overhead of CPU instruction operations is greatly reduced.
[0104] The original sparse matrix is rearranged in rows to reduce the zero-padding operation ratio, improve the utilization of parallel units, and increase the branch prediction hit rate.
[0105] Transposing each block improves the locality of non-zero elements of the matrix read into the vector register.
[0106] An exemplary embodiment of the present disclosure also provides a sparse matrix storage method, which applies the method described in the present disclosure to sparse matrices and corresponding source vectors in several circuit simulation fields, and the data type is double-precision floating point numbers (double). The processor architecture used is x86-64, the CPU model is Intel Xeon Gold 6226, and the frequency is 2.7GHz. The L1 instruction cache and data cache of this CPU are both 32KB, the L2 cache is 1024KB, and the L3 cache is 19712KB.
[0107] Table 1 compares the performance of SPMV operations based on the CSR format and the improved format. Table 1 shows the CPU time (us) and the corresponding number of floating-point operations (GFLOPS) required for each SPMV operation. It can be seen that for matrices of varying sizes, the improved format achieves significant speedup compared to the traditional CSR format.
[0108] Table 1 Comparison of SPMV operation performance based on CSR format and improved format
[0109]
[0110]
[0111] An exemplary embodiment of the present disclosure further provides a sparse matrix storage device, the structure of which is as follows: Figure 9 As shown, including:
[0112] A first grouping module 901 is configured to group a plurality of rows in a sparse matrix whose number of non-zero matrix elements in the rows meets a preset first condition into a first group;
[0113] A block processing module 902, configured to divide the rows in the first group into a plurality of blocks;
[0114] A matrix transposition module 903 is configured to transpose each of the blocks in the sparse matrix to obtain a second sparse matrix;
[0115] The storage processing module 904 is configured to store the second sparse matrix.
[0116] Furthermore, the first condition includes:
[0117] The number of rows that match the following expression is at least N:
[0118] The difference between the number of non-zero matrix elements in this row and the first threshold value is less than the first threshold value, where N is an integer greater than or equal to 1, and the first threshold value is a preset value not greater than the number of columns of the sparse matrix.
[0119] The structure of the block processing module 902 is as follows Figure 10 As shown, including:
[0120] A sorting submodule 1001 is configured to sort the rows in the first group in descending order according to the number of non-zero matrix elements;
[0121] The block submodule 1002 is used to divide every K rows into a block according to the sorting result, where K is the number of single instruction multiple data (SIMD) parallel processing.
[0122] Furthermore, the device is as follows Figure 11 As shown, it also includes:
[0123] The second grouping module 905 is configured to group rows whose difference in the number of non-zero matrix elements from any other row in the sparse matrix reaches a preset first threshold into a second group.
[0124] Furthermore, the structure of the storage processing module 904 is as follows: Figure 12 As shown, including:
[0125] The first storage submodule 1201 is used to store the transposed blocks one by one in a row-first mode;
[0126] The second storage submodule 1202 is configured to perform parallel processing on non-zero matrix elements within each row of the second group according to the SIMD parallel processing quantity.
[0127] Each module in the above-mentioned sparse matrix storage device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each module.
[0128] In an exemplary embodiment, a computer device is provided, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, any of the above-mentioned sparse matrix storage methods is implemented.
[0129] In one exemplary embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When executed by a processor, the computer program implements any of the above-described sparse matrix storage methods. The computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, or optical data storage device.
[0130] In an exemplary embodiment, a computer program product is provided, including a computer program, which implements any of the above-mentioned sparse matrix storage methods when executed by a processor.
[0131] refer to Figure 13 , a block diagram of a computer device that can serve as the camera 2 or terminal 1 of the present disclosure will now be described. The computer device includes a computing unit 1301, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 1302 or a computer program loaded from a storage unit 1308 into a random access memory (RAM) 103. Various programs and data required for the operation of the computer device 1300 may also be stored in the RAM 1303. The computing unit 1301, ROM 1302, and RAM 1303 are connected to each other via a bus 1304. An input / output (I / O) interface 1305 is also connected to the bus 1304.
[0132] Multiple components in the computer device 1300 are connected to the I / O interface 1305, including: an input unit 1306, an output unit 1307, a storage unit 1308, and a communication unit 1309. The input unit 1306 can be any type of device that can input information to the computer device 1300. The input unit 1306 can receive input digital or character information and generate key signal input related to user settings and / or function control of the computer device 1300, and can include but is not limited to a mouse, a keyboard, a touch screen, a trackpad, a trackball, a joystick, a microphone, and / or a remote control. The output unit 1307 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 1308 can include but is not limited to a magnetic disk and an optical disk. The communication unit 1309 allows the computer device 1300 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and may include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver and / or a chipset, such as a Bluetooth™ device, a WiFi device, a WiMax device, a cellular communication device and / or the like.
[0133] The computing unit 1301 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1301 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 101 performs the various methods and processes described above, such as the sparse matrix storage method. For example, in some embodiments, the sparse matrix storage method can be implemented as a computer software program that is tangibly included in a machine-readable medium, such as a storage unit 1308. In some embodiments, part or all of the computer program can be loaded and / or installed on the computer device 1300 via ROM 1302 and / or communication unit 1309. When the computer program is loaded into RAM 1303 and executed by the computing unit 1301, one or more steps of the sparse matrix storage method described above can be performed.
[0134] Alternatively, in other embodiments, the computing unit 1301 may be configured to execute the sparse matrix storage method in any other appropriate manner (eg, by means of firmware).
[0135] The computer device 1300 can be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-mentioned shooting method.
[0136] Embodiments of the present disclosure provide a sparse matrix storage method, apparatus, computer device, and storage medium. Multiple rows in a sparse matrix whose number of non-zero matrix elements meets a preset first condition are divided into a first group. The rows in the first group are then divided into multiple blocks. Each of the blocks in the sparse matrix is transposed to obtain a second sparse matrix, which is then stored. Multiple rows are divided into blocks based on the number of non-zero matrix elements, and SIMD processing is performed within the blocks. This solves the problem of low parallel processing efficiency caused by multiple zero-padding operations, optimizes computing performance, and significantly improves branch prediction hit rates.
[0137] A notable feature of sparse matrices is that the number of non-zero matrix elements in each row is distributed in a completely random state. When applying SIMD instructions for calculations, for adjacent rows of different lengths, in order to adapt to the requirements of SIMD instructions for data length consistency, zero padding is usually used to align the data of shorter rows. However, this zero padding operation will affect the effective utilization of computing resources to a certain extent. In order to maximize the utilization of parallel units, the technical solution provided by the present disclosure innovatively performs a descending row rearrangement operation on the sparse matrix in the preprocessing stage of the calculation. By adjusting rows of similar lengths to adjacent positions, the proportion of zero padding operations in the entire calculation process is effectively reduced, the computing performance is further optimized, and the branch prediction hit rate is significantly improved. At the same time, the descending order brings the rows with more non-zero matrix elements to the front, so that they can be completely covered by the SIMD units, and avoids excessive zero padding operations or scalar operations at the end of the matrix. In addition, for rows where the number of non-zero matrix elements is significantly higher than that of other rows, in order to avoid wasting parallel computing units, the intra-row SIMD method is used for calculation, that is, k non-zero matrix elements are read into the vector register in units of the row and multiplication and addition operations are performed, and finally the elements in the vector register are summed.
[0138] In the process of reading the non-zero matrix elements of the sparse matrix into the vector register across rows, since the non-zero matrix elements of the sparse matrix are usually stored in a row-first arrangement, this storage structure results in poor locality of memory access when reading data, which is not conducive to efficient data reading. In view of the memory access mode unique to SIMD instructions, the embodiment of the present disclosure proposes an optimization scheme, that is, dividing the sparse matrix into blocks according to a group of K rows. After the block division is completed, a matrix transposition operation is performed on each block, and the blocks are re-stored in a row-first mode. After such processing, in the subsequent calculation process, the memory access requirements of the SIMD instructions can be better matched, the efficiency of data reading is improved, and the overall performance of the SPMV calculation process based on the SIMD characteristics is improved.
[0139] Those skilled in the art will appreciate that all or part of the steps in the above method can be performed by a program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps in the above embodiment can be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or software functional modules. The present disclosure is not limited to any particular combination of hardware and software.
[0140] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.
[0141] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims
1. A sparse matrix storage method, characterized in that: include: Dividing a plurality of rows in the sparse matrix whose number of non-zero matrix elements in the rows meets a preset first condition into a first group; Dividing the rows in the first group into a plurality of blocks; Transposing each of the blocks in the sparse matrix to obtain a second sparse matrix; The second sparse matrix is stored.
2. The sparse matrix storage method according to claim 1, characterized in that: The first condition includes: The number of rows that match the following expression is at least N: The difference between the number of non-zero matrix elements in this row and the first threshold value; Wherein, N is an integer greater than or equal to 1, and the first threshold is a preset value that is not greater than the number of columns of the sparse matrix.
3. The sparse matrix storage method according to claim 1 or 2, characterized in that: The step of dividing the rows in the first group into a plurality of blocks comprises: Sort the rows in the first group in descending order according to the number of non-zero matrix elements; According to the sorting results, every K rows are divided into a block, where K is the number of single instruction multiple data (SIMD) parallel processing.
4. The sparse matrix storage method according to claim 3, characterized in that: The step of storing the second sparse matrix comprises: The transposed blocks are stored one by one in a row-first mode.
5. The sparse matrix storage method according to claim 1, wherein: Before the step of storing the second sparse matrix, the method further includes: The rows whose difference in the number of non-zero matrix elements from any other row in the sparse matrix reaches a preset first threshold are divided into the second group.
6. The sparse matrix storage method according to claim 5, characterized in that: The step of storing the second sparse matrix further comprises: For each row in the second group, non-zero matrix elements are processed in parallel within the row according to the SIMD parallel processing quantity.
7. A sparse matrix storage device, characterized in that: The device comprises: A first grouping module is configured to group a plurality of rows in the sparse matrix whose number of non-zero matrix elements in the rows meets a preset first condition into a first group; A block processing module, configured to divide the rows in the first group into a plurality of blocks; a matrix transposition module, configured to transpose each of the blocks in the sparse matrix to obtain a second sparse matrix; A storage processing module is used to store the second sparse matrix.
8. The sparse matrix storage device according to claim 1, wherein: The first condition includes: The number of rows that match the following expression is at least N: The difference between the number of non-zero matrix elements in this row and the first threshold value is less than the first threshold value, where N is an integer greater than or equal to 1, and the first threshold value is a preset value not greater than the number of columns of the sparse matrix. The block processing module includes: a sorting submodule, configured to sort the rows in the first group in descending order according to the number of non-zero matrix elements; The block submodule is used to divide every K rows into a block according to the sorting results, where K is the number of single instruction multiple data (SIMD) parallel processing.
9. The sparse matrix storage device according to claim 8, characterized in that: The device further comprises: The second grouping module is configured to group rows whose difference in the number of non-zero matrix elements from any other row in the sparse matrix reaches a preset first threshold into a second group.
10. The sparse matrix storage device according to claim 9, characterized in that: The storage processing module includes: A first storage submodule is used to store each of the transposed blocks one by one in a row-first mode; The second storage submodule is configured to perform parallel processing on non-zero matrix elements within each row of the second group according to the SIMD parallel processing quantity.
11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.
12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.