SIMD multi-thread distributed parallel interpretation calculation method

Abstract

The application belongs to the cross field of aviation equipment guarantee and predictive maintenance, and relates to a SIMD multithread distributed parallel interpretation calculation method. The application forms a hardware acceleration closed loop without software intervention through single calculation node (SIMD vectorization processing) -> RDMA network (sub-microsecond transmission) -> FPGA (nanosecond level timing verification), constructs a four-stage thread pipeline of "data prefetching -> arithmetic operation -> logic combination -> threshold comparison", directly writes the state vector of each thread calculation into the RDMA registration memory pool, realizes zero-copy transmission of the state vector between nodes through RDMA, introduces a distributed state machine to realize duration tracking, initiates cooperative verification when the timer value is greater than or equal to the preset duration threshold, greatly reduces feature interpretation delay and threshold update delay, reduces network bandwidth occupation and communication overhead, guarantees accuracy, and greatly improves interpretation speed.

Description

Technical Field

[0001] The present invention belongs to the intersection field of aviation equipment support and predictive maintenance, and relates to a SIMD multi-threaded distributed parallel interpretation and calculation method. Background Art

[0002] With the continuous iteration of aircraft, the flight data of aviation equipment has increased exponentially. Existing Fetion data processing software has shown obvious performance bottlenecks in handling the growing amount of flight data. Modern aviation equipment, especially military equipment, needs more urgent rapid support due to the need for systematic and coordinated operations. However, existing Fetion data processing software and existing technologies have three technical gaps:

[0003] 1) Idle SIMD computing power and computational fragmentation: Current mainstream systems (such as Spark Streaming) convert interpretation rules into scalar instructions, resulting in less than 5% CPU vector register utilization. For example, Intel AVX-512, while a 512-bit register can handle 16 floating-point comparisons in parallel, existing frameworks (such as Flink CEP) still rely on point-by-point computation.

[0004] 2) Inefficient multi-threaded collaboration: Complex interpretation rules (such as "(A>B)&&(C <D||E∈[F,G])")需多级运算嵌套,现有线程池方案(如Java ForkJoinPool)存在严重瓶颈:任务调度开销占时比超30%,线程间数据传递依赖内存拷贝,违反局部性原理,锁竞争导致吞吐量随线程数增加不升反降。各线程间由于数据循环等待还易造成死锁。

[0005] 3) Distributed state synchronization lag: Continuous cross-node verification requires maintaining global state, and existing solutions have inherent flaws, namely: Solution type: Flaws: Example: Consequences: Centralized arbitration: A single node handles 20% of cross-domain verification requests, becoming a bottleneck in system throughput. Gossip protocol: State convergence requires 3-5 rounds of broadcasts, with delays in the second range, failing to meet real-time requirements. Full synchronization: A single synchronous transmission of 1MB of state data consumes 95% of the cluster network bandwidth.

[0006] 4) Limitations of existing improvement solutions: GPU acceleration: While it improves parallelism (e.g., CUDA achieves 100x acceleration), it cannot handle dynamic rule changes, and cold starts take over 500ms. FPGA hard parsing: After the rules are solidified, they must be re-programmed, resulting in a loss of business flexibility. In-memory computing engines: They are still limited by the μs-level latency of the TCP / IP protocol stack and cannot achieve sub-millisecond state consistency. These deficiencies collectively result in existing systems experiencing difficulty breaking the 10ms end-to-end latency barrier when processing the entire chain of "numerical calculation → logical interpretation → continuous verification," severely restricting the high-speed interpretation of massive amounts of data.

[0007] In summary of the above, the present application intends to design an aviation equipment real-time parameter distributed interpretation method integrating SIMD vectorization acceleration, multi-thread pipeline optimization and RDMA direct transmission technology. SUMMARY

[0008] The present application aims at the defects of the existing data interpretation method in parallel computing efficiency, distributed collaboration and continuous verification, and proposes a distributed parallel interpretation method integrating SIMD vectorization, multi-thread pipeline and RDMA direct transmission. The method is aimed at the massive group flight parameter data packets generated by modern aviation equipment (such as C919 and new fighter aircraft) per second, and solves the real-time bottleneck problem of traditional serial processing architecture in key scenarios such as flight parameter rapid interpretation.

[0009] The technical scheme of the present application is as follows:

[0010] A SIMD multi-thread distributed parallel interpretation calculation method, the steps are as follows:

[0011] Step 1: Build an LLVM intermediate representation (IR) of the feature interpretation rule, and decompose the composite logical expression into an atomic operation sequence, and map it to a SIMD instruction template.

[0012] Step 1-1: Convert the arithmetic operations inside the feature interpretation rule into atomic operation arithmetic operations: extract the two objects A and B involved in the arithmetic operations inside the feature interpretation rule, convert them into SIMD arithmetic instructions, and represent the operation result as an AVX vector object, as shown in formula (1.1). It should be particularly noted that there may be not less than 1 arithmetic operation inside the feature interpretation rule, and A and B used in formula 1.1 and step 1-1 are an abstract expression of the objects involved in the arithmetic operation. The actual operation object may be an expression with not less than 1 original parameter after arithmetic operation, logical operation or both, or it may be 1 original parameter, a calculation parameter or a coefficient.

[0013] (1.1)

[0014] Wherein: represents multiplication, in addition to multiplication, there are addition, subtraction, division, multiplication and addition, etc., which need to be mapped differently according to the actual arithmetic operation used in the feature interpretation rule.

[0015] Step 1-2: Convert the comparison operation inside the feature interpretation rule into atomic operation comparison and map it to a SIMD instruction template: extract the two comparison objects C and D before and after the comparison operation inside the feature interpretation rule, convert them into SIMD comparison instructions, and store the comparison result in a mask vector Inside, as shown in formula (1.2). It should be particularly noted that there can be no less than 1 comparison operation inside the feature interpretation rule, and C and D used in formula 1.2 and step 1-2 are an abstract expression of the comparison objects involved in the comparison operation. The actual comparison object can be an expression obtained by performing arithmetic operations, logical operations, or both on no less than 1 original parameter, or it can be 1 original parameter or a calculation parameter.

[0016] (1.2)

[0017] Wherein: represents a comparison instruction, which consists of three parts: comparison object C, comparison object D, and comparison type; "comparison type" includes equal_CMP_EQ_OQ, less than_CMP_LT_OS, less than or equal_CMP_LE_OS, not equal_CMP_NEQ_UQ, greater than_CMP_GT_OQ, greater than or equal_CMP_NLT_US, etc. It needs to be mapped according to the actual comparison operation used.

[0018] Step 1-3, atomic operation logic combination, after combining the arithmetic operation object obtained in step 1-1 with the logical operation in 1-2, a mask vector is obtained, and the mask vector is ANDed to obtain a result vector, as shown in formula (1.3).

[0019] (1.3)

[0020] Wherein: represents logical AND, in addition to logical AND, logical OR and logical NOT will also be used, which needs to be mapped according to the actual logical operation used. It should be particularly noted that according to different feature interpretation rules, multiple mask vectors can be obtained. When there are more than 2 mask vectors, the result of formula 1.3 needs to be further ANDed with the remaining mask vectors for corresponding logical operations. Through the above operation, 16 data points of rule interpretation are completed in a single instruction cycle.

[0021] Step 2, single computing node multi-threaded hierarchical pipeline: four-stage processing pipeline is constructed for complex rules. For complex rules, a four-stage pipeline of "data prefetching → arithmetic operation → logical combination → threshold comparison" is constructed. Threads in each stage exchange data through RDMA-registered memory with remote direct memory access, and a lock-free ring buffer is used. The producer thread updates the head pointer after writing data, and the head pointer is implemented through RDMA atomic addition. The consumer thread tracks readable data through the tail pointer, and data is loaded according to memory order. In addition, in the data prefetching stage, a directed acyclic graph of parameters required by each thread is constructed to solve the deadlock problem.

[0022] Step 2-1 data prefetching: read raw data from disk, calculate the amount of calculation parameters used in the feature interpretation rule, and align all parameters used in the rule. In this process, thread deadlock problem may occur due to the mutual dependence of the amount of calculation parameters. Abstract each calculation thread as a "node" in graph theory, construct a one-way edge between nodes according to the demand relationship of each calculation, and save the number of arrows from each node to other nodes as the "out-degree" of each node, thereby constructing a directed graph of the mutual dependence of the amount of calculation parameters of each thread. By detecting whether there is a loop in the directed graph, the deadlock problem is detected, and the thread scheduling is performed according to the node out-degree. Thus, the possible deadlock problem is solved, and the thread scheduling process is optimized.

[0023] Step 2-2 complete the arithmetic operation and logical operation of the parameters disassembled in step 1, and synchronize the results to the result vector buffer registered in RDMA. In the process of synchronizing the results, sparse state synchronization optimization is introduced, and bit mask compression technology is used to transmit state changes. That is: extract the 16-bit mask (1 bit / data point) of the SIMD comparison result, only transmit the data value corresponding to the non-zero mask bit, and use _mm512_mask_expandloadu_ps to reorganize the result vector.

[0024] Step 2-3: Traverse the result vector in the RDMA cache in 16-bit, record the number of consecutive conditions n, and increment the count when the feature is detected to meet the condition, clear it when interrupted, and check whether n reaches the duration. If the duration is reached, trigger the distributed collaborative authentication of step S3. It should be particularly noted that each floating-point data is 32 bits, and avx512 registers can simultaneously perform 16 floating-point comparison operations and obtain 16-bit polynomial operation results. Therefore, step 2-3 needs to be traversed in 16 bits, and if avx256 registers are used, it needs to be traversed in 8 bits.

[0025] Step 3: Distributed continuous verification mechanism. When the local node detects that the feature duration reaches the threshold, it broadcasts a verification request to the arbitration group through RDMA Write with Immediate, which contains the data point ID and the current state. The receiving node loads the corresponding data point using _mm512_mask_load_ps, compares the local state, and returns the confirmation through the RDMA atomic operation. After receiving N / 2+1 confirmations, it is determined that the feature is established.

[0026] The beneficial effects of the present application are:

[0027] The application decomposes complex rules in data interpretation into multiple atomic operations and maps them into SIMD instruction templates by hardware reconstruction combined with software innovation; constructs a four-stage pipeline architecture of "data prefetching -> arithmetic operation -> logical combination -> threshold comparison" for single computing node multi-thread interpretation; constructs a one-way graph based on data association for thread deadlock problems caused by mutual dependence and cyclic waiting of calculation parameters in the data prefetching process of single computing node multi-thread interpretation, detects thread deadlock problems by detecting whether there is a ring in the directed graph, and schedules threads according to the out-degree in the directed graph; uses RDMA technology to realize distributed collaborative update of SIMD operation results of multiple computing nodes; designs a timer update algorithm for the duration of data interpretation to track and verify the duration of data interpretation, and finally realizes distributed collaborative interpretation of data. While ensuring the accuracy of interpretation, the parallel computing efficiency, distributed collaborative ability and continuous verification ability of interpretation are greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a distributed hardware framework of the application;

[0029] Figure 2 is a whole process flowchart of the application;

[0030] Figure 3 is a single node computing flowchart of the application;

[0031] Figure 4 is a multi-thread four-stage pipeline of the application;

[0032] Figure 5 is a lock-free cache diagram of the application;

[0033] Figure 6 is a lock cache diagram of the application. DETAILED DESCRIPTION

[0034] The advantages and effects of the application can be easily understood by those skilled in the art from the disclosure of the specification. The application can also be implemented and applied by different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0035] It should be noted that in the following description, reference should be made to the accompanying drawings which describe several embodiments and application processes of the application, and it should be understood that.

[0036] Before the invention is further described in detail, the terms and phrases involved in the embodiments of the invention are explained, and the terms and phrases involved in the embodiments of the invention are applicable to the following explanations:

[0037] <1> Judgment: Judgment of whether the data meets a certain feature, including arithmetic operations (such as addition, subtraction, multiplication, and division), logical operations (and, or, and not), and comparisons (greater than or less than a threshold) and lasts for a certain period of time.

[0038] <2> Flight data: Flight data of an aerial vehicle, including analog and digital (switching) quantities.

[0039] <3> Raw data: Directly read from the flight data packet.

[0040] <4> Calculated quantity parameter: Data obtained by arithmetic operations, logical operations, etc. on raw data.

[0041] <5> SIMD: Single Instruction, Multiple Data (SIMD) is a parallel computing architecture that allows a processor to process multiple data elements simultaneously using a single instruction. Compared with traditional serial processing (SISD), SIMD can significantly improve the performance of data-intensive operations.

[0042] <6> RDMA: Remote Direct Memory Access (RDMA) is a technology that bypasses the operating system kernel to transfer data directly between network hosts, achieving zero-copy and zero-CPU data exchange, designed for low-latency and high-throughput scenarios.

[0043] <7> LLVM: LLVM (Low Level Virtual Machine) is an open-source compiler infrastructure project developed by the University of Illinois and maintained by the LLVM developer community. Its core is a modular and reusable compiler toolchain.

[0044] <8> Intermediate representation IR: LLVM defines a hardware-independent intermediate language LLVM IR as a common representation in the compilation process, usually with strong typing, static single assignment (SSA) form, and support for various optimization transformations.

[0045] <9> Complex rules: Usually more than 5 parameters are involved in arithmetic operations, logical operations, or even further nesting. In addition to raw data, the parameters involved in the operation also include calculated quantity parameters and history-based variable parameters due to individual differences in equipment.

[0046] <10> Local node: A single computing node where the current operation thread is located.

[0047] The embodiments of the present application will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily implement the present application. The present application can be embodied in various different forms, and is not limited to the embodiments described herein.

[0048] The method comprises:

[0049] Step S1: hardware architecture deployment, Figure 1 For the hardware architecture required by the present application, in addition to the plurality of computing nodes of the core part and the RDMA cache space for data exchange of each computing node, some additional supporting hardware devices are also required. The configuration of the hardware devices includes the following steps:

[0050] Step S11: single computing node hardware configuration: the core processor uses Intel Sapphire Rapids Xeon CPU (16 cores / 32 threads) and is configured through BIOS Advanced→CPU Configuration→AVX-512 Enable = True and

[0051] Advanced→Power Management→Turbo Boost Max 3.0 = Disabled; the memory channel uses 8-channel DDR5-4800 (2 DIMMs per channel), and NUMA balancing is achieved through numactl --interleave=all. It should be particularly noted that as the performance of the single computing node CPU improves, the efficiency of the interpretation scheme described in the present application can be further improved.

[0052] Step S12: configure single-node network acceleration module. The network card uses Mellanox ConnectX-6 DX 100Gbps dual-port, and the driver parameters are loaded through modprobe mlx5_core log_num_mgm_entry_size=-1 and echo 2048 > / sys / class / infiniband / mlx5_0 / device / sriov_numvfs; the physical link uses QSFP28 optical fiber direct connection arbitration node, and the MTU is set to 4096 bytes (ip link set dev eth0 mtu 4096).

[0053] Step S13 physically deploys the topology. The data path of a single computing node and a TOR switch is configured, and through direct connection with RDMA, the operating system protocol stack is bypassed, and the remote memory is directly read and written through ibv_post_send, avoiding CPU participation, so as to realize microsecond-level data injection; the TOR switch and the arbitration cluster (the arbitration cluster is composed of multiple peer nodes rather than a single point, and ECMP automatically avoids faulty links to ensure 99.99% availability, and each arbitration node independently processes subset states) interact to solve the state synchronization bottleneck; the arbitration cluster and the FPGA acceleration card are configured, and through the 64 GB / s bidirectional bandwidth provided by the PCIe Gen4 x16 backplane, the FPGA timing acceleration card processes 1024 timers in parallel and accesses the timing state in the on-chip memory without delay to break through the performance wall of continuous duration verification. Finally, a hardware acceleration closed loop without software intervention is formed, which is computing node (SIMD vectorized processing) → RDMA network (sub-microsecond transmission) → FPGA (nanosecond-level timing verification). It is ensured that each computing node is deployed with dual-path Xeon CPU (supporting AVX-512), equipped with Mellanox ConnectX-6 DX network card (100 Gbps RDMA), and all data buffers are aligned according to 64 bytes (posix_memalign allocation), ensuring that SIMD can be directly loaded. It should be noted that in order to achieve optimal performance, the CPU needs to be set to performance mode and the network card energy saving needs to be disabled.

[0054] Step S2 vectorized interpretation flow. Figure 2 is the whole process flowchart of the present application. For the convenience of understanding, step S21 will be introduced in combination with specific examples. The specific process includes:

[0055] Step S21 pre-processing stage-rule compilation: the input rule is disassembled into atomic operations, taking the rule shown in formula (1.4) as an example.

[0056] (1.4)

[0057] This formula represents the expert rule that “the vibration value is greater than 5 for 10 seconds and the temperature is higher than 80 degrees Celsius”, and after disassembly, three atomic operations shown in formula (1.5) are obtained:

[0058] (1.5)

[0059] Among them, represents the temperature, The vibration value is represented, the final processing result is stored as a 16-bit state mask (1 bit / data point), and the changed bit is synchronized to the RMDA corresponding cache. For a small amount of data, it is recommended to complete the data interpretation of the same feature rule by multi-threading within the same computing node. When the data amount is large, it is recommended to perform non-overlapping segmentation on the data, and the data interpretation is completed in different computing nodes.

[0060] Step S22, pre-processing stage-RDMA state synchronization. A shared area is created by ibv_reg_mr, and the attribute is set to IBV_ACCESS_REMOTE_ATOMIC; the state vector of each computing node is directly written into the RDMA registration memory pool (the memory page is aligned at 64 bytes), when the result is updated, the immediate number operation (RDMA Write with Immediate) is used to broadcast the threshold value update; the change mask is calculated by formula (1.6), and only the change bit mask and the new value need to be transmitted, so that the compression efficiency of the result vector can be further improved to 90%.

[0061] (1.6)

[0062] Step S23, duration tracking. A timer update algorithm is designed for the final result of the SIMD operation, that is, 16 bits (avx512 registers can simultaneously and parallelly process 16 floating point comparison operations) are used to traverse the result vector in the RDMA cache, the number n of continuous conditions that are true (when the feature is continuously detected to meet the condition, the count is incremented, and the count is cleared when interrupted) is recorded, and whether n reaches the duration is verified, if the duration threshold required for the continuous rule to be true is reached, the distributed collaborative authentication of step S24 is triggered, that is, the time when each data point continuously meets the feature is tracked, when the local timer reaches the duration threshold, cross-node collaborative verification is initiated.

[0063] Step S24, collaborative verification. The state verification request (including the data point ID and the current state) is multicast to the arbitration group node, the receiving node compares the local state through the RDMA atomic operation, when the majority of nodes (N / 2+1) confirm, it is determined that the feature continuously meets the condition, the decision output is triggered and the related timer is reset. The collaborative verification is completed.

[0064] Step S3, single computing node constructs a multi-threaded four-stage pipeline. Figure 3 It is a single computing node interpretation scheme of the application, and a single computing node realizes raw data reading, calculation parameter calculation, arithmetic operation, logical operation and logical combination through multi-threading technology, and synchronizes the final SIMD operation result to the RDMA cache space.

[0065] Step S31, multi-threaded pipeline. For complex rules, a multi-threaded pipeline is constructedFigure 4 The four-stage pipeline of "data prefetching → arithmetic operation → logical combination → threshold comparison" is shown. Each stage thread exchanges data through RDMA registered memory, reduces the additional communication overhead caused by distributed cross-boundary point communication, and balances the dynamic load of each pipeline stage.

[0066] Step S32: The data prefetching stage constructs a directed acyclic graph of the required parameters of each thread to solve the deadlock problem. Each thread needs to complete data prefetching of the required parameters before performing arithmetic operations. For some complex operations, some parameters required by the current thread may be calculated by other threads (such parameters are referred to as calculation parameters in the present application). When multiple threads calculate parameters in a circular wait manner, thread deadlock may occur. The present application constructs a directed acyclic graph according to the required parameters of the calculation parameters of each thread in the working thread of the thread pool, and realizes lock-free scheduling between threads. Figure 5 A directed acyclic graph constructed by the present application is shown. The construction steps include:

[0067] Step S33: List the required parameters of the calculation parameters in each thread. Taking five threads as an example, the required parameters of the calculation parameters of each thread are listed as shown in Table 1.

[0068] Table 1: Required parameters of calculation parameters of each thread

[0069]

[0070] Among them: capital letters A, B, C, D represent calculation parameters, lowercase letters a, b, c, d, e represent original data, and the calculation parameters are separated by "," (only for illustration, other separators can be used in actual implementation).

[0071] Step S34: Each thread is abstracted as a node of a graph, and a directed acyclic graph is constructed between each node according to the required parameters of the calculation parameters of each thread. For example, if the calculation parameter A needs to use the calculation parameter B, the calculation thread of the calculation parameter A is unidirectionally pointed to the calculation thread of the calculation parameter B. Similarly, if a certain thread n needs more than two calculation parameters, the calculation thread node of the required calculation parameter is unidirectionally pointed to from n. In this way, a directed acyclic graph of the waiting threads in the data prefetching stage can be constructed. In addition, each node needs to additionally save an "out-degree", and the value of the out-degree is the number of arrows pointing to other nodes from the node.

[0072] Step S35 periodically checks the directed acyclic graph by the worker threads of the thread pool to check whether a loop is formed, i.e., whether a node is returned to after passing through a unidirectional path, and if so, the loop is cut off in time. If no loop is formed, a node with an out-degree of 0 is preferentially scheduled for operation. Thus, a directed acyclic graph is constructed to realize lock-free caching of flight parameter data. It should be particularly noted that the definition of a loop here must be that a node is returned to after passing through a unidirectional path, as shown in FIG. 3. Figure 6 Although the loop shown in FIG. 4 has a physical meaning, it does not constitute the strict definition of a loop of the present application. Figure 5 Although the loop shown in FIG. 4 has a physical meaning, it does not constitute the strict definition of a loop of the present application.

[0073] In summary, the present application proposes a parallel computing method that fuses a SIMD instruction set, multi-thread scheduling, and distributed node cooperation, forms a hardware-accelerated closed loop without software intervention through single computing nodes (SIMD vectorization processing) -> RDMA network (sub-microsecond transmission) -> FPGA (nanosecond-level verification), constructs a four-stage thread pipeline of "data prefetching -> arithmetic operation -> logical combination -> threshold comparison", directly writes the state vectors of thread calculation into an RDMA registration memory pool, realizes zero-copy transmission of state vectors between nodes through RDMA, introduces a distributed state machine to realize duration tracking, initiates cooperative verification when the timer value is greater than or equal to a preset duration threshold, greatly reduces feature interpretation delay and threshold update delay, reduces network bandwidth occupation and communication overhead, and ensures accuracy while greatly improving interpretation speed.

Claims

1. A SIMD multi-threaded distributed parallel interpretation and calculation method, characterized in that: Here are the steps: Step 1: Construct the LLVM intermediate representation (IR) of the feature interpretation rule, decompose the complex logical expression into a sequence of atomic operations, and map it to a SIMD instruction template. Step 1-1 Convert the arithmetic operation within the feature interpretation rule into an atomic arithmetic operation: Extract the two objects A and B involved in the arithmetic operation within the feature interpretation rule, convert them into SIMD arithmetic instructions, and represent the operation result as an AVX vector object, as shown in formula (1.1); （1.1） in, Indicates multiplication. In addition to multiplication, there are addition, subtraction, division, and multiplication and addition; Step 1-2 Convert the comparison operation inside the feature judgment rule into an atomic comparison operation and map it into a SIMD instruction template: Extract the two comparison objects C and D before and after the comparison operation inside the feature judgment rule, convert them into SIMD comparison instructions, and store the comparison results in a Boolean mask vector. Inside, as shown in formula (1.2); （1.2） in: Represents a comparison instruction. The instruction consists of three parts: comparison object C, comparison object D, and comparison type. "Comparison type" includes equal_CMP_EQ_OQ, less than_CMP_LT_OS, less than or equal to_CMP_LE_OS, not equal to_CMP_NEQ_UQ, greater than_CMP_GT_OQ, and greater than or equal to_CMP_NLT_US. Step 1-3: Atomic operation logical combination. After combining the arithmetic operation object obtained in step 1-1 with the logical operation in step 1-2, a mask vector is obtained. The mask vector is ANDed together to obtain the result vector, as shown in formula (1.3). （1.3） in: Indicates logical AND. In addition to logical AND, logical OR and logical NOT are also used. Mapping is required based on the actual logical operation used. This allows for the regular interpretation of 16 data points in a single instruction cycle. Step 2: Multi-threaded hierarchical pipeline on a single computing node: A four-stage processing pipeline is constructed for complex rules. For complex rules, a four-stage pipeline consisting of data prefetch, arithmetic operations, logical combination, and threshold comparison is constructed. Threads at each stage exchange data via remote direct memory access (RDMA) registered memory, implemented using a lock-free ring buffer. After writing data, the producer thread updates the head pointer using RDMA atomic additions. The consumer thread tracks readable data using the tail pointer, and data is loaded in memory order. During the data prefetch phase, deadlock is resolved by constructing a directed acyclic graph of the parameters required by each thread. Step 3: Distributed continuous verification mechanism; When the local node detects that the duration of a feature reaches the threshold, it broadcasts a verification request to the arbitration group using RDMA Write with Immediate. The verification request must include the data point ID and current status. The receiving node uses _mm512_mask_load_ps to load the corresponding data point, compares the local status, and returns a confirmation through RDMA atomic operations. After receiving N / 2+1 confirmations, the feature is considered valid.

2. A SIMD multi-threaded distributed parallel interpretation and calculation method according to claim 1, characterized in that: The specific operations of step 2 are as follows: Step 2-1 Data prefetching: Read the original data from the disk, calculate the computational parameters used in the feature interpretation rules, and align all the parameters used in the rules; The threads containing each computational workload are abstracted as "nodes" in graph theory. Based on the demand relationship of each computational workload, one-way edges from "demand → source" are constructed between nodes. Each node stores the number of arrows pointing from itself to other nodes as its "out-degree," thereby constructing a directed graph of the interdependence of computational workload parameters of each thread. Detect deadlock problems by detecting whether there are cycles in the directed graph and schedule threads based on the node out-degree; Step 2-2: Complete the arithmetic and logical operations on the parameters decomposed in step 1 and synchronize the results to the result vector cache registered in RDMA. During the synchronization process, sparse state synchronization optimization is introduced, using bit mask compression technology to transmit state changes. Step 2-3 traverses the result vector in the RDMA cache with 16 bits, records the number n of times the condition is met continuously, increments the count when the feature is continuously detected, resets it to zero when it is interrupted, and checks whether n reaches the duration. If so, the distributed collaborative authentication of step S3 is triggered.

3. A SIMD multi-threaded distributed parallel interpretation and calculation method according to claim 1, characterized in that: In the above steps 1-3, when there are more than two mask vectors, the result of formula 1.3 needs to be further subjected to corresponding logical operations with the remaining mask vectors in sequence.

4. A SIMD multi-threaded distributed parallel interpretation and calculation method according to claim 2, characterized in that: The specific operations of step 2-2 are as follows: extract the 16-bit mask of the SIMD comparison result, transmit only the data values ​​corresponding to the non-zero mask bits, and reassemble the result vector using _mm512_mask_expandloadu_ps.

5. A SIMD multi-threaded distributed parallel interpretation and calculation method according to claim 2, characterized in that: In the steps 2-3, each floating-point data used is 32 bits. The avx512 register can process 16 floating-point comparison operations in parallel and obtain a 16-bit Boolean operation result. Steps 2-3 are traversed with 16 bits. When using the avx256 register, it is necessary to traverse with 8 bits.

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