Test indication information generation method and device, electronic equipment and storage medium

Abstract

The invention discloses a test indication information generation method and device, electronic equipment and a storage medium, and relates to the technical field of storage, and the method comprises the steps that when a central processing unit obtains word offset position information of target data, bit offset position information can be generated based on a first preset generation rule and a preset word length, and then the word offset position information of the target data is generated; and generating a test bit number based on the bit offset position information and a preset word length, and generating data modification information according to the test bit number and a second preset generation rule. The bit offset position information, the number of test bits and the data modification information are generated based on a certain rule instead of fixed information, so that the test indication information is generated according to the word offset position information, the bit offset position information, the number of test bits and the data modification information, and then the test indication information is transmitted to the test device. Test indication information which is generated in real time and has particularity can be used for testing, and the flexibility and comprehensiveness of the test are improved.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method, device, electronic device, and storage medium for generating test indication information. Background Art

[0002] With the rapid development of information technology, the demand for data processing technology continues to grow. To improve the efficiency of the Central Processing Unit (CPU), data movement operations previously performed by the CPU can generally be offloaded to the storage controller. In some application scenarios, the storage controller also needs to perform data modification operations. To ensure that the storage controller can correctly perform data movement and modification operations, it is necessary to test the storage controller.

[0003] In current testing scenarios, fixed test instructions are typically pre-set, and the storage controller is instructed to perform data movement and modification operations based on these instructions. Finally, the modified data is read from the destination address and compared with the expected result to determine whether the storage controller performed the data movement and modification operations normally. However, using fixed test instructions results in limited test flexibility. Summary of the Invention

[0004] The present application provides a method, device, electronic device, storage medium, and program product for generating test indication information to solve the problem of poor test flexibility.

[0005] The present application provides a method for generating test indication information, which is applied to a data transmission system. The data transmission system includes a central processing unit, a storage controller, and a memory. The method is executed by the central processing unit and includes:

[0006] Acquiring word offset position information of target data, wherein the target data is any one of a plurality of data stored in the memory;

[0007] Generate bit offset position information according to a first preset generation rule and a preset word length;

[0008] Generate the number of test bits according to the bit offset position information and the preset word length;

[0009] generating data modification information according to the number of test bits and a second preset generation rule;

[0010] Test indication information is generated according to the word offset position information, the bit offset position information, the number of test bits, and the data modification information to test whether the storage controller performs modification and movement operations on the target data normally.

[0011] The present application also provides a device for generating test indication information, which is applied to a data transmission system. The data transmission system includes a central processing unit, a storage controller, and a memory. The device includes:

[0012] an acquisition module, configured to acquire word offset position information of target data, wherein the target data is any one of a plurality of data stored in the memory;

[0013] A generation module is used to generate bit offset position information based on a first preset generation rule and a preset word length; generate a test bit quantity based on the bit offset position information and the preset word length; generate data modification information based on the test bit quantity and a second preset generation rule; and generate test indication information based on the word offset position information, the bit offset position information, the test bit quantity, and the data modification information, so as to test whether the storage controller can normally modify and move the target data.

[0014] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned methods for generating test indication information when executing the computer program.

[0015] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for generating test indication information are implemented.

[0016] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned methods for generating test indication information when the computer program is executed by a processor.

[0017] Through the present application, for any data, taking the target data as an example, when the central processing unit obtains the word offset position information of the target data, it can generate bit offset position information based on a first preset generation rule and a preset word length. Then, based on the bit offset position information and the preset word length, it can generate the number of test bits. Then, based on the number of test bits and a second preset generation rule, it can generate data modification information. Because the bit offset position information, the number of test bits, and the data modification information are all generated based on certain rules rather than fixed information, after generating the test indication information based on the word offset position information, the bit offset position information, the number of test bits, and the data modification information, the test can be performed using the specific test indication information generated in real time. Furthermore, different test indication information can be used for different data, improving the flexibility of the test. Moreover, even for the same data, different test indication information can be used in multiple tests, which can improve the coverage of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic diagram of the architecture of a data transmission system provided in an embodiment of the present application;

[0020] Figure 2 A flowchart of a method for generating test indication information provided in an embodiment of the present application;

[0021] Figure 3 A flowchart of a storage controller testing method provided in an embodiment of the present application;

[0022] Figure 4 A flowchart of another storage controller testing method provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of another method for generating test indication information provided in an embodiment of the present application;

[0024] Figure 6 A schematic diagram of the structure of a device for generating test indication information provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0027] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0028] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0029] The method for generating the test indication information provided in this application can be implemented by a data transmission system. The data transmission system can be a system on chip (SoC). Figure 1 As shown, the data transmission system may include a storage controller, a memory, and a central processing unit (CPU). Alternatively, it may also include a hardware engine. Among them, the storage controller may be a direct memory access (DMA). The memory may be a memory. The various components may be connected via a bus. The storage controller and the central processing unit cooperate with each other to generate test indication information and test whether the data modification and move operations are performed normally. The relevant data flow can be referred to Figure 1 The dashed arrow in .

[0030] To enable the CPU to operate quickly and efficiently, the storage controller handles data movement, particularly large amounts of data from memory or peripherals. This frees the CPU from time-consuming data movement operations and allows it to perform more meaningful tasks, significantly improving the CPU's ability to handle requests and tasks. During storage controller verification, a common approach is to initialize the data to be moved. After the CPU configures the source address, destination address, and total data length, it starts the storage controller to execute the move. After the move is complete, a data comparison is performed to verify that the move was executed correctly.

[0031] Furthermore, the storage controller can also perform data modification operations, reading the source data into the storage controller, modifying it according to agreed-upon rules, and then moving it to the destination address. This function is particularly suitable for storing the execution commands of the hardware engine in memory. During initialization, the commands to be executed are stored in advance according to the hardware engine's working scenario. Once the hardware engine is ready, the storage controller moves the executed commands to the destination address for the hardware engine to read and execute. When the hardware engine needs to execute a different command again, it does not need to reinitialize the entire command. It only needs to modify some fields based on the existing command as required to continue working, which speeds up the hardware engine's ability to process tasks.

[0032] To verify that the storage controller can perform both modification and migration operations, manual test instructions must be constructed. The storage controller then modifies the metadata based on the test instructions before performing the migration. Current test instructions are typically fixed, unable to cover a wide range of scenarios and lacking flexibility. Furthermore, constructing test instructions for all scenarios is labor-intensive.

[0033] In order to solve the above technical problems, the embodiment of the present application provides a method for generating test indication information, which can be executed by a central processing unit, such as Figure 2 As shown, the specific processing steps of the method for generating test indication information may include:

[0034] Step S201: Obtain word offset position information of target data.

[0035] Wherein, the target data is any one of the multiple data stored in the memory. The target data can be data in a double word (Dword) format, that is, the length of the target data is the length of a double word. Generally, the length of each word can be 2 bytes, and the length of a double word is 4 bytes, that is, 32 bits. The word offset position information can generally be represented by a dword offset.

[0036] Specifically, the length of each data stored in the memory is fixed and can be a preset word length (i.e., the length of the double word mentioned above). A test process can generally be a test for a group of data, and each group of data can include multiple data. When the central processing unit obtains the pre-specified source address, destination address, and total data length (which can be less than or equal to 1024 bytes), it can determine the word offset position information corresponding to each data to be tested based on the source address, preset word length, and total data length. Specifically, it can be that the source address is used as the starting address, and the preset initial value (for example, it can be 0) is determined as the word offset position information of the first data, and the word offset position information of the non-first data can be the product of the preset word length and the number of the non-first data. The data number can start with 0 and increase by 1 in sequence, and the maximum number is the ratio of the total data length to the preset word length minus 1. The target data can be the above-mentioned first data, or any non-first data.

[0037] In some optional embodiments, a test process may also be a test for a piece of data. Accordingly, the central processing unit may directly obtain pre-specified word offset position information, or randomly select an integer as a target number and use the product of the target number and the preset word length as the word offset position information.

[0038] Step S202: Generate bit offset position information according to a first preset generation rule and a preset word length.

[0039] The first preset generation rule may be a random generation rule, for example, a random function rand().

[0040] Specifically, the central processing unit may randomly generate a value (referred to as a third random number) using a first preset generation rule, and use a preset word length as a first modulus. Furthermore, the central processing unit may perform a modulo operation on the third random number based on the first modulus to obtain a first value, and determine the first value as the bit offset position information.

[0041] For example, step S202 may adopt the following mathematical expression:

[0042] bitoffset=rand()%L1(1)

[0043] Among them, bitoffset is the bit offset position information, rand() is the first preset generation rule, and L1 is the preset word length.

[0044] This modulo operation ensures that the bit offset position information always remains within the range [0, L1-1], preventing out-of-bounds access and improving system stability. Furthermore, regardless of how L1 is adjusted (e.g., due to different hardware configurations or protocol versions), the offset value remains valid, eliminating the need for additional validation logic. Furthermore, this solution requires only the use of random functions and modulo operations, eliminating the need for complex algorithms. This approach is highly efficient and suitable for resource-constrained environments. Furthermore, the bit offset position information generated each time is unique, providing increased flexibility.

[0045] Step S203: Generate the number of test bits according to the bit offset position information and the preset word length.

[0046] Specifically, because the sum of the offset position of the field to be modified in the target data and the number of test bits cannot be greater than the preset word length, the central processing unit can first randomly generate a value (referred to as a fourth random number) based on the first preset generation rule described above, and determine a second modulus based on the preset word length and bit offset position information. Furthermore, the central processing unit can perform a modulus operation on the fourth random number based on the second pattern to obtain a second value, which is determined as the number of test bits.

[0047] For example, step S203 can be calculated using the following mathematical expression:

[0048] bitnum=rand()%(L1+1-bitoffset)(2)

[0049] Among them, bitnum is the number of test bits, rand() is the first preset generation rule, L1 is the preset word length, and bitoffset is the bit offset position information.

[0050] Step S204: Generate data modification information according to the number of test bits and a second preset generation rule.

[0051] The second preset generation rule may include a random generation rule, a preset value, and a preset initial variable. The random generation rule may be the random function mentioned above, and the preset value may be 1.

[0052] Specifically, to ensure the validity of the data modification information, the central processing unit may set a preset initial variable based on the number of test bits, and then obtain the data modification information by calculating the set data with the randomly generated data. Accordingly, step S204 may specifically include the following steps:

[0053] Step 1: Generate a first intermediate variable according to the number of test bits, a preset value, and a preset initial variable.

[0054] Step 2: Generate a first random number based on a random generation rule.

[0055] Step three: Generate data modification information based on the first random number and the first intermediate variable.

[0056] Specifically, the central processing unit can determine the same number of low-order values ​​as the number of test bits in the preset initial variable based on the number of test bits, and set all the low-order values ​​to the preset values. For example, when the number of test bits is 3 and the preset value is 1, the low-order 3 bits in the first intermediate variable can be all set to 1, and the low-order bits to the high-order bits can be from the left to the right of the binary number. The relevant code can be as follows:

[0057] "for(i=0;i <bit_num;i++)

[0058] {

[0059] temp_sec_val1|=(1< <i);

[0060] }”

[0061] Among them, bit_num is the number of test bits, and temp_sec_val1 is the first intermediate variable.

[0062] Furthermore, in order to make the data modification information flexible, the central processing unit may randomly generate a value based on a random generation rule. For example, the following mathematical expression may be used:

[0063] rand val=rand()(3)

[0064] Among them, rand val is the first random number, and rand() is the random generation rule.

[0065] Finally, the central processing unit can perform a bitwise AND operation on the first intermediate variable with validity and the first random number with randomness to generate data modification information. For example, the following mathematical expression can be used:

[0066] sec_val=rand_val&temp_sec_val1(4)

[0067] Among them, sec_val is data modification information, rand val is the first random number, and temp_sec_val1 is the first intermediate variable.

[0068] Step S205 , generating test indication information according to the word offset position information, the bit offset position information, the number of test bits, and the data modification information.

[0069] Specifically, the central processing unit can generate test position information based on the word offset position information, the bit offset position information, and the number of test bits, and store the test position information in a first storage area in the memory, and store the data modification information in a second storage area in the memory. The central processing unit can obtain the starting address of the first storage area as the first starting address, and obtain the starting address of the second storage area as the second starting address. Then, the first starting address is stored in the first register, and the second starting address is stored in the second register. Finally, the identification information of the first register and the identification information of the second register are sent to the storage controller, so that the storage controller can read the corresponding starting address from the register based on the identification information of the register, and then read the test position information and data modification information based on the starting address.

[0070] For example, the test position information may be expressed as sec_mask, the format of which may refer to Table 1.

[0071] Table 1

[0072] Bit width name [31:19] Preserve field information [18:11] Word offset position information [10:6] Bit offset position information [5:0] Number of test bits

[0073] Among them, the first column of Table 1 indicates the position of the corresponding information in the test position information, and the second column indicates the name of the corresponding information. The length of the test position information of each data can be a preset word length, such as the above-mentioned 32 bits. The number of test bits occupies the 0th to 5th bits of the test position information (length 6 bits), the bit offset position information occupies the 6th to 10th bits of the test position information (length 5 bits), the word offset position information occupies the 11th to 18th bits of the test position information (length 8 bits), and the reserved field information occupies the 19th to 31st bits of the test position information (length 13 bits) for expanding other functions.

[0074] The format of data modification information can be found in Table 2.

[0075] Table 2

[0076] bit width name [31:0] Data modification information

[0077] The length of the data modification information corresponding to each data may be a preset word length, such as the aforementioned 32 bits.

[0078] For the above-mentioned test location information and data modification information, by defining multiple field information in one dword, the operation is efficient and memory space can be saved.

[0079] Furthermore, the central processing unit can initiate a task notification (for example, it can be an enable signal) to the storage controller. After receiving the task notification, the storage controller can read the target data from the memory, and based on the first starting address read from the first register, read the test location information of the target data, and based on the second starting address read from the second register, read the data modification information of the target data. Then, the storage controller can determine the modification field in the target data based on the test location information, and then modify the modification field based on the data modification information, while other fields remain unchanged. After the modification is completed, the modified target data is stored in the memory based on the destination address. Finally, the central processing unit can determine whether the storage controller has performed the modification and move operations on the target data normally by judging whether the modified target data is consistent with the expected data. For specific processing, please refer to steps S301 to S304 below, which will not be repeated here.

[0080] In some optional implementations, there are multiple data transmission channels between the storage controller and the memory. Therefore, before the storage controller performs data modification and transfer operations, it is necessary to first configure the channels to be tested. Accordingly, the central processing unit may perform the following specific steps:

[0081] Step 1: Get the identification information of the channel to be tested.

[0082] Specifically, the central processing unit may first obtain a channel identification information range, and then, based on the above-mentioned first preset generation rule, randomly select a channel identification information within the channel identification information range as the identification information of the channel to be tested.

[0083] Alternatively, the central processing unit may also obtain the current timestamp and determine the identification information of the channel to be tested based on the current timestamp and the number of channels. Determining the identification information of the channel to be tested based on the current timestamp and the number of channels may include:

[0084] Step 1: Generate the target sequence based on the current timestamp and the preset function.

[0085] The target sequence includes multiple values. The preset function may be srand(unsigned int).

[0086] Step 2: Randomly select a value in the target sequence as the second random number.

[0087] Step 3: Determine identification information of the channel to be tested based on the second random number and the number of channels.

[0088] Specifically, the central processing unit can use the current timestamp as the random number seed of the preset function to generate the target sequence. Then, based on the first preset generation rule, the central processing unit randomly selects a value in the target sequence as the second random number. Finally, the central processing unit can use the number of channels as the third modulus to perform a modulus operation on the second random number to obtain a third value, and determine the third value as the identification information of the channel to be tested. For example, the following data expression can be used:

[0089] chx=rand()%N(5)

[0090] Wherein, chx is the identification information of the channel to be tested, rand() is the first preset generation rule, and N is the number of channels.

[0091] In this way, through double-layer randomization, that is, the first layer of randomization is to generate the target sequence through the timestamp to ensure the unpredictability of the sequence itself, and the second layer of randomization is to randomly select values ​​from the target sequence, which greatly improves the randomness of the identification information of the channel to be tested.

[0092] Since the total data length varies in different tests, a target sequence may be generated based on the total data length and a preset function.

[0093] Step 2: Based on the identification information of the channel to be tested, the data transmission channel corresponding to the identification information of the channel to be tested is set as the channel to be tested, so that the storage controller can modify and move the target data through the channel to be tested.

[0094] Specifically, after determining the identification information of the channel to be tested, the central processing unit can configure the data transmission channel between the storage controller and the memory based on the identification information of the channel to be tested. Specifically, it can open the data transmission channel corresponding to the identification information of the channel to be tested and close other data transmission channels. In this way, the storage controller can perform data modification and transfer operations through the configured data transmission channel.

[0095] In the method for generating test indication information in an embodiment of the present application, for any data, such as the target data, upon obtaining the word offset position information of the target data, the central processing unit can generate bit offset position information based on a first preset generation rule and a preset word length. Furthermore, based on the bit offset position information and the preset word length, the number of test bits is generated. Finally, data modification information is generated based on the number of test bits and a second preset generation rule. Because the bit offset position information, the number of test bits, and the data modification information are all generated based on certain rules rather than fixed information, after generating the test indication information based on the word offset position information, the bit offset position information, the number of test bits, and the data modification information, testing can be performed using the specific test indication information generated in real time. Furthermore, different test indication information can be used for different data, improving test flexibility. Furthermore, even for the same data, different test indication information can be used in multiple tests, improving test coverage.

[0096] The embodiment of the present application provides a storage controller testing method that can be executed by a central processing unit, such as Figure 3 As shown, the specific processing steps of the storage controller testing method may include:

[0097] Step S301: Acquire the source address and destination address.

[0098] Specifically, the source address and the destination address may be obtained in the above step S201.

[0099] Step S302 : Read the modified target data according to the destination address, the word offset position information, and the preset word length.

[0100] Specifically, the central processing unit can determine the starting storage address of the modified target data based on the destination address and the word offset position information (for example, the sum of the destination address and the word offset position information is determined as the starting storage address), and then, using the starting storage address as the starting point, read the modified target data having a length equal to the preset word length from the memory. Alternatively, the central processing unit can use the destination address as the total starting address, read the modified total data having a length equal to the total data length from the memory, and then, using the word offset position information as a sub-starting address, extract data having the preset word length from the total data as the modified target data.

[0101] Step S303: Generate expected data according to the source address, the word offset position information, the first intermediate variable, the data modification information, and the bit offset position information.

[0102] Specifically, in order to improve the efficiency and accuracy of the test, the central processing unit may first read the target data, and then directly obtain the corresponding expected data after performing relevant calculations based on the above-mentioned test indication information and the target data. Accordingly, step S303 may include:

[0103] Step 1: Read the target data according to the source address, word offset position information, and preset word length.

[0104] Step 2: Generate a second intermediate variable based on the first intermediate variable and the bit offset position information.

[0105] Step three: Generate expected data based on the target data, the second intermediate variable, the data modification information, and the bit offset position information.

[0106] Specifically, the CPU can first determine the starting storage address of the target data based on the source address and word offset position information, and then, using the starting storage address as a starting point, read data of a length equal to the preset word length from the memory as the target data. Alternatively, the CPU can use the source address as the total starting address, read a total data of a length equal to the total data length from the memory, and then, using the word offset position information as a sub-starting address, extract data of the preset word length from the total data as the target data.

[0107] Then, the central processing unit can left-shift the binary value of the first intermediate variable by the number of bits corresponding to the bit offset position information to obtain the second intermediate variable. For example, the following expression can be used:

[0108] temp_sec_val2=temp_sec_val1< <bit_offset (6)

[0109] Among them, temp_sec_val1 is the first intermediate variable, and temp_sec_val2 is the second intermediate variable.

[0110] The central processing unit can first invert each bit in the binary value of the second intermediate variable (i.e., 0 becomes 1, 1 becomes 0) to obtain a third intermediate variable, so as to be used to clear the bit corresponding to the second intermediate variable in the target data. Afterwards, the central processing unit can perform a bitwise AND operation on the third intermediate variable and a preset mask (whose length is equal to the preset word length) to obtain a first operation result to ensure that the final generated result is an unsigned integer of the same length as the preset word length. Further, a bitwise AND operation is performed on the target data and the first operation result to obtain a second operation result, so as to clear the bit corresponding to the second intermediate variable in the target data and retain the other bits. The central processing unit can use the numerical value corresponding to the bit offset position information as the number of left shift bits, and left-shift the value of the data modification information to obtain a third operation result, so as to free up the bit of the modification position. Finally, the central processing unit performs a bitwise OR operation on the second operation result and the third operation result to obtain the expected data.

[0111] For example, step three can be expressed as follows:

[0112] finaldata=(sourcedata&(0xffffffff&(~temp_sec_val2)))|(sec_val< <bitoffset)(7)

[0113] Among them, finaldata is the expected data, sourcedata is the source data (the source data here can be the target data mentioned above, that is, the target data that has not been modified and moved), 0xffffffff is the preset mask, temp_sec_val2 is the second intermediate variable, sec_val is the data modification information, and bit offset is the bit start information.

[0114] The above formula can be used to perform calculations simply and quickly, which is more convenient.

[0115] Alternatively, the central processing unit may also modify the read target data according to the test position indication information and the modification data, and obtain the modified data as the expected data.

[0116] Step S304: Determine whether the storage controller performs modification and migration operations on the target data normally based on the expected data and the modified target data.

[0117] Specifically, after the central processing unit determines the expected data and reads the modified target data, it can determine whether the expected data is equal to the modified target data. If so, it can be determined that the storage controller has performed the modification and move operations on the target data normally. If not, it can be determined that the storage controller has not performed the modification and move operations on the target data normally.

[0118] Alternatively, the central processing unit may also perform a bit-by-bit comparison operation on the binary number of the expected data and the binary number of the modified target data to determine whether each bit in the expected data is consistent with the corresponding bit in the modified target data. If so, the comparison result of the bit is determined to be passed; if not, the comparison result of the bit is determined to be failed. In this way, after comparing each bit, if there is a bit that fails the comparison result, it can be determined that the storage controller did not modify and move the target data normally, and the bit identification information that failed is recorded for subsequent analysis operations. If the comparison results of all bits are passed, it can be determined that the storage controller modified and moved the target data normally. Through refined comparison, not only can it be accurately tested whether the storage controller modified and moved the target data normally, but it can also facilitate subsequent analysis of the cause of the error.

[0119] In the storage controller testing method of an embodiment of the present application, after using the test instruction information generated by the above method to modify and move data, the storage controller can calculate and generate accurate expected data based on the content of the test instruction information. Furthermore, by comparing the expected data with the read modified data, it is possible to test whether the storage controller has properly modified and moved the target data. Accordingly, for different data, different test locations and modified contents are different, which can greatly improve the comprehensiveness and accuracy of the test.

[0120] The following describes in detail the execution process of the above-mentioned method for generating test indication information using a specific example.

[0121] like Figure 4 As shown, after the system on chip is powered on and reset, the central processing unit can enable the clock of the memory controller and prepare for subsequent generation of test indication information and performing test operations.

[0122] When there are multiple channels for data transmission between the storage controller and the memory, for example, the number of channels is N, and the starting identification information of the data transmission channel is 0, the C language library function rand() can be used to randomly generate a random number between 0 and N-1 as the identification information of the channel to be tested. Alternatively, since the random number generated by the C language library function rand() is a pseudo-random number, in order to further improve the randomness, the current timestamp can be obtained first, and then the current timestamp can be used as the random number seed of the C language library function srand(unsigned int), and then the identification information of the channel to be tested can be determined using mathematical expression (5). The central processing unit can configure the data transmission channel corresponding to the identification information of the channel to be tested as the channel to be tested, so that the subsequent storage controller can perform data transmission operations through the data transmission channel.

[0123] The CPU obtains the pre-specified source address, destination address, total data length, and identification information for the first and second registers, and sends them to the memory controller. The first register can be used to store the starting address of the storage location where the test location information is located, and the second register can be used to store the starting address of the storage location where the data modification information is located. Each test location information corresponds to a piece of data modification information, and the two pieces of data are stored in memory in a one-to-one correspondence, in DWord order.

[0124] The CPU can determine multiple dword offsets according to step S201. Then, for each dwordoffset, the CPU can generate a random sec_val and sec_mask, such as Figure 5 As shown, the process includes: first generating a random bit offset (for a specific generation method, refer to step S202 above) and a random bit num (for a specific generation method, refer to step S203 above). Further, generating a first intermediate variable temp_sec_val1 based on bit num (for a specific generation method, refer to step 1 in step S204 above). After generating any random number, generating the final sec_val based on the random number and the first intermediate variable temp_sec_val1 (for a specific generation method, refer to step 3 in step S204 above). Based on the randomly generated bit offset, bit num, and sec_val, the final modified data is calculated (for a specific generation method, refer to step S303 above).

[0125] After generating the random sec_val and sec_mask, the CPU checks whether the storage controller's buffer is full. For example, the buffer can be a First In First Out (FIFO) area. If so, it waits 1 μs before continuing to check whether the buffer is full, and proceeds to the next step when it detects that it is not full. If not, the storage controller's interrupt reporting mode is configured to be unmasked, so that after completing data modification and transfer operations, the storage controller interrupts and notifies the CPU for further processing. The CPU can then enable the storage controller to perform data modification and transfer operations.

[0126] The storage controller can read the source data dword1 from the corresponding position in the memory (the specific reading method can refer to step 1 in the above step S303). And, read the first starting address for storing sec_mask from the first register, and read the second starting address for storing sec_val from the second register. Further, the storage controller can read the sec_mask1 corresponding to dword1 from the memory based on the first starting address, word offset position information, and preset word length (the specific reading method can refer to step 1 in the above step S303), and, based on the second starting address, word offset position information, and preset word length, read the sec_val1 corresponding to dword1 (the specific reading method can refer to step 1 in the above step S303). The storage controller can determine the modification position in dword1 based on sec_mask1, and modify the value of the modification position based on sec_val1. Finally, the storage controller determines the first storage address based on the destination address and word offset position information (for example, summing the destination address and word offset position information), uses the first storage address as the starting address, and stores the modified dword1 in the memory. Alternatively, when the memory controller obtains the modified total data, it uses the destination address as the starting address and stores the modified total data in the memory. After completing the modification and move operations of all Dwords, the memory controller can set the status value of its own status register to the target value.

[0127] The central processing unit can check the status value of the status register of the storage controller at a period of 1us, and determine whether the storage controller has completed the data modification and transfer operation based on the status value, for example, determine whether the status value is the target value. If so, the central processing unit can read the modified dword1 from the corresponding position in the memory (the specific reading method can refer to the above step S302). If not, the status value can continue to be read from the status register according to the above cycle until it is determined that the status value is the target value, and then the modified dword1 is read from the corresponding position in the memory.

[0128] The central processing unit can use the above mathematical expression (6) and the first intermediate variable corresponding to dword1 to calculate the second intermediate variable corresponding to dword1, and then use mathematical expression (7), sec_mask1, sec_val1, and the second intermediate variable corresponding to dword1 to calculate the modified expected data corresponding to dword1 (i.e., final data1).

[0129] The CPU can compare final_data1 corresponding to dword1 with the modified dword1 to see if they are consistent. If they are consistent, it is determined that the storage controller correctly executed the data modification and move operations. If they are inconsistent, it is determined that the storage controller did not correctly execute the data modification and move operations (for specific analysis steps, please refer to step S304 above). Furthermore, the CPU can count the number of dwords that were correctly modified and moved during a test to indicate the degree of abnormality of the storage controller, so that technicians can analyze and make improvements.

[0130] Based on the above test method, different dwords can correspond to random sec_mask and sec_val during a test, so that the modification position and modification value have greater flexibility, thereby improving the accuracy of the test.

[0131] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0132] The embodiment of the present application also provides a device for generating test indication information, such as Figure 6 Shown, including:

[0133] An acquisition module 610 is configured to acquire word offset position information of target data, wherein the target data is any one of a plurality of data stored in the memory;

[0134] The generation module 620 is used to generate bit offset position information according to a first preset generation rule and a preset word length; generate the number of test bits according to the bit offset position information and the preset word length; generate data modification information according to the number of test bits and a second preset generation rule; and generate test indication information according to the word offset position information, the bit offset position information, the number of test bits, and the data modification information, so as to test whether the storage controller can normally modify and move the target data.

[0135] In some optional implementations, the target data includes a multi-digit value, and the generation module 620 is specifically configured to:

[0136] Generate a first intermediate variable according to the number of test bits, a preset value, and a preset initial variable;

[0137] Generate a first random number based on a random generation rule;

[0138] Data modification information is generated according to the first random number and the first intermediate variable.

[0139] In some optional embodiments, the device further includes a testing module 630 for:

[0140] Get the source and destination addresses;

[0141] Read the modified target data according to the destination address, word offset position information, and preset word length;

[0142] Generate expected data according to the source address, the word offset position information, the first intermediate variable, the data modification information, and the bit offset position information;

[0143] Based on the expected data and the modified target data, it is determined whether the storage controller performs modification and migration operations on the target data normally.

[0144] In some optional implementations, the testing module 630 is specifically configured to:

[0145] Read the target data according to the source address, word offset position information, and preset word length;

[0146] generating a second intermediate variable according to the first intermediate variable and the bit offset position information;

[0147] Expected data is generated according to the target data, the second intermediate variable, the data modification information, and the bit offset position information.

[0148] In some optional implementations, the acquisition module 610 is further configured to:

[0149] When there are multiple data transmission channels between the storage controller and the memory, obtaining identification information of the channel to be tested;

[0150] Based on the identification information of the channel to be tested, the data transmission channel corresponding to the identification information of the channel to be tested is set as the channel to be tested, so that the storage controller performs data modification and movement operations on the target data through the channel to be tested.

[0151] In some optional implementations, the acquisition module 610 is specifically configured to:

[0152] Get the current timestamp;

[0153] Determine the identification information of the channel to be tested based on the current timestamp and the number of channels.

[0154] In some optional implementations, the acquisition module 610 is specifically configured to:

[0155] Generate a target sequence based on a current timestamp and a preset function, wherein the target sequence includes multiple numerical values;

[0156] Randomly select a value in the target sequence as the second random number;

[0157] Based on the second random number and the number of channels, identification information of the channel to be tested is determined.

[0158] For the description of the features in the embodiment corresponding to the device for generating test indication information, reference can be made to the relevant description of the embodiment corresponding to the method for generating test indication information, which will not be repeated here.

[0159] The embodiment of the present application also provides an electronic device, such as Figure 7 As shown, the electronic device includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to execute the computer program to perform the steps of any of the above-mentioned test instruction information generation method embodiments. The electronic device can be the above-mentioned system-on-chip. The processor 20 can be the above-mentioned central processing unit, and the memory 10 can be a storage component in the system-on-chip for storing relevant test instructions (i.e., the computer program).

[0160] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned test indication information generation method embodiments when running.

[0161] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0162] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned test indication information generation method embodiments are implemented.

[0163] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned test indication information generation method embodiments.

[0164] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0165] The above is a detailed introduction to the method, device, electronic device, storage medium, and program product for generating test indication information provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A method for generating test indication information, characterized in that: The method is applied to a data transmission system, the data transmission system including a central processing unit, a storage controller, and a memory. The method is executed by the central processing unit and includes: Acquiring word offset position information of target data, wherein the target data is any one of a plurality of data stored in the memory; Generate bit offset position information according to a first preset generation rule and a preset word length; generating a test bit quantity according to the bit offset position information and the preset word length; generating data modification information according to the number of test bits and a second preset generation rule; Test indication information is generated according to the word offset position information, the bit offset position information, the number of test bits, and the data modification information to test whether the storage controller performs modification and movement operations on the target data normally.

2. The method for generating test instruction information according to claim 1, wherein: The target data includes a multi-digit value, and the second preset rule includes a preset value, a preset initial variable, and a random generation rule; generating data modification information according to the number of test bits and the second preset generation rule includes: Generate a first intermediate variable according to the number of test bits, the preset value, and the preset initial variable; Based on the random generation rule, generate a first random number; The data modification information is generated according to the first random number and the first intermediate variable.

3. The method for generating test instruction information according to claim 2, wherein: The method further comprises: Get the source and destination addresses; Reading the modified target data according to the destination address, the word offset position information, and the preset word length; Generate expected data according to the source address, the word offset position information, the first intermediate variable, the data modification information, and the bit offset position information; According to the expected data and the modified target data, it is determined whether the storage controller performs modification and movement operations on the target data normally.

4. The method for generating test instruction information according to claim 3, wherein: Generating expected data according to the source address, the word offset position information, the first intermediate variable, the data modification information, and the bit offset position information includes: Reading the target data according to the source address, the word offset position information, and the preset word length; generating a second intermediate variable according to the first intermediate variable and the bit offset position information; The expected data is generated according to the target data, the second intermediate variable, the data modification information, and the bit offset position information.

5. The method for generating test instruction information according to any one of claims 1 to 4, characterized in that: The method further comprises: When there are multiple data transmission channels between the storage controller and the memory, obtaining identification information of the channel to be tested; Based on the identification information of the channel to be tested, a data transmission channel corresponding to the identification information of the channel to be tested is set as the channel to be tested, so that the storage controller performs data modification and movement operations on the target data through the channel to be tested.

6. The method for generating test instruction information according to claim 5, characterized in that: When there are multiple data transmission channels between the storage controller and the memory, obtaining identification information of the channels to be tested includes: Get the current timestamp; Determine identification information of the channel to be tested according to the current timestamp and the number of channels.

7. The method for generating test instruction information according to claim 6, wherein: The determining, according to the current timestamp and the number of channels, identification information of the channel to be tested includes: Generate a target sequence based on the current timestamp and a preset function, wherein the target sequence includes a plurality of numerical values; Randomly selecting a value in the target sequence as a second random number; Based on the second random number and the number of channels, identification information of the channel to be tested is determined.

8. A device for generating test instruction information, characterized in that: The device is applied to a data transmission system, which includes a central processing unit, a storage controller, and a memory. The device includes: an acquisition module, configured to acquire word offset position information of target data, wherein the target data is any one of a plurality of data stored in the memory; A generation module is used to generate bit offset position information based on a first preset generation rule and a preset word length; generate a test bit quantity based on the bit offset position information and the preset word length; generate data modification information based on the test bit quantity and a second preset generation rule; and generate test indication information based on the word offset position information, the bit offset position information, the test bit quantity, and the data modification information, for testing whether the storage controller normally performs modification and movement operations on the target data.

9. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the method for generating test indication information according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method for generating test instruction information according to any one of claims 1 to 7 are implemented.

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