Data management method and device, medium and product

Abstract

The invention discloses a data management method and device, a medium and a product, and relates to the technical field of computers, when data of a program operated on a certain processor core needs to be inserted into a shared cache, data belonging to different application programs are placed at positions with different priorities according to the types of the application programs. It is ensured that the shortest time for the data to stay in the private cache is that the data travels from the highest priority position matched with the processor core to which the data belongs to to the lowest priority position, and the intermediate process is not accessed again. Furthermore, the storage time of the data blocks with higher hit rate in the cache system is longer, so that the overall hit rate of the cache system is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data management method, device, medium, and product. Background Art

[0002] The inclusive cache system in multi-core processors occupies a certain share in the multi-core processor market because it can effectively reduce the amount of cache consistency communication data.

[0003] However, when an inclusive cache system replaces a piece of data in the shared cache, it needs to simultaneously process the corresponding data in the private cache to meet the inclusive requirements; and if the data is accessed frequently, it will cause a cache miss, thereby affecting the performance of the overall cache system.

[0004] Therefore, there is an urgent need for a data management method that can improve the cache hit rate while meeting the inclusive requirements to solve the above technical problems. Summary of the Invention

[0005] The present application provides a data management method, device, medium and product to at least solve the problems in the related art.

[0006] This application provides a data management method, including: In response to receiving a data access request initiated by a target processor core, obtaining an access data block matching the data access request; Trigger cache replacement operations based on the access data blocks and the data distribution characteristics of the cache system: Determining a target replacement data block based on cached data blocks in a preset cache interval in the shared cache and cached data blocks in the private cache; Insert the access data block to the target insertion position matching the target processor core and delete the target replacement data block.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned data management methods when executing the computer program.

[0008] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned data management methods are implemented.

[0009] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned data management methods when executed by a processor.

[0010] In the data management method disclosed in this application, when data from a program running on a processor core needs to be inserted into a shared cache, data belonging to different applications is placed in locations of different priorities based on the application category. This ensures that the shortest time data stays in the private cache is the time it takes for the data to move from the highest priority location matching the processor core to which the data belongs to to the lowest priority location without being accessed again in the middle. This further allows data blocks with a higher hit rate to remain in the cache system for a longer period of time, thereby improving the overall hit rate of the cache system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A flow chart of a data management method provided in an embodiment of the present application; Figure 2 A schematic diagram of traditional data management provided in an embodiment of the present application; Figure 3 A data management diagram provided in an embodiment of the present application; Figure 4 A schematic diagram of an insertion position provided in an embodiment of the present application; Figure 5 A schematic diagram of a cache system storage provided in an embodiment of the present application; Figure 6 A schematic diagram of cache system storage after cache replacement provided in an embodiment of the present application; Figure 7 A data management system architecture diagram provided in an embodiment of the present application; Figure 8 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0014] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0015] As discussed in the background technology disclosure, the cache system within a processor chip is used to store frequently accessed instructions and data, reducing access to off-chip main memory and playing a crucial role in improving system performance. Cache systems typically feature a multi-layered architecture, such as a typical three-layer architecture. The first and second level caches closest to the target processor core are private to the target processor core, known as private caches. The final level, the third level cache, is shared by multiple target processor cores within the processor chip, known as shared caches.

[0016] Based on the data inclusion relationship between the private and shared caches, cache systems are divided into three categories: inclusive cache, non-inclusive cache, and mutually exclusive cache. Inclusive caches require that the data in the private cache must be a subset of the shared cache data. That is, data in the private cache can be found in the shared cache, and data not in the shared cache will definitely not be stored in the private cache. Non-inclusive caches do not require that the data in the private cache must be a subset of the shared cache data. Mutually exclusive caches require that data in the private cache is not included in the shared cache, and vice versa.

[0017] Compared to other types, inclusive caching has both advantages and disadvantages. The advantage is that it effectively reduces the amount of cache coherence communication. For example, if data is determined not to be in the shared cache, there is no need to search the private cache. However, the disadvantage is that the overall cache hit rate is low. This is because when the shared cache replaces a piece of data from its cache space, if the data still exists in the private cache, it must be invalidated in the private cache to meet the inclusive requirement. If this data is frequently accessed and is subsequently accessed, a cache miss will occur, affecting system performance.

[0018] The solution of the existing technical solution is as follows: the shared cache no longer directly determines the target data block to be replaced, but determines multiple data blocks to be replaced; then the target private cache is selected based on the multiple data blocks to be replaced, and the target private cache selects the target data block to be replaced from the multiple data blocks to be replaced. By handing over the operation of selecting the target replacement data block originally performed by the shared cache to the target private cache for execution, it can be avoided that the shared cache cannot know the hotness of each cache block in each private cache, resulting in the invalidation of the hot cache blocks in the private cache, and the number of times the hot cache blocks in the private cache are invalidated is reduced, so that the cache hit rate of the cache system is improved. However, the method of determining the data block to be replaced in the existing technology is unreasonable. Since the data block to be replaced is determined by the private cache from the data blocks to be replaced it contains, it will inevitably cause a data block in the private cache to be invalidated. In addition, the existing technical solutions do not take into account the memory access characteristics of applications running on different target processor cores. Some applications have good locality in memory access, and the accessed data will be accessed again in a short period of time. Keeping this data block in the cache is beneficial to improving the cache hit rate; while some applications have one-time memory access, that is, the data is only used once and will not be accessed again. Keeping this data block in the cache is not conducive to improving the cache hit rate, so it wastes cache space.

[0019] Therefore, facing the inclusive cache system in a multi-core processor, improving the cache hit rate while ensuring the inclusive cache requirements has become an urgent problem that needs to be solved.

[0020] The embodiment of the present application provides a data management method that, under the premise of meeting the requirements of inclusive cache, takes into account the memory access characteristics of programs running on different processor cores, ensures the rationality of storing data blocks in the cache system, and improves the hit rate of the overall cache system. Figure 1 As shown, the method disclosed in the embodiment of the present application is applied to manage data blocks in the cache system, including: S100 : In response to receiving a data access request initiated by a target processor core, obtaining an access data block matching the data access request.

[0021] The data management method disclosed in this application is applied to an inclusive cache system in a multi-processor. The inclusive cache system includes a private first-level cache and a second cache (i.e., a private cache) for each processor core, and a shared cache. Existing methods for inclusive cache systems propose that when a shared cache needs to replace a data block, several data blocks with the lowest access frequency in the shared cache are identified as candidate data blocks to be replaced; then the number of data blocks to be replaced contained in the private cache of each processor core is determined, and the private cache of the processor core containing the largest number of data blocks to be replaced is identified as the target private cache; the target private cache then determines the final data block to be replaced from the data blocks to be replaced it contains, and the information is then sent down level by level until it reaches the shared cache; the shared cache receives the final data block information to be replaced and then performs the replacement operation. However, the data block to be replaced ultimately determined by this processing scheme is not reasonable, and may cause a valid data block in the private cache to be set to invalid.

[0022] It is understood that if data access requests are received simultaneously from multiple target processor cores, they can be responded to concurrently or in a sequential order to perform data feedback and data replacement. To conserve computing resources, operations corresponding to multiple data access requests received within a certain period can be consolidated and then managed accordingly. Of course, to ensure efficient responses, data access requests can also be processed immediately. This application does not impose any limitations on this.

[0023] S200: triggering a cache replacement operation based on the access data block and data distribution characteristics of the cache system.

[0024] The data distribution characteristics include cached data blocks and cache occupancy status. Specifically, the cache replacement operation is triggered based on the data distribution characteristics of the accessed data blocks and the cache system, including: If there is a cached data block that matches the access data block in the cache system, the cached data block is fed back in response to the data access request. That is, the access data block hits in the cache system, and the corresponding data block information can be directly fed back to the target processor core that initiates the data access request. If there is no cached data block that matches the access data block in the cache system, it is determined whether to trigger a cache replacement operation based on the cache occupancy status of the shared cache. It can be understood that when the access data block does not hit the cache system, the method disclosed in the embodiment of the present application obtains the corresponding access data block from the main memory and sends it to the corresponding target processor core in a timely manner; at the same time, the corresponding access data block is inserted into the shared cache, and further judged whether a cache replacement operation needs to be triggered based on the cache occupancy status of the shared cache.

[0025] Furthermore, the above-mentioned determination of whether to trigger a cache replacement operation based on the cache occupancy status of the shared cache includes: in response to detecting that the cache occupancy status of the shared cache is a full state, triggering a cache replacement operation; in response to detecting that the cache occupancy status of the shared cache is a non-full state, inserting the access data block to the target insertion position that matches the target processor core. At this time, there is any free position in the shared cache to meet the storage requirements of the access data block, and there is no need to trigger a cache replacement operation.

[0026] The embodiment of the present application sets trigger conditions, i.e., corresponding multi-level logical judgment steps, while ensuring timely data feedback; it ensures that the cache replacement operation is triggered only when the accessed data block does not hit the cache system and the shared cache is full, thereby saving cache system computing resources.

[0027] Furthermore, since different processor cores run different applications, there's no connection between them, and no data is shared. Theoretically, the probability of one processor core accessing data that exists in another core's private cache is small, but not absolute. Therefore, to improve the accuracy of data block replacement and further ensure the stability of the cache system, this application addresses this extreme scenario by proposing the following actions upon detecting the presence of a cached data block matching the accessed data block: If the cached data block that matches the accessed data block belongs to the private cache and belongs to the target processor core, the cached data block is fed back to respond to the data access request. If the cached data block that matches the accessed data block belongs to the private cache but belongs to a non-target processor core, the data state of the cached data block is set to an invalid state in the non-target processor core and the cached data block is fed back to the target processor core to respond to the data access request. If the cached data block that matches the accessed data block belongs to the shared cache, the cached data block is fed back to the target processor core to respond to the data access request. That is, by further determining the cache type that is hit and triggering the corresponding operation, in the above extreme scenario, the corresponding data block in the private cache of the non-target processor core is transferred to the target processor core, ensuring that the processor core's request is responded to while avoiding the problem of low cache system performance caused by duplicate storage.

[0028] It is understandable that in traditional data management methods, no distinction is made as to which processor core the data belongs to, and access to data blocks is usually placed at the highest priority position, such as Figure 2 The data management method disclosed in this application proposes that when the data of a program running on a certain processor core needs to be inserted into the shared cache, the data belonging to different applications are placed in positions with different priorities according to the types of the applications, such as Figure 3As shown. When the shared cache is full and data replacement is required, the cache usually selects data blocks from low-priority locations for replacement. Data with lower hit rates are no longer placed in the highest-priority location, which can slow down the replacement of high-hit-rate data and improve the overall cache hit rate. When the data is accessed again, it will be promoted to the highest-priority location that matches the processor core. Therefore, the shortest time that data stays in the private cache is when the data moves from the highest-priority location that matches the processor core to which the data belongs to the lowest-priority location, and is not accessed again in the middle. This ensures that data blocks with higher hit rates are stored in the cache system for a longer time, thereby improving the overall hit rate of the cache system.

[0029] Specifically, the above step S200 includes: S210 : Determine a target replacement data block based on cached data blocks in a preset cache interval in the shared cache and cached data blocks in the private cache.

[0030] Specifically, the preset cache interval is determined by the fourth insertion position and the lowest priority position in the shared cache. The determination of the fourth insertion position is described in detail below and is omitted here. The above-mentioned determination of the target replacement data block based on the cached data blocks in the first cache interval in the shared cache and the cached data blocks in the private cache includes: A data block matching operation is performed to select a first cached data block from the cached data blocks in the preset cache interval for comparison with the cached data blocks in the private cache; in response to not detecting that the first cached data block is duplicated with the cached data blocks in the private cache, the first cached data block is determined to be the target replacement data block; in response to detecting that the first cached data block is duplicated with the cached data block in the private cache, the data block matching operation is repeatedly performed until all cached data blocks in the preset cache interval are traversed. In response to detecting that the first cached data block is duplicated with the cached data block in the private cache, whether the first cached data block is the data block with the highest priority in the preset cache interval is detected; in response to detecting that the first cached data block is the data block with the highest priority in the preset cache interval is determined to be the target replacement data block. The above-mentioned data block matching operation specifically includes selecting the first cached data block from the cached data blocks in the preset cache interval according to the order of priority from low to high; and detecting whether the first cached data block is duplicated with the cached data block in the private cache. Specifically, when a cache replacement operation is triggered, i.e., when a data block in the shared cache needs to be replaced, the current data block (i.e., the first cached data block) is sequentially determined within a preset cache interval to determine whether it still exists in the private cache of a processor core. If it does not exist in the private cache of the processor core, the data block is determined to be the target replacement data block. If the final target replacement data block is not found after traversing the preset cache interval, the data block with the highest priority within the preset cache interval is selected as the final target replacement data block. Furthermore, if it is determined that the first cached data block duplicates an already cached data block in the private cache, the first cached data block is moved to the cache insertion position that matches the first processor core to which the hit private cache belongs.

[0031] According to the above steps, when a cache replacement operation is triggered, the final target replacement data block is selected within the preset cache interval, ensuring that the data block finally replaced is data with low access efficiency, thereby improving the hit rate of the overall cache system in subsequent data access.

[0032] In order to improve the efficiency of determining whether the first data block exists in the private cache of a certain processor core, the embodiment of the present application further proposes adding n bits to each data row in the cached data block in the shared cache to identify which processor core the current data row belongs to. If the total number of processor cores in a computer system is M, then n= . When a data block matching operation is required, the processor core to be compared that matches the data block is determined based on the bit; it is detected whether the first cache data block and the data block in the processor core to be compared are repeated. If there is a cached data block in the processor core to be compared that is repeated with the first cache data block, the first cache data block is not a replaceable data block. If there is no cached data block in the processor core to be compared that is repeated with the first cache data block, the first cache data block is the final replaceable data block. By narrowing the operating range of data matching, when comparing data blocks, the bits added in the data row are used to limit a processor core that needs to be compared, without the need for broadcasting, which greatly improves the comparison efficiency, thereby improving the data block replacement efficiency of the entire cache system.

[0033] S220 , inserting the access data block to the target insertion position that matches the target processor core and deleting the target replacement data block.

[0034] Specifically, after the accessed data block is inserted into the target insertion position in the shared cache, the original data block is moved based on its positional relationship with the target insertion position. If the priority corresponding to the target insertion position is higher than the priority of the original data block, the original data block is moved one position in descending order of priority.

[0035] The method for determining the target insertion position specifically includes obtaining the target program category that matches the current running program of the target processor core, wherein the program category is determined according to a preset program classification rule; determining the target insertion position from multiple cache insertion positions according to the target program category and a preset mapping relationship table, wherein the mapping relationship table includes the relationship between the program category and the cache insertion position in the shared cache.

[0036] Among them, program categories include the first category, the second category, the third category and the fourth category. The first category represents private cache-friendly programs. Data hits of this type of program mostly occur in the private cache space of the processor core, and the memory access locality is relatively high. The second category represents shared cache-friendly programs. This type of program has medium memory access locality, and memory access data hits are distributed in the private cache and shared cache. The third category represents shared cache jitter programs, which have poor memory access locality. If a part of the data can be retained in the shared cache, there will be a hit. The fourth category represents streaming programs, which have extremely poor memory access locality and almost no data hits. It is understandable that the essence of the above four program types is to divide them according to the memory access characteristics. Specifically, if the working set is smaller than the private cache space, the program category of the corresponding application is determined to be the first category; if the private cache space is smaller than the working set, and the working set is smaller than the shared cache space, the program category of the corresponding application is determined to be the second category; if the working set is larger than the shared cache space, the program category of the corresponding application is determined to be the third category; if the working set is much larger than the shared cache space, the program category of the corresponding application is determined to be the fourth category; wherein, the working set refers to the data set accessed by the application within a certain time period. The time period is set by those skilled in the art according to the performance of the cache system, and is not limited in this application. However, the division of each program category based on the size of the working set in the previous article is a division in principle, and it is difficult to achieve accurate division in actual operation.

[0037] Therefore, on this basis, an embodiment of the present application provides a program classification rule, including: obtaining the highest non-zero bit position of the access register in the target processor core, the access register is used to record the number of data access requests initiated by the target processor core, that is, each time the register is read and written, the recorded value is increased by 1, regardless of whether it is a hit; searching for the first bit value that matches the highest non-zero bit position and the second bit value that matches the bit position after the highest non-zero bit position in the hit register in the target processor core, the hit register is used to record the number of hits of the data access request in the target processor core, and it can be determined that the value of the hit register is definitely less than the value of the access register; determining the program category according to the first bit value and the second bit value. The access register and the hit register can be set to 32-bit registers, and of course they can also be set according to the actual scenario, which is not limited in this application. The embodiment of the present application describes the access characteristics of the application running in each processor core by setting the above-mentioned access register and hit register in each processor core, thereby achieving a reasonable division of program categories and further ensuring the accuracy of the access data block insertion position determined subsequently.

[0038] Specifically, the above-mentioned determination of the program category based on the first bit value and the second bit value includes: in response to detecting that the first bit value and the second bit value are both the first preset value, determining the target program category as the first category; in response to detecting that the first bit value is the first preset value and the second bit value is the second preset value, determining the target program category as the second category; in response to detecting that the first bit value is the second preset value and the second bit value is both the first preset value, determining the target program category as the third category; in response to detecting that the first bit value and the second bit value are both the second preset value, determining the target program category as the fourth category. Preferably, the first preset value is set to 1 and the second preset value is set to 0; of course, the values ​​can also be changed according to actual conditions, and this application does not limit this.

[0039] It's understandable that when an application switches or a new application runs on a target processor core, by default during this initialization phase, the corresponding access register value for that target processor core is 2 (10b in binary), and the hit register value is 1 (01b in binary). Based on the application classification above, the default assumption is that the application falls into the third category (i.e., a shared cache jittering program). As the application executes, the values ​​of these two registers change dynamically, and consequently, the insertion position of the data belonging to this target processor core in the shared cache also changes dynamically.

[0040] In some implementation scenarios, the above-mentioned program classification rules can also determine the program category of the application running on the target processor core based on the private first-level cache hit rate of the target processor core. Specifically, in response to detecting that the first-level cache hit rate of the target processor core is greater than or equal to the high hit rate, the target program category is determined to be the first category; in response to detecting that the first-level cache hit rate of the target processor core is greater than or equal to the medium hit rate and less than the high hit rate, the target program category is determined to be the second category; in response to detecting that the first-level cache hit rate of the target processor core is greater than or equal to the low hit rate and less than the medium hit rate, the target program category is determined to be the third category; in response to detecting that the first-level cache hit rate of the target processor core is less than the low hit rate, the target program category is determined to be the fourth category. The embodiment of the present application provides an exemplary hit rate parameter: high hit rate ɑ=80%, medium hit rate β=50% and low hit rate γ=20%; of course, the above-mentioned hit rate parameters can be adjusted by those skilled in the art according to actual conditions, and this application does not limit this. At this time, when an application is switched or a new application is run on the target processor core, by default in this initialization phase, the first-level cache hit rate corresponding to the target processor core is 50%, and it is assumed by default that the application is of the third category (i.e., a shared cache jitter type program); subsequently, as the application is executed, the hit rate changes dynamically, and then the insertion position of the data belonging to this target processor core in the shared cache also changes dynamically.

[0041] Specifically, the cache insertion position includes a first insertion position, a second insertion position, a third insertion position, and a fourth insertion position. The method for determining the cache insertion position includes: According to the first set of connectivity of the shared cache, the first insertion position is determined, which is the highest priority position for cache insertion; according to the first set of connectivity, the second set of connectivity of the private cache and the first preset formula, the second insertion position is determined, wherein the first preset formula is L1=X+(YX) / 3, X represents the second set of connectivity, Y represents the first set of connectivity, and L1 represents the second insertion position; according to the first set of connectivity, the second set of connectivity and the second preset formula, the third insertion position is determined, wherein the first preset formula is L2=Y-(YX) / 3, and L2 represents the third insertion position; according to the second set of connectivity, the fourth insertion position is determined, which is the lowest priority position for cache insertion. For ease of understanding, Figure 4 Take the insertion position diagram under the specific public scenario as an example to illustrate. At this time, the first group connectivity corresponding to the shared cache is 16, and the second group connectivity corresponding to the private cache is 4. Then the first insertion position is 16, the second insertion position is 16-(16-4) / 3=12, the third insertion position is 4+(16-4) / 3=7, and the fourth insertion position is 4.

[0042] Specifically, the above determination of the target insertion position according to the target program category and the preset mapping relationship table includes: in response to detecting that the program category is the first category, determining the first insertion position as the target insertion position; in response to detecting that the program category is the second category, determining the second insertion position as the target insertion position; in response to detecting that the program category is the third category, determining the third insertion position as the target insertion position; in response to detecting that the program category is the fourth category, determining the fourth insertion position as the target insertion position. That is, the first category matches the first insertion position, the second category matches the second insertion position, the third category matches the third insertion position, and the fourth category matches the fourth insertion position. Correspondingly, Figure 4 Taking the insertion position diagram under the specific scenario disclosed as an example, the target insertion position corresponding to the first category is 16, the target insertion position corresponding to the second category is 12, the target insertion position corresponding to the third category is 7, and the target insertion position corresponding to the fourth category is 4.

[0043] Through the above steps, the present application realizes that when an application running on the target processor core needs to be inserted into the shared cache, the insertion position matching the program category is found from the preset mapping relationship table according to the category of the application, so as to place data belonging to different programs at positions of different priorities, further ensure that data with low hit rates will no longer be placed at high priority, slow down the rate at which high hit rate data is replaced, and improve the overall cache hit rate.

[0044] For ease of understanding, this application provides the following specific implementation scenario. Assume that at a certain moment, the data blocks stored in the cache system are as follows: Figure 5 As shown in the figure, the processor includes four cores: Core 1, Core 2, Core 3, and Core 4. The second-level cache system architecture has a private first-level cache set associativity of 4 and a shared second-level cache set associativity of 16. Programs running on Core 1 are of the first category, those running on Core 2 are of the second category, those running on Core 3 are of the third category, and those running on Core 4 are of the fourth category.

[0045] As shown above, the data blocks belonging to different cores are inserted into the shared cache at positions 16 for core 1, 12 for core 2, 7 for core 3, and 4 for core 4. The number of bits added to a data row in the shared cache is 2.

[0046] Assume that core 1 accesses data A11 at this time, and there is no hit in the private cache and the shared cache. At this time, data A11 needs to be read from the main memory into the cache system. At the same time, because the shared cache is full, a replacement operation needs to be performed. Traversing the data blocks from the low priority position 1 to the fourth insertion position 4 of the shared cache (i.e., the preset cache area), C2 is still in the private cache of core 3 and needs to be inserted into the third insertion position corresponding to the third category, i.e., position 7; B9 is still in the private cache of core 2 and needs to be inserted into the position corresponding to the second category, i.e., position 12; A1 does not exist in any processor core and is selected as the final data block to be replaced. In addition, the read data block A11 belongs to core 1, and its insertion position in the cache is the first insertion position corresponding to the first category, which happens to be the highest priority. After the above operations are completed, the cache system appears as follows Figure 6 shown.

[0047] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0048] The present application embodiment provides a data management system, such as Figure 7 As shown, including: a request receiving module 710 for, in response to receiving a data access request initiated by a target processor core, obtaining an access data block matching the data access request; The cache replacement module 720 is used to trigger a cache replacement operation based on the access data block and the data distribution characteristics of the cache system: The cache replacement module 720 is further configured to determine a target replacement data block based on cached data blocks in a preset cache interval within the shared cache and cached data blocks in the private cache; insert the access data block into a target insertion position that matches the target processor core and delete the target replacement data block.

[0049] An embodiment of the present application further provides an electronic device, comprising: one or more processors; and a memory associated with the one or more processors, the memory being configured to store program instructions. When the program instructions are read and executed by the one or more processors, the program instructions perform the following operations: In response to receiving a data access request initiated by a target processor core, obtaining an access data block matching the data access request; Trigger cache replacement operations based on the access data blocks and the data distribution characteristics of the cache system: Determining a target replacement data block based on cached data blocks in a preset cache interval in the shared cache and cached data blocks in the private cache; Insert the access data block to the target insertion position matching the target processor core and delete the target replacement data block.

[0050] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further execute a method for determining a target insertion position: Obtaining a target program category that matches a currently running program on a target processor core, wherein the program category is determined according to a preset program classification rule; A target insertion position is determined from a plurality of cache insertion positions according to a target program category and a preset mapping relationship table, wherein the mapping relationship table includes a relationship between a program category and a cache insertion position in a shared cache.

[0051] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program classification rules are also executed: Obtaining the highest non-zero bit position of an access register within a target processor core, the access register being used to record the number of data access requests initiated by the target processor core; searching a hit register in a target processor core for a first bit value that matches a highest non-zero bit position and a second bit value that matches a bit position following the highest non-zero bit position, the hit register being used to record a hit count of the data access request in the target processor core; The program category is determined according to the first bit value and the second bit value.

[0052] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further perform the following operations: In response to detecting that the first bit value and the second bit value are both first preset values, determining that the target program category is a first category; In response to detecting that the first bit value is a first preset value and the second bit value is a second preset value, determining that the target program category is a second category; In response to detecting that the first bit value is the second preset value and the second bit values ​​are both the first preset value, determining that the target program category is the third category; In response to detecting that the first bit value and the second bit value are both second preset values, the target program category is determined to be a fourth category.

[0053] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further execute a method for determining a cache insertion position: Determining a first insertion position according to a first set of connectivity of the shared cache; Determining a second insertion position according to the first set of connectivity, the second set of connectivity of the private cache, and a first preset formula, wherein the first preset formula is L1=X+(YX) / 3, where X represents the second set of connectivity, Y represents the first set of connectivity, and L1 represents the second insertion position; Determining a third insertion position according to the first set of connectivity, the second set of connectivity, and a second preset formula, wherein the first preset formula is L2=Y-(YX) / 3, and L2 represents the third insertion position; A fourth insertion position is determined according to the second set of connectivity.

[0054] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further perform the following operations: In response to detecting that the program category is the first category, determining the first insertion position as the target insertion position; In response to detecting that the program category is the second category, determining the second insertion position as the target insertion position; In response to detecting that the program category is the third category, determining the third insertion position as the target insertion position; In response to detecting that the program category is the fourth category, the fourth insertion position is determined as the target insertion position.

[0055] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further perform the following operations: Performing a data block matching operation to select a first cached data block from the cached data blocks within the preset cache interval and compare it with the cached data blocks of the private cache; In response to not detecting that the first cached data block is duplicated with a cached data block in the private cache, determining the first cached data block as a target replacement data block; In response to detecting that the first cached data block is duplicated with a cached data block in the private cache, the data block matching operation is repeatedly performed until all cached data blocks in the preset cache interval are traversed.

[0056] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further perform the following data block matching operations: Selecting a first cache data block from the cached data blocks in the preset cache interval according to the order of priority from low to high; Detect whether the first cache data block and the cached data blocks in the private cache are duplicated.

[0057] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further perform the following operations: In response to detecting that the first cached data block is duplicated with a cached data block in the private cache, detecting whether the first cached data block is a data block with the highest priority in a preset cache interval; In response to detecting that the first cached data block is the data block with the highest priority in the preset cache interval, the first cached data block is determined to be the target replacement data block.

[0058] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further perform the following operations: If there is a cached data block matching the accessed data block in the cache system, the cached data block is fed back to respond to the data access request; If there is no cached data block matching the accessed data block in the cache system, whether to trigger a cache replacement operation is determined based on the cache occupancy status of the shared cache.

[0059] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further perform the following operations: In response to detecting that the shared cache is in a full state, triggering a cache replacement operation; In response to detecting that the cache occupancy state of the shared cache is not full, inserting the accessed data block into a target insertion position that matches the target processor core.

[0060] In some implementation scenarios, when the program instructions are read and executed by one or more processors, the program instructions further perform the following operations: If the cached data block that matches the accessed data block belongs to the private cache and belongs to the target processor core, feeding back the cached data block in response to the data access request; If the cached data block that the accessed data block matches belongs to the private cache but belongs to the non-target processor core, setting the data state of the cached data block to an invalid state in the non-target processor core and feeding the cached data block back to the target processor core in response to the data access request; If the cached data block that matches the accessed data block belongs to the shared cache, the cached data block is fed back to the target processor core to respond to the data access request.

[0061] in, Figure 8 The electronic device architecture is shown as an example, and may include a processor 810, a video display adapter 811, a disk drive 812, an input / output interface 813, a network interface 814, and a memory 820. The processor 810, the video display adapter 811, the disk drive 812, the input / output interface 813, the network interface 814, and the memory 820 may be communicatively connected via a bus 830.

[0062] Among them, the processor 410 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc., to execute relevant programs to implement the technical solutions provided in this application.

[0063] The memory 820 can be implemented in the form of ROM (Read Only Memory, programmable memory), RAM (Random Access Memory, random access memory), static storage device, dynamic storage device, etc. The memory 820 can store an operating system 821 for controlling the execution of the electronic device 800, and a basic input and output system (BIOS) 822 for controlling the low-level operations of the electronic device 800. In addition, a web browser 823, a data storage management system 824, and an icon font processing system 825, etc. can also be stored. The above-mentioned icon font processing system 825 can be an application program that specifically implements the operations of the aforementioned steps in the embodiment of the present application. In short, when the technical solution provided by the present application is implemented by software or firmware, the relevant program code is stored in the memory 820 and is called and executed by the processor 810.

[0064] The input / output interface 813 is used to connect to input / output modules to enable information input and output. The input / output modules can be configured as components within the device (not shown) or externally connected to the device to provide corresponding functions. Input devices may include a keyboard, mouse, touch screen, microphone, and various sensors, while output devices may include a display, speaker, vibrator, indicator light, and the like.

[0065] The network interface 814 is used to connect to a communication module (not shown) to enable communication between the device and other devices. The communication module can communicate via wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, Wi-Fi, Bluetooth, etc.).

[0066] The bus 830 comprises a pathway for transmitting information between the various components of the device (eg, the processor 810 , the video display adapter 811 , the disk drive 812 , the input / output interface 813 , the network interface 814 , and the memory 820 ).

[0067] In addition, the electronic device 800 can also obtain information on specific collection conditions from the virtual resource object collection condition information database for use in condition judgment.

[0068] It should be noted that although the above device only shows the processor 810, video display adapter 811, disk drive 812, input / output interface 813, network interface 818, memory 820, bus 830, etc., in the specific implementation process, the device may also include other components necessary for normal execution. In addition, those skilled in the art will understand that the above device may also include only the components necessary to implement the solution of the present application, and does not necessarily include all the components shown in the figure.

[0069] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned data management method embodiments when running.

[0070] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0071] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above data management method embodiments are implemented.

[0072] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned data management method embodiments are implemented.

[0073] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0074] The above is a detailed introduction to a data management method provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be noted that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and such improvements and modifications also fall within the scope of protection of the present application.

Claims

1. A data management method, characterized in that: Applied to a cache system, the cache system including a shared cache and a private cache, the method comprising: In response to receiving a data access request initiated by a target processor core, obtaining an access data block matching the data access request; According to the access data block and the data distribution characteristics of the cache system, a cache replacement operation is triggered: Determining a target replacement data block based on cached data blocks in a preset cache interval in the shared cache and cached data blocks in the private cache; The access data block is inserted into a target insertion position matching the target processor core and the target replacement data block is deleted.

2. The method according to claim 1, characterized in that Method for determining the target insertion position: Obtaining a target program category that matches a currently running program on the target processor core, wherein the program category is determined according to a preset program classification rule; The target insertion position is determined from a plurality of cache insertion positions according to the target program category and a preset mapping relationship table, wherein the mapping relationship table includes a relationship between program categories and the cache insertion positions in the shared cache.

3. The method according to claim 2, characterized in that The program categories include the first category, the second category, the third category, and the fourth category. The program classification rules include: Obtaining a highest non-zero bit position of an access register within the target processor core, the access register being used to record the number of data access requests initiated by the target processor core; searching a hit register in the target processor core for a first bit value that matches the highest non-zero bit position and a second bit value that matches a bit position following the highest non-zero bit position, the hit register being used to record a hit count of the data access request in the target processor core; The program category is determined according to the first bit value and the second bit value.

4. The method according to claim 3, characterized in that The determining the program category according to the first bit value and the second bit value includes: In response to detecting that both the first bit value and the second bit value are first preset values, determining that the target program category is a first category; In response to detecting that the first bit value is the first preset value and the second bit value is the second preset value, determining that the target program category is a second category; In response to detecting that the first bit value is the second preset value and the second bit values ​​are both the first preset value, determining that the target program category is a third category; In response to detecting that both the first bit value and the second bit value are the second preset value, the target program category is determined to be a fourth category.

5. The method according to claim 3, characterized in that The cache insertion position includes a first insertion position, a second insertion position, a third insertion position, and a fourth insertion position. The method for determining the cache insertion position includes: determining a first insertion position according to a first set of connectivity of the shared cache; Determining a second insertion position according to the first set of connectivity, the second set of connectivity of the private cache, and a first preset formula, wherein the first preset formula is L1=X+(YX) / 3, where X represents the second set of connectivity, Y represents the first set of connectivity, and L1 represents the second insertion position; Determining a third insertion position according to the first set of connectivity, the second set of connectivity, and a second preset formula, wherein the first preset formula is L2=Y-(YX) / 3, and L2 represents the third insertion position; A fourth insertion position is determined according to the second set of connectivity degrees.

6. The method according to claim 5, characterized in that The step of determining the target insertion position according to the target program category and a preset mapping relationship table includes: In response to detecting that the program category is the first category, determining the first insertion position as a target insertion position; In response to detecting that the program category is the second category, determining the second insertion position as a target insertion position; In response to detecting that the program category is the third category, determining the third insertion position as a target insertion position; In response to detecting that the program category is the fourth category, the fourth insertion position is determined as a target insertion position.

7. The method according to claim 1, characterized in that The step of determining a target replacement data block based on cached data blocks in a preset cache interval in the shared cache and cached data blocks in the private cache includes: performing a data block matching operation to select a first cache data block from the cached data blocks within the preset cache interval and compare it with the cached data blocks of the private cache; In response to not detecting that the first cached data block is duplicated with a cached data block in the private cache, determining that the first cached data block is a target replacement data block; In response to detecting that the first cached data block is duplicated with a cached data block in the private cache, the data block matching operation is repeatedly performed until all cached data blocks in the preset cache interval are traversed.

8. The method according to claim 7, characterized in that The data block matching operation includes: Selecting a first cache data block from the cached data blocks in the preset cache interval according to the order of priority from low to high; Detect whether the first cache data block and the cached data blocks in the private cache are duplicated.

9. The method according to claim 7, characterized in that The step of determining a target replacement data block based on the cached data blocks in the preset cache interval in the shared cache and the cached data blocks in the private cache further includes: In response to detecting that the first cached data block is duplicated with a cached data block in the private cache, detecting whether the first cached data block is a data block with the highest priority in a preset cache interval; In response to detecting that the first cached data block is the data block with the highest priority in the preset cache interval, the first cached data block is determined to be a target replacement data block.

10. The method according to claim 1, characterized in that The data distribution characteristics include cached data blocks and cache occupancy status, and triggering a cache replacement operation based on the accessed data blocks and the data distribution characteristics of the cache system includes: If there is a cached data block matching the accessed data block in the cache system, feeding back the cached data block in response to the data access request; If there is no cached data block matching the accessed data block in the cache system, determining whether to trigger a cache replacement operation is determined according to the cache occupancy status of the shared cache.

11. The method according to claim 10, characterized in that The determining whether to trigger a cache replacement operation according to the cache occupancy status of the shared cache includes: In response to detecting that the cache occupancy state of the shared cache is full, triggering a cache replacement operation; In response to detecting that the cache occupancy state of the shared cache is not full, inserting the access data block into a target insertion position that matches the target processor core.

12. The method according to claim 10, characterized in that If there is a cached data block in the cache system that matches the accessed data block, feeding back the cached data block in response to the data access request includes: If the cached data block that matches the accessed data block belongs to a private cache and belongs to the target processor core, feeding back the cached data block in response to the data access request; If the cached data block matched by the accessed data block belongs to a private cache but belongs to a non-target processor core, setting a data state of the cached data block to an invalid state in the non-target processor core and feeding the cached data block back to the target processor core to respond to the data access request; If the cached data block that matches the accessed data block belongs to a shared cache, the cached data block is fed back to the target processor core to respond to the data access request.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data management method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data management method according to any one of claims 1 to 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data management method according to any one of claims 1 to 12 are implemented.

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