Communication system

Abstract

The invention relates to a communication system. Comprising a first level conversion circuit and a second level conversion circuit, the first level conversion circuit is used for being connected with an external master device, the second level conversion circuit is used for being connected with an external slave device, and the first level conversion circuit is connected with the second level conversion circuit. The first level conversion circuit is used for converting a clock signal of a first level into a clock signal of a second level and converting a data signal of a third level into a data signal of a fourth level. The second level conversion circuit is used for converting the clock signal of the second level into the clock signal of the fifth level and converting the received data signal of the fourth level into the data signal of the sixth level. By the adoption of the communication system, an IIC communication architecture can be achieved, the driving capacity and the anti-interference capacity of clock signals and data signals in the communication process are higher, the communication system can adapt to long-distance communication, and the accuracy of signal transmission is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a communication system. Background Art

[0002] With the development of communication technology, Inter-Integrated Circuit (IIC) communication technology has emerged. This communication technology enables communication between multiple devices through a single clock signal line and a single data signal line, with advantages such as saving hardware resources and a simple and convenient architecture. However, the existing IIC communication architecture has a short communication range and is susceptible to interference. Summary of the Invention

[0003] Based on this, it is necessary to provide a communication system with stronger communication anti-interference capability to address the above technical problems.

[0004] A communication system includes: a first level conversion circuit and a second level conversion circuit, wherein the first level conversion circuit is used to connect to an external master device, and the second level conversion circuit is used to connect to an external slave device, and the first level conversion circuit and the second level conversion circuit are connected; wherein:

[0005] The first level conversion circuit is configured to receive a clock signal of a first level sent by the external master device, convert the clock signal of the first level into a clock signal of a second level, and output the signal to the second level conversion circuit; and to convert a data signal of a third level sent by the external master device into a data signal of a fourth level, and output the signal to the second level conversion circuit; and further to convert a data signal of a fourth level received from the second level conversion circuit into a data signal of a third level, and output the signal to the external master device; wherein the amplitude of the second level is greater than the amplitude of the first level, and the amplitude of the fourth level is greater than the amplitude of the third level;

[0006] The second level conversion circuit is used to receive a clock signal of the second level, convert the clock signal of the second level into a clock signal of the fifth level and output it to the external slave device, and to convert a received data signal of the fourth level into a data signal of the sixth level and output it to the external slave device, and also to convert a data signal of the sixth level sent by the external slave device into a data signal of the fourth level and output it to the first level conversion circuit; wherein the amplitude of the second level is greater than the amplitude of the fifth level, and the amplitude of the fourth level is greater than the amplitude of the sixth level.

[0007] In one embodiment, the communication system includes a plurality of the second level conversion circuits, and each of the second level conversion circuits is connected to an external slave device.

[0008] In one embodiment, the communication system further comprises:

[0009] a clock signal channel, wherein a first end of the clock signal channel is connected to the first level conversion circuit, a second end of the clock signal channel is connected to the second level conversion circuit, and the clock signal channel is used to transmit a clock signal of the second level;

[0010] A data signal channel, wherein a first end of the data signal channel is connected to the first level conversion circuit, a second end of the data signal channel is connected to the second level conversion circuit, and the data signal channel is used to transmit the data signal of the fourth level.

[0011] In one embodiment, the first level conversion circuit includes:

[0012] a first clock level conversion circuit, comprising a first input terminal and a first output terminal, wherein the first input terminal is used to connect to an external master device, and the first output terminal is connected to the clock signal channel, and the first clock level conversion circuit is used to convert a received clock signal of the first level into a clock signal of the second level and output the clock signal through the first output terminal;

[0013] a switch circuit, comprising a control terminal, a second input terminal, a second output terminal, and a data transceiver terminal, wherein the data transceiver terminal is configured to be connected to the external host device, and the switch circuit is configured to receive an external control signal through the control terminal and, under the action of the control signal, conduct a path between the second input terminal and the data transceiver terminal, or conduct a path between the second output terminal and the data transceiver terminal;

[0014] a first data level conversion circuit comprising a third input terminal and a third output terminal, wherein the third input terminal is connected to the second output terminal, and the third output terminal is connected to the data signal channel, wherein the first data level conversion circuit is configured to convert the third level data signal received from the external master device into a fourth level data signal and output the fourth level data signal through the third output terminal when the switch circuit is turned on;

[0015] The second data level conversion circuit includes a fourth input terminal and a fourth output terminal, the fourth output terminal is connected to the second input terminal, and the connection node between the fourth input terminal and the third output terminal is connected to the data signal channel. The second data level conversion circuit is used to receive a fourth-level data signal through the fourth input terminal, and convert the fourth-level data signal into a third-level data signal and output it through the fourth output terminal. When the switch circuit is turned on, the third-level data signal is output to the external master device.

[0016] In one embodiment, the first clock level conversion circuit includes:

[0017] a first input unit, wherein an input end of the first input unit is used to connect to an external host device, and the first input unit is used to receive a clock signal of the first level and output a first control signal according to the clock signal of the first level;

[0018] A first output unit, wherein the input end of the first output unit is connected to the output end of the first input unit, and the output end of the first output unit is connected to the clock signal channel, and is used to output a clock signal of a second level according to the received first control signal.

[0019] In one embodiment, the first output unit includes: a first switching tube, a first capacitor, a second resistor, and a third resistor. The control end of the first switching tube and the first end of the second resistor are connected to the output end of the first input unit, the second end of the second resistor is connected to the first end of the first switching tube and connected to a first low-level potential, the second end of the first switching tube is respectively connected to the first end of the first capacitor and the first end of the third resistor and serves as the output end of the first output unit, the second end of the first capacitor is grounded, and the second end of the third resistor is used to connect to a first high-level potential, wherein the second-level clock signal includes at least one of the first low-level potential and the first high-level potential.

[0020] In one embodiment, the first output unit further includes an electrostatic protection device, a first end of the electrostatic protection device is connected to the second end of the first switch tube, and a second end of the electrostatic protection device is grounded.

[0021] In one embodiment, the first output unit further includes: a first resistor, a first end of the first resistor is connected to the output end of the first input unit, and a second end of the first resistor is respectively connected to the control end of the first switch tube and the first end of the second resistor.

[0022] In one embodiment, the first input unit includes: a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube, a fourth resistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, and a twelfth resistor, wherein the first end of the fourth resistor is connected to the first end of the second switching tube and is used to connect to an external main device, the second end of the fourth resistor is connected to a power signal, the control end of the second switching tube is connected to a power signal, the second end of the second switching tube is respectively connected to the first end of the sixth resistor and the first end of the third switching tube, the control end of the third switching tube is connected to the power signal, the second end of the third switching tube is respectively connected to the first end of the eighth resistor and the control end of the fourth switching tube, the first end of the fourth switching tube is grounded, and the second end of the fourth switching tube is connected to the power signal. The first terminal of the ninth resistor is connected to the power supply signal, the first terminal of the tenth resistor, and the control terminal of the fifth switch tube, respectively. The second terminal of the tenth resistor is grounded, the first terminal of the fifth switch tube is grounded, the second terminal of the fifth switch tube is connected to the first terminal of the twelfth resistor and the control terminal of the sixth switch tube, respectively. The first terminal of the sixth switch tube serves as the output terminal of the first input unit for outputting the first control signal. The second terminal of the sixth resistor, the second terminal of the eighth resistor, the second terminal of the ninth resistor, the second terminal of the twelfth resistor, and the second terminal of the sixth switch tube are all connected to the power supply signal. The second, third, fourth, fifth, and sixth switch tubes are of the same type, and the type of the sixth switch tube is different from that of the other switch tubes.

[0023] In one embodiment, the first input unit includes: a seventh switching tube, an eighth switching tube, a ninth switching tube, a tenth switching tube, a fourteenth resistor, a fifteenth resistor, a seventeenth resistor, an eighteenth resistor, a twentieth resistor, and a twenty-first resistor, wherein the first end of the fourteenth resistor, the first end of the fifteenth resistor, the first end of the seventh switching tube, and the control end of the eighth switching tube are connected and used to connect to an external main device, the second end of the fourteenth resistor is connected to a power signal, the control end of the seventh switching tube is connected to a power signal, the second end of the seventh switching tube is connected to the first end of the twentieth resistor, the first end of the ninth switching tube, and the control end of the tenth switching tube, respectively, the first end of the eighth switching tube is grounded, and the The second end of the eighth switching tube is respectively connected to the power signal, the first end of the seventeenth resistor, the first end of the eighteenth resistor, and the control end of the ninth switching tube; the second end of the eighteenth resistor is grounded; the second end of the ninth switching tube is grounded; the first end of the tenth switching tube is connected to the first end of the twenty-first resistor; the second end of the tenth switching tube serves as the output end of the first input unit for outputting the first control signal; the second end of the fifteenth resistor, the second end of the seventeenth resistor, the second end of the twentieth resistor, and the second end of the twenty-first resistor are all connected to the power signal; wherein the seventh, eighth, and ninth switching tubes are of the same type, and the type of the tenth switching tube is different from that of the other switching tubes.

[0024] In one embodiment, the first input unit includes: an eleventh switching tube, a twelfth switching tube, a twenty-second resistor, a twenty-third resistor, a twenty-fifth resistor, and a twenty-sixth resistor. The first end of the twenty-second resistor, the first end of the twenty-third resistor, and the first end of the eleventh switching tube are connected and used to connect to an external main device. The control end of the eleventh switching tube is connected to a power signal. The second end of the eleventh switching tube is connected to the control ends of the twenty-fifth resistor and the twelfth switching tube respectively. The first end of the twelfth switching tube is connected to the twenty-sixth resistor. The second end of the twelfth switching tube serves as the output end of the first input unit for outputting the first control signal. The second end of the twenty-second resistor, the second end of the twenty-third resistor, the second end of the twenty-fifth resistor, and the second end of the twenty-sixth resistor are all connected to the power signal. The eleventh switching tube and the twelfth switching tube are of different types.

[0025] In one embodiment, the first input unit further includes: a fifth resistor, a seventh resistor, an eleventh resistor, and a thirteenth resistor, wherein the first end of the fifth resistor is connected to the control end of the second switch tube, the first end of the seventh resistor is connected to the control end of the third switch tube, the first end of the eleventh resistor is connected to the second end of the fourth switch tube, the second end of the eleventh resistor is connected to the control end of the fifth transistor, the second end of the thirteenth resistor is connected to the control end of the sixth switch tube, and the second end of the fifth resistor and the second end of the seventh resistor are both connected to the power supply signal.

[0026] In one embodiment, the first input unit further includes: a sixteenth resistor and a nineteenth resistor, wherein the first end of the sixteenth resistor is connected to the control end of the seventh switch tube, the second end of the nineteenth resistor is connected to the control end of the ninth switch tube, and the second end of the sixteenth resistor is connected to the power signal.

[0027] In one embodiment, the first input unit further includes: a twenty-fourth resistor, a first end of the twenty-fourth resistor is connected to the control end of the eleventh switch tube, and a second end of the twenty-fourth resistor is connected to the power signal.

[0028] In one embodiment, the first data level conversion circuit includes:

[0029] a second input unit, wherein an input end of the second input unit is connected to the second output end of the switch circuit, and the second input unit is configured to receive the data signal of the third level and output a second control signal according to the data signal of the third level;

[0030] a second output unit, wherein the input end of the second output unit is connected to the output end of the second input unit, and the output end of the second output unit is connected to the data signal channel, and is used to output a fourth-level data signal to the second level conversion circuit according to the second control signal received from the second input unit.

[0031] In one embodiment, the second output unit includes: a thirteenth switch tube, a second capacitor, a twenty-eighth resistor, and a twenty-ninth resistor. The control end of the thirteenth switch tube and the first end of the twenty-eighth resistor are connected to the output end of the second input unit. The second end of the twenty-eighth resistor is connected to the first end of the thirteenth switch tube and is connected to a first low-level potential. The second end of the thirteenth switch tube is respectively connected to the first end of the second capacitor and the first end of the twenty-ninth resistor and serves as the output end of the second output unit. The second end of the second capacitor is grounded, and the second end of the twenty-ninth resistor is used to connect to a first high-level potential. The fourth-level clock signal includes at least one of the first low-level potential and the first high-level potential.

[0032] In one embodiment, the second output unit further includes: a twenty-seventh resistor, a first end of the twenty-seventh resistor being connected to the output end of the second control circuit, and a second end of the twenty-seventh resistor being connected to the control end of the thirteenth switch tube and the first end of the twenty-eighth resistor respectively.

[0033] In one embodiment, the second input unit includes: a fourteenth switching tube, a fifteenth switching tube, a sixteenth switching tube, a seventeenth switching tube, an eighteenth switching tube, a thirtieth resistor, a thirty-second resistor, a thirty-fourth resistor, a thirty-fifth resistor, a thirty-sixth resistor, and a thirty-eighth resistor, wherein a first end of the thirtieth resistor is connected to a first end of the fourteenth switching tube and is used to be connected to a second output end of the switching circuit, a second end of the thirtieth resistor is connected to a power signal, a control end of the fourteenth switching tube is connected to a power signal, a second end of the fourteenth switching tube is respectively connected to a first end of the thirty-second resistor and a first end of the fifteenth switching tube, a control end of the fifteenth switching tube is respectively connected to a power signal, a second end of the fifteenth switching tube is respectively connected to a first end of the thirty-fourth resistor and a control end of the sixteenth switching tube, a first end of the sixteenth switching tube is grounded, and The second ends of the sixteenth switching tube are respectively connected to the power supply signal, the first end of the thirty-fifth resistor, the first end of the thirty-sixth resistor, and the control end of the seventeenth switching tube. The second end of the thirty-sixth resistor is grounded, and the first end of the seventeenth switching tube is grounded. The second end of the seventeenth switching tube is respectively connected to the first end of the thirty-eighth resistor and the control end of the eighteenth switching tube. The first end of the eighteenth switching tube serves as the output end of the second input unit for outputting the first control signal. The second end of the thirty-second resistor, the second end of the thirty-fourth resistor, the second end of the thirty-fifth resistor, the second end of the thirty-eighth resistor, and the second end of the eighteenth switching tube are all connected to the power supply signal. The fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth switching tubes are of the same type, and the type of the eighteenth switching tube is different from that of the other switching tubes.

[0034] In one embodiment, the second input unit includes: a 19th switching tube, a 20th switching tube, a 21st switching tube, a 22nd switching tube, a 40th resistor, a 41st resistor, a 43rd resistor, a 44th resistor, a 46th resistor, and a 47th resistor. The first end of the 40th resistor, the first end of the 41st resistor, the first end of the 19th switching tube, and the control end of the 20th switching tube are connected and used to be connected to the second output end of the switching circuit. The second end of the 40th resistor is connected to the power signal, and the control end of the 19th switching tube is connected to the power signal. The second end of the 19th switching tube is respectively connected to the first end of the 46th resistor, the first end of the 21st switching tube, and the control end of the 22nd switching tube. The first end of the 20th switching tube is grounded. The second end of the 20th switch tube is respectively connected to the power signal, the first end of the 43rd resistor, the first end of the 44th resistor, and the control end of the 21st switch tube. The second end of the 44th resistor is grounded, and the second end of the 21st switch tube is grounded. The first end of the 22nd switch tube is connected to the first end of the 47th resistor. The second end of the 22nd switch tube serves as the output end of the second input unit for outputting the first control signal. The second end of the 41st resistor, the second end of the 43rd resistor, the second end of the 46th resistor, and the second end of the 47th resistor are all connected to the power signal. The 19th, 20th, and 21st switch tubes are of the same type, and the type of the 22nd switch tube is different from that of the other switch tubes.

[0035] In one embodiment, the second input unit includes: a twenty-third switching tube, a twenty-fourth switching tube, a forty-eighth resistor, a forty-ninth resistor, a fifty-first resistor, and a fifty-second resistor. The first end of the forty-eighth resistor, the first end of the forty-ninth resistor, and the first end of the twenty-third switching tube are connected and used to be connected to the second output end of the switching circuit. The control end of the twenty-third switching tube is connected to the power signal. The second end of the twenty-third switching tube is connected to the control ends of the fifty-first resistor and the twenty-fourth switching tube respectively. The first end of the twenty-fourth switching tube is connected to the fifty-second resistor. The second end of the twenty-fourth switching tube serves as the output end of the second input unit and is used to output the first control signal. The second end of the forty-eighth resistor, the second end of the forty-ninth resistor, the second end of the fifty-first resistor, and the second end of the fifty-second resistor are all connected to the power signal. The twenty-third switching tube and the twenty-fourth switching tube are of different types.

[0036] In one embodiment, the second input unit further includes: a thirty-first resistor, a thirty-third resistor, a thirty-seventh resistor, and a thirty-ninth resistor, wherein the first end of the thirty-first resistor is connected to the control end of the fourteenth switch tube, the first end of the thirty-third resistor is connected to the control end of the fifteenth switch tube, the second end of the thirty-seventh resistor is connected to the control end of the seventeenth switch tube, the first end of the thirty-ninth resistor is respectively connected to the second end of the seventeenth switch tube and the first end of the thirty-eighth resistor, the second end of the thirty-ninth resistor is connected to the control end of the eighteenth switch tube, and the second end of the thirty-first resistor and the second end of the thirty-third resistor are both connected to the power supply signal.

[0037] In one embodiment, the second input unit includes: a 42nd resistor and a 45th resistor, the first end of the 42nd resistor is connected to the control end of the 19th switch tube, the second end of the 45th resistor is connected to the control end of the 21st switch tube, and the second end of the 42nd resistor is connected to the power signal.

[0038] In one embodiment, the second input unit further includes: a 50th resistor, a first end of the 50th resistor is connected to the control end of the 23rd switch tube, and a second end of the 50th resistor is connected to the power signal.

[0039] In one embodiment, the second data level conversion circuit includes: a twenty-fifth switch tube, a twenty-sixth switch tube, a fifty-third resistor, a fifty-fourth resistor, a fifty-fifth resistor, and a fifty-sixth resistor. The first end of the twenty-fifth switch tube is connected to the first end of the fifty-third resistor and to the second input end of the switch circuit. The second end of the fifty-third resistor is connected to the power signal. The second end of the twenty-fifth switch tube is grounded. The control end of the twenty-fifth switch tube is respectively connected to the first end of the fifty-fourth resistor, the first end of the fifty-fifth resistor, and the first end of the twenty-sixth switch tube. The second end of the fifty-fourth resistor and the second end of the fifty-fifth resistor are connected to the power signal. The second end of the twenty-sixth switch tube is grounded. The control end of the twenty-sixth switch tube is connected to the first end of the fifty-sixth resistor. The second end of the fifty-sixth resistor serves as the fourth input end of the second data level conversion circuit.

[0040] In one embodiment, the switching circuit includes: a switching chip, a third capacitor, the first end of the third capacitor is connected to the second pin of the switching chip and receives a power signal, the second end of the third capacitor is connected to the third pin of the switching chip and is grounded, the first pin of the switching chip serves as a control end to receive an external control signal, the fourth pin of the switching chip serves as a second input end to be connected to the fourth output end of the second data level conversion circuit, the fifth pin of the switch chip serves as a data transceiver end to be connected to the external host device, and the sixth pin of the switch chip serves as a second output end to be connected to the third input end of the first data level conversion circuit.

[0041] In one embodiment, the second level conversion circuit includes:

[0042] The second clock level conversion circuit includes a fifth input terminal and a fifth output terminal, wherein the fifth input terminal is connected to the clock signal channel, and the fifth output terminal is used to connect to an external slave device. The second clock level conversion circuit is used to convert the received clock signal of the second level into a clock signal of a fifth level and output it through the fifth output terminal.

[0043] a third data level conversion circuit, comprising a sixth input terminal and a sixth output terminal, wherein the sixth input terminal is connected to the data signal channel, the sixth output terminal is used to connect to an external slave device, and the third data level conversion circuit is used to convert the received data signal of the fourth level into a data signal of the sixth level and output it through the sixth output terminal;

[0044] A fourth data level conversion circuit includes a seventh input terminal and a seventh output terminal, wherein a connection node between the seventh input terminal and the sixth output terminal is connected to the external slave device, and a connection node between the seventh output terminal and the sixth input terminal is connected to the data signal channel. The fourth data level conversion circuit is used to receive a data signal of a sixth level sent by the external slave device and convert the data signal of the sixth level into a data signal of a fourth level and output it through the seventh output terminal.

[0045] In one embodiment, the second clock level conversion circuit includes: a twenty-seventh switching transistor, a twenty-eighth switching transistor, a fifty-seventh resistor, a fifty-eighth resistor, a fifty-ninth resistor, a sixtieth resistor, a sixtieth resistor, a sixtieth resistor, and a sixtieth resistor. A first end of the fifty-seventh resistor is connected to a first end of the fifty-eighth resistor and is used to receive a clock signal of the second level. A second end of the fifty-seventh resistor is connected to a first end of the fifty-eighth resistor and is used to receive a first high-level potential. A second end of the fifty-eighth resistor is connected to a control end of the twenty-seventh switching transistor. A first end of the twenty-seventh switching transistor is connected to a first end of the twenty-eighth switching transistor and is grounded. A second end of the twenty-seventh switching transistor is respectively connected to a first end of the fifty-ninth resistor, a first end of the sixtieth resistor, and a first end of the sixtieth resistor. A second end of the fifty-ninth resistor and a second end of the sixtieth resistor are respectively connected to a power supply signal. A second end of the sixtieth resistor is connected to a control end of the twenty-eighth switching transistor. A second end of the twenty-eighth switching transistor is connected to a first end of the sixtieth resistor and serves as an output end of the second clock level conversion circuit. A second end of the sixtieth resistor is connected to a power supply signal.

[0046] In one embodiment, the third data level conversion circuit includes: a 29th switching transistor, a 30th switching transistor, a 63rd resistor, a 64th resistor, a 65th resistor, a 66th resistor, a 67th resistor, a 68th resistor, and a first voltage-stabilizing diode. The first end of the 63rd resistor is connected to the first end of the 64th resistor and is used to receive the fourth-level data signal. The second end of the 63rd resistor is connected to the first end of the 64th resistor and is used to receive the first high-level potential. The second end of the 64th resistor is connected to the control end of the 29th switching transistor. The first end of the 29th switching transistor is connected to the first end of the 30th switching transistor and is grounded. The second end of the 29th switching transistor is respectively connected to the first end of the 65th resistor, the first end of the 66th resistor, and the first end of the 67th resistor. The second end of the 65th resistor and the second end of the 66th resistor are connected to the power supply signal. The second end of the 67th resistor is connected to the control end of the 30th switching transistor. The second end of the 30th switching transistor is connected to the anode of the first voltage-stabilizing diode. The cathode of the first voltage-stabilizing diode is connected to the first end of the 68th resistor and serves as the output end of the third data level conversion circuit. The second end of the 68th resistor is connected to the power supply signal.

[0047] In one embodiment, the third data level conversion circuit includes: a 31st switching transistor, a 32nd switching transistor, a 69th resistor, a 70th resistor, a 71st resistor, a 72nd resistor, a 73rd resistor, a 74th resistor, and a first Schottky diode. The first end of the 69th resistor is connected to the first end of the 70th resistor and is used to receive the fourth level data signal. The second end of the 69th resistor is connected to the first end of the 70th resistor and is used to receive the first high level potential. The second end of the 70th resistor is connected to the control end of the 31st switching transistor. The first end of the 31st switching transistor is connected to the cathode of the first Schottky diode and is grounded. The second end of the 31st switching transistor is respectively connected to the first end of the 71st resistor, the first end of the 72nd resistor, and the first end of the 73rd resistor. The second end of the 71st resistor and the second end of the 72nd resistor are connected to the power signal. The second end of the 73rd resistor is connected to the control end of the 32nd switching transistor. The first end of the 32nd switching transistor is connected to the anode of the first Schottky diode. The second end of the 32nd switching transistor is connected to the first end of the 74th resistor and serves as the output end of the third data level conversion circuit. The second end of the 74th resistor is connected to the power signal.

[0048] In one embodiment, the fourth data level conversion circuit includes: a 33rd switching transistor, a 34th switching transistor, a 35th switching transistor, a 36th switching transistor, a 75th resistor, a 77th resistor, a 79th resistor, an 81st resistor, an 82nd resistor, and a second voltage regulator diode. The first end of the 33rd switching transistor serves as the output end of the fourth data level conversion circuit, the second end of the 33rd switching transistor is connected to the first end of the 75th resistor and is connected to a first low-level potential, the control end of the 33rd switching transistor is respectively connected to the second end of the 75th resistor and the first end of the 34th switching transistor, and the second end of the 34th switching transistor is connected to the first end of the 77th resistor. The control end of the thirty-fourth switch tube is respectively connected to the first end of the seventy-ninth resistor and the first end of the thirty-fifth switch tube, and the control end of the thirty-fifth switch tube is connected to a power signal. The second end of the thirty-fifth switch tube is respectively connected to the first end of the eighty-first resistor and the first end of the thirty-sixth switch tube, and the control end of the thirty-sixth switch tube is respectively connected to the first end of the eighty-second resistor and the cathode of the second Zener diode, and the anode of the second Zener diode is grounded. The second end of the seventy-seventh resistor, the second end of the seventy-ninth resistor, and the second end of the eighty-first resistor are all connected to a power signal, and the second end of the thirty-sixth switch tube serves as the input end of the fourth data level conversion circuit.

[0049] In one embodiment, the fourth data level conversion circuit includes: a thirty-seventh switching tube, a thirty-eighth switching tube, a thirty-ninth switching tube, an eighty-fourth resistor, an eighty-sixth resistor, an eighty-eighth resistor, an eighty-ninth resistor, a ninety-first resistor, a second Schottky diode, and a third Schottky diode. The first end of the thirty-seventh switching tube serves as the output end of the fourth data level conversion circuit, the second end of the thirty-seventh switching tube is connected to the first end of the eighty-fourth resistor and is connected to the first low-level potential, the control end of the thirty-seventh switching tube is respectively connected to the second end of the eighty-fourth resistor and the first end of the thirty-eighth switching tube, and the second end of the thirty-eighth switching tube is connected to the first end of the eighty-sixth resistor. The control end of the thirty-eighth switching tube is respectively connected to the first end of the eighty-eighth resistor and the first end of the thirty-ninth switching tube. The control end of the thirty-ninth switching tube is respectively connected to the first end of the eighty-ninth resistor, the first end of the ninety-first resistor, and the anode of the second Schottky diode. The cathode of the second Schottky diode is connected to the anode of the third Schottky diode. The cathode of the third Schottky diode is grounded. The second end of the eighty-ninth resistor, the second end of the eighty-sixth resistor, and the second end of the eighty-eighth resistor are all connected to the power supply signal. The second end of the thirty-ninth switching tube is connected to the second end of the ninety-first resistor and serves as the input end of the fourth data level conversion circuit.

[0050] In one embodiment, the fourth data level conversion circuit further includes: a seventy-sixth resistor, a seventy-eighth resistor, an eightieth resistor, and an eighty-third resistor, wherein the first end of the seventy-sixth resistor is respectively connected to the control end of the thirty-third switch tube and the second end of the seventy-fifth resistor, the second end of the seventy-sixth resistor is respectively connected to the first end of the thirty-fourth switch tube, the first end of the seventy-eighth resistor is connected to the control end of the thirty-fourth switch tube, the second end of the seventy-eighth resistor is respectively connected to the first end of the seventy-ninth resistor and the first end of the thirty-fifth switch tube, the first end of the eightieth resistor is connected to the control end of the thirty-fifth switch tube, the second end of the eightieth resistor is connected to the power supply signal, the first end of the eighty-third resistor is connected to the control end of the thirty-sixth switch tube, and the second end of the eighty-third resistor is respectively connected to the first end of the eighty-second resistor and the cathode of the second voltage stabilizing diode.

[0051] In one embodiment, the fourth data level conversion circuit further includes: an eighty-fifth resistor, an eighty-seventh resistor, and a ninety-second resistor, wherein the first end of the eighty-fifth resistor is respectively connected to the control end of the thirty-seventh switch tube and the second end of the eighty-fourth resistor, the second end of the eighty-fifth resistor is respectively connected to the first end of the thirty-eighth switch tube, the first end of the eighty-seventh resistor is connected to the control end of the thirty-eighth switch tube, the second end of the eighty-seventh resistor is respectively connected to the first end of the eighty-eighth resistor and the first end of the thirty-ninth switch tube, the first end of the ninety-second resistor is connected to the control end of the thirty-ninth switch tube, and the second end of the ninety-second resistor is respectively connected to the first end of the eighty-ninth resistor, the first end of the ninety-first resistor, and the anode of the second Schottky diode.

[0052] The above-mentioned communication system includes a first level conversion circuit and a second level conversion circuit. The first level conversion circuit is used to connect to an external master device, and the second level conversion circuit is used to connect to an external slave device. The first level conversion circuit is connected to the second level conversion circuit. The first level conversion circuit is used to receive a first-level clock signal sent by the external master device, convert the first-level clock signal into a second-level clock signal, and output it to the second level conversion circuit. The amplitude of the second level is greater than the amplitude of the first level, so that the amplitude of the clock signal can be converted to a larger level amplitude for transmission. The clock signal with a larger level amplitude has a stronger driving capability, so it can adapt to longer-distance transmission, is not affected by smaller interference signals, and has stronger anti-interference capabilities. The first level conversion circuit is further configured to convert a third-level data signal transmitted by an external master device into a fourth-level data signal and output it to the second level conversion circuit, and to convert a fourth-level data signal received from the second level conversion circuit into a third-level data signal and output it to the external master device. The fourth-level amplitude is greater than the third-level amplitude, thereby converting the amplitude of the data signal into a larger-level amplitude for transmission. A data signal with a larger amplitude has a stronger driving capability, thereby adapting to longer-distance transmission and being unaffected by smaller interference signals, thereby having a stronger anti-interference capability. Furthermore, the transmitted data signal with a larger amplitude is converted into a data signal with a smaller amplitude that meets the processing requirements of the master device, thereby facilitating reception by the master device. The second level conversion circuit is configured to receive a second-level clock signal and convert the second-level clock signal into a fifth-level clock signal and output it to the external slave device. The second-level amplitude is greater than the fifth-level amplitude, thereby converting the transmitted clock signal with a larger amplitude into a clock signal with a smaller amplitude that meets the processing requirements of the slave device, thereby facilitating reception by the slave device. The second level conversion circuit is also used to convert the received fourth-level data signal into a sixth-level data signal and output it to the external slave device, and convert the sixth-level data signal sent by the external slave device into a fourth-level data signal and output it to the first level conversion circuit. The amplitude of the fourth level is greater than the sixth level, so that the amplitude of the data signal can be converted into a larger level amplitude and sent out. The data signal with a larger level amplitude has a stronger driving ability, so it can adapt to longer distance transmission and will not be affected by smaller interference signals. It has a stronger anti-interference ability and can convert the transmitted data signal with a larger level amplitude into a data signal with a smaller level amplitude that meets the processing requirements of the slave device, which is convenient for the slave device to receive. In summary, the communication system of the present application can realize the IIC communication architecture, and the driving ability and anti-interference ability of the clock signal and data signal in the communication process are stronger, can adapt to long-distance communication, and improve the accuracy of signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 is a schematic structural diagram of a communication system in one embodiment;

[0055] Figure 2 is a schematic structural diagram of a communication system in another embodiment;

[0056] Figure 3 is a schematic structural diagram of a first clock level conversion circuit in one embodiment;

[0057] Figure 4 is a circuit diagram of a first clock level conversion circuit in one embodiment;

[0058] Figure 5 FIG2 is a second circuit diagram of a first clock level conversion circuit in one embodiment;

[0059] Figure 6 FIG3 is a circuit diagram of a first clock level conversion circuit according to an embodiment;

[0060] Figure 7 FIG4 is a fourth circuit diagram of a first clock level conversion circuit in one embodiment;

[0061] Figure 8 FIG5 is a fifth circuit diagram of a first clock level conversion circuit in one embodiment;

[0062] Figure 9 FIG6 is a sixth circuit diagram of a first clock level conversion circuit in one embodiment;

[0063] Figure 10 is a schematic structural diagram of a first data level conversion circuit in one embodiment;

[0064] Figure 11 FIG2 is a second circuit diagram of a first data level conversion circuit in one embodiment;

[0065] Figure 12 FIG3 is a third circuit diagram of a first data level conversion circuit in one embodiment;

[0066] Figure 13 FIG4 is a fourth circuit diagram of a first data level conversion circuit in one embodiment;

[0067] Figure 14 FIG5 is a fifth circuit diagram of a first data level conversion circuit in one embodiment;

[0068] Figure 15 FIG6 is a sixth circuit diagram of a first data level conversion circuit in one embodiment;

[0069] Figure 16 FIG7 is a seventh circuit diagram of a first data level conversion circuit in one embodiment;

[0070] Figure 17 is a circuit diagram of a second data level conversion circuit in one embodiment;

[0071] Figure 18 FIG2 is a second circuit diagram of a second data level conversion circuit in one embodiment;

[0072] Figure 19 is a circuit diagram of a switching circuit in one embodiment;

[0073] Figure 20 is a structural diagram of a communication system in yet another embodiment;

[0074] Figure 21 is a circuit diagram of a second clock level conversion circuit in one embodiment;

[0075] Figure 22 FIG2 is a second circuit diagram of a second clock level conversion circuit in one embodiment;

[0076] Figure 23 is a circuit diagram of a third data level conversion circuit in one embodiment;

[0077] Figure 24 FIG2 is a second circuit diagram of a third data level conversion circuit in one embodiment;

[0078] Figure 25 FIG3 is a third circuit diagram of a third data level conversion circuit in one embodiment;

[0079] Figure 26 FIG4 is a fourth circuit diagram of a third data level conversion circuit in one embodiment;

[0080] Figure 27 is a circuit diagram of a fourth data level conversion circuit in one embodiment;

[0081] Figure 28 FIG2 is a second circuit diagram of a fourth data level conversion circuit in one embodiment;

[0082] Figure 29 FIG3 is a circuit diagram of a fourth data level conversion circuit according to an embodiment;

[0083] Figure 30 FIG4 is a fourth circuit diagram of a fourth data level conversion circuit in an embodiment.

[0084] Description of reference numerals:

[0085] 10-first level conversion circuit, 20-second level conversion circuit, 30-external master device, 40-external slave device, 100-clock signal channel, 200-data signal channel, 11-first clock level conversion circuit, 12-switch circuit, 13-first data level conversion circuit, 14-second data level conversion circuit, 111-first input unit, 112-first output unit, 131-second input unit, 132-second output unit, 21-second clock level conversion circuit, 22-third data level conversion circuit, 23-fourth data level conversion circuit. DETAILED DESCRIPTION

[0086] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0087] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0088] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0089] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc., if there is transmission of electrical signals or data between the connected objects.

[0090] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0091] In one embodiment, Figure 1As shown, a communication system is provided, including: a first level conversion circuit 10 and a second level conversion circuit 20, wherein the first level conversion circuit 10 is used to connect to an external master device 30, and the second level conversion circuit 20 is used to connect to an external slave device 40, and the first level conversion circuit 10 and the second level conversion circuit 20 are connected.

[0092] The first level conversion circuit 10 is used to receive a first-level clock signal sent by the external master device 30, convert the first-level clock signal into a second-level clock signal and output it to the second level conversion circuit 20, and to receive a third-level data signal sent by the external master device 30, convert the third-level data signal into a fourth-level data signal, and then output the fourth-level data signal to the second level conversion circuit 20.

[0093] The first level conversion circuit 10 is further configured to receive a fourth-level data signal from the second level conversion circuit 20 , convert the fourth-level data signal into a third-level data signal, and transmit the third-level data signal to the external host device 30 .

[0094] The amplitude of the second level is greater than that of the first level, and the amplitude of the fourth level is greater than that of the third level. The first level conversion circuit 10 can convert the first level clock signal into a second level clock signal. A clock signal with a larger level amplitude has a stronger driving capability, so it can adapt to longer distance transmission, is not affected by smaller interference signals, and has a stronger anti-interference capability. The first level conversion circuit 10 can convert the third level data signal into a fourth level data signal. A data signal with a larger level amplitude has a stronger driving capability, so it can adapt to longer distance transmission, is not affected by smaller interference signals, and has a stronger anti-interference capability.

[0095] Exemplarily, the amplitude of the clock signal of the first level may be 0V~VCC1 (VCC1 may be 1.8V~5.5V), the amplitude of the clock signal of the second level may be -HVDD~+HVDD (-HVDD may be -3.3V~-20V, +HVDD may be 3.3V~20V), the amplitude of the data signal of the third level may be 0V~VCC1 (VCC1 may be 1.8V~5.5V), and the amplitude of the data signal of the fourth level may be -HVDD~+HVDD (-HVDD may be -3.3V~-20V, +HVDD may be 3.3V~20V).

[0096] The second level conversion circuit 20 is used to receive a second-level clock signal and convert the second-level clock signal into a fifth-level clock signal and output it to the external slave device 40; the second level conversion circuit 20 is used to receive a fourth-level data signal from the first level conversion circuit 10 and convert the fourth-level data signal into a sixth-level data signal and output the sixth-level data signal to the external slave device 40.

[0097] The second level conversion circuit 20 is further configured to receive a data signal of a sixth level from the external slave device 40 , convert the data signal of the sixth level into a data signal of a fourth level, and output the data signal of the fourth level to the first level conversion circuit 10 .

[0098] The amplitude of the second level is greater than the amplitude of the fifth level, and the amplitude of the fourth level is greater than the amplitude of the sixth level. The second level conversion circuit 20 can convert the second-level clock signal into a fifth-level clock signal and output it to the external slave device 40. It can also convert the transmitted clock signal with a larger amplitude into a clock signal with a smaller amplitude that meets the processing requirements of the slave device, making it easier for the slave device to receive it. The second level conversion circuit 20 can convert the sixth-level data signal sent by the external slave device 40 into a fourth-level data signal. The data signal with a larger amplitude has a stronger driving capability, so it can adapt to longer-distance transmission and is not affected by smaller interference signals, thus having a stronger anti-interference capability.

[0099] Exemplarily, the amplitude of the clock signal of the fifth level may be 0V~VCC2 (VCC2 may be 1.8V~5.5V), the amplitude of the clock signal of the second level may be -HVDD~+HVDD (-HVDD may be -3.3V~-20V, +HVDD may be 3.3V~20V), the amplitude of the data signal of the sixth level may be 0V~VCC2 (VCC2 may be 1.8V~5.5V), and the amplitude of the data signal of the fourth level may be -HVDD~+HVDD (-HVDD may be -3.3V~-20V, +HVDD may be 3.3V~20V).

[0100] In this embodiment, the communication system includes a first level conversion circuit and a second level conversion circuit. The first level conversion circuit is configured to connect to an external master device, and the second level conversion circuit is configured to connect to an external slave device. The first level conversion circuit is connected to the second level conversion circuit. The first level conversion circuit is configured to receive a first-level clock signal transmitted by the external master device, convert the first-level clock signal into a second-level clock signal, and output the second-level clock signal to the second level conversion circuit. The second-level clock signal has a greater amplitude than the first level, thereby converting the clock signal to a larger amplitude for transmission. The larger-amplitude clock signal has a stronger driving capability, thereby accommodating longer-distance transmission, and is less susceptible to smaller interference signals, thereby enhancing anti-interference capabilities. The first level conversion circuit is further configured to convert a third-level data signal transmitted by an external master device into a fourth-level data signal and output it to the second level conversion circuit, and to convert a fourth-level data signal received from the second level conversion circuit into a third-level data signal and output it to the external master device. The fourth-level amplitude is greater than the third-level amplitude, thereby converting the amplitude of the data signal into a larger-level amplitude for transmission. A data signal with a larger amplitude has a stronger driving capability, thereby adapting to longer-distance transmission and being unaffected by smaller interference signals, thereby having a stronger anti-interference capability. Furthermore, the transmitted data signal with a larger amplitude is converted into a data signal with a smaller amplitude that meets the processing requirements of the master device, thereby facilitating reception by the master device. The second level conversion circuit is configured to receive a second-level clock signal and convert the second-level clock signal into a fifth-level clock signal and output it to the external slave device. The second-level amplitude is greater than the fifth-level amplitude, thereby converting the transmitted clock signal with a larger amplitude into a clock signal with a smaller amplitude that meets the processing requirements of the slave device, thereby facilitating reception by the slave device. The second level conversion circuit is also used to convert the received fourth-level data signal into a sixth-level data signal and output it to the external slave device, and convert the sixth-level data signal sent by the external slave device into a fourth-level data signal and output it to the first level conversion circuit. The amplitude of the fourth level is greater than the sixth level, so that the amplitude of the data signal can be converted into a larger level amplitude and sent out. The data signal with a larger level amplitude has a stronger driving ability, so it can adapt to longer distance transmission and will not be affected by smaller interference signals. It has a stronger anti-interference ability and can convert the transmitted data signal with a larger level amplitude into a data signal with a smaller level amplitude that meets the processing requirements of the slave device, which is convenient for the slave device to receive. In summary, the communication system of the present application can realize the IIC communication architecture, and the driving ability and anti-interference ability of the clock signal and data signal in the communication process are stronger, can adapt to long-distance communication, and improve the accuracy of signal transmission.

[0101] In one embodiment, Figure 2As shown, the communication system includes a plurality of second level conversion circuits 20 , and each second level conversion circuit 20 is correspondingly connected to an external slave device 40 .

[0102] Among them, an external master device 30 can be connected to multiple external slave devices 40 through a first level conversion circuit 10 and multiple second level conversion circuits 20. The external master device 30 sends a clock signal, and the external slave device 40 only receives the clock signal but does not send a clock signal. The IIC communication bus is a serial, half-duplex bus that includes a data line and a clock line. The data line is used to send and receive data, and the clock line is used to synchronize the clocks of both communicating parties. Each external slave device 40 has a unique address. The external master device 30 can address the external slave device 40 based on the device address of the external slave device 40, determine the external slave device 40 with which to communicate, and then send a clock signal to synchronize the clock of the external slave device 40, and then send data signals to or receive data signals from the external slave device 40.

[0103] In this embodiment, the communication system includes multiple second level conversion circuits 20, each of which is connected to an external slave device 40. Thus, multiple external slave devices 40 can be connected to one IIC communication bus, facilitating the external master device 30 to detect and communicate with each of the multiple external slave devices 40.

[0104] In one embodiment, Figure 3 As shown, the communication system further includes: a clock signal channel 100 and a data signal channel 200, wherein:

[0105] A first end of the clock signal channel 100 is connected to the first level conversion circuit 10 , and a second end of the clock signal channel 100 is connected to the second level conversion circuit 20 . The clock signal channel 100 is used to transmit a clock signal of a second level.

[0106] A first end of the data signal channel 200 is connected to the first level conversion circuit 10 , and a second end of the data signal channel 200 is connected to the second level conversion circuit 20 . The data signal channel 200 is used to transmit a data signal of a fourth level.

[0107] Among them, the IIC communication bus is a serial, half-duplex bus, including a data line and a clock line. The data line is used to send and receive data, and the clock line is used to synchronize the clocks of the communicating parties. The clock signal channel 100 can be a clock signal cable, that is, the clock line in the IIC communication bus. Since it transmits a second-level clock signal, the amplitude of the second-level clock signal can be -HVDD~+HVDD (-HVDD can be -3.3V~-20V, +HVDD can be 3.3V~20V). The amplitude of the second-level clock signal is large, and the driving ability and anti-interference ability are stronger, so the length of the clock signal channel 100 can be longer, for example, more than 1m. The data signal channel 200 can be a data signal cable, that is, a data line in the IIC communication bus. Since it transmits a fourth-level data signal, the amplitude of the fourth-level data signal can be -HVDD~+HVDD (-HVDD can be -3.3V~-20V, +HVDD can be 3.3V~20V). The amplitude of the fourth-level data signal is large, and the driving capability and anti-interference capability are stronger, so the length of the data signal cable 200 can be longer, for example, more than 1m.

[0108] Among them, such as Figure 2 As shown, when an external master device 30 is connected to multiple external slave devices 40 , multiple second level conversion circuits 20 can be directly connected to the clock signal channel 100 and the data signal channel 200 .

[0109] In this embodiment, by providing a clock signal channel 100 and a data signal channel 200 and connecting the first level conversion circuit 10 and the second level conversion circuit 20, the transmission of clock signals and data signals can be achieved. Moreover, since the first level conversion circuit 10 converts the amplitude of the clock signal to a larger amplitude before transmitting it through the clock signal channel 100, and the first level conversion circuit 10 and the second level conversion circuit 20 respectively convert the amplitude of the data signal to a larger amplitude before transmitting it through the data signal channel 200, the lengths of the clock signal channel 100 and the data signal channel 200 can be longer.

[0110] In one embodiment, Figure 3 As shown, the first level conversion circuit 10 includes: a first clock level conversion circuit 11, a switch circuit 12, a first data level conversion circuit 13, and a second data level conversion circuit 14, wherein:

[0111] The first clock level conversion circuit 11 includes a first input terminal and a first output terminal. The first input terminal is used to connect to the external master device 30, and the first output terminal is connected to the clock signal channel 100. The first clock level conversion circuit 11 is used to convert the received first-level clock signal into a second-level clock signal and output it through the first output terminal.

[0112] Among them, the first input end of the first clock level conversion circuit 11 is connected to the clock end of the external master device 30, receives the first level clock signal sent by the external master device 30, and converts the received first level clock signal into a second level clock signal, and then outputs it to the clock signal channel 100 through the first output end.

[0113] The switching circuit 12 includes a control end, a second input end, a second output end, and a data transceiver end. The data transceiver end is used to connect to the external host device 30. The switching circuit 12 is used to receive an external control signal through the control end. Under the action of the control signal, the path between the second input end and the data transceiver end is connected, or the path between the second output end and the data transceiver end is connected.

[0114] When the switch circuit 12 conducts a path between the second input terminal and the data transceiver, the third-level data signal received at the second input terminal can be transmitted to the external host device 30 via the data transceiver. When the switch circuit 12 conducts a path between the second output terminal and the data transceiver, the third-level data signal sent by the external host device 30 can be transmitted to the second output terminal via the data transceiver. Since these two paths are selectively conducted at the same time, the data transceiver will not be simultaneously transmitting and receiving data, thus avoiding deadlock at the data transceiver of the external host device 30.

[0115] The first data level conversion circuit 13 includes a third input terminal and a third output terminal. The third input terminal is connected to the second output terminal, and the third output terminal is connected to the data signal channel 200. The first data level conversion circuit 13 is used to convert the third level data signal received from the external master device 30 into a fourth level data signal and output it through the third output terminal when the switch circuit 12 is turned on.

[0116] The first data level conversion circuit 13 can convert the third level data signal sent by the external host device 30 into a fourth level data signal and transmit the fourth level data signal through the data signal channel 200 .

[0117] The second data level conversion circuit 14 includes a fourth input terminal and a fourth output terminal. The fourth output terminal is connected to the second input terminal. The connection node between the fourth input terminal and the third output terminal is connected to the data signal channel 200. The second data level conversion circuit 14 is used to receive a fourth-level data signal through the fourth input terminal, and convert the fourth-level data signal into a third-level data signal and output it through the fourth output terminal. When the switch circuit 12 is turned on, the third-level data signal is output to the external master device 30.

[0118] The second data level conversion circuit 14 can convert the fourth-level data signal transmitted from the data signal channel 200 into a third-level data signal and transmit it to the external host device 30. Due to the function of the switch circuit 12, the first data level conversion circuit 13 and the second data level conversion circuit 14 operate in a time-sharing manner. Therefore, the fourth input terminal of the second data level conversion circuit 14 and the third output terminal of the first data level conversion circuit 13 can be connected together to the data signal channel 200, and the fourth-level data signal can be transmitted and received through a single port.

[0119] In this embodiment, the first level conversion circuit 10 includes a first clock level conversion circuit 11, a switch circuit 12, a first data level conversion circuit 13, and a second data level conversion circuit 14, thereby realizing the transmission and level conversion of clock signals, and realizing the transmission, reception, and level conversion of data signals.

[0120] In one embodiment, Figure 3 As shown, the first clock level conversion circuit 11 includes: a first input unit 111 and a first output unit 112, wherein:

[0121] An input end of the first input unit 111 is used to connect to the external host device 30 . The first input unit 111 is used to receive a clock signal of a first level and output a first control signal according to the clock signal of the first level.

[0122] Among them, the input end of the first input unit 111 is connected to the clock signal of the first level, and outputs the first control signal according to the clock signal of the first level. For example, the clock signal of the first level is a digital signal, which includes a low level 0 and a high level 1. The first input unit 111 will output the corresponding first control signal (for example, also including a low level and a high level) according to whether the clock signal of the first level is a low level or a high level.

[0123] The input end of the first output unit 112 is connected to the output end of the first input unit 111 , and the output end of the first output unit 112 is connected to the clock signal channel 100 , and is configured to output a clock signal of a second level according to the received first control signal.

[0124] Among them, the second-level clock signal includes a low level -HVDD and a high level +HVDD (-HVDD can be -3.3V~-20V, +HVDD can be 3.3V~20V), and the first output unit 112 is connected to the first control signal. According to whether the first control signal is a low level or a high level, the corresponding output is a low level -HVDD or a high level +HVDD of the second-level clock signal.

[0125] In this embodiment, the first clock level conversion circuit 11 includes a first input unit 111 and a first output unit 112 , thereby achieving conversion between a received clock signal of a first level and an output clock signal of a second level.

[0126] In one embodiment, Figure 4 As shown, the first output unit 112 includes: a first switch tube Q1, a first capacitor C1, a second resistor R2, and a third resistor R3, wherein:

[0127] The control end of the first switching tube Q1 and the first end of the second resistor R2 are connected to the output end of the first input unit 111. The second end of the second resistor R2 is connected to the first end of the first switching tube Q1 and is connected to the first low-level potential -HVDD. The second end of the first switching tube Q1 is respectively connected to the first end of the first capacitor C1 and the first end of the third resistor R3 and serves as the output end of the first output unit. The second end of the first capacitor C1 is grounded GND. The second end of the third resistor R3 is used to connect to the first high-level potential +HVDD.

[0128] The second level clock signal includes at least one of a first low level potential and a first high level potential.

[0129] The first switch tube Q1 is a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor), for example, an NMOS tube.

[0130] The second resistor R2 can ensure that the first switch Q1 has a fixed voltage level when it is powered on, preventing the transistor from working in an unstable state and enhancing the anti-interference ability of the circuit. The third resistor R3 is a pull-up resistor.

[0131] The gate of the first switch Q1 is connected to a first control signal and is turned on or off by the first control signal. When the first switch Q1 is turned on, -HVDD is transmitted to the output end of the first output unit and output to the clock signal channel 100. When the first switch Q1 is turned off, +HVDD is transmitted to the output end of the first output unit through the pull-up resistor and output to the clock signal channel 100.

[0132] In this embodiment, by setting the circuit structure of the first output unit to include the first switch tube Q1, the first capacitor C1, the second resistor R2, and the third resistor R3, the output of the clock signal of the second level can be achieved.

[0133] In one embodiment, Figure 5As shown, the first output unit 112 includes: a first switch tube Q1, a first resistor R1, a first capacitor C1, a second resistor R2, and a third resistor R3, wherein:

[0134] A first end of the first resistor R1 is connected to the output end of the first input unit. A second end of the first resistor R1 is respectively connected to the control end of the first switch tube Q1 and the first end of the second resistor R2. A second end of the second resistor R2 is connected to the first end of the first switch tube Q1 and is connected to the first low-level potential -HVDD. A second end of the first switch tube Q1 is respectively connected to the first end of the first capacitor C1 and the first end of the third resistor R3 and serves as the output end of the first output unit. A second end of the first capacitor C1 is grounded GND. A second end of the third resistor R3 is used to connect to the first high-level potential +HVDD.

[0135] The second level clock signal includes at least one of a first low level potential and a first high level potential.

[0136] The first switch Q1 is a transistor, such as an NPN transistor. The first resistor R1 is a current-limiting resistor, preventing excessive base current from damaging the transistor and ensuring that the transistor operates in a saturated conduction state. The second resistor R2 ensures a constant voltage level at the moment the first switch Q1 is powered on, preventing unstable operation and enhancing the circuit's anti-interference capabilities. The third resistor R3 is a pull-up resistor.

[0137] The gate of the first switch Q1 is connected to a first control signal and is turned on or off by the first control signal. When the first switch Q1 is turned on, -HVDD is transmitted to the output end of the first output unit and output to the clock signal channel 100. When the first switch Q1 is turned off, +HVDD is transmitted to the output end of the first output unit through the pull-up resistor and output to the clock signal channel 100.

[0138] In this embodiment, by configuring the circuit of the first output unit to include the first switch Q1 , the first resistor R1 , the first capacitor C1 , the second resistor R2 , and the third resistor R3 , the output of the clock signal of the second level can be achieved.

[0139] In one embodiment, Figure 4 、 Figure 5 As shown, the first output unit further includes an electrostatic protection device D1 , a first end of the electrostatic protection device D1 is connected to the second end of the first switch tube, and a second end of the electrostatic protection device D1 is grounded GND.

[0140] The electrostatic protection device is a bidirectional electrostatic protection device, for example, a bidirectional voltage regulator diode, which can prevent external voltage interference and release static electricity.

[0141] In this embodiment, the anti-interference capability of the circuit is improved by providing an electrostatic protection device.

[0142] In one embodiment, Figure 4 As shown, the first input unit 111 includes: a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5, a sixth switch tube Q6, a fourth resistor R4, a sixth resistor R6, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and a twelfth resistor R12. The first end of the fourth resistor R4 is connected to the first end of the second switch tube Q2 and is used to connect to the external master device 30 (connected to the clock end SCL of the external master device). The second end of the fourth resistor R4 is connected to the power signal VCC1, and the control end of the second switch tube Q2 is connected to the power signal VCC1. The second end of the second switch tube Q2 is respectively connected to the first end of the sixth resistor R6 and the first end of the third switch tube Q3. The control end of the third switch tube Q3 is connected to the power signal VCC1. The second end of the third switch tube Q3 is respectively connected to the first end of the sixth resistor R6 and the first end of the third switch tube Q3. A first end of the eighth resistor R8 is connected to the control end of the fourth switch transistor Q4. The first end of the fourth switch transistor Q4 is grounded GND. The second end of the fourth switch transistor Q4 is respectively connected to the first end of the ninth resistor R9, the first end of the tenth resistor R10, and the control end of the fifth switch transistor Q5. The second end of the tenth resistor R10 is grounded GND. The first end of the fifth switch transistor Q5 is grounded GND. The second end of the fifth switch transistor Q5 is respectively connected to the first end of the twelfth resistor R12 and the control end of the sixth switch transistor Q6. The first end of the sixth switch transistor Q6 serves as the output end of the first input unit for outputting the first control signal. The second end of the sixth resistor R6, the second end of the eighth resistor R8, the second end of the ninth resistor R9, the second end of the twelfth resistor R12, and the second end of the sixth switch transistor Q6 are all connected to the power supply signal VCC1.

[0143] Exemplarily, the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, and the sixth switch tube Q6 are all MOS tubes, and the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, and the sixth switch tube Q6 are of the same type, for example, they may be NMOS, and the type of the sixth switch tube Q6 is different from the types of the other switch tubes, for example, it may be PMOS.

[0144] Here, the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, and the sixth switch tube Q6 are all NMOS tubes (they turn on when the voltage difference Vgs between the control terminal and the one end is greater than the threshold voltage), and the sixth switch tube Q6 is a PMOS tube (they turn on when the voltage difference Vgs between the control terminal and the one end is less than the threshold voltage).

[0145] When the external host device 30 inputs a low-level signal, the low-level signal is transmitted to the first terminal of the second switch Q2. The control terminal of the second switch Q2 is connected to the power signal VCC1, turning on the second switch Q2. The low-level signal is then transmitted to the first terminal of the third switch Q3. The control terminal of the third switch Q3 is connected to the power signal VCC1, turning on the third switch Q3. The low-level signal is then transmitted to the control terminal of the fourth switch Q4, turning off the fourth switch Q4. Because the fourth switch Q4 is off, the control terminal of the fifth switch Q5 is connected to the power signal VCC1. Since the first terminal of the fifth switch Q5 is grounded to GND, the fifth switch Q5 is turned on. Since the fifth switch Q5 is turned on, the low-level signal, with the first terminal of the fifth switch Q5 grounded to GND, is transmitted to the control terminal of the sixth switch Q6. Since the sixth switch Q6 is a PMOS transistor, the sixth switch Q6 is turned on. The power supply signal VCC1 at the second terminal of the sixth switch Q6 is transmitted to the control terminal of the first switch, so the first switch is turned on and transmits -HVDD to the output terminal of the first output unit, which is then output to the clock signal channel 100. In summary, when the external master device 30 inputs a low-level signal, the first switch Q2, the third switch Q3, the fifth switch Q5, and the sixth switch Q6 are turned on, while the fourth switch Q4 is turned off. -HVDD is transmitted to the output terminal of the first output unit and is then output to the clock signal channel 100. Similarly, when the external master device inputs a high-level signal, the first switch Q2, the third switch Q3, the fifth switch Q5, and the sixth switch Q6 are turned off, while the fourth switch Q4 is turned on. +HVDD is transmitted to the output terminal of the first output unit 112 through the pull-up resistor and is then output to the clock signal channel 100.

[0146] Among them, the fourth resistor R4, the sixth resistor R6, the eighth resistor R8, the tenth resistor R10, and the twelfth resistor R12 can ensure that the corresponding connected switching tubes have a fixed level at the moment of power-on, prevent the switching tubes from working in an unstable state, and enhance the anti-interference ability of the circuit.

[0147] In this embodiment, by setting the first input unit to include a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5, a sixth switch tube Q6, a fourth resistor R4, a sixth resistor R6, an eighth resistor R8, a tenth resistor R10, and a twelfth resistor R12, the high and low levels of the output second-level clock signal can be controlled.

[0148] In one embodiment, Figure 5 As shown, the first input unit 111 further includes: a fifth resistor R5, a seventh resistor R7, an eleventh resistor R11, and a thirteenth resistor R13, wherein:

[0149] A first end of the fifth resistor R5 is connected to the control end of the second switching tube Q2, a first end of the seventh resistor R7 is connected to the control end of the third switching tube Q3, a first end of the eleventh resistor R11 is connected to the second end of the fourth switching tube Q4, a second end of the eleventh resistor R11 is connected to the control end of the fifth transistor, a first end of the thirteenth resistor R13 is connected to the second end of the fifth switching tube Q5, a second end of the thirteenth resistor R13 is connected to the control end of the sixth switching tube Q6, and the second end of the fifth resistor R5 and the second end of the seventh resistor R7 are both connected to the power supply signal VCC1.

[0150] Exemplarily, the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, and the sixth switch tube Q6 are all transistors, and the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, and the sixth switch tube Q6 are of the same type, for example, they may be NPN transistors, and the type of the sixth switch tube Q6 is different from the types of the other switch tubes, for example, it may be a PNP transistor.

[0151] Among them, the fifth resistor R5, the seventh resistor R7, the ninth resistor R9, and the thirteenth resistor R13 are all current limiting resistors, which can prevent the base current of the transistor from being too large and burning the transistor, and secondly, make the transistor work in a saturated conduction state.

[0152] The working principle and process of the circuit of this embodiment are the same as those of the above embodiment and will not be described in detail.

[0153] In this embodiment, a specific circuit structure of a first input unit is provided, which can control the high and low levels of the output second-level clock signal.

[0154] In one embodiment, Figure 6 As shown, the first input unit 111 includes: a seventh switch tube Q7, an eighth switch tube Q8, a ninth switch tube Q9, a tenth switch tube Q10, a fourteenth resistor R14, a fifteenth resistor R15, a seventeenth resistor R17, an eighteenth resistor R18, a twentieth resistor R20, and a twenty-first resistor R21, wherein:

[0155] A first end of the fourteenth resistor R14, a first end of the fifteenth resistor R15, a first end of the seventh switch tube Q7, and a control end of the eighth switch tube Q8 are connected and used to connect to the external main device 30. A second end of the fourteenth resistor R14 is connected to the power signal VCC1, and a control end of the seventh switch tube Q7 is connected to the power signal VCC1. A second end of the seventh switch tube Q7 is respectively connected to the first end of the twentieth resistor R20, the first end of the ninth switch tube Q9, and the control end of the tenth switch tube Q10. A first end of the eighth switch tube Q8 is grounded GND, and a second end of the eighth switch tube Q8 is respectively connected to the seventeenth resistor R14. A first end of R17, a first end of the eighteenth resistor R18, and a control end of the ninth switch tube Q9 are connected. A second end of the eighteenth resistor R18 is grounded GND. A second end of the ninth switch tube Q9 is grounded GND. A first end of the tenth switch tube Q10 is connected to a first end of the twenty-first resistor R21. A second end of the tenth switch tube Q10 serves as an output end of the first input unit 111 for outputting a first control signal. A second end of the fifteenth resistor R15, a second end of the seventeenth resistor R17, a second end of the twentieth resistor R20, and a second end of the twenty-first resistor R21 are all connected to the power supply signal VCC1.

[0156] Among them, the seventh switch tube Q7, the eighth switch tube Q8, the ninth switch tube Q9, and the tenth switch tube Q10 are all MOS tubes, and the seventh switch tube Q7, the eighth switch tube Q8, and the ninth switch tube Q9 are of the same type, for example, they may be NMOS, and the tenth switch tube Q10 is of a different type from the other switch tubes, for example, it may be PMOS.

[0157] When the external master device 30 inputs a low-level signal, the first switch transistor, the seventh switch transistor Q7, the ninth switch transistor Q9, and the tenth switch transistor Q10 are turned on, and the eighth switch transistor Q8 is turned off. -HVDD is transmitted to the output terminal of the first output unit 112 and output to the clock signal channel 100. Similarly, when the external master device 30 inputs a high-level signal, the first switch transistor, the seventh switch transistor Q7, the ninth switch transistor Q9, and the tenth switch transistor Q10 are turned off, and the eighth switch transistor Q8 is turned on. +HVDD is transmitted to the output terminal of the first output unit 112 through the pull-up resistor and output to the clock signal channel 100. The principle of this conduction has been described in the above embodiment and will not be repeated here.

[0158] In this embodiment, a specific circuit structure of the first input unit 111 is provided, which can control the high and low levels of the output second-level clock signal.

[0159] In one embodiment, Figure 7 As shown, the first input unit 111 further includes: a sixteenth resistor R16 and a nineteenth resistor R19.

[0160] A first end of the sixteenth resistor R16 is connected to the control end of the seventh switch tube Q7 , a second end of the nineteenth resistor R19 is connected to the control end of the ninth switch tube Q9 , and a second end of the sixteenth resistor R16 is connected to the power signal VCC1 .

[0161] Exemplarily, the seventh switch tube Q7, the eighth switch tube Q8, the ninth switch tube Q9, and the tenth switch tube Q10 are all transistors, and the seventh switch tube Q7, the eighth switch tube Q8, and the ninth switch tube Q9 are of the same type, for example, they may be NPN transistors, and the type of the tenth switch tube Q10 is different from the types of the other switch tubes, for example, it may be a PNP transistor.

[0162] The sixteenth resistor R16 and the nineteenth resistor R19 are both current limiting resistors, which can prevent the base current of the transistor from being too large and burning the transistor, and secondly, make the transistor work in a saturated conduction state.

[0163] The working principle and process of the circuit of this embodiment are the same as those of the above embodiment and will not be described in detail.

[0164] In this embodiment, a specific circuit structure of the first input unit 111 is provided, which can control the high and low levels of the output second-level clock signal.

[0165] In one embodiment, Figure 8 As shown, the first input unit 111 includes: an eleventh switch tube Q11, a twelfth switch tube Q12, a twenty-second resistor R22, a twenty-third resistor R23, a twenty-fifth resistor R25, and a twenty-sixth resistor R26, wherein:

[0166] A first end of the twenty-second resistor R22, a first end of the twenty-third resistor R23, and a first end of the eleventh switch tube Q11 are connected and used to connect to the external main device 30. The control end of the eleventh switch tube Q11 is connected to the power signal VCC1. The second end of the eleventh switch tube Q11 is respectively connected to the control ends of the twenty-fifth resistor R25 and the twelfth switch tube Q12. The first end of the twelfth switch tube Q12 is connected to the twenty-sixth resistor R26. The second end of the twelfth switch tube Q12 serves as the output end of the first input unit 111 for outputting the first control signal. The second end of the twenty-second resistor R22, the second end of the twenty-third resistor R23, the second end of the twenty-fifth resistor R25, and the second end of the twenty-sixth resistor R26 are all connected to the power signal VCC1.

[0167] The eleventh switch transistor Q11 and the twelfth switch transistor Q12 are of different types and are both MOS transistors. The eleventh switch transistor Q11 can be, for example, an NMOS, and the twelfth switch transistor Q12 can be, for example, a PMOS.

[0168] When the external master device 30 inputs a low-level signal, the first switch transistor, the eleventh switch transistor Q11, and the twelfth switch transistor Q12 are turned on, and -HVDD is transmitted to the output terminal of the first output unit 112 and output to the clock signal channel 100. Similarly, when the external master device 30 inputs a high-level signal, the first switch transistor, the eleventh switch transistor Q11, and the twelfth switch transistor Q12 are turned off, and +HVDD is transmitted to the output terminal of the first output unit 112 through the pull-up resistor and output to the clock signal channel 100. The principle of this conduction has been described in the above embodiment and will not be repeated here.

[0169] In this embodiment, a specific circuit structure of the first input unit 111 is provided, which can control the high and low levels of the output second-level clock signal.

[0170] In one embodiment, Figure 9 As shown, the first input unit 111 further includes: a twenty-fourth resistor R24 ​​, a first end of the twenty-fourth resistor R24 ​​is connected to the control end of the eleventh switch tube Q11 , and a second end of the twenty-fourth resistor R24 ​​is connected to the power signal VCC1 .

[0171] The eleventh switch tube Q11 and the twelfth switch tube Q12 are of different types and are both transistors. The eleventh switch tube Q11 can be, for example, an NPN transistor, and the twelfth switch tube Q12 can be, for example, a PNP transistor.

[0172] The twenty-fourth resistor R24 ​​is a current-limiting resistor, which can prevent the base current of the transistor from being too large and burning the transistor, and secondly, allows the transistor to operate in a saturated conduction state.

[0173] In this embodiment, a specific circuit structure of the first input unit 111 is provided, which can control the high and low levels of the output second-level clock signal.

[0174] In one embodiment, Figure 10 As shown, the first data level conversion circuit 13 includes: a second input unit 131 and a second output unit 132, wherein:

[0175] An input terminal of the second input unit 131 is connected to the second output terminal of the switch circuit 12 . The second input unit 131 is configured to receive a data signal of a third level and output a second control signal according to the data signal of the third level.

[0176] Among them, the input end of the second input unit 131 is connected to the data signal of the third level, and outputs the second control signal according to the data signal of the third level. For example, the data signal of the third level is a digital signal, which includes a low level 0 and a high level 1. The second input unit 131 will output the corresponding second control signal (for example, also including a low level and a high level) according to whether the data signal of the third level is a low level or a high level.

[0177] The input end of the second output unit 132 is connected to the output end of the second input unit 131 , and the output end of the second output unit 132 is connected to the data signal channel 200 , and is configured to output a fourth-level data signal to the second level conversion circuit 20 according to the second control signal received from the second input unit 131 .

[0178] Among them, the fourth level data signal includes a low level -HVDD and a high level +HVDD (-HVDD can be -3.3V~-20V, +HVDD can be 3.3V~20V), and the second output unit 132 is connected to the second control signal. According to whether the second control signal is a low level or a high level, the corresponding output is a low level -HVDD or a high level +HVDD of the fourth level data signal.

[0179] In this embodiment, the first data level conversion circuit 13 includes a second input unit 131 and a second output unit 132 , thereby achieving conversion between a received data signal of the third level and an output data signal of the fourth level.

[0180] In one embodiment, Figure 11 As shown, the second output unit 132 includes: a thirteenth switch tube Q13, a second capacitor C2, a twenty-eighth resistor R28, and a twenty-ninth resistor R29, wherein:

[0181] The control end of the thirteenth switch tube Q13 and the first end of the twenty-eighth resistor R28 are connected to the output end of the second input unit 131. The second end of the twenty-eighth resistor R28 is connected to the first end of the thirteenth switch tube Q13 and is connected to the first low-level potential -HVDD. The second end of the thirteenth switch tube Q13 is respectively connected to the first end of the second capacitor C2 and the first end of the twenty-ninth resistor R29 and serves as the output end of the second output unit 132. The second end of the second capacitor C2 is grounded GND. The second end of the twenty-ninth resistor R29 is used to connect to the first high-level potential +HVDD.

[0182] The fourth level data signal includes at least one of a first low level potential and a first high level potential.

[0183] The thirteenth switch tube Q13 is a MOS tube, for example, an NMOS tube.

[0184] The gate of the thirteenth switch Q13 is connected to the first control signal and is turned on or off by the second control signal. When the thirteenth switch Q13 is turned on, -HVDD is transmitted to the output end of the second output unit 132 and output to the data signal channel 200. When the thirteenth switch Q13 is turned off, +HVDD is transmitted to the output end of the second output unit 132 through the pull-up resistor (the twenty-ninth resistor R29) and output to the clock signal channel 100.

[0185] In this embodiment, by configuring the second output unit 132 to include the thirteenth switch Q13 , the second capacitor C2 , the twenty-eighth resistor R28 , and the twenty-ninth resistor R29 , the output of the data signal at the fourth level can be achieved.

[0186] In one embodiment, Figure 12 As shown, the second output unit 132 also includes: a twenty-seventh resistor R27, a first end of the twenty-seventh resistor R27 is connected to the output end of the second control circuit, and a second end of the twenty-seventh resistor R27 is respectively connected to the control end of the thirteenth switch tube Q13 and the first end of the twenty-eighth resistor R28.

[0187] The thirteenth switch Q13 is a transistor, such as an NPN transistor. The twenty-seventh resistor R27 is a current limiting resistor that can prevent the base current of the transistor from being too large and burning the transistor, and secondly, allows the transistor to work in a saturated conduction state.

[0188] In this embodiment, by configuring the second output unit 132 to include the twenty-seventh resistor R27 , another circuit structure of the second output unit 132 is provided, which can implement the output of the fourth level data signal.

[0189] In one embodiment, Figure 11 、 Figure 12 As shown, the second output unit 132 further includes an electrostatic protection device D2 , a first end of the electrostatic protection device D2 is connected to the second end of the thirteenth switch tube Q13 , and a second end of the electrostatic protection device D2 is grounded GND.

[0190] The electrostatic protection device is a bidirectional electrostatic protection device, for example, a bidirectional voltage regulator diode, which can prevent external voltage interference and release static electricity.

[0191] In this embodiment, the anti-interference capability of the circuit is improved by providing an electrostatic protection device.

[0192] In one embodiment, Figure 11As shown, the second input unit 131 includes: a fourteenth switch tube Q14, a fifteenth switch tube Q15, a sixteenth switch tube Q16, a seventeenth switch tube Q17, an eighteenth switch tube Q18, a thirtieth resistor R30, a thirty-second resistor R32, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, and a thirty-eighth resistor R38, wherein:

[0193] A first end of the 30th resistor R30 is connected to a first end of the 14th switch tube Q14 and is used to be connected to the second output end of the switch circuit 12. A second end of the 30th resistor R30 is connected to the power signal VCC1. A control end of the 14th switch tube Q14 is connected to the power signal VCC1. A second end of the 14th switch tube Q14 is connected to a first end of the 32nd resistor R32 and a first end of the 15th switch tube Q15 respectively. A control end of the 15th switch tube Q15 is connected to the power signal VCC1. A second end of the 15th switch tube Q15 is connected to a first end of the 34th resistor R34 and a control end of the 16th switch tube Q16 respectively. A first end of the 16th switch tube Q16 is grounded GND. A second end of the 16th switch tube Q16 is connected to A first end of the thirty-fifth resistor R35, a first end of the thirty-sixth resistor R36, and a control end of the seventeenth switch Q17 are connected. A second end of the thirty-sixth resistor R36 is grounded to GND. A first end of the seventeenth switch Q17 is grounded to GND. A second end of the seventeenth switch Q17 is respectively connected to the first end of the thirty-eighth resistor R38 and the control end of the eighteenth switch Q18. The first end of the eighteenth switch Q18 serves as the output end of the second input unit 131 for outputting the first control signal. The second end of the thirty-second resistor R32, the second end of the thirty-fourth resistor R34, the second end of the thirty-fifth resistor R35, the second end of the thirty-eighth resistor R38, and the second end of the eighteenth switch Q18 are all connected to the power supply signal VCC1.

[0194] The fourteenth switch tube Q14 , the fifteenth switch tube Q15 , the sixteenth switch tube Q16 , the seventeenth switch tube Q17 , and the thirteenth switch tube Q13 are of the same type, and the eighteenth switch tube Q18 is of a different type from the other switch tubes.

[0195] Exemplarily, the fourteenth switch tube Q14, the fifteenth switch tube Q15, the sixteenth switch tube Q16, the seventeenth switch tube Q17, the thirteenth switch tube Q13, and the eighteenth switch tube Q18 are all MOS tubes, and the fourteenth switch tube Q14, the fifteenth switch tube Q15, the sixteenth switch tube Q16, the seventeenth switch tube Q17, and the thirteenth switch tube Q13 are of the same type, for example, they may be NMOS, and the type of the eighteenth switch tube Q18 is different from that of the other switch tubes, for example, it may be PMOS.

[0196] When the external master device inputs a low-level signal, the fourteenth switch transistor Q14, the fifteenth switch transistor Q15, the seventeenth switch transistor Q17, the thirteenth switch transistor Q13, and the eighteenth switch transistor Q18 are turned on, and the sixteenth switch transistor Q16 is turned off. -HVDD is transmitted to the output end of the second output unit 132 and output to the data signal channel 200. Similarly, when the external master device inputs a high-level signal, the fourteenth switch transistor Q14, the fifteenth switch transistor Q15, the seventeenth switch transistor Q17, the thirteenth switch transistor Q13, and the eighteenth switch transistor Q18 are turned off, and the sixteenth switch transistor Q16 is turned on. +HVDD is transmitted to the output end of the second output unit 132 through the pull-up resistor (twenty-ninth resistor R29) and output to the data signal channel 200.

[0197] Among them, the 30th resistor R30, the 32nd resistor R32, the 34th resistor R34, the 36th resistor R36, and the 38th resistor R38 can ensure that the corresponding connected switching tubes have a fixed voltage level at the moment of power-on, prevent the switching tubes from operating in an unstable state, and enhance the circuit's anti-interference ability.

[0198] In this embodiment, by setting the second input unit 131 to include: a fourteenth switch tube Q14, a fifteenth switch tube Q15, a sixteenth switch tube Q16, a seventeenth switch tube Q17, an eighteenth switch tube Q18, a thirtieth resistor R30, a thirty-second resistor R32, a thirty-fourth resistor R34, a thirty-sixth resistor R36, and a thirty-eighth resistor R38, the high and low levels of the output fourth level data signal can be controlled.

[0199] In one embodiment, Figure 12 As shown, the second input unit 131 further includes: a thirty-first resistor R31, a thirty-third resistor R33, a thirty-seventh resistor R37, and a thirty-ninth resistor R39, wherein:

[0200] A first end of the thirty-first resistor R31 is connected to the control end of the fourteenth switch transistor Q14. A first end of the thirty-third resistor R33 is connected to the control end of the fifteenth switch transistor Q15. A second end of the thirty-seventh resistor R37 is connected to the control end of the seventeenth switch transistor Q17. A first end of the thirty-ninth resistor R39 is respectively connected to the second end of the seventeenth switch transistor Q17 and the first end of the thirty-eighth resistor R38. A second end of the thirty-ninth resistor R39 is connected to the control end of the eighteenth switch transistor Q18. The second end of the thirty-first resistor R31 and the second end of the thirty-third resistor R33 are both connected to the power supply signal VCC1.

[0201] Exemplarily, the fourteenth switch tube Q14, the fifteenth switch tube Q15, the sixteenth switch tube Q16, the seventeenth switch tube Q17, the thirteenth switch tube Q13, and the eighteenth switch tube Q18 are all transistors, and the fourteenth switch tube Q14, the fifteenth switch tube Q15, the sixteenth switch tube Q16, the seventeenth switch tube Q17, and the thirteenth switch tube Q13 are of the same type, for example, they may be NPN transistors, and the type of the eighteenth switch tube is different from that of the other switch tubes, for example, it may be a PNP transistor.

[0202] Among them, the thirty-first resistor R31, the thirty-third resistor R33, the thirty-seventh resistor R37, and the thirty-ninth resistor R39 are all current limiting resistors, which can prevent the base current of the switching tube from being too large and burning the switching tube, and secondly allow the switching tube to operate in a saturated conduction state.

[0203] The working principle and process of the circuit of this embodiment are the same as those of the above embodiment and will not be described in detail.

[0204] In this embodiment, a specific circuit structure of the second input unit 131 is provided, which can control the high and low levels of the outputted fourth-level data signal.

[0205] In one embodiment, Figure 13 As shown, the second input unit 131 includes: a 19th switch tube Q19, a 20th switch tube Q20, a 21st switch tube Q21, a 22nd switch tube Q22, a 40th resistor R40, a 41st resistor R41, a 43rd resistor R43, a 44th resistor R44, a 46th resistor R46, and a 47th resistor R47, wherein:

[0206] A first end of the 40th resistor R40, a first end of the 41st resistor R41, a first end of the 19th switch tube Q19, and a control end of the 20th switch tube Q20 are connected and used to be connected to the second output end of the switch circuit 12. A second end of the 40th resistor R40 is connected to the power signal VCC1, and a control end of the 19th switch tube Q19 is connected to the power signal VCC1. A second end of the 19th switch tube Q19 is respectively connected to the first end of the 46th resistor R46, the first end of the 21st switch tube Q21, and the control end of the 22nd switch tube Q22. A first end of the 20th switch tube Q20 is grounded GND, and a second end of the 20th switch tube Q20 is respectively connected to the 46th resistor R46, the first end of the 21st switch tube Q21, and the control end of the 22nd switch tube Q22. A first end of the forty-third resistor R43, a first end of the forty-fourth resistor R44, and a control end of the twenty-first switch tube Q21 are connected; a second end of the forty-fourth resistor R44 is grounded GND; a second end of the twenty-first switch tube Q21 is grounded GND; a first end of the twenty-second switch tube Q22 is connected to a first end of the forty-seventh resistor R47; a second end of the twenty-second switch tube Q22 serves as an output end of the second input unit 131 for outputting the first control signal; a second end of the forty-first resistor R41, a second end of the forty-third resistor R43, a second end of the forty-sixth resistor R46, and a second end of the forty-seventh resistor R47 are all connected to the power supply signal VCC1.

[0207] Among them, the nineteenth switch tube Q19, the twentieth switch tube Q20, the twenty-first switch tube Q21, and the twenty-second transistor are all MOS tubes. The nineteenth switch tube Q19, the twentieth switch tube Q20, and the twenty-first switch tube Q21 are of the same type, for example, they may be NMOS, and the type of the twenty-second switch tube Q22 is different from the types of the other switch tubes, for example, it may be PMOS.

[0208] When the external master device inputs a low-level signal, the thirteenth switch Q13, the nineteenth switch Q19, the twenty-first switch Q21, and the twenty-second transistor are turned on, while the twentieth switch Q20 is turned off. -HVDD is transmitted to the output terminal of the second output unit 132 and output to the data signal channel 200. Similarly, when the external master device inputs a high-level signal, the thirteenth switch Q13, the nineteenth switch Q19, the twenty-first switch Q21, and the twenty-second transistor are turned off, while the twentieth switch Q20 is turned on. +HVDD is transmitted to the output terminal of the second output unit 132 through the pull-up resistor (twenty-ninth resistor R29) and output to the data signal channel 200. The principle of this conduction has been described in the above embodiment and will not be repeated here.

[0209] In this embodiment, a specific circuit structure of the second input unit 131 is provided, which can control the high and low levels of the outputted fourth-level data signal.

[0210] In one embodiment, Figure 14As shown, the second input unit 131 includes: a forty-second resistor R42 and a forty-fifth resistor R45. The first end of the forty-second resistor R42 is connected to the control end of the nineteenth switch tube Q19, the second end of the forty-fifth resistor R45 is connected to the control end of the twenty-first switch tube Q21, and the second end of the forty-second resistor R42 is connected to the power signal VCC1.

[0211] Exemplarily, the nineteenth switch tube Q19, the twentieth switch tube Q20, the twenty-first switch tube Q21, and the twenty-second transistor are all transistors, and the nineteenth switch tube Q19, the twentieth switch tube Q20, and the twenty-first switch tube Q21 are of the same type, for example, they may be NPN transistors, and the type of the twenty-second transistor is different from that of the other switch tubes, for example, it may be a PNP transistor.

[0212] Among them, the forty-second resistor R42 and the forty-fifth resistor R45 are both current-limiting resistors, which can prevent the base current of the transistor from being too large and burning the transistor, and secondly allow the transistor to operate in a saturated conduction state.

[0213] The working principle and process of the circuit of this embodiment are the same as those of the above embodiment and will not be described in detail.

[0214] In this embodiment, a specific circuit structure of the second input unit 131 is provided, which can control the high and low levels of the outputted fourth-level data signal.

[0215] In one embodiment, Figure 15 As shown, the second input unit 131 includes: a twenty-third switch tube Q23, a twenty-fourth switch tube Q24, a forty-eighth resistor R48, a forty-ninth resistor R49, a fifty-first resistor R51, and a fifty-second resistor R52, wherein:

[0216] A first end of the forty-eighth resistor R48, a first end of the forty-ninth resistor R49, and a first end of the twenty-third switch tube Q23 are connected and used to be connected to the second output end of the switch circuit 12. The control end of the twenty-third switch tube Q23 is connected to the power signal VCC1. The second end of the twenty-third switch tube Q23 is respectively connected to the control ends of the fifty-first resistor R51 and the twenty-fourth switch tube Q24. The first end of the twenty-fourth switch tube Q24 is connected to the fifty-second resistor R52. The second end of the twenty-fourth switch tube Q24 serves as the output end of the second input unit 131 for outputting the first control signal. The second end of the forty-eighth resistor R48, the second end of the forty-ninth resistor R49, the second end of the fifty-first resistor R51, and the second end of the fifty-second resistor R52 are all connected to the power signal VCC1.

[0217] The twenty-third switch transistor Q23 and the twenty-fourth switch transistor Q24 are of different types and are both MOS transistors. The twenty-third switch transistor Q23 may be, for example, an NMOS, and the twenty-fourth switch transistor Q24 may be, for example, a PMOS.

[0218] When the external master device inputs a low-level signal, the thirteenth switch Q13, the twenty-third switch Q23, and the twenty-fourth switch Q24 are turned on, and -HVDD is transmitted to the output terminal of the second output unit 132 and output to the data signal channel 200. Similarly, when the external master device inputs a high-level signal, the thirteenth switch Q13, the twenty-third switch Q23, and the twenty-fourth switch Q24 are turned off, and +HVDD is transmitted to the output terminal of the second output unit 132 and output to the data signal channel 200. The principle of this conduction has been described in the above embodiment and will not be repeated here.

[0219] In this embodiment, a specific circuit structure of the second input unit 131 is provided, which can control the high and low levels of the outputted fourth-level data signal.

[0220] In one embodiment, Figure 16 As shown, the second input unit 131 further includes: a 50th resistor R50, a first end of the 50th resistor R50 is connected to the control end of the 23rd switch tube Q23, and a second end of the 50th resistor R50 is connected to the power signal VCC1.

[0221] The twenty-third switch Q23 and the twenty-fourth switch Q24 are of different types and are both transistors. The twenty-third switch Q23 can be an NPN transistor, and the twenty-fourth switch Q24 can be a PNP transistor.

[0222] The fifty-fourth resistor R54 is a current-limiting resistor, which can prevent the base current of the transistor from being too large and burning the transistor, and secondly, allows the transistor to operate in a saturated conduction state.

[0223] In this embodiment, a specific circuit structure of the second input unit 131 is provided, which can control the high and low levels of the outputted fourth-level data signal.

[0224] In one embodiment, Figure 17 As shown, the second data level conversion circuit includes: a twenty-fifth switch tube Q25, a twenty-sixth switch tube Q26, a fifty-third resistor R53, a fifty-fourth resistor R54, a fifty-fifth resistor R55, and a fifty-sixth resistor R56, wherein:

[0225] A first end of the twenty-fifth switch transistor Q25 is connected to the first end of the fifty-third resistor R53 and to the second input end of the switch circuit 12. The second end of the fifty-third resistor R53 is connected to the power signal VCC1. The second end of the twenty-fifth switch transistor Q25 is connected to the ground GND. The control end of the twenty-fifth switch transistor Q25 is respectively connected to the first end of the fifty-fourth resistor R54, the first end of the fifty-fifth resistor R55, and the first end of the twenty-sixth switch transistor Q26. The second end of the fifty-fourth resistor R54 and the second end of the fifty-fifth resistor R55 are connected to the power signal VCC1. The second end of the twenty-sixth switch transistor Q26 is connected to the ground GND. The control end of the twenty-sixth switch transistor Q26 is connected to the first end of the fifty-sixth resistor R56. The second end of the fifty-sixth resistor R56 serves as the fourth input end of the second data level conversion circuit.

[0226] For example, the twenty-fifth switch tube Q25 and the twenty-sixth switch tube Q26 may be NPN transistors. Figure 18 As shown, the twenty-fifth switch tube Q25 and the twenty-sixth switch tube Q26 can be NMOS tubes.

[0227] The second end of the fifty-sixth resistor R56 serves as the fourth input of the second data level conversion circuit and is connected to the data signal channel 200. When the second end of the fifty-sixth resistor R56 receives the low-level -HVDD of the fourth-level data signal through the data signal channel 200, the twenty-sixth switch Q26 is off and the twenty-fifth switch Q25 is on. At this time, the second input of the switch circuit 12 is connected to the first end of the twenty-fifth switch Q25, and the second input of the switch circuit 12 is grounded to GND through the second end of the twenty-fifth switch Q25. The second input of the switch circuit 12 receives the low-level signal. When the second end of the fifty-sixth resistor R56 receives the high-level +HVDD of the fourth-level data signal through the data signal channel 200, the twenty-sixth switch Q26 is on and the twenty-fifth switch Q25 is off. The second input of the switch circuit 12 receives the power supply signal VCC1, i.e., a high-level signal, through the pull-up resistor (the fifty-third resistor R53). This achieves conversion of the fourth-level data signal to the third-level data signal (0 to the power supply signal VCC1).

[0228] The turn-on voltage of the twenty-sixth switch Q26 is approximately 0.7V. Therefore, when a data signal of the fourth level (-HVDD to +HVDD) is input, an external interference voltage needs to provide an interference voltage with an amplitude of 0.7V+HVDD (when the data signal of the fourth level is -HVDD), or an interference voltage with an amplitude of HVDD-0.7V (when the data signal of the fourth level is +HVDD) in order to affect the conduction of the twenty-sixth switch Q26. Since HVDD is a level with a larger amplitude after conversion, the external interference voltage is unlikely to reach an amplitude of 0.7V+HVDD or HVDD-0.7V. Moreover, an interference voltage with an amplitude less than 0.7V+HVDD or HVDD-0.7V will not interfere with the conduction state of the twenty-sixth switch Q26. Therefore, this receiving circuit has a strong anti-interference capability.

[0229] The fifty-sixth resistor R56 and the fifty-fourth resistor R54 are current-limiting resistors of the switching tube, which prevent the base current of the switching tube from being too large and burning the switching tube. Secondly, they allow the switching tube to operate in a saturated conduction state.

[0230] In this embodiment, a circuit structure of a second data level conversion circuit is provided, which can realize conversion between a third-level data signal and a fourth-level data signal and has a strong anti-interference capability.

[0231] In one embodiment, Figure 19 As shown, the switch circuit includes: a switch chip U1, a third capacitor C3, wherein:

[0232] The first end of the third capacitor C3 is connected to the second pin of the switch chip U1 and is connected to the power supply signal VCC1. The second end of the third capacitor C3 is connected to the third pin of the switch chip U1 and is connected to the ground GND. The first pin of the switch chip U1 is connected to the external control signal SELECT as a control end. The fourth pin of the switch chip U1 is connected to the fourth output end of the second data level conversion circuit as a second input end. The fifth pin of the switch chip U1 is connected to the external main device as a data transceiver end. The sixth pin of the switch chip U1 is connected to the third input end of the first data level conversion circuit as a second output end.

[0233] The first pin of the switch chip U1 is connected to the external control signal SELECT. Under the control of the external control signal SELECT, the fourth pin and the fifth pin are turned on, or the sixth pin and the fifth pin are turned on.

[0234] For example, when the first pin is connected to the external control signal SELECT=0, the fourth pin and the fifth pin are turned on, and the external master device reads the data signal of the external slave device transmitted from the second data level conversion circuit. When the first pin is connected to the external control signal SELECT=1, the sixth pin and the fifth pin are turned on, and the external master device sends the data signal to the external slave device through the first data level conversion circuit.

[0235] In this embodiment, by providing a switch circuit including the switch chip U1 and the third capacitor C3, it is possible to control whether the external host device sends or receives data, thereby avoiding the deadlock problem at the data transceiver end of the external host device.

[0236] In one embodiment, Figure 20 As shown, the second level conversion circuit 20 includes: a second clock level conversion circuit 21, a third data level conversion circuit 22, and a fourth data level conversion circuit 23, wherein:

[0237] The second clock level conversion circuit 21 includes a fifth input terminal and a fifth output terminal. The fifth input terminal is connected to the clock signal channel 100, and the fifth output terminal is used to connect to the external slave device 40. The second clock level conversion circuit 21 is used to convert the received second-level clock signal into a fifth-level clock signal and output it through the fifth output terminal.

[0238] The amplitude of the second-level clock signal can be -HVDD to +HVDD (-HVDD can be -3.3V to -20V, and +HVDD can be 3.3V to 20V). The second-level clock signal has a larger amplitude and stronger driving and anti-interference capabilities, so the length of the clock signal channel 100 can be longer, for example, exceeding 1m. The amplitude of the fifth-level clock signal can be 0V to VCC2 (VCC2 can be 1.8V to 5.5V).

[0239] The third data level conversion circuit 22 includes a sixth input terminal and a sixth output terminal. The sixth input terminal is connected to the data signal channel 200, and the sixth output terminal is used to connect to the external slave device 40. The third data level conversion circuit 22 is used to convert the received fourth-level data signal into a sixth-level data signal and output it through the sixth output terminal.

[0240] The amplitude of the fourth level data signal may be -HVDD to +HVDD (-HVDD may be -3.3V to -20V, +HVDD may be 3.3V to 20V), and the amplitude of the sixth level data signal may be 0V to VCC2 (VCC2 may be 1.8V to 5.5V).

[0241] The fourth data level conversion circuit 23 includes a seventh input terminal and a seventh output terminal. The connection node between the seventh input terminal and the sixth output terminal is connected to the external slave device 40, and the connection node between the seventh output terminal and the sixth input terminal is connected to the data signal channel 200. The fourth data level conversion circuit 23 is used to receive a sixth-level data signal sent by the external slave device 40, and convert the sixth-level data signal into a fourth-level data signal and output it through the seventh output terminal.

[0242] In this embodiment, the second level conversion circuit 20 includes a second clock level conversion circuit 21, a third data level conversion circuit 22, and a fourth data level conversion circuit 23, thereby realizing the reception and level conversion of clock signals, and realizing the reception and level conversion of data signals.

[0243] In one embodiment, Figure 21 As shown, the second clock level conversion circuit includes: a twenty-seventh switch tube Q27, a twenty-eighth switch tube Q28, a fifty-seventh resistor R57, a fifty-eighth resistor R58, a fifty-ninth resistor R59, a sixtieth resistor R60, a sixtieth resistor R61, and a sixtieth resistor R62, wherein:

[0244] A first end of the fifty-seventh resistor R57 is connected to the first end of the fifty-eighth resistor R58 and is used to receive a clock signal of the second level. A second end of the fifty-seventh resistor R57 is connected to the first end of the fifty-eighth resistor R58 and is connected to the first high-level potential. A second end of the fifty-eighth resistor R58 is connected to the control end of the twenty-seventh switch Q27. A first end of the twenty-seventh switch Q27 is connected to the first end of the twenty-eighth switch Q28 and is connected to ground GND. A second end of the twenty-seventh switch Q27 is connected to the first end of the fifty-ninth resistor R59, the first end of the sixtieth resistor R60, and the first end of the sixtieth resistor R61, respectively. A second end of the fifty-ninth resistor R59 and a second end of the sixtieth resistor R60 are connected to the power supply signal VCC2. A second end of the sixtieth resistor R61 is connected to the control end of the twenty-eighth switch Q28. A second end of the twenty-eighth switch Q28 is connected to the first end of the sixtieth resistor R62 and serves as an output end of the second clock level conversion circuit. A second end of the sixtieth resistor R62 is connected to the power supply signal VCC2.

[0245] For example, the twenty-seventh switch tube Q27 and the twenty-eighth switch tube Q28 may be NPN transistors. Figure 22 As shown, the twenty-seventh switch tube Q27 and the twenty-eighth switch tube Q28 can be NMOS tubes.

[0246] The first end of the fifty-seventh resistor R57 serves as the fifth input of the second clock level conversion circuit and is connected to the clock signal channel 100. When the first end of the fifty-seventh resistor R57 receives the low-level -HVDD of the second-level clock signal through the clock signal channel 100, the twenty-seventh switch Q27 is off, the twenty-eighth switch Q28 is on, and the external slave device 40 is connected to ground GND via the twenty-eighth switch Q28. The external slave device 40 receives the low-level 0 signal of the fifth-level clock signal. When the first end of the fifty-seventh resistor R57 receives the high-level +HVDD of the second-level clock signal through the clock signal channel 100, the twenty-seventh switch Q27 is on, the twenty-eighth switch Q28 is off, and the external slave device 40 receives the power supply signal VCC2, i.e., the high-level signal of the fifth-level clock signal, through the pull-up resistor (the sixty-second resistor R62). This achieves conversion from the second-level clock signal to the fifth-level clock signal (0 to the power supply signal VCC2).

[0247] Among them, the turn-on voltage of the twenty-seventh switch tube Q27 is approximately 0.7V. Therefore, when the second-level clock signal (-HVDD to +HVDD) is connected, in order for an external interference voltage to affect the conduction of the twenty-seventh switch tube Q27, it is necessary to provide an interference voltage with an amplitude of 0.7V+HVDD (when the second-level clock signal is -HVDD), or it is necessary to provide an interference voltage with an amplitude of HVDD-0.7V (when the second-level clock signal is +HVDD). Since HVDD is a level with a larger amplitude after conversion, it is difficult for the external interference voltage to reach an amplitude of 0.7V+HVDD or HVDD-0.7V. Moreover, an interference voltage with an amplitude less than 0.7V+HVDD or HVDD-0.7V will not interfere with the conduction state of the twenty-seventh switch tube Q27. Therefore, this receiving circuit has a strong anti-interference capability.

[0248] The fifty-eighth resistor R58 and the sixty-first resistor R61 are current-limiting resistors of the switching tube, which prevent the base current of the switching tube from being too large and burning the switching tube. Secondly, they allow the switching tube to operate in a saturated conduction state.

[0249] In this embodiment, a circuit structure of a second clock level conversion circuit is provided, which can realize conversion between a second-level clock signal and a fifth-level clock signal and has a strong anti-interference capability.

[0250] In one embodiment, Figure 23 As shown, the third data level conversion circuit includes: a twenty-ninth switch tube Q29, a thirtieth switch tube Q30, a sixty-third resistor R63, a sixty-fourth resistor R64, a sixty-fifth resistor R65, a sixty-sixth resistor R66, a sixty-seventh resistor R67, a sixty-eighth resistor R68, and a first voltage stabilizing diode D3, wherein:

[0251] A first end of the sixty-third resistor R63 is connected to a first end of the sixty-fourth resistor R64 and is configured to receive a data signal of the fourth level. A second end of the sixty-third resistor R63 is connected to a first high-level potential. A second end of the sixty-fourth resistor R64 is connected to the control end of the twenty-ninth switch Q29. A first end of the twenty-ninth switch Q29 is connected to a first end of the thirtieth switch Q30 and to ground GND. A second end of the twenty-ninth switch Q29 is connected to a first end of a sixty-fifth resistor R65, a first end of a sixty-sixth resistor R66, and a first end of a sixty-seventh resistor R67, respectively. The second ends of the sixty-fifth resistor R65 and the second ends of the sixty-sixth resistor R66 are connected to the power supply signal VCC2. A second end of the sixty-seventh resistor R67 is connected to the control end of the thirtieth switch Q30. A second end of the thirtieth switch Q30 is connected to the anode of the first Zener diode D3. The cathode of the first Zener diode D3 is connected to a first end of a sixty-eighth resistor R68 and serves as an output end of the third data level conversion circuit. A second end of the sixty-eighth resistor R68 is connected to the power supply signal VCC2.

[0252] For example, the twenty-ninth switch tube Q29 and the thirtieth switch tube Q30 may be NPN transistors. Figure 24 As shown, the twenty-ninth switch tube Q29 and the thirtieth switch tube Q30 can be NMOS tubes.

[0253] The first end of the sixty-third resistor R63 serves as the sixth input of the third data level conversion circuit and is connected to the data signal channel 200. When the first end of the sixty-third resistor R63 receives the low-level -HVDD signal of the fourth-level data signal through the data signal channel 200, the twenty-ninth switch Q29 is off, the thirtieth switch Q30 is on, and the voltage received by the external slave device 40 is the voltage of the first Zener diode D3 (approximately 0.4V), i.e., the low-level signal of the sixth-level data signal. When the first end of the sixty-third resistor R63 receives the high-level +HVDD signal of the fourth-level data signal through the data signal channel 200, the twenty-ninth switch Q29 is on, the thirtieth switch Q30 is off, and the external slave device 40 receives the power supply signal VCC2, i.e., the high-level signal of the sixth-level data signal, through the pull-up resistor (the sixty-eighth resistor R68). This achieves conversion from the fourth-level data signal to the sixth-level data signal (0 to the power supply signal VCC2).

[0254] Among them, the turn-on voltage of the twenty-ninth switch tube Q29 is approximately 0.7V. Therefore, when the fourth level data signal (-HVDD to +HVDD) is connected, if an external interference voltage wants to affect the conduction of the twenty-ninth switch tube Q29, it is necessary to provide an interference voltage with an amplitude of 0.7V+HVDD (when the fourth level data signal is -HVDD), or it is necessary to provide an interference voltage with an amplitude of HVDD-0.7V (when the fourth level data signal is +HVDD). Since HVDD is a level with a larger amplitude after conversion, it is difficult for the external interference voltage to reach an amplitude of 0.7V+HVDD or HVDD-0.7V. Moreover, an interference voltage with an amplitude less than 0.7V+HVDD or HVDD-0.7V will not interfere with the conduction state of the twenty-ninth switch tube Q29. Therefore, this receiving circuit has a strong anti-interference capability.

[0255] Resistors R64 and R67 act as current-limiting resistors for the switching transistors, preventing excessive base current from damaging them and ensuring they operate in a saturated conduction state. Resistors R63 and R66 ensure a constant voltage level at the instant the switching transistors are powered on, preventing unstable operation and enhancing the circuit's anti-interference capabilities. Resistors R68 act as current-limiting resistors for the first Zener diode D3, ensuring the output voltage of the first Zener diode D3 is 0.4V.

[0256] In this embodiment, a circuit structure of a third data level conversion circuit is provided, which can realize conversion between a fourth-level data signal and a sixth-level data signal and has a strong anti-interference capability.

[0257] In one embodiment, Figure 25 As shown, the third data level conversion circuit includes: a 31st switch tube Q31, a 32nd switch tube Q32, a 69th resistor R69, a 70th resistor R70, a 71st resistor R71, a 72nd resistor R72, a 73rd resistor R73, a 74th resistor R74, and a first Schottky diode D4, wherein:

[0258] A first end of the sixty-ninth resistor R69 is connected to the first end of the seventieth resistor R70 and is configured to receive a data signal of the fourth level. A second end of the sixty-ninth resistor R69 is connected to the first end of the seventieth resistor R70 and is configured to receive a data signal of the fourth level. A second end of the sixty-ninth resistor R69 is connected to the first end of the seventieth resistor R70 and is configured to receive a first high-level potential. A second end of the seventieth resistor R70 is connected to the control end of the thirty-first switch Q31. A first end of the thirty-first switch Q31 is connected to the cathode of the first Schottky diode D4 and to ground GND. A second end of the thirty-first switch Q31 is connected to the first end of the seventieth resistor R71, the first end of the seventieth resistor R72, and the first end of the seventieth resistor R73, respectively. The second end of the seventieth resistor R71 and the second end of the seventieth resistor R72 are connected to the power supply signal VCC2. A second end of the seventieth resistor R73 is connected to the control end of the thirty-second switch Q32. A first end of the thirty-second switch Q32 is connected to the anode of the first Schottky diode D4. A second end of the thirty-second switch Q32 is connected to the first end of the seventieth resistor R74 and serves as an output end of the third data level conversion circuit. A second end of the seventieth resistor R74 is connected to the power supply signal VCC2.

[0259] For example, the thirty-first switch tube Q31 and the thirty-second switch tube Q32 may be NPN transistors. Figure 26 As shown, the thirty-first switch transistor Q31 and the thirty-second switch transistor Q32 can be NMOS transistors.

[0260] The first Schottky diode D4 has a turn-on voltage of 0.3-0.4V. Since a Zener diode requires power to operate, a Schottky diode can operate without power. Therefore, it can be placed between the 32nd switch Q32 and ground GND. The control terminal resistor of the 32nd switch Q32 can generate a turn-on voltage of 0.3-0.4V.

[0261] The first end of the 70th resistor R70 serves as the sixth input end of the third data level conversion circuit and is connected to the data signal channel 200. When the first end of the 70th resistor R70 receives the low level -HVDD of the fourth level data signal through the data signal channel 200, the 31st switch Q31 is off, the 32nd switch Q32 is on, and the voltage received by the external slave device 40 is the voltage of the first Schottky diode D4 (approximately 0.3-0.4V), i.e., the low level signal of the sixth level data signal. When the first end of the 70th resistor R70 receives the high level +HVDD of the fourth level data signal through the data signal channel 200, the 31st switch Q31 is on, the 32nd switch Q32 is off, and the external slave device 40 receives the power supply signal VCC2, i.e., the high level signal of the sixth level data signal, through the pull-up resistor (the 74th resistor R74). This achieves conversion of the fourth level data signal to the sixth level data signal (0 to the power supply signal VCC2).

[0262] In this embodiment, a circuit structure of a third data level conversion circuit is provided, which can realize conversion between a fourth-level data signal and a sixth-level data signal and has a strong anti-interference capability.

[0263] In one embodiment, Figure 27 As shown, the fourth data level conversion circuit includes: a 33rd switch tube Q33, a 34th switch tube Q34, a 35th switch tube Q35, a 36th switch tube Q36, a 75th resistor R75, a 77th resistor R77, a 79th resistor R79, an 81st resistor R81, an 82nd resistor R82, and a second voltage stabilizing diode D5, wherein:

[0264] The first end of the thirty-third switch transistor Q33 serves as the output end of the fourth data level conversion circuit. The second end of the thirty-third switch transistor Q33 is connected to the first end of the seventy-fifth resistor R75 and is connected to the first low-level potential. The control end of the thirty-third switch transistor Q33 is respectively connected to the second end of the seventy-fifth resistor R75 and the first end of the thirty-fourth switch transistor Q34. The second end of the thirty-fourth switch transistor Q34 is connected to the first end of the seventy-seventh resistor R77. The control end of the thirty-fourth switch transistor Q34 is respectively connected to the first end of the seventy-ninth resistor R79 and the first end of the thirty-fifth switch transistor Q35. The control end is connected to the power supply signal VCC2. The second end of the thirty-fifth switch transistor Q35 is respectively connected to the first end of the eighty-first resistor R81 and the first end of the thirty-sixth switch transistor Q36. The control end of the thirty-sixth switch transistor Q36 is respectively connected to the first end of the eighty-second resistor R82 and the cathode of the second Zener diode D5. The anode of the second Zener diode D5 is grounded GND. The second end of the seventy-seventh resistor R77, the second end of the seventy-ninth resistor R79, and the second end of the eighty-first resistor R81 are all connected to the power supply signal VCC2. The second end of the thirty-sixth switch transistor Q36 serves as the input end of the fourth data level conversion circuit.

[0265] Among them, the thirty-third switch tube Q33, the thirty-fourth switch tube Q34, the thirty-fifth switch tube Q35, and the thirty-sixth switch tube Q36 are all MOS tubes. The thirty-third switch tube Q33, the thirty-fifth switch tube Q35, and the thirty-sixth switch tube Q36 are of the same type, for example, they may be NMOS. The type of the thirty-fourth switch tube Q34 is different from the types of the other switch tubes, for example, it may be PMOS.

[0266] Among them, since the seventh input end of the fourth data level conversion circuit is connected to the sixth output end of the third data level conversion circuit and is connected to the external slave device 40, the second end of the thirty-sixth switch tube Q36 serves as the seventh input end of the fourth data level conversion circuit and is respectively connected to the sixth output end of the third data level conversion circuit and the external slave device 40, and the first end of the thirty-third switch tube Q33 serves as the seventh output end of the fourth data level conversion circuit and is connected to the data signal channel 200.

[0267] When the second end of the thirty-sixth switch tube Q36, i.e., the seventh input end of the fourth data level conversion circuit, receives a low-level signal (e.g., 0.4 V) sent from the sixth output end of the third data level conversion circuit, this signal is a low-level signal sent by the external master device and received by the third data level conversion circuit. The thirty-third switch tube Q33, the thirty-fourth switch tube Q34, the thirty-fifth switch tube Q35, and the thirty-sixth switch tube Q36 are not turned on, and the signal at the seventh output end of the fourth data level conversion circuit remains unchanged. In other words, the signal output by the fourth data level conversion circuit is not affected by the signal output by the third data level conversion circuit.

[0268] When the external slave device 40 inputs a low-level signal of the sixth-level data signal to the second terminal of the thirty-sixth switch Q36, the thirty-third, thirty-fourth, thirty-fifth, and thirty-sixth switches Q33, Q34, Q35, and Q36 are turned on, and -HVDD is transmitted to the data signal channel 200 via the thirty-third switch Q33. When the external slave device 40 inputs a high-level signal of the sixth-level data signal to the second terminal of the thirty-sixth switch Q36, the thirty-third, thirty-fourth, thirty-fifth, and thirty-sixth switches Q33, Q34, Q35, and Q36 are turned off, and +HVDD is transmitted to the data signal channel 200 via the pull-up resistor (the sixty-third resistor R63). This achieves conversion between the sixth-level data signal transmitted by the external slave device 40 and the fourth-level data signal (-HVDD to +HVDD).

[0269] Exemplarily, the eighty-second resistor R82 is a current-limiting resistor of the second voltage-stabilizing diode D5 , and the output voltage of the second voltage-stabilizing diode D5 is 0.8V.

[0270] In this embodiment, a fourth data level conversion circuit is provided. This circuit structure can convert data signals at the sixth level into data signals at the fourth level and has strong anti-interference capabilities. Furthermore, the fourth data level conversion circuit does not respond to signals output by the third data level conversion circuit, but only to signals sent from the external slave device 40. This prevents the fourth data level conversion circuit from being affected by the third data level conversion circuit, thus resolving the latch-up issue.

[0271] In one embodiment, Figure 28 As shown, the fourth data level conversion circuit further includes: a seventy-sixth resistor R76, a seventy-eighth resistor R78, an eightieth resistor R80, and an eighty-third resistor R83, wherein:

[0272] A first end of the seventy-sixth resistor R76 is respectively connected to the control end of the thirty-third switch tube Q33 and the second end of the seventy-fifth resistor R75. A second end of the seventy-sixth resistor R76 is respectively connected to the first end of the thirty-fourth switch tube Q34. A first end of the seventy-eighth resistor R78 is respectively connected to the control end of the thirty-fourth switch tube Q34. A second end of the seventy-eighth resistor R78 is respectively connected to the first end of the seventy-ninth resistor R79 and the first end of the thirty-fifth switch tube Q35. A first end of the eightieth resistor R80 is connected to the control end of the thirty-fifth switch tube Q35. A second end of the eightieth resistor R80 is connected to the power supply signal VCC2. A first end of the eighty-third resistor R83 is connected to the control end of the thirty-sixth switch tube Q36. A second end of the eighty-third resistor R83 is respectively connected to the first end of the eighty-second resistor R82 and the cathode of the second Zener diode D5.

[0273] Among them, the thirty-third switch tube Q33, the thirty-fourth switch tube Q34, the thirty-fifth switch tube Q35, and the thirty-sixth switch tube Q36 are all transistors. The thirty-third switch tube Q33, the thirty-fifth switch tube Q35, and the thirty-sixth switch tube Q36 are of the same type, for example, they can be NPN transistors. The type of the thirty-fourth switch tube Q34 is different from the types of the other switch tubes, for example, it can be a PNP transistor.

[0274] Among them, the seventy-sixth resistor R76, the seventy-eighth resistor R78, the eightieth resistor R80, and the eighty-third resistor R83 are all current limiting resistors, which can prevent the base current of the transistor from being too large and burning the transistor, and secondly allow the transistor to operate in a saturated conduction state.

[0275] The working principle and process of the circuit of this embodiment are the same as those of the above embodiment and will not be described in detail.

[0276] In this embodiment, a circuit structure of a fourth data level conversion circuit is provided, which can realize conversion between a sixth-level data signal and a fourth-level data signal and has a strong anti-interference capability.

[0277] In one embodiment, Figure 29 As shown, the fourth data level conversion circuit includes: a 37th switch tube Q37, a 38th switch tube Q38, a 39th switch tube Q39, an 84th resistor R84, an 86th resistor R86, an 88th resistor R88, an 89th resistor R89, a 91st resistor R91, a second Schottky diode D6, and a third Schottky diode D7, wherein:

[0278] The first end of the thirty-seventh switch transistor Q37 serves as the output end of the fourth data level conversion circuit. The second end of the thirty-seventh switch transistor Q37 is connected to the first end of the eighty-fourth resistor R84 and is connected to the first low-level potential. The control end of the thirty-seventh switch transistor Q37 is respectively connected to the second end of the eighty-fourth resistor R84 and the first end of the thirty-eighth switch transistor Q38. The second end of the thirty-eighth switch transistor Q38 is connected to the first end of the eighty-sixth resistor R86. The control end of the thirty-eighth switch transistor Q38 is respectively connected to the first end of the eighty-eighth resistor R88 and the first end of the thirty-ninth switch transistor Q39. The control end of Q39 is respectively connected to the first end of the eighty-ninth resistor R89, the first end of the ninety-first resistor R91, and the anode of the second Schottky diode D6. The cathode of the second Schottky diode D6 is connected to the anode of the third Schottky diode D7. The cathode of the third Schottky diode D7 is grounded GND. The second end of the eighty-ninth resistor R89, the second end of the eighty-sixth resistor R86, and the second end of the eighty-eighth resistor R88 are all connected to the power supply signal VCC2. The second end of the thirty-ninth switch tube Q39 is connected to the second end of the ninety-first resistor R91 and serves as the input end of the fourth data level conversion circuit.

[0279] Among them, the thirty-seventh switch tube Q37, the thirty-eighth switch tube Q38, and the thirty-ninth switch tube Q39 are all MOS tubes. The thirty-seventh switch tube Q37 and the thirty-ninth switch tube Q39 are of the same type, for example, they may be NMOS, and the type of the thirty-eighth switch tube Q38 is different from the types of the other switch tubes, for example, it may be PMOS.

[0280] Among them, since the seventh input terminal of the fourth data level conversion circuit is connected to the sixth output terminal of the third data level conversion circuit and is connected to the external slave device 40, the second end of the thirty-ninth switch tube Q39 serves as the seventh input terminal of the fourth data level conversion circuit and is respectively connected to the sixth output terminal of the third data level conversion circuit and the external slave device 40, and the first end of the thirty-seventh switch tube Q37 serves as the seventh output terminal of the fourth data level conversion circuit and is connected to the data signal channel 200.

[0281] When the second end of the thirty-ninth switch tube Q39, i.e., the seventh input end of the fourth data level conversion circuit, receives a low-level signal (e.g., 0.4 V) sent from the sixth output end of the third data level conversion circuit, this signal is a low-level signal sent by the external master device and received by the third data level conversion circuit. The thirty-seventh switch tube Q37, the thirty-eighth switch tube Q38, and the thirty-ninth switch tube Q39 are not turned on, and the signal at the seventh output end of the fourth data level conversion circuit remains unchanged. In other words, the signal output by the fourth data level conversion circuit will not be affected by the signal output by the third data level conversion circuit.

[0282] When the external slave device 40 inputs a low-level signal of the sixth-level data signal to the second terminal of the thirty-ninth switch Q39, the thirty-seventh, thirty-eighth, and thirty-ninth switches Q37, Q38, and Q39 are turned on, and -HVDD is transmitted to the data signal path 200 via the thirty-seventh switch Q37. When the external slave device 40 inputs a high-level signal of the sixth-level data signal to the second terminal of the thirty-ninth switch Q39, the thirty-seventh, thirty-eighth, and thirty-ninth switches Q37, Q38, and Q39 are turned off, and +HVDD is transmitted to the data signal path 200 via the pull-up resistor (the sixty-third resistor R63). This achieves conversion between the sixth-level data signal transmitted by the external slave device 40 and the fourth-level data signal (-HVDD to +HVDD).

[0283] Exemplarily, the second Schottky diode D6 and the third Schottky diode D7 are connected in series, and the total conduction voltage is 0.8V.

[0284] In this embodiment, a circuit structure of a fourth data level conversion circuit is provided, which can realize conversion between a sixth-level data signal and a fourth-level data signal and has a strong anti-interference capability.

[0285] In one embodiment, Figure 30 As shown, the fourth data level conversion circuit further includes: an eighty-fifth resistor R85, an eighty-seventh resistor R87, and a ninetieth resistor R90, wherein:

[0286] A first end of the eighty-fifth resistor R85 is respectively connected to the control end of the thirty-seventh switching tube Q37 and the second end of the eighty-fourth resistor R84. A second end of the eighty-fifth resistor R85 is respectively connected to the first end of the thirty-eighth switching tube Q38. A first end of the eighty-seventh resistor R87 is connected to the control end of the thirty-eighth switching tube Q38. A second end of the eighty-seventh resistor R87 is respectively connected to the first end of the eighty-eighth resistor R88 and the first end of the thirty-ninth switching tube Q39. A first end of the ninetieth resistor R90 is connected to the control end of the thirty-ninth switching tube Q39. A second end of the ninetieth resistor R90 is respectively connected to the first end of the eighty-ninth resistor R89, the first end of the ninety-first resistor R91, and the anode of the second Schottky diode D6.

[0287] Among them, the thirty-seventh switch tube Q37, the thirty-eighth switch tube Q38, and the thirty-ninth switch tube Q39 are all transistors. The thirty-seventh switch tube Q37 and the thirty-ninth switch tube Q39 are of the same type, for example, they can be NPN transistors, and the type of the thirty-eighth switch tube Q38 is different from the types of the other switch tubes, for example, it can be a PNP transistor.

[0288] Among them, the eighty-fifth resistor R85, the eighty-seventh resistor R87, and the ninetieth resistor R90 are all current-limiting resistors, which can prevent the base current of the transistor from being too large and burning the transistor, and secondly allow the transistor to operate in a saturated conduction state.

[0289] The working principle and process of the circuit of this embodiment are the same as those of the above embodiment and will not be described in detail.

[0290] In this embodiment, a circuit structure of a fourth data level conversion circuit is provided, which can realize conversion between a sixth-level data signal and a fourth-level data signal and has a strong anti-interference capability.

[0291] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0292] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0293] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A communication system, characterized in that: include: a first level conversion circuit and a second level conversion circuit, wherein the first level conversion circuit is used to connect to an external master device, the second level conversion circuit is used to connect to an external slave device, and the first level conversion circuit and the second level conversion circuit are connected; wherein: The first level conversion circuit is configured to receive a clock signal of a first level sent by the external master device, convert the clock signal of the first level into a clock signal of a second level, and output the signal to the second level conversion circuit; and to convert a data signal of a third level sent by the external master device into a data signal of a fourth level, and output the signal to the second level conversion circuit; and further to convert a data signal of a fourth level received from the second level conversion circuit into a data signal of a third level, and output the signal to the external master device; wherein the amplitude of the second level is greater than the amplitude of the first level, and the amplitude of the fourth level is greater than the amplitude of the third level; The second level conversion circuit is used to receive a clock signal of the second level, convert the clock signal of the second level into a clock signal of the fifth level and output it to the external slave device, and to convert a received data signal of the fourth level into a data signal of the sixth level and output it to the external slave device, and also to convert a data signal of the sixth level sent by the external slave device into a data signal of the fourth level and output it to the first level conversion circuit; wherein the amplitude of the second level is greater than the amplitude of the fifth level, and the amplitude of the fourth level is greater than the amplitude of the sixth level.

2. The communication system according to claim 1, wherein: It includes a plurality of second level conversion circuits, and each second level conversion circuit is correspondingly connected to an external slave device.

3. The communication system according to claim 1, wherein: Also includes: a clock signal channel, wherein a first end of the clock signal channel is connected to the first level conversion circuit, a second end of the clock signal channel is connected to the second level conversion circuit, and the clock signal channel is used to transmit a clock signal of the second level; A data signal channel, wherein a first end of the data signal channel is connected to the first level conversion circuit, a second end of the data signal channel is connected to the second level conversion circuit, and the data signal channel is used to transmit the data signal of the fourth level.

4. The communication system according to claim 3, wherein: The first level conversion circuit includes: a first clock level conversion circuit, comprising a first input terminal and a first output terminal, wherein the first input terminal is used to connect to an external master device, and the first output terminal is connected to the clock signal channel, and the first clock level conversion circuit is used to convert a received clock signal of the first level into a clock signal of the second level and output the clock signal through the first output terminal; a switch circuit, comprising a control terminal, a second input terminal, a second output terminal, and a data transceiver terminal, wherein the data transceiver terminal is configured to be connected to the external host device, and the switch circuit is configured to receive an external control signal through the control terminal and, under the action of the control signal, conduct a path between the second input terminal and the data transceiver terminal, or conduct a path between the second output terminal and the data transceiver terminal; a first data level conversion circuit comprising a third input terminal and a third output terminal, wherein the third input terminal is connected to the second output terminal, and the third output terminal is connected to the data signal channel, wherein the first data level conversion circuit is configured to convert the third level data signal received from the external master device into a fourth level data signal and output the fourth level data signal through the third output terminal when the switch circuit is turned on; The second data level conversion circuit includes a fourth input terminal and a fourth output terminal, the fourth output terminal is connected to the second input terminal, and the fourth input terminal is connected to the data signal channel. The second data level conversion circuit is used to receive a fourth-level data signal through the fourth input terminal, and convert the fourth-level data signal into a third-level data signal and output it through the fourth output terminal. When the switch circuit is turned on, the third-level data signal is output to the external master device.

5. The communication system according to claim 4, characterized in that The first clock level conversion circuit includes: a first input unit, wherein an input end of the first input unit is used to connect to an external host device, and the first input unit is used to receive a clock signal of the first level and output a first control signal according to the clock signal of the first level; A first output unit, wherein the input end of the first output unit is connected to the output end of the first input unit, and the output end of the first output unit is connected to the clock signal channel, and is used to output a clock signal of a second level according to the received first control signal.

6. The communication system according to claim 5, characterized in that The first output unit includes: a first switching tube, a first capacitor, a second resistor, and a third resistor. The control end of the first switching tube and the first end of the second resistor are connected to the output end of the first input unit. The second end of the second resistor is connected to the first end of the first switching tube and is connected to a first low-level potential. The second end of the first switching tube is respectively connected to the first end of the first capacitor and the first end of the third resistor and serves as the output end of the first output unit. The second end of the first capacitor is grounded, and the second end of the third resistor is used to connect to a first high-level potential. The second-level clock signal includes at least one of the first low-level potential and the first high-level potential.

7. The communication system according to claim 6, wherein: The first output unit further includes an electrostatic protection device, a first end of the electrostatic protection device is connected to the second end of the first switch tube, and a second end of the electrostatic protection device is grounded.

8. The communication system according to claim 6, wherein: The first output unit further includes: a first resistor, a first end of the first resistor is connected to the output end of the first input unit, and a second end of the first resistor is respectively connected to the control end of the first switch tube and the first end of the second resistor.

9. The communication system according to claim 4, wherein: The first input unit includes: a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, a sixth switching tube, a fourth resistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, and a twelfth resistor. The first end of the fourth resistor is connected to the first end of the second switching tube and is used to connect to an external main device. The second end of the fourth resistor is connected to a power signal. The control end of the second switching tube is connected to a power signal. The second end of the second switching tube is respectively connected to the first end of the sixth resistor and the first end of the third switching tube. The control end of the third switching tube is connected to a power signal. The second end of the third switching tube is respectively connected to the first end of the eighth resistor and the control end of the fourth switching tube. The first end of the fourth switching tube is grounded. The second ends of the fourth switching tubes are respectively connected to power signals. a first end of the ninth resistor, a first end of the tenth resistor, and a control end of the fifth switch tube are connected; a second end of the tenth resistor is grounded; a first end of the fifth switch tube is grounded; a second end of the fifth switch tube is respectively connected to the first end of the twelfth resistor and the control end of the sixth switch tube; a first end of the sixth switch tube serves as an output end of the first input unit for outputting the first control signal; a second end of the sixth resistor, a second end of the eighth resistor, a second end of the ninth resistor, a second end of the twelfth resistor, and a second end of the sixth switch tube are all connected to a power supply signal; wherein the second, third, fourth, fifth, and sixth switch tubes are of the same type, and the type of the sixth switch tube is different from that of the other switch tubes; Alternatively, the first input unit includes: a seventh switching tube, an eighth switching tube, a ninth switching tube, a tenth switching tube, a fourteenth resistor, a fifteenth resistor, a seventeenth resistor, an eighteenth resistor, a twentieth resistor, and a twenty-first resistor, wherein the first end of the fourteenth resistor, the first end of the fifteenth resistor, the first end of the seventh switching tube, and the control end of the eighth switching tube are connected and used to connect to an external main device, the second end of the fourteenth resistor is connected to a power signal, the control end of the seventh switching tube is connected to a power signal, the second end of the seventh switching tube is respectively connected to the first end of the twentieth resistor, the first end of the ninth switching tube, and the control end of the tenth switching tube, the first end of the eighth switching tube is grounded, and the eighth switching tube is grounded. The second end of the transistor is respectively connected to the power signal, the first end of the seventeenth resistor, the first end of the eighteenth resistor, and the control end of the ninth switching transistor; the second end of the eighteenth resistor is grounded; the second end of the ninth switching transistor is grounded; the first end of the tenth switching transistor is connected to the first end of the twenty-first resistor; the second end of the tenth switching transistor serves as the output end of the first input unit for outputting the first control signal; the second end of the fifteenth resistor, the second end of the seventeenth resistor, the second end of the twentieth resistor, and the second end of the twenty-first resistor are all connected to the power signal; wherein the seventh, eighth, and ninth switching transistors are of the same type, and the tenth switching transistor is of a different type from the other switching transistors; Alternatively, the first input unit includes: an eleventh switching tube, a twelfth switching tube, a twenty-second resistor, a twenty-third resistor, a twenty-fifth resistor, and a twenty-sixth resistor, wherein the first end of the twenty-second resistor, the first end of the twenty-third resistor, and the first end of the eleventh switching tube are connected and used to connect to an external main device, the control end of the eleventh switching tube is connected to a power signal, the second end of the eleventh switching tube is connected to the control ends of the twenty-fifth resistor and the twelfth switching tube respectively, the first end of the twelfth switching tube is connected to the twenty-sixth resistor, the second end of the twelfth switching tube serves as the output end of the first input unit for outputting the first control signal, and the second end of the twenty-second resistor, the second end of the twenty-third resistor, the second end of the twenty-fifth resistor, and the second end of the twenty-sixth resistor are all connected to the power signal; wherein the eleventh switching tube and the twelfth switching tube are of different types.

10. The communication system according to claim 9, characterized in that The first input unit further includes: a fifth resistor, a seventh resistor, an eleventh resistor, and a thirteenth resistor, wherein a first end of the fifth resistor is connected to the control end of the second switch tube, a first end of the seventh resistor is connected to the control end of the third switch tube, a first end of the eleventh resistor is connected to the second end of the fourth switch tube, a second end of the eleventh resistor is connected to the control end of the fifth transistor, a second end of the thirteenth resistor is connected to the control end of the sixth switch tube, and a second end of the fifth resistor and a second end of the seventh resistor are both connected to a power signal; Alternatively, the first input unit further includes: a sixteenth resistor and a nineteenth resistor, wherein a first end of the sixteenth resistor is connected to the control end of the seventh switch tube, a second end of the nineteenth resistor is connected to the control end of the ninth switch tube, and the second end of the sixteenth resistor is connected to the power signal; Alternatively, the first input unit further includes: a twenty-fourth resistor, a first end of the twenty-fourth resistor is connected to the control end of the eleventh switch tube, and a second end of the twenty-fourth resistor is connected to the power signal.

11. The communication system according to claim 4, wherein: The first data level conversion circuit includes: a second input unit, wherein an input end of the second input unit is connected to the second output end of the switch circuit, and the second input unit is configured to receive the data signal of the third level and output a second control signal according to the data signal of the third level; a second output unit, wherein the input end of the second output unit is connected to the output end of the second input unit, and the output end of the second output unit is connected to the data signal channel, and is used to output a fourth-level data signal to the second level conversion circuit according to the second control signal received from the second input unit.

12. The communication system according to claim 11, wherein: The second output unit includes: a thirteenth switching tube, a second capacitor, a twenty-eighth resistor, and a twenty-ninth resistor. The control end of the thirteenth switching tube and the first end of the twenty-eighth resistor are connected to the output end of the second input unit. The second end of the twenty-eighth resistor is connected to the first end of the thirteenth switching tube and is connected to a first low-level potential. The second end of the thirteenth switching tube is respectively connected to the first end of the second capacitor and the first end of the twenty-ninth resistor and serves as the output end of the second output unit. The second end of the second capacitor is grounded, and the second end of the twenty-ninth resistor is used to connect to a first high-level potential. The fourth-level clock signal includes at least one of the first low-level potential and the first high-level potential.

13. The communication system according to claim 12, wherein: The second output unit also includes: a twenty-seventh resistor, a first end of the twenty-seventh resistor is connected to the output end of the second control circuit, and a second end of the twenty-seventh resistor is respectively connected to the control end of the thirteenth switch tube and the first end of the twenty-eighth resistor.

14. The communication system according to claim 11, wherein: The second input unit includes: a fourteenth switching tube, a fifteenth switching tube, a sixteenth switching tube, a seventeenth switching tube, an eighteenth switching tube, a thirtieth resistor, a thirty-second resistor, a thirty-fourth resistor, a thirty-fifth resistor, a thirty-sixth resistor, and a thirty-eighth resistor, wherein a first end of the thirtieth resistor is connected to a first end of the fourteenth switching tube and is used to be connected to a second output end of the switching circuit, a second end of the thirtieth resistor is connected to a power signal, and a control end of the fourteenth switching tube is connected to a power signal, a second end of the fourteenth switching tube is respectively connected to a first end of the thirty-second resistor and a first end of the fifteenth switching tube, a control end of the fifteenth switching tube is respectively connected to a power signal, a second end of the fifteenth switching tube is respectively connected to a first end of the thirty-fourth resistor and a control end of the sixteenth switching tube, a first end of the sixteenth switching tube is grounded, and a The second end of the first resistor is connected to the power signal, the first end of the thirty-fifth resistor, the first end of the thirty-sixth resistor, and the control end of the seventeenth switch tube, respectively. The second end of the thirty-sixth resistor is grounded, the first end of the seventeenth switch tube is grounded, the second end of the seventeenth switch tube is connected to the first end of the thirty-eighth resistor and the control end of the eighteenth switch tube, respectively. The first end of the eighteenth switch tube serves as the output end of the second input unit for outputting the first control signal. The second end of the thirty-second resistor, the second end of the thirty-fourth resistor, the second end of the thirty-fifth resistor, the second end of the thirty-eighth resistor, and the second end of the eighteenth switch tube are all connected to the power signal. The fourteenth, fifteenth, sixteenth, seventeenth, and eighteenth switches are of the same type, and the type of the eighteenth switch tube is different from that of the other switches. Alternatively, the second input unit includes: a nineteenth switching tube, a twentieth switching tube, a twenty-first switching tube, a twenty-second switching tube, a fortieth resistor, a forty-first resistor, a forty-third resistor, a forty-fourth resistor, a forty-sixth resistor, and a forty-seventh resistor, wherein the first end of the fortieth resistor, the first end of the forty-first resistor, the first end of the nineteenth switching tube, and the control end of the twentieth switching tube are connected and used to be connected to the second output end of the switching circuit, the second end of the fortieth resistor is connected to the power signal, the control end of the nineteenth switching tube is connected to the power signal, the second end of the nineteenth switching tube is respectively connected to the first end of the forty-sixth resistor, the first end of the twenty-first switching tube, and the control end of the twenty-second switching tube, the first end of the twentieth switching tube is grounded, and the The second end of the 20th switch is respectively connected to the power signal, the first end of the 43rd resistor, the first end of the 44th resistor, and the control end of the 21st switch. The second end of the 44th resistor is grounded, and the second end of the 21st switch is grounded. The first end of the 22nd switch is connected to the first end of the 47th resistor. The second end of the 22nd switch serves as the output end of the second input unit for outputting the first control signal. The second end of the 41st resistor, the second end of the 43rd resistor, the second end of the 46th resistor, and the second end of the 47th resistor are all connected to the power signal. The 19th, 20th, and 21st switches are of the same type, and the type of the 22nd switch is different from that of the other switches. Alternatively, the second input unit includes: a twenty-third switching tube, a twenty-fourth switching tube, a forty-eighth resistor, a forty-ninth resistor, a fifty-first resistor, and a fifty-second resistor, wherein the first end of the forty-eighth resistor, the first end of the forty-ninth resistor, and the first end of the twenty-third switching tube are connected and used to be connected to the second output end of the switching circuit, the control end of the twenty-third switching tube is connected to the power signal, the second end of the twenty-third switching tube is connected to the control ends of the fifty-first resistor and the twenty-fourth switching tube respectively, the first end of the twenty-fourth switching tube is connected to the fifty-second resistor, the second end of the twenty-fourth switching tube serves as the output end of the second input unit and is used to output the first control signal, and the second end of the forty-eighth resistor, the second end of the forty-ninth resistor, the second end of the fifty-first resistor, and the second end of the fifty-second resistor are all connected to the power signal; wherein the twenty-third switching tube and the twenty-fourth switching tube are of different types.

15. The communication system according to claim 14, wherein: The second input unit further includes: a thirty-first resistor, a thirty-third resistor, a thirty-seventh resistor, and a thirty-ninth resistor, wherein a first end of the thirty-first resistor is connected to the control end of the fourteenth switch tube, a first end of the thirty-third resistor is connected to the control end of the fifteenth switch tube, a second end of the thirty-seventh resistor is connected to the control end of the seventeenth switch tube, a first end of the thirty-ninth resistor is respectively connected to the second end of the seventeenth switch tube and the first end of the thirty-eighth resistor, a second end of the thirty-ninth resistor is connected to the control end of the eighteenth switch tube, and a second end of the thirty-first resistor and a second end of the thirty-third resistor are both connected to the power signal; Alternatively, the second input unit includes: a 42nd resistor and a 45th resistor, wherein a first end of the 42nd resistor is connected to the control end of the 19th switch tube, a second end of the 45th resistor is connected to the control end of the 21st switch tube, and the second ends of the 42nd resistors are both connected to the power signal; Alternatively, the second input unit further includes: a 50th resistor, a first end of the 50th resistor is connected to the control end of the 23rd switch tube, and a second end of the 50th resistor is connected to the power signal.

16. The communication system according to claim 4, wherein: The second data level conversion circuit includes: a twenty-fifth switching transistor, a twenty-sixth switching transistor, a fifty-third resistor, a fifty-fourth resistor, a fifty-fifth resistor, and a fifty-sixth resistor. The first end of the twenty-fifth switching transistor is connected to the first end of the fifty-third resistor and to the second input end of the switching circuit. The second end of the fifty-third resistor is connected to a power signal. The second end of the twenty-fifth switching transistor is grounded. The control end of the twenty-fifth switching transistor is respectively connected to the first end of the fifty-fourth resistor, the first end of the fifty-fifth resistor, and the first end of the twenty-sixth switching transistor. The second end of the fifty-fourth resistor and the second end of the fifty-fifth resistor are connected to the power signal. The second end of the twenty-sixth switching transistor is grounded. The control end of the twenty-sixth switching transistor is connected to the first end of the fifty-sixth resistor. The second end of the fifty-sixth resistor serves as the fourth input end of the second data level conversion circuit.

17. The communication system according to claim 4, wherein: The switching circuit includes: a switch chip and a third capacitor. The first end of the third capacitor is connected to the second pin of the switch chip and receives a power signal. The second end of the third capacitor is connected to the third pin of the switch chip and is grounded. The first pin of the switch chip serves as a control end to receive an external control signal. The fourth pin of the switch chip serves as a second input end to be connected to the fourth output end of the second data level conversion circuit. The fifth pin of the switch chip serves as a data transceiver end to be connected to the external host device. The sixth pin of the switch chip serves as a second output end to be connected to the third input end of the first data level conversion circuit.

18. The communication system according to claim 3, wherein: The second level conversion circuit includes: The second clock level conversion circuit includes a fifth input terminal and a fifth output terminal, wherein the fifth input terminal is connected to the clock signal channel, and the fifth output terminal is used to connect to an external slave device. The second clock level conversion circuit is used to convert the received clock signal of the second level into a clock signal of a fifth level and output it through the fifth output terminal. a third data level conversion circuit, comprising a sixth input terminal and a sixth output terminal, wherein the sixth input terminal is connected to the data signal channel, the sixth output terminal is used to connect to an external slave device, and the third data level conversion circuit is used to convert the received data signal of the fourth level into a data signal of the sixth level and output it through the sixth output terminal; The fourth data level conversion circuit includes a seventh input terminal and a seventh output terminal, the seventh input terminal is connected to the external slave device, and the seventh output terminal is connected to the data signal channel. The fourth data level conversion circuit is used to receive a sixth-level data signal sent by the external slave device and convert the sixth-level data signal into a fourth-level data signal and output it through the seventh output terminal.

19. The communication system according to claim 18, wherein: The second clock level conversion circuit includes: a twenty-seventh switching transistor, a twenty-eighth switching transistor, a fifty-seventh resistor, a fifty-eighth resistor, a fifty-ninth resistor, a sixtieth resistor, a sixtieth resistor, a sixtieth resistor, and a sixtieth resistor. A first end of the fifty-seventh resistor is connected to the first end of the fifty-eighth resistor and is used to receive the second-level clock signal. A second end of the fifty-seventh resistor is connected to the first end of the fifty-eighth resistor and is used to receive the first high-level potential. A second end of the fifty-eighth resistor is connected to the control end of the twenty-seventh switching transistor. A first end of the twenty-seventh switching transistor is connected to the first end of the twenty-eighth switching transistor and is grounded. A second end of the twenty-seventh switching transistor is respectively connected to the first end of the fifty-ninth resistor, the first end of the sixtieth resistor, and the first end of the sixtieth resistor. A second end of the fifty-ninth resistor and a second end of the sixtieth resistor are connected to the power supply signal. A second end of the sixtieth resistor is connected to the control end of the twenty-eighth switching transistor. A second end of the twenty-eighth switching transistor is connected to the first end of the sixtieth resistor and serves as the output end of the second clock level conversion circuit. A second end of the sixtieth resistor is connected to the power supply signal.

20. The communication system according to claim 18, wherein: The third data level conversion circuit includes: a 29th switching transistor, a 30th switching transistor, a 63rd resistor, a 64th resistor, a 65th resistor, a 66th resistor, a 67th resistor, a 68th resistor, and a first voltage-stabilizing diode. The first end of the 63rd resistor is connected to the first end of the 64th resistor and is used to receive the data signal of the fourth level. The second end of the 63rd resistor is connected to the first end of the 64th resistor and is used to receive the first high-level potential. The second end of the 64th resistor is connected to the control end of the 29th switching transistor. The first end of the 29th switching transistor is connected to the first end of the 30th switching transistor and is grounded. The second end of the 29th switching transistor is respectively connected to the first end of the 65th resistor, the first end of the 66th resistor, and the first end of the 67th resistor. The second end of the 65th resistor and the second end of the 66th resistor are connected to the power supply signal. The second end of the 67th resistor is connected to the control end of the 30th switching transistor. The second end of the 30th switching transistor is connected to the anode of the first voltage-stabilizing diode. The cathode of the first voltage-stabilizing diode is connected to the first end of the 68th resistor and serves as the output end of the third data level conversion circuit. The second end of the 68th resistor is connected to the power supply signal. Alternatively, the third data level conversion circuit includes: a 31st switching transistor, a 32nd switching transistor, a 69th resistor, a 70th resistor, a 71st resistor, a 72nd resistor, a 73rd resistor, a 74th resistor, and a first Schottky diode. The first end of the 69th resistor is connected to the first end of the 70th resistor and is used to receive the data signal of the fourth level. The second end of the 69th resistor is connected to the first end of the 70th resistor and is used to receive the first high-level potential. The second end of the 70th resistor is connected to the control end of the 31st switching transistor. The first end of the 31st switching transistor is connected to the cathode of the first Schottky diode and is grounded. The second end of the 31st switching transistor is respectively connected to the first end of the 71st resistor, the first end of the 72nd resistor, and the first end of the 73rd resistor. The second end of the 71st resistor and the second end of the 72nd resistor are connected to the power supply signal. The second end of the 73rd resistor is connected to the control end of the 32nd switching transistor. The first end of the 32nd switching transistor is connected to the anode of the first Schottky diode. The second end of the 32nd switching transistor is connected to the first end of the 74th resistor and serves as the output end of the third data level conversion circuit. The second end of the 74th resistor is connected to the power supply signal.

21. The communication system according to claim 18, wherein: The fourth data level conversion circuit includes: a thirty-third switching tube, a thirty-fourth switching tube, a thirty-fifth switching tube, a thirty-sixth switching tube, a seventy-fifth resistor, a seventy-seventh resistor, a seventy-ninth resistor, an eighty-first resistor, an eighty-second resistor, and a second voltage-stabilizing diode. The first end of the thirty-third switching tube serves as the output end of the fourth data level conversion circuit, the second end of the thirty-third switching tube is connected to the first end of the seventy-fifth resistor and is connected to a first low-level potential, the control end of the thirty-third switching tube is respectively connected to the second end of the seventy-fifth resistor and the first end of the thirty-fourth switching tube, the second end of the thirty-fourth switching tube is connected to the first end of the seventy-seventh resistor, and the thirty-fourth switching tube is connected to the first end of the seventy-seventh resistor. a control terminal of the gate transistor connected to the first terminal of the seventy-ninth resistor and the first terminal of the thirty-fifth switching transistor, respectively; a control terminal of the thirty-fifth switching transistor connected to a power signal; a second terminal of the thirty-fifth switching transistor connected to the first terminal of the eighty-first resistor and the first terminal of the thirty-sixth switching transistor, respectively; a control terminal of the thirty-sixth switching transistor connected to the first terminal of the eighty-second resistor and the cathode of the second Zener diode, respectively; an anode of the second Zener diode connected to ground; a second terminal of the seventy-seventh resistor, a second terminal of the seventy-ninth resistor, and a second terminal of the eighty-first resistor all connected to a power signal; and a second terminal of the thirty-sixth switching transistor serving as an input terminal of the fourth data level conversion circuit; Alternatively, the fourth data level conversion circuit includes: a thirty-seventh switching tube, a thirty-eighth switching tube, a thirty-ninth switching tube, an eighty-fourth resistor, an eighty-sixth resistor, an eighty-eighth resistor, an eighty-ninth resistor, a ninety-first resistor, a second Schottky diode, and a third Schottky diode, wherein the first end of the thirty-seventh switching tube serves as the output end of the fourth data level conversion circuit, the second end of the thirty-seventh switching tube is connected to the first end of the eighty-fourth resistor and is connected to the first low-level potential, the control end of the thirty-seventh switching tube is respectively connected to the second end of the eighty-fourth resistor and the first end of the thirty-eighth switching tube, the second end of the thirty-eighth switching tube is connected to the first end of the eighty-sixth resistor, and the The control end of the thirty-eighth switching tube is respectively connected to the first end of the eighty-eighth resistor and the first end of the thirty-ninth switching tube. The control end of the thirty-ninth switching tube is respectively connected to the first end of the eighty-ninth resistor, the first end of the ninety-first resistor, and the positive electrode of the second Schottky diode. The negative electrode of the second Schottky diode is connected to the positive electrode of the third Schottky diode. The negative electrode of the third Schottky diode is grounded. The second end of the eighty-ninth resistor, the second end of the eighty-sixth resistor, and the second end of the eighty-eighth resistor are all connected to the power supply signal. The second end of the thirty-ninth switching tube is connected to the second end of the ninety-first resistor and serves as the input end of the fourth data level conversion circuit.

22. The communication system according to claim 21, wherein: The fourth data level conversion circuit further includes: a seventy-sixth resistor, a seventy-eighth resistor, an eightieth resistor, and an eighty-third resistor, wherein a first end of the seventy-sixth resistor is respectively connected to the control end of the thirty-third switch transistor and the second end of the seventy-fifth resistor, a second end of the seventy-sixth resistor is respectively connected to the first end of the thirty-fourth switch transistor, a first end of the seventy-eighth resistor is connected to the control end of the thirty-fourth switch transistor, a second end of the seventy-eighth resistor is respectively connected to the first end of the seventy-ninth resistor and the first end of the thirty-fifth switch transistor, a first end of the eightieth resistor is connected to the control end of the thirty-fifth switch transistor, a second end of the eightieth resistor is connected to a power supply signal, a first end of the eightieth resistor is connected to the control end of the thirty-sixth switch transistor, and a second end of the eightieth resistor is respectively connected to the first end of the eighty-second resistor and the cathode of the second voltage stabilizing diode; Alternatively, the fourth data level conversion circuit further includes: an eighty-fifth resistor, an eighty-seventh resistor, and a ninety-second resistor, wherein the first end of the eighty-fifth resistor is respectively connected to the control end of the thirty-seventh switch tube and the second end of the eighty-fourth resistor, the second end of the eighty-fifth resistor is respectively connected to the first end of the thirty-eighth switch tube, the first end of the eighty-seventh resistor is connected to the control end of the thirty-eighth switch tube, the second end of the eighty-seventh resistor is respectively connected to the first end of the eighty-eighth resistor and the first end of the thirty-ninth switch tube, the first end of the ninety-second resistor is connected to the control end of the thirty-ninth switch tube, and the second end of the ninety-second resistor is respectively connected to the first end of the eighty-ninth resistor, the first end of the ninety-first resistor, and the anode of the second Schottky diode.

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