Distributed system, simulation system and method, and high-speed clock alignment system and method

Abstract

The invention belongs to the technical field of data information transmission, and provides a distributed system, a simulation system and method, and a high-speed clock alignment system and method, and the high-speed clock alignment method comprises the steps: obtaining a calibration low-frequency clock of a to-be-aligned distributed system; switching a to-be-aligned distributed system clock source to a calibrated low-frequency clock; in a state that the clock source is a calibrated low-frequency clock, correcting path delays of all the sub-clocks, so that all the sub-clocks are aligned; and switching the clock source from the low-frequency clock to the high-frequency clock. The method can be applied to high-speed clock path delay alignment, and the periodic sliding phenomenon is avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of data information transmission, and relates to a distributed system, a simulation method and system, and a high-speed clock alignment system and method. Background Art

[0002] In high-speed digital logic or mixed-analog logic circuits, the clock is a very important core part of the system. When the clock is applied, considering the different positions of the clock receiving modules in the structure, the clock source will distribute the sub-clocks to various parts of the system through the distributed system. Figure 1 It is a typical distributed system with a clock tree built on a buffer level. The total clock (CLKs) at the clock source is generated through three buffer levels to generate four sub-clocks (CLK1, CLK2, CLK3, CLK4) and distributed to various parts of the system.

[0003] Figure 2 The figure shows an application scenario of a distributed system applied to a sequential logic system. The clock source distributes multiple sub-clocks to multiple sequential logic modules of the sequential logic system through the clock tree. Figure 2 As shown, the data driven by the sub-clocks CLK1 and CLK2 will continue to be correlated with the output data DATA1 and DATA2 of the subsequent first sequential logic module A and the second sequential logic module B. The clock information carried by DATA1 and DATA2, which comes from CLK1 and CLK2 respectively, will be reflected at the input end of the combinational sequential logic module AB. For another example, the data DATA3 generated by the third sequential logic module C driven by the sub-clock CLK3 enters the fourth sequential logic module D and is processed by the logic driven by the sub-clock CLK4. Good setup time and hold time require the sub-clocks CLK3 and CLK4 to be aligned.

[0004] Figure 3 The figure shows an application scenario of a distributed system applied to a TX transmitter system. The clock source distributes multiple sub-clocks to multiple TX transmitters of the TX transmitter system through the clock tree. Figure 3 As shown in the figure, high-speed signal transmitters (TXs) typically have multiple channels, such as UCIE and PCIE. Data paths are clock-driven, and clock misalignment can lead to inter-channel skew. These high-speed interface protocols all have strict limits on skew. Therefore, such applications also require distributed system sub-clock delay alignment.

[0005] Although in a system that requires a clock distribution system, different applications may have different clock alignment index requirements (referred to as alignment requirements), such as Figure 3 High-speed protocols have varying tolerances for offsets. For example, some fixed-frequency systems, under a range of constraints, may require only phase alignment, but absolute delay alignment offers the highest robustness. As system data transmission speeds increase and clocks become faster, the need for absolute delay alignment of sub-clocks becomes increasingly stringent.

[0006] Figure 4 The clock delay path alignment method commonly used in distributed systems in the prior art is shown. Figure 4 As shown in the figure, in a clock distribution system with a period of T, a delay adjustment module is added to the sub-clock distribution path to correct the phase difference. The clock delay path alignment method is described using the sub-clocks CLKp and CLKq as an example. Assuming the clock delay difference is Δ, the sub-clock to be corrected is connected to the CLKp and CLKq phase detectors PD. The phase detector detection result is used as feedback to control the delay adjustment module to achieve the purpose of correcting the phase difference between the sub-clocks CLKp and CLKq.

[0007] With technological advancements, system clock frequencies are increasing, meaning that the period T is becoming shorter and shorter. However, existing methods for aligning clock delay paths in distributed systems can only achieve "phase alignment" but not absolute delay alignment. Consequently, they cannot reliably provide path delay alignment for high-speed clock systems. Figure 5 The left part is the two sub-clock phases before correction. Figure 5 The right side of Figure 4 The result after adjusting the clock path delay alignment method is Figure 5 It can be seen that when the clock is periodically repeated, Figure 4 The clock path delay alignment method cannot distinguish different clock edges (①, ②, ③). For example, Figure 5 The lower edge ① will be aligned with the upper edge ②. This can only achieve "phase alignment" but not absolute delay alignment (the difference is an integer multiple of the period T).

[0008] In addition, the delay error of distributed systems is further exacerbated by various constraints such as physical conditions, system resource consumption, and cost efficiency: On the one hand, due to physical limitations, distributed systems cannot be reduced in linear proportion; On the other hand, in modern systems, due to comprehensive considerations of power consumption and area, the clock distribution system may be made complex and large, which will worsen the delay error.

[0009] When the maximum delay error (Δmax) in the system is comparable to the period T, or even much larger than T, period slippage will occur. After delay alignment, the maximum delay error not only does not decrease but expands to an integer multiple of the period.

[0010] Therefore, the need to reliably provide path delay alignment for high-speed clock systems is an important issue that needs to be urgently addressed in the industry. Summary of the Invention

[0011] In view of this, the present invention provides a distributed system simulation method and a high-speed clock alignment method. One or more embodiments of the present invention also relate to a distributed system, a simulation system, and a high-speed clock alignment system to address technical deficiencies in the prior art.

[0012] According to a first aspect of the present invention, a simulation method for a distributed system is provided, wherein the distributed system includes a clock source and at least one buffer level, and the simulation method includes: High-frequency simulation step: Collect the maximum delay errors of multiple sub-clocks of the distributed system when the clock source is a high-frequency clock, and use them as the first high-frequency maximum delay error; Clock frequency setting step: setting a low-frequency clock, wherein the low-frequency period of the low-frequency clock is not less than a set multiple of the first high-frequency maximum delay error; Clock switching steps: switch the high-frequency clock of the clock source to a low-frequency clock; Clock switching back step: switch the clock source from low-frequency clock to high-frequency clock; Clock switchback simulation steps: collect the delay error introduced when the clock source switches from a low-frequency clock to a high-frequency clock, and use it as the introduced delay error; An introduced error determination step: determining whether the introduced delay error is less than a set percentage of the first high frequency maximum delay error; If the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, the simulation is terminated to obtain a calibrated low-frequency clock, wherein the low-frequency period of the calibrated low-frequency clock is not less than the set multiple of the first high-frequency maximum delay error and the introduced delay error is less than the set percentage of the first high-frequency maximum delay error; If the introduced delay error is not less than the set percentage of the first high-frequency maximum delay error, the frequency of the low-frequency clock is increased under the constraint that it is less than the frequency of the high-frequency clock, and the clock frequency setting step is returned to repeat the cycle until the introduced delay error is less than the set percentage of the first high-frequency maximum delay error to obtain a calibrated low-frequency clock.

[0013] In a possible implementation, the simulation method further includes: A simulation database is constructed, which stores system data, simulation data and mapping between the system data and simulation data of the distributed system. The system data includes structural data and high-frequency clocks that characterize the composition of the distributed system. The simulation data includes the first high-frequency maximum delay error and the calibrated low-frequency clock.

[0014] In a possible implementation, the set multiple is not less than 2, and the set percentage is not greater than 50%.

[0015] According to a second aspect of the present invention, there is provided a high-speed clock alignment method, comprising: The distributed system to be aligned is simulated by the above simulation method to obtain a calibrated low-frequency clock of the distributed system to be aligned; Low-frequency clock switching step: Switch the high-frequency clock of the distributed system clock source to be aligned to the calibrated low-frequency clock; Low-frequency clock alignment steps: When the clock source is a calibrated low-frequency clock, correct the path delays of all sub-clocks to align them. Steps for switching back the high-frequency clock: Switch the clock source from the calibrated low-frequency clock back to the high-frequency clock.

[0016] In a possible implementation, after the high-frequency clock switching back step, the step further includes: High-frequency error collection step: Collect the maximum delay errors of multiple sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock, and use this as the second high-frequency maximum delay error. High frequency error judgment step: judging whether the second high frequency maximum delay error does not exceed the first delay error threshold; If the second high frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed; If the second high-frequency maximum delay error exceeds the first delay error threshold, performing a high-frequency clock alignment step; High-frequency clock alignment step: When the clock source is a high-frequency clock, the path delays of all sub-clocks are corrected so that all sub-clocks are aligned.

[0017] In a possible implementation, the first delay error threshold is 0.

[0018] In a possible implementation, the step of correcting the path delays of all sub-clocks includes: Phase detection step: perform phase detection on the two sub-clocks to obtain the phase error; Phase error judgment step: judging whether the phase error is less than the phase threshold; If the phase error is less than the phase threshold, the path delays of the two sub-clocks are not adjusted; If the phase error is not less than the phase threshold, the path delay of one or two sub-clocks is adjusted in a trend toward decreasing the phase error, and the process returns to the phase detection step.

[0019] According to a third aspect of the present invention, there is provided a high-speed clock alignment method, comprising: Obtaining a distributed system with the highest similarity to the distributed system to be aligned from a simulation database constructed using a simulation method, and setting a low-frequency period of a calibrated low-frequency clock of the distributed system to be aligned to be no less than the low-frequency period of the calibrated low-frequency clock of the distributed system with the highest similarity; Low-frequency clock switching step: Switch the high-frequency clock of the distributed system clock source to be aligned to the calibrated low-frequency clock; Low-frequency clock alignment steps: When the clock source is a calibrated low-frequency clock, correct the path delays of all sub-clocks to align them. Steps for switching back the high-frequency clock: Switch the clock source from the calibrated low-frequency clock back to the high-frequency clock.

[0020] In a possible implementation, after the high-frequency clock switching back step, the step further includes: High-frequency error collection step: Collect the maximum delay errors of multiple sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock, and use this as the second high-frequency maximum delay error. High frequency error judgment step: judging whether the second high frequency maximum delay error does not exceed the first delay error threshold; If the second high frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed; If the second high-frequency maximum delay error exceeds the first delay error threshold, performing a high-frequency clock alignment step; High-frequency clock alignment step: When the clock source is a high-frequency clock, the path delays of all sub-clocks are corrected so that all sub-clocks are aligned.

[0021] In a possible implementation, after the high-frequency clock switching back step, the step further includes: High-frequency error collection step: Collect the maximum delay errors of multiple sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock, and use this as the second high-frequency maximum delay error. First high frequency error judgment step: judging whether the second high frequency maximum delay error does not exceed the first delay error threshold; If the second high frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed; If the second high frequency maximum delay error exceeds the first delay error threshold, executing a second high frequency error determination step; A second high frequency error determination step: determining whether the second high frequency maximum delay error is less than a second delay error threshold, wherein the second delay error threshold is greater than the first delay error threshold and is not greater than 0.5 times the first high frequency maximum delay error; If the second high-frequency maximum delay error is less than the second delay error threshold, performing a high-frequency clock alignment step; High-frequency clock alignment step: In the high-frequency clock state, the path delays of all sub-clocks are corrected to align all sub-clocks. If the second high frequency maximum delay error is not less than the second delay error threshold, performing the intermediate frequency clock switching step; An intermediate frequency clock switching step: switching the clock source from the high frequency clock to an intermediate frequency clock, wherein the intermediate frequency period of the intermediate frequency clock is smaller than the low frequency period of the calibrated low frequency clock and larger than the high frequency period of the high frequency clock; In the intermediate frequency clock alignment step, the path delays of all sub-clocks are corrected in the intermediate frequency clock state so that all sub-clocks are aligned, and then the high frequency clock switching back step is performed.

[0022] In a possible implementation, before the intermediate frequency clock alignment step, the following steps are further included: The maximum delay error acquisition step of the intermediate frequency is as follows: when the clock source is the intermediate frequency clock, the maximum delay error of the intermediate frequency of multiple sub-clocks is acquired; Intermediate frequency period determination step: determining whether the intermediate frequency period corresponding to the intermediate frequency clock is not less than a set multiple of the intermediate frequency maximum delay error; If the intermediate frequency period is not less than the set multiple of the intermediate frequency maximum delay error, performing an intermediate frequency clock alignment step; If the intermediate frequency period is less than the set multiple of the intermediate frequency maximum delay error, executing the step of reducing the clock frequency; Clock frequency reduction step: Reduce the frequency of the intermediate frequency clock until the corresponding intermediate frequency period is not less than the set multiple of the intermediate frequency maximum delay error, and then perform the intermediate frequency clock alignment step.

[0023] In a possible implementation, the step of correcting the path delays of all sub-clocks includes: Phase detection step: perform phase detection on the two sub-clocks to obtain the phase error; Phase error judgment step: judging whether the phase error is less than the phase threshold; If the phase error is less than the phase threshold, the path delays of the two sub-clocks are not adjusted; If the phase error is not less than the phase threshold, the path delay of one or two sub-clocks is adjusted in a trend toward decreasing the phase error, and the process returns to the phase detection step.

[0024] According to a fourth aspect of the present invention, a high-speed clock alignment method is provided, comprising: Obtaining a distributed system with the highest similarity to the distributed system to be aligned from a simulation database constructed using a simulation method, and setting a low-frequency period of a calibrated low-frequency clock of the distributed system to be aligned to be no less than the low-frequency period of the calibrated low-frequency clock of the distributed system with the highest similarity; Low-frequency clock switching step: Switch the high-frequency clock of the distributed system clock source to be aligned to the calibrated low-frequency clock; Low-frequency clock alignment steps: When the clock source is a calibrated low-frequency clock, correct the path delays of all sub-clocks to align them. An intermediate frequency clock switching step: switching the clock source from the calibrated low frequency clock to an intermediate frequency clock, wherein the frequency of the intermediate frequency clock is higher than the frequency of the low frequency clock and lower than the frequency of the high frequency clock; The intermediate frequency clock alignment step corrects the path delays of all sub-clocks when the clock source is the intermediate frequency clock, so that all sub-clocks are aligned. Steps for switching back the high-frequency clock: Switch the clock source from the intermediate-frequency clock back to the high-frequency clock.

[0025] In a possible implementation, after the high-frequency clock switching back step, the step further includes: High-frequency error collection step: Collect the maximum delay errors of multiple sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock, and use this as the second high-frequency maximum delay error. High frequency error judgment step: judging whether the second high frequency maximum delay error does not exceed the first delay error threshold; If the second high frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed; If the second high-frequency maximum delay error exceeds the first delay error threshold, performing a high-frequency clock alignment step; High-frequency clock alignment step: When the clock source is a high-frequency clock, the path delays of all sub-clocks are corrected so that all sub-clocks are aligned.

[0026] In a possible implementation, multiple intermediate frequency clock switching steps to intermediate frequency clock alignment steps are performed before the high-frequency clock switching back step, and the intermediate frequency period corresponding to the intermediate frequency clock of the intermediate frequency clock switching step to be performed is smaller than the intermediate frequency period corresponding to the intermediate frequency clock of the previous intermediate frequency clock switching step.

[0027] In a possible implementation, before the intermediate frequency clock alignment step, the following steps are further included: The maximum delay error acquisition step of the intermediate frequency is as follows: when the clock source is the intermediate frequency clock, the maximum delay error of the intermediate frequency of multiple sub-clocks is acquired; Intermediate frequency period determination step: determining whether the intermediate frequency period corresponding to the intermediate frequency clock is not less than a set multiple of the intermediate frequency maximum delay error; If the intermediate frequency period is not less than the set multiple of the intermediate frequency maximum delay error, performing an intermediate frequency clock alignment step; If the intermediate frequency period is less than the set multiple of the intermediate frequency maximum delay error, executing the step of reducing the clock frequency; Clock frequency reduction step: Reduce the frequency of the intermediate frequency clock until the corresponding intermediate frequency period is not less than the set multiple of the intermediate frequency maximum delay error, and then perform the intermediate frequency clock alignment step.

[0028] In a possible implementation, the step of correcting the path delays of all sub-clocks includes: Phase detection step: perform phase detection on the two sub-clocks to obtain the phase error; Phase error judgment step: judging whether the phase error is less than the phase threshold; If the phase error is less than the phase threshold, the path delays of the two sub-clocks are not adjusted; If the phase error is not less than the phase threshold, the path delay of one or two sub-clocks is adjusted in a trend toward decreasing the phase error, and the process returns to the phase detection step.

[0029] According to a fifth aspect of the present invention, there is provided a simulation system for a distributed system, comprising: a high-frequency error acquisition module configured to acquire a maximum delay error of multiple sub-clocks of the distributed system when the clock source is a high-frequency clock, as a first high-frequency maximum delay error; a low-frequency clock setting module configured to set a low-frequency clock based on the first high-frequency maximum delay error acquired by the high-frequency error acquisition module, wherein a low-frequency period of the low-frequency clock is not less than a set multiple of the first high-frequency maximum delay error; A clock switching module configured to switch the high-frequency clock of the clock source to the low-frequency clock set by the low-frequency clock setting module; A clock switchback module is configured to switch the clock source from the low-frequency clock back to the high-frequency clock; an introduced error collection module configured to collect, as an introduced delay error, a delay error introduced when the clock switching back module switches the clock source from the low-frequency clock to the high-frequency clock; an introduced error judgment module, configured to judge whether the introduced delay error collected by the introduced error collection module is less than a set percentage of the first high-frequency maximum delay error collected by the high-frequency error collection module; if the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, jump to the low-frequency clock acquisition module; if the introduced delay error is not less than the set percentage of the first high-frequency maximum delay error, jump to the low-frequency improvement module; a low frequency increasing module configured to increase the low frequency clock set by the low frequency clock setting module under the constraint that the frequency is lower than that of the high frequency clock; The low-frequency clock acquisition module is configured to obtain a calibrated low-frequency clock, the low-frequency period of which is not less than a set multiple of the first high-frequency maximum delay error and the introduced delay error is less than a set percentage of the first high-frequency maximum delay error.

[0030] In a possible implementation, the simulation system further includes: A simulation database stores system data, simulation data, and a mapping between the system data and the simulation data of a distributed system. The system data includes structural data and a high-frequency clock representing the composition of the distributed system. The simulation data includes a first high-frequency maximum delay error and a calibrated low-frequency clock.

[0031] According to a sixth aspect of the present invention, a high-speed clock alignment system is provided, comprising: The clock frequency adjustment module is configured to switch the clock source of the distributed system to be aligned back and forth between a high-frequency clock and a calibrated low-frequency clock of the distributed system to be aligned obtained through the simulation system.

[0032] In a possible implementation, the high-speed clock alignment system further includes a phase correction module configured to correct the path delays of all sub-clocks when the clock frequency adjustment module switches the clock source to the calibrated low-frequency clock.

[0033] In one possible implementation, the phase correction module is further configured to correct the path delay of all sub-clocks when the clock source is a high-frequency clock after the clock frequency adjustment module switches the clock source from a calibrated low-frequency clock back to a high-frequency clock.

[0034] In a possible implementation, the phase correction module includes a delay module, a delay adjustment module, and a phase detector: The delay module is provided on the sub-clock path of the distributed system, and the delay module is electrically connected to the delay adjustment module; The delay adjustment module is configured to adjust the delay of the delay module; The phase detector is electrically connected to the delay adjustment module and is configured to detect the phases of any two sub-clocks and output a delay error of the two sub-clocks, and feed the delay error back to the delay adjustment module. The delay adjustment module adjusts the path delay of one or two sub-clocks based on the delay error in a direction of decreasing the delay error. The delay module, the delay adjustment module and the phase detection module form a feedback loop, so that the delay errors of all sub-clocks are smaller than the delay threshold.

[0035] In a possible implementation, the phase detector is a phase detector.

[0036] In a possible implementation, the delay threshold is a phase detection accuracy of a phase detector.

[0037] In a possible implementation, the high-speed clock alignment system further includes a simulation system.

[0038] According to a seventh aspect of the present invention, a distributed system is provided, comprising a clock source and at least one buffer level, wherein the clock source generates a plurality of sub-clocks through the buffer level, and the plurality of sub-clocks are configured to be clock aligned by the above-mentioned high-speed clock alignment method.

[0039] In a possible implementation, the clock source is a programmable clock source.

[0040] In a possible implementation, the distributed system further includes a phase correction module, which is configured to correct path delays of all sub-clocks.

[0041] In a possible implementation, the phase correction module includes a delay module, a delay adjustment module, and a phase detector: The delay module is arranged on the sub-clock path, and the delay module is electrically connected to the delay adjustment module; The delay adjustment module is configured to adjust the delay of the delay module; The phase detector is electrically connected to the delay adjustment module and is configured to detect the phases of any two sub-clocks and output a delay error of the two sub-clocks, and feed the delay error back to the delay adjustment module. The delay adjustment module adjusts the path delay of one or two sub-clocks based on the delay error in a direction of decreasing the delay error. The delay module, the delay adjustment module and the phase detection module form a feedback loop, so that the delay errors of all sub-clocks are smaller than the delay threshold.

[0042] The simulation method and system described in the present invention simulate the first high-frequency maximum delay error of a distributed system at a high-frequency clock, set the low-frequency period of the low-frequency clock to be no less than 2 times the first high-frequency maximum delay error, so that the phase difference under the low-frequency clock is always within an unambiguous range; then, the clock source is switched to the low-frequency clock and then switched back to the high-frequency clock, and then the delay error introduced by the clock switching is simulated. Finally, when the introduced error is no less than 50%, the low-frequency clock is recalibrated, avoiding the cycle slip phenomenon caused by excessive delay error introduced by switching from low frequency to high frequency; the accuracy of the calibrated low-frequency clock is guaranteed from two aspects of the low-frequency period and the delay error introduced by the clock switching, avoiding the cycle slip phenomenon.

[0043] The high-speed clock alignment system and method described in the present invention can use the above-mentioned simulation system or simulation method to simulate the distributed system to be aligned to obtain the corresponding calibrated low-frequency error, switch the clock source of the distributed system to be aligned from the high-frequency clock to the calibrated low-frequency clock, and the low-frequency period of the calibrated low-frequency clock is not less than 2 times the first high-frequency maximum delay error of the distributed system to be aligned, so that the phase difference under the calibrated low-frequency clock is always within the unambiguous range, and then perform clock path delay alignment under the calibrated low-frequency clock, and also eliminate the baseband phase difference, thereby avoiding the cycle slip phenomenon.

[0044] The high-speed clock alignment system and method of the present invention can also obtain the calibrated low-frequency clock of the distributed system with the highest similarity to the distributed system to be aligned from the simulation database. Although the accuracy of this method of obtaining the calibrated low-frequency clock of the distributed system to be aligned is lower than that of directly simulating the distributed system to be aligned to obtain the calibrated low-frequency clock, this method can be applied to situations where simulation is not possible. When the distributed system to be aligned has a high similarity with the distributed system in the simulation database, clock path delay alignment is performed under the similar calibrated low-frequency clock. While performing clock alignment, the cycle slip phenomenon is also prevented. It is also possible to switch from the low-frequency clock to the intermediate-frequency clock, and then switch back to the high-frequency clock after the intermediate-frequency clock is aligned, thereby reducing the introduced error and preventing the cycle slip phenomenon. When the distributed system to be aligned has a low similarity with the distributed system in the simulation database, the present invention judges the second high-frequency maximum delay error after the introduced delay error after the similar calibrated low-frequency clock is switched back to the high-frequency clock, performs clock path delay alignment under the high-frequency clock, reduces the delay error caused by the similar calibrated low-frequency clock, and prevents the cycle slip phenomenon.

[0045] The multiple sub-clocks of the distributed system described in the present invention are aligned through the above-mentioned high-speed clock alignment method, which solves the problem of delay mismatch of the clock tree itself based on the clock tree, and realizes high-speed, reliable and accurate path delay correction of multiple sub-clocks. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1This is a schematic diagram of the structure of an embodiment of a distributed clock tree system in the prior art; Figure 2 This is a schematic diagram of an application scenario of an embodiment in which a distributed system is applied to a temporal logic system; Figure 3 This is a schematic diagram of an application scenario of another embodiment in which a distributed system is applied to a temporal logic system; Figure 4 This is a schematic diagram of an embodiment of a clock delay path alignment method commonly used in distributed systems in the prior art; Figure 5 yes Figure 4 A waveform diagram of an embodiment of a clock delay path alignment method; Figure 6 1 is a flow chart of an embodiment of the simulation method of the present invention; Figure 7 1 is a flow chart of an embodiment of the high-speed clock alignment method of the present invention; Figure 8 1 is a schematic diagram of waveform changes in an embodiment of the high-speed clock alignment method of the present invention; Figure 9 is a flow chart of a second embodiment of the high-speed clock alignment method of the present invention; Figure 10 1 is a flow chart of a third embodiment of the high-speed clock alignment method of the present invention; Figure 11 1 is a flow chart of a fourth embodiment of the high-speed clock alignment method of the present invention; Figure 12 It is a schematic block diagram of an embodiment of the simulation system of the present invention; Figure 13 is a schematic diagram of an embodiment of the distributed system of the present invention; Figure 14 is a schematic diagram of an embodiment of the high-speed clock alignment system of the present invention; Among them: A, first sequential logic module; B, second sequential logic module; AB, combinational sequential logic module; C, third sequential logic module; D, fourth sequential logic module; PD, phase detector; 1, simulation system; 11, high-frequency error acquisition module; 12, low-frequency clock setting module; 13, clock switching module; 14, clock switch back module; 15, introduced error acquisition module; 16, introduced error judgment module; 17, low-frequency improvement module; 18, low-frequency clock acquisition module; 19, simulation database; 2, distributed system; 21, clock source; 22, buffer level; 221, buffer; 3, clock frequency adjustment module; 4, phase correction module; 41, delay module; 42, delay adjustment module; 43, switch matrix; 44, phase detector; 10, high-speed clock alignment system. DETAILED DESCRIPTION

[0047] The following description sets forth many specific details to facilitate a thorough understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the scope of this specification. Therefore, this specification is not limited to the specific implementations disclosed below.

[0048] The terms used in one or more embodiments of this specification are for the purpose of describing specific embodiments only and are not intended to limit one or more embodiments of this specification. The singular forms "a," "an," and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0049] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0050] First, the terms involved in one or more embodiments of this specification are explained.

[0051] UCIE: Unified Chiplet Interconnect Express, which is universal chiplet interconnect technology; PCIE: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard; Cycle slip: When the clock path delay error is too large, the phase detector (such as a digital phase detector or phase-frequency detector) cannot distinguish whether the phase difference falls within a single cycle or spans multiple cycles, resulting in incorrect judgment of integer multiple cycles during the correction process.

[0052] The existing technology uses link training based on data paths to align clock data, which requires data to be in a fixed format and requires a receiver, and is not suitable for situations where there is no receiver (such as Figure 2 In addition, the phase detection method in the prior art cannot distinguish different clock edges and can only achieve phase alignment. When the delay error is large, cycle slippage is likely to occur.

[0053] Based on the technical problems of the prior art, the present application solves the delay mismatch problem from the clock tree itself.

[0054] The present invention can obtain a calibrated low-frequency clock that can realize unambiguous phase detection of multiple sub-clocks by simulating the distributed system to be aligned; then, unambiguous clock path delay correction is performed under the calibrated low-frequency clock, avoiding cycle slippage while eliminating large delay errors and even achieving absolute delay alignment; the clock source is switched back from the calibrated low-frequency clock to the high-frequency clock, and even if an error is introduced, the introduced error is very small, which can meet the clock alignment requirements of most distributed systems; even in situations where strict absolute alignment is required, the very small introduced error can be eliminated by switching back to the high-frequency clock and performing clock path delay correction.

[0055] The present invention can also be based on a simulation database that stores multiple distributed systems and their calibrated low-frequency clocks, and select the calibrated low-frequency clock of the distributed system with the highest similarity to the distributed system to be aligned as the calibrated low-frequency clock of the distributed system to be aligned by similarity. Although the accuracy of the calibrated low-frequency clock of the distributed system to be aligned obtained by this similarity method may not be as accurate as the accuracy of the calibrated low-frequency clock obtained by directly simulating the distributed system to be aligned due to the influence of the degree of similarity, the present invention can ensure the reliability of clock path delay alignment from one or more of the following aspects: First, a low-frequency clock with a sufficiently larger low-frequency period than the calibration low-frequency clock corresponding to the distributed system with the highest similarity can be selected as the calibration low-frequency clock of the distributed system to be aligned. Second, when the delay error introduced by switching from a calibrated low-frequency clock to a high-frequency clock is small, the delay error can be eliminated by correcting the clock path delay under the high-frequency clock. Third, when the delay error introduced by switching the calibrated low-frequency clock back to the high-frequency clock is large, the clock source can be calibrated and calibrated with the low-frequency clock and the intermediate-frequency clock and calibrated at least once before switching back to the high-frequency clock; or the maximum delay error can be judged after switching back to the high-frequency clock to maintain the high-frequency clock, calibrate the high-frequency clock, or switch to the intermediate-frequency clock and calibrate at least once before returning to the high-frequency clock.

[0056] Figure 6 FIG. 1 is a flow chart of an embodiment of the simulation method of the present invention. Figure 6 As shown, the simulation method includes: Step S11, high-frequency simulation step: collecting the maximum delay errors of multiple sub-clocks of the distributed system when the clock source is a high-frequency clock, as a first high-frequency maximum delay error; Step S12, clock frequency setting step: setting a low-frequency clock, wherein the low-frequency period of the low-frequency clock is not less than a set multiple of the first high-frequency maximum delay error, preferably, the set multiple is not less than 2; Step S13, clock switching step: switching the high-frequency clock of the clock source to a low-frequency clock; Step S14, clock switching back step: switching the clock source from the low-frequency clock back to the high-frequency clock; Step S15, clock switching back simulation step: collecting the delay error introduced when the clock source switches from the low-frequency clock to the high-frequency clock as the introduced delay error; Step S16, an introduced error judgment step: judging whether the introduced delay error is less than a set percentage of the first high frequency maximum delay error, preferably, the set percentage is not greater than 50%; If the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, executing step S18: ending the simulation, obtaining a calibrated low-frequency clock, wherein the low-frequency period of the calibrated low-frequency clock is not less than the set multiple of the first high-frequency maximum delay error and the introduced delay error is less than the set percentage of the first high-frequency maximum delay error; If the introduced delay error is not less than the set percentage of the first high-frequency maximum delay error, execute step S17: increase the frequency of the low-frequency clock under the constraint that it is less than the frequency of the high-frequency clock, return to the clock frequency setting step, and repeat the cycle until the introduced delay error is less than the set percentage of the first high-frequency maximum delay error to obtain a calibrated low-frequency clock.

[0057] In a feasible embodiment of the present invention, the above simulation method further includes: A simulation database is constructed, which stores system data, simulation data and mapping between the system data and simulation data of the distributed system. The system data includes structural data and high-frequency clocks that characterize the composition of the distributed system. The simulation data includes the first high-frequency maximum delay error and the calibrated low-frequency clock.

[0058] Figure 7 FIG. 1 is a flow chart of an embodiment of the high-speed clock alignment method of the present invention. Figure 7 As shown, the high-speed clock alignment method includes: Step S1: Obtain the first high-frequency maximum delay error of the clock source of the distributed system to be aligned under the high-frequency clock (e.g. Figure 8 As shown) and a calibrated low-frequency clock, the low-frequency period of the calibrated low-frequency clock is not less than 2 times the first high-frequency maximum delay error and the introduced delay error is less than 50% of the first high-frequency maximum delay error; the calibrated low-frequency clock of the distributed system to be aligned can be obtained by simulating the distributed system to be aligned using a simulation method, or the calibrated low-frequency clock of the distributed system with the highest similarity to the distributed system to be aligned can be obtained from a simulation database as the calibrated low-frequency clock of the distributed system to be aligned; a low-frequency clock with a low-frequency period that is a multiple of the low-frequency period corresponding to the calibrated low-frequency clock of the distributed system with the highest similarity (for example, much greater than 2 times, 5 times, 20 times, etc.) can also be used as the calibrated low-frequency clock of the distributed system to be aligned; the similarity can be analyzed by combining one or more similarities of structural parameters, timing indicators, and dynamic responses; the structural parameters include one or more of the topology type, node distribution, and hierarchy of the distributed system; the timing indicators include clock skew comparison and / or jitter tolerance; the dynamic response includes dynamic time warping and / or Euclidean distance; Step S2, low frequency clock switching step: switch the high frequency clock of the distributed system clock source to be aligned to the calibrated low frequency clock. In the calibrated low frequency clock state, the clock waveforms of the two sub-clocks corresponding to the first high frequency maximum delay error are as follows: Figure 8 As shown; Step S3, low frequency clock alignment step: When the clock source is the calibrated low frequency clock, the path delay of all sub-clocks is corrected so that all sub-clocks are aligned. The clock waveforms of the two sub-clocks in the aligned calibrated low frequency clock state are as follows: Figure 8 As shown; Step S4, high-frequency clock switching back step: switch the clock source back to the high-frequency clock. After switching back to the high-frequency clock, the clock waveforms of the two sub-clocks are as follows: Figure 8 shown.

[0059] The present invention simulates the distributed system to be aligned using the simulation method described in the present invention, and can obtain a calibrated low-frequency clock with a period not less than 2 times the first high-frequency maximum delay error, or even much larger than the maximum delay error, so that the maximum phase difference of the maximum delay error after the calibrated low-frequency clock is switched is strictly limited to within 180°. Since a conventional phase detector can accurately measure the phase difference within the range of -180° to 180°, it will not misjudge multi-cycle errors, and achieve unambiguous phase detection. Through clock delay path correction, the phase difference of all clock paths is reset to zero, achieving precise alignment. When switching back to high-frequency mode, the compensation value is directly applied to the high-frequency clock path to keep the path delay consistent with the low-frequency alignment state. The low-frequency correction has eliminated the baseband phase difference, and the correction amount inherited in the high-frequency mode ensures the initial phase alignment.

[0060] In addition, the present invention calibrates the low-frequency period of the low-frequency clock to be no less than 2 times the first high-frequency maximum delay error, providing a larger phase margin, ensuring that the phase detection process is not disturbed, and enhancing the correction robustness.

[0061] In a distributed system with steep clock edges, the delay on each sub-clock path is basically fixed. After the high-speed clock alignment method, the delay changes slightly, so that each sub-clock is basically aligned.

[0062] However, in a distributed system with a non-steep clock edge, the delay may change significantly when switching back from a low-frequency clock to a high-frequency clock operating mode.

[0063] In addition, the delay of some circuits is not fixed at different frequencies. For example, the delay has been adjusted at low frequency, but after switching to high frequency, the inventors found that the absolute delay of some branches has changed due to different clock frequencies.

[0064] Furthermore, in systems requiring high precision, even the slight delay error introduced by switching from a low-frequency clock to a high-frequency clock cannot be ignored and affects system performance.

[0065] To solve the above technical problems, the present invention further provides the following multiple high-speed clock alignment methods.

[0066] Figure 9 FIG. 1 is a flow chart of a second embodiment of the high-speed clock alignment method of the present invention. Figure 9 As shown, the high-speed clock alignment method includes: Step S10, obtaining a calibrated low-frequency clock of the distributed system to be aligned; Step S20, low frequency clock switching step: switching the clock source to a calibrated low frequency clock; Step S30, low-frequency clock alignment step: in the state of calibrating the low-frequency clock, correcting the path delays of all sub-clocks; Step S40, high-frequency clock switching back step: switching the clock source clock back to the high-frequency clock; Step S50, high-frequency error collection step: collecting the maximum delay errors of multiple sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock, as the second high-frequency maximum delay error; Step S60, high frequency error acquisition step: high frequency error judgment step: judging whether the second high frequency maximum delay error does not exceed the first delay error threshold; If the second high frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed; If the second high frequency maximum delay error exceeds the first delay error threshold, executing step S70; Step S70, high-frequency clock alignment step: in a state where the clock source is a high-frequency clock, the path delays of all sub-clocks are corrected so that all sub-clocks are aligned.

[0067] The high-speed clock alignment method mentioned above eliminates the delay error introduced by frequency switching.

[0068] In the above embodiment, the first delay error threshold may be set to 0 to achieve absolute alignment of all sub-clocks in the distributed system.

[0069] Figure 10 FIG. 1 is a flow chart of a third embodiment of the high-speed clock alignment method of the present invention. Figure 10 As shown, the high-speed clock alignment method includes: Step S100, obtaining a calibrated low-frequency clock of the distributed system to be aligned; Step S200, low frequency clock switching step: switching the clock source to a calibrated low frequency clock; Step S300, low-frequency clock alignment step: in a state where the clock source is a calibrated low-frequency clock, the path delays of all sub-clocks are corrected so that all sub-clocks are aligned; Step S400, intermediate frequency clock switching step: switching the clock source from the low frequency clock to the intermediate frequency clock, wherein the frequency of the intermediate frequency clock is higher than the frequency of the low frequency clock and lower than the frequency of the high frequency clock; Step S500, an intermediate frequency clock alignment step, in which the path delays of all sub-clocks are corrected when the clock source is an intermediate frequency clock, so that all sub-clocks are aligned; Step S600, high frequency clock switching back step: switching the clock source from the intermediate frequency clock back to the high frequency clock.

[0070] In one feasible embodiment, steps S400 to S500 are performed multiple times before step S600, and the intermediate frequency period corresponding to the intermediate frequency clock in the intermediate frequency clock switching step to be performed is smaller than the intermediate frequency period corresponding to the intermediate frequency clock in the previous intermediate frequency clock switching step.

[0071] The high-speed clock alignment method described above transforms the clocks into a high-frequency clock, a low-frequency clock, an intermediate-frequency clock, and finally a high-frequency clock. This eliminates the delay error introduced by the high-frequency-low-frequency clock transition through multiple path delay corrections at different frequencies. The low-frequency clock is switched back to the high-frequency clock only after passing through the intermediate-frequency clock. This avoids the significant delay error introduced by switching directly from the low-frequency clock back to the high-frequency clock, and eliminates the risk of cycle slippage when switching directly back to the target high-frequency clock.

[0072] Normally, the delay error introduced by clock frequency switching is relatively low, and cycle slippage generally does not occur. However, in extremely poor circuit conditions, switching from a low-frequency clock back to a high-frequency clock may introduce a large delay error, which may increase the risk of cycle slippage. To address this technical issue, the following embodiments are provided: Figure 11 FIG. 4 is a flow chart of a fourth embodiment of the high-speed clock alignment method of the present invention. Figure 11 As shown, the high-speed clock alignment method includes: Step S1000: obtaining a calibrated low-frequency clock of the distributed system to be aligned; Step S2000, low frequency clock switching step: switching the clock source to a calibrated low frequency clock; Step S3000, low-frequency clock alignment step: in a state where the clock source is a calibrated low-frequency clock, the path delays of all sub-clocks are corrected so that all sub-clocks are aligned; Step S4000, high-frequency clock switching back step: switching the clock source from the low-frequency clock back to the high-frequency clock; Step S5000, high-frequency error collection step: collecting the maximum delay errors of multiple sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock, as the second high-frequency maximum delay error; Step S6000, first high frequency error determination step: determining whether the second high frequency maximum delay error does not exceed a first delay error threshold; If the second high frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed; If the second high frequency maximum delay error exceeds the first delay error threshold, executing step S7000; Step S7000, second high-frequency error determination step: determining whether the second high-frequency maximum delay error is less than a second delay error threshold, where the second delay error threshold is greater than the first delay error threshold and not greater than 0.5 times the first high-frequency maximum delay error. For example, if the alignment requirement is absolute delay alignment, the first delay error threshold is 0, and the second delay error threshold is 0.5 times the first high-frequency maximum delay error. If the second high frequency maximum delay error is less than the second delay error threshold, executing step S7100; Step S7100, high-frequency clock alignment step: in the high-frequency clock state, correct the path delays of all sub-clocks so that all sub-clocks are aligned; If the second high frequency maximum delay error is not less than the second delay error threshold, executing step S7200; Step S7200, intermediate frequency clock switching step: switching the clock source from the high frequency clock to the intermediate frequency clock, wherein the intermediate frequency period of the intermediate frequency clock is less than the low frequency period of the calibrated low frequency clock and greater than the high frequency period of the high frequency clock; Step S7210, IF maximum delay error collection step: collecting the IF maximum delay errors of multiple sub-clocks when the clock source is an IF clock; Step S7220, intermediate frequency error determination step: determining whether the maximum intermediate frequency delay error does not exceed a first delay error threshold; If the maximum delay error of the intermediate frequency exceeds the first delay error threshold, step S7230 is executed; Step S7230: IF clock alignment step: In the IF clock state, correct the path delays of all sub-clocks, and then execute step S7240; Step S7240: Switch the clock source from the intermediate frequency clock back to the high frequency clock; If the maximum intermediate frequency delay error does not exceed the first delay error threshold, step S7240 is executed.

[0073] In one feasible embodiment, the high-speed clock alignment method performs steps S7200 to S7230 multiple times, and the intermediate frequency period corresponding to the intermediate frequency clock in the intermediate frequency clock switching step to be executed is smaller than the intermediate frequency period corresponding to the intermediate frequency clock in the previous intermediate frequency clock switching step.

[0074] In one feasible embodiment, in the high-speed clock alignment method: if the maximum delay error of the intermediate frequency exceeds the first delay error threshold, step S7221 is executed; Step S7221, intermediate frequency period determination step: determining whether the intermediate frequency period is not less than 2 times the maximum intermediate frequency delay error; If the intermediate frequency period is not less than 2 times the maximum intermediate frequency delay error, executing step S7230; If the period is less than 2 times the maximum delay error of the intermediate frequency, executing step S7221; Step S7221, step of reducing the clock frequency: reducing the frequency of the intermediate frequency clock to a corresponding intermediate frequency period not less than 2 times the intermediate frequency maximum delay error collected in step S7210, and then executing step S7230.

[0075] The above describes four embodiments of the high-speed clock alignment method of the present invention. However, the present invention is not limited thereto and may be any combination of the technical features of the above embodiments. For example, the fourth embodiment and the second embodiment may be combined to first execute steps S1000-S7240 and then execute steps S50-S70. For another example, the third embodiment and the second embodiment may be combined to first execute steps S100-S600 and then execute steps S50-S70.

[0076] In a feasible embodiment, the steepness of the clock edge can be determined according to the slew rate and / or the edge slope, and different embodiments can be adopted according to different steepness.

[0077] In a feasible embodiment, the period corresponding to the low-frequency clock is much larger than the maximum delay error of the high-frequency clock when it is twice as large as that of the high-frequency clock. For example, it can be 5 times, 10 times, etc. of the maximum delay error, thereby improving reliability and reducing the impact of non-ideal factors in actual environments.

[0078] In a specific embodiment, the high-speed clock alignment method of the present invention is used to align three Figure 2 The sub-clocks of the sequential logic system shown are aligned: This step was performed on all three sequential logic systems: the maximum delay error of the initial sub-clock's first high frequency was 500 ps, ​​and the working clock (high-frequency clock) fH = 10 GHz (period 100 ps). The working clock was switched to a calibrated low-frequency clock of 1 MHz. Each path was corrected under the calibrated low-frequency clock state, achieving absolute delay alignment of the four sub-clocks under the calibrated low-frequency state. For the first sequential logic system, after switching the clock source from the calibrated low-frequency 1M clock directly back to the working clock 10G, the maximum delay error of the second high-frequency clock was reduced to 10ps. The path delay of each sub-clock was corrected under the 10G high-frequency clock, achieving absolute delay alignment of the four sub-clocks. For the second sequential logic system: the clock source is switched from a 1M calibrated low-frequency clock to a 1G intermediate-frequency clock; the path delay of each sub-clock is corrected in the 1G intermediate-frequency clock state; the clock source is switched from a 1G intermediate-frequency clock to a 2G intermediate-frequency clock; the path delay of each sub-clock is corrected in the 2G intermediate-frequency clock state; the clock source is switched back from 2G to a 10G high-frequency clock, achieving absolute delay alignment of the four sub-clocks.

[0079] For the third sequential logic system: after switching the clock source directly from the 1M calibrated low-frequency clock to the 10G, the maximum delay error of the second high frequency is 300ps, which is 0.5 times the maximum delay error of the first high frequency. The clock source is switched from the high-frequency clock source to the 3G intermediate-frequency clock. The path delay of each sub-clock is corrected in the 3G intermediate-frequency clock state. The clock source is switched from 3G back to the 10G high-frequency clock, achieving absolute delay alignment of the four sub-clocks.

[0080] In the above embodiments, the step of correcting the path delays of all sub-clocks includes: Phase detection step: perform phase detection on the two sub-clocks to obtain the phase error; Phase error judgment step: judging whether the phase error is less than the phase threshold; If the phase error is less than the phase threshold, the path delays of the two sub-clocks are not adjusted; If the phase error is not less than the phase threshold, the path delay of one or two sub-clocks is adjusted in a trend toward decreasing the phase error, and the process returns to the phase detection step.

[0081] Figure 12 FIG. 1 is a schematic block diagram of an embodiment of the simulation system of the present invention. Figure 12 As shown, the simulation system 1 includes: The high-frequency error acquisition module 11 is configured to acquire the maximum delay error of multiple sub-clocks of the distributed system 2 when the clock source 21 is a high-frequency clock, as a first high-frequency maximum delay error; a low-frequency clock setting module 12 configured to set a low-frequency clock based on the first high-frequency maximum delay error acquired by the high-frequency error acquisition module 11, wherein the low-frequency period of the low-frequency clock is not less than a set multiple of the first high-frequency maximum delay error; A clock switching module 13 is configured to switch the high-frequency clock of the clock source 21 to the low-frequency clock set by the low-frequency clock setting module 12; The clock switching back module 14 is configured to switch the clock source 21 from the low-frequency clock back to the high-frequency clock; The introduced error acquisition module 15 is configured to acquire a delay error introduced when the clock switching back module 14 switches the clock source 21 from a low-frequency clock to a high-frequency clock, as an introduced delay error; The introduced error judgment module 16 is configured to determine whether the introduced delay error collected by the introduced error collection module 15 is less than a set percentage of the first high-frequency maximum delay error collected by the high-frequency error collection module 11; if the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, the process jumps to the low-frequency clock acquisition module 18; if the introduced delay error is not less than the set percentage of the first high-frequency maximum delay error, the process jumps to the low-frequency improvement module 17; A low frequency increasing module 17 is configured to increase the low frequency clock set by the low frequency clock setting module 12 under the constraint that the frequency is lower than the high frequency clock; The low-frequency clock acquisition module 18 is configured to obtain a calibrated low-frequency clock, the low-frequency period of which is not less than a set multiple of the first high-frequency maximum delay error and the introduced delay error is less than a set percentage of the first high-frequency maximum delay error.

[0082] In a feasible embodiment, the simulation system 1 further includes: The simulation database 19 stores the system data, simulation data and the mapping between the system data and the simulation data of the distributed system 2. The system data includes the structural data and high-frequency clock representing the composition of the distributed system 2. The simulation data includes the first high-frequency maximum delay error and the calibrated low-frequency clock.

[0083] This specification also involves a distributed system 2 and a high-speed clock alignment system 10. Different distributed systems 2 use high-speed clock alignment systems 10 with different configurations, which are described in detail one by one in the following embodiments in conjunction with the distributed system 2 and the high-speed clock alignment system 10.

[0084] The distributed system 2 of the present invention can be Figure 1-Figure 4 A distributed system 2 in any application scenario, wherein the distributed system 2 is configured to perform clock alignment using the high-frequency clock alignment method of the present invention.

[0085] In one possible embodiment, if Figure 13 As shown, the distributed system 2 includes a clock source 21 and at least one buffer stage 22 . The buffer stage 22 may include one or more buffers 221 . The clock source 21 generates multiple sub-clocks through the buffer stage 22 .

[0086] Corresponding to the distributed system 2 of this embodiment, as Figure 14 As shown, the high-speed clock alignment system 10 of the present invention includes a clock frequency adjustment module 3 and a phase correction module 4: The clock frequency adjustment module 3 is configured to switch the clock source 21 of the distributed system to be aligned 2 back and forth between a high-frequency clock and a calibrated low-frequency clock of the distributed system to be aligned obtained by the simulation system 1 ; The phase correction module 4 is configured to correct the path delays of all sub-clocks when the clock frequency adjustment module 3 switches the clock source 21 to the calibrated low-frequency clock.

[0087] In another possible embodiment, Figure 13 As shown, the distributed system 2 includes a clock source 21 , at least one buffer stage 22 and a phase correction module 4 .

[0088] The high-speed clock alignment system 10 corresponding to the distributed system 2 of this embodiment includes a clock frequency adjustment module 3 .

[0089] In the above two embodiments, the clock frequency adjustment module 3 can be implemented by software and / or hardware; the phase correction module 4 can be implemented by hardware or a combination of hardware and software; the simulation system 1 can be implemented by software or a combination of software and hardware.

[0090] In a feasible embodiment, the clock source 21 of the distributed system 2 is a programmable clock source, and the clock frequency adjustment module 3 is a computer program. When the computer program is executed by the programmable clock source, the clock source 21 switches back and forth between a high-frequency clock and a calibrated low-frequency clock.

[0091] In the above embodiments, the phase correction module 4 includes a delay module 41, a delay adjustment module 42 and a phase detector 44: The delay module 41 is provided on the sub-clock path, and the delay module 41 is electrically connected to the delay adjustment module 42; The delay adjustment module 42 is configured to adjust the delay of the delay module 41; The phase detector 44 is electrically connected to the delay adjustment module 42 and is configured to detect the phase of any two sub-clocks and output the delay error of the two sub-clocks, and feed the delay error back to the delay adjustment module 42. The delay adjustment module 42 adjusts the path delay of one or two sub-clocks based on the delay error in a trend of decreasing the delay error. The delay module 41 , the delay adjustment module 42 and the phase detection module form a feedback loop, so that the delay errors of all sub-clocks are smaller than the delay threshold.

[0092] In the above embodiments, the phase correction module 4 may include multiple phase detectors 44, and any two sub-clocks correspond to one phase detector 44. However, in order to save resources, reduce costs and facilitate miniaturization, the phase correction module 4 may include a switch matrix 43 and a phase detector 44. The switch matrix 43 is used to control the conduction and shutdown of the delay adjustment module 42 and the phase detector 44.

[0093] In a preferred embodiment, the phase detection module is a phase detector, and the delay threshold is the accuracy of the phase detector. The accuracy can be close to 0, and the theoretical value under ideal conditions is 0.

[0094] In the above embodiments, the high-speed clock alignment system 10 may further include a simulation system 1 .

[0095] In an application scenario, the simulation system 1 is implemented through software and can be installed on a client (computer, mobile phone, etc.) in the form of an APP; the distributed system 2 is a chip, and the distributed system 2 is composed of a clock source 21 and a buffer stage; the high-speed clock alignment system 10 is a circuit board, and a clock frequency adjustment module 3 and a phase correction module 4 are provided on the circuit board.

[0096] In another application scenario, the distributed system 2 is a chip, and the distributed system 2 is composed of a programmable clock source, a buffer stage and a phase correction module 4; the simulation system 1 is implemented by software, and the high-speed clock system is composed of a clock frequency adjustment module 3, and the clock frequency adjustment module 3 is implemented by software. The software corresponding to the simulation system 1 and the software corresponding to the high-speed clock system can be installed on the client in the form of an APP.

[0097] The foregoing description of this specification describes specific embodiments. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0098] It should be noted that for the aforementioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0099] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0100] The preferred embodiments disclosed above are intended only to help illustrate this specification. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of the embodiments described herein. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the embodiments, thereby enabling those skilled in the art to better understand and utilize this specification.

Claims

1. A method for simulating a distributed system, the distributed system comprising a clock source and at least one buffer level, characterized in that: include: High-frequency simulation step: Collect the maximum delay errors of multiple sub-clocks of the distributed system when the clock source is a high-frequency clock, and use them as the first high-frequency maximum delay error; Clock frequency setting step: setting a low-frequency clock, wherein the low-frequency period of the low-frequency clock is not less than a set multiple of the first high-frequency maximum delay error, and the set multiple is not less than 2; Clock switching steps: switch the high-frequency clock of the clock source to a low-frequency clock; Clock switching back step: switch the clock source from low-frequency clock to high-frequency clock; Clock switchback simulation steps: collect the delay error introduced when the clock source switches from a low-frequency clock to a high-frequency clock, and use it as the introduced delay error; An introduced error determination step: determining whether the introduced delay error is less than a set percentage of the first high frequency maximum delay error; If the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, the simulation is terminated to obtain a calibrated low-frequency clock, wherein the low-frequency period of the calibrated low-frequency clock is not less than the set multiple of the first high-frequency maximum delay error and the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, and the set percentage is not greater than 50%; If the introduced delay error is not less than the set percentage of the first high-frequency maximum delay error, the frequency of the low-frequency clock is increased under the constraint that it is less than the frequency of the high-frequency clock, and the clock frequency setting step is returned to repeat the cycle until the introduced delay error is less than the set percentage of the first high-frequency maximum delay error to obtain a calibrated low-frequency clock.

2. The distributed system simulation method according to claim 1, characterized in that: include: A simulation database is constructed, which stores system data, simulation data and mapping between the system data and simulation data of the distributed system. The system data includes structural data and high-frequency clocks that characterize the composition of the distributed system. The simulation data includes the first high-frequency maximum delay error and the calibrated low-frequency clock.

3. A high-speed clock alignment method, characterized in that: include: The distributed system to be aligned is simulated by the simulation method according to claim 1 to obtain a calibrated low-frequency clock of the distributed system to be aligned; Low-frequency clock switching step: Switch the high-frequency clock of the distributed system clock source to be aligned to the calibrated low-frequency clock; Low-frequency clock alignment steps: When the clock source is a calibrated low-frequency clock, correct the path delays of all sub-clocks to align them. Steps for switching back the high-frequency clock: Switch the clock source from the calibrated low-frequency clock back to the high-frequency clock.

4. A high-speed clock alignment method, characterized in that: include: Obtaining a distributed system with the highest similarity to the distributed system to be aligned from the simulation database constructed by the simulation method according to claim 2, and setting the low-frequency period of the calibrated low-frequency clock of the distributed system to be aligned to be no less than the low-frequency period of the calibrated low-frequency clock of the distributed system with the highest similarity; Low-frequency clock switching step: Switch the high-frequency clock of the distributed system clock source to be aligned to the calibrated low-frequency clock; Low-frequency clock alignment steps: When the clock source is a calibrated low-frequency clock, correct the path delays of all sub-clocks to align them. Steps for switching back the high-frequency clock: Switch the clock source from the calibrated low-frequency clock back to the high-frequency clock.

5. A high-speed clock alignment method, characterized in that: include: Obtaining a distributed system with the highest similarity to the distributed system to be aligned from the simulation database constructed by the simulation method according to claim 2, and setting the low-frequency period of the calibrated low-frequency clock of the distributed system to be aligned to be no less than the low-frequency period of the calibrated low-frequency clock of the distributed system with the highest similarity; Low-frequency clock switching step: Switch the high-frequency clock of the distributed system clock source to be aligned to the calibrated low-frequency clock; Low-frequency clock alignment steps: When the clock source is a calibrated low-frequency clock, correct the path delays of all sub-clocks to align them. An intermediate frequency clock switching step: switching the clock source from the calibrated low frequency clock to an intermediate frequency clock, wherein the frequency of the intermediate frequency clock is higher than the frequency of the low frequency clock and lower than the frequency of the high frequency clock; The intermediate frequency clock alignment step corrects the path delays of all sub-clocks when the clock source is the intermediate frequency clock, so that all sub-clocks are aligned. Steps for switching back the high-frequency clock: Switch the clock source from the intermediate-frequency clock back to the high-frequency clock.

6. The high-speed clock alignment method according to any one of claims 3 to 5, characterized in that: After the high-frequency clock switching back step, the following steps are further included: High-frequency error collection step: Collect the maximum delay errors of multiple sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock, and use this as the second high-frequency maximum delay error. High frequency error judgment step: judging whether the second high frequency maximum delay error does not exceed the first delay error threshold; If the second high frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed; If the second high-frequency maximum delay error exceeds the first delay error threshold, performing a high-frequency clock alignment step; High-frequency clock alignment step: When the clock source is a high-frequency clock, the path delays of all sub-clocks are corrected so that all sub-clocks are aligned.

7. The high-speed clock alignment method according to any one of claims 3 to 5, characterized in that: After the high-frequency clock switching back step, the following steps are further included: High-frequency error collection step: Collect the maximum delay errors of multiple sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock, and use this as the second high-frequency maximum delay error. First high frequency error judgment step: judging whether the second high frequency maximum delay error does not exceed the first delay error threshold; If the second high frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed; If the second high frequency maximum delay error exceeds the first delay error threshold, executing a second high frequency error determination step; A second high frequency error determination step: determining whether the second high frequency maximum delay error is less than a second delay error threshold, wherein the second delay error threshold is greater than the first delay error threshold and is not greater than 0.5 times the first high frequency maximum delay error; If the second high-frequency maximum delay error is less than the second delay error threshold, performing a high-frequency clock alignment step; High-frequency clock alignment step: In the high-frequency clock state, the path delays of all sub-clocks are corrected to align all sub-clocks. If the second high frequency maximum delay error is not less than the second delay error threshold, performing the intermediate frequency clock switching step; An intermediate frequency clock switching step: switching the clock source from the high frequency clock to an intermediate frequency clock, wherein the intermediate frequency period of the intermediate frequency clock is smaller than the low frequency period of the calibrated low frequency clock and larger than the high frequency period of the high frequency clock; In the intermediate frequency clock alignment step, the path delays of all sub-clocks are corrected in the intermediate frequency clock state so that all sub-clocks are aligned, and then the high frequency clock switching back step is performed.

8. The high-speed clock alignment method according to claim 7, wherein: Before the intermediate frequency clock alignment step, the following steps are further included: The maximum delay error acquisition step of the intermediate frequency is as follows: when the clock source is the intermediate frequency clock, the maximum delay error of the intermediate frequency of multiple sub-clocks is acquired; Intermediate frequency period determination step: determining whether the intermediate frequency period corresponding to the intermediate frequency clock is not less than a set multiple of the intermediate frequency maximum delay error; If the intermediate frequency period is not less than the set multiple of the intermediate frequency maximum delay error, performing an intermediate frequency clock alignment step; If the intermediate frequency period is less than the set multiple of the intermediate frequency maximum delay error, executing the step of reducing the clock frequency; Clock frequency reduction step: Reduce the frequency of the intermediate frequency clock until the corresponding intermediate frequency period is not less than the set multiple of the intermediate frequency maximum delay error, and then perform the intermediate frequency clock alignment step.

9. The high-speed clock alignment method according to any one of claims 3 to 5, characterized in that: The step of correcting the path delays of all sub-clocks includes: Phase detection step: perform phase detection on the two sub-clocks to obtain the phase error; Phase error judgment step: judging whether the phase error is less than the phase threshold; If the phase error is less than the phase threshold, the path delays of the two sub-clocks are not adjusted; If the phase error is not less than the phase threshold, the path delay of one or two sub-clocks is adjusted in a trend toward decreasing the phase error, and the process returns to the phase detection step.

10. The high-speed clock alignment method according to claim 5, wherein: Before the high-frequency clock switching back step, multiple intermediate frequency clock switching steps to intermediate frequency clock alignment steps are performed, and the intermediate frequency period corresponding to the intermediate frequency clock in the intermediate frequency clock switching step to be performed is smaller than the intermediate frequency period corresponding to the intermediate frequency clock in the previous intermediate frequency clock switching step.

11. A simulation system for a distributed system, characterized in that: include: a high-frequency error acquisition module configured to acquire a maximum delay error of multiple sub-clocks of the distributed system when the clock source is a high-frequency clock, as a first high-frequency maximum delay error; a low-frequency clock setting module, configured to set a low-frequency clock based on the first high-frequency maximum delay error acquired by the high-frequency error acquisition module, wherein a low-frequency period of the low-frequency clock is not less than a set multiple of the first high-frequency maximum delay error, and the set multiple is not less than 2; A clock switching module configured to switch the high-frequency clock of the clock source to the low-frequency clock set by the low-frequency clock setting module; A clock switchback module is configured to switch the clock source from the low-frequency clock back to the high-frequency clock; an introduced error collection module configured to collect, as an introduced delay error, a delay error introduced when the clock switching back module switches the clock source from the low-frequency clock to the high-frequency clock; an introduced error judgment module, configured to judge whether the introduced delay error collected by the introduced error collection module is less than a set percentage of the first high-frequency maximum delay error collected by the high-frequency error collection module; if the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, jump to the low-frequency clock acquisition module; if the introduced delay error is not less than the set percentage of the first high-frequency maximum delay error, jump to the low-frequency improvement module; the set percentage is not greater than 50%; a low frequency increasing module configured to increase the low frequency clock set by the low frequency clock setting module under the constraint that the frequency is lower than that of the high frequency clock; The low-frequency clock acquisition module is configured to obtain a calibrated low-frequency clock, the low-frequency period of which is not less than a set multiple of the first high-frequency maximum delay error and the introduced delay error is less than a set percentage of the first high-frequency maximum delay error.

12. The distributed system simulation system according to claim 11, characterized in that: Also includes: A simulation database stores system data, simulation data, and a mapping between the system data and the simulation data of a distributed system. The system data includes structural data and a high-frequency clock representing the composition of the distributed system. The simulation data includes a first high-frequency maximum delay error and a calibrated low-frequency clock.

13. A high-speed clock alignment system, characterized in that: include: The clock frequency adjustment module is configured to switch the clock source of the distributed system to be aligned back and forth between the high-frequency clock and the calibrated low-frequency clock of the distributed system to be aligned obtained by the simulation system according to claim 11 or 12.

14. The high-speed clock alignment system according to claim 13, wherein: Also includes: The phase correction module is configured to correct the path delays of all sub-clocks when the clock frequency adjustment module switches the clock source to the calibrated low-frequency clock.

15. The high-speed clock alignment system according to claim 14, wherein: The phase correction module is further configured to correct the path delays of all sub-clocks when the clock source is the high-frequency clock after the clock frequency adjustment module switches the clock source from the calibrated low-frequency clock back to the high-frequency clock.

16. The high-speed clock alignment system according to claim 14, wherein: The phase correction module includes a delay module, a delay adjustment module and a phase detector: The delay module is provided on the sub-clock path of the distributed system, and the delay module is electrically connected to the delay adjustment module; The delay adjustment module is configured to adjust the delay of the delay module; The phase detector is electrically connected to the delay adjustment module and is configured to detect the phases of any two sub-clocks and output a delay error of the two sub-clocks, and feed the delay error back to the delay adjustment module. The delay adjustment module adjusts the path delay of one or two sub-clocks based on the delay error in a direction of decreasing the delay error. The delay module, the delay adjustment module and the phase detection module form a feedback loop, so that the delay errors of all sub-clocks are smaller than the delay threshold.

17. The high-speed clock alignment system according to claim 16, wherein: The phase detector is a phase detector.

18. The high-speed clock alignment system according to claim 13, wherein: Also includes: The simulation system according to claim 11 or 12.

19. A distributed system, characterized in that: The method comprises a clock source and at least one buffer stage, wherein the clock source generates a plurality of sub-clocks through the buffer stage, and the plurality of sub-clocks are configured to be clock aligned by the high-speed clock alignment method according to any one of claims 3 to 10.

20. The distributed system according to claim 19, wherein: The clock source is a programmable clock source.

21. The distributed system according to claim 19, wherein: The distributed system further includes a phase correction module configured to correct the path delays of all sub-clocks.

22. The distributed system according to claim 21, characterized in that: The phase correction module includes a delay module, a delay adjustment module and a phase detector: The delay module is arranged on the sub-clock path, and the delay module is electrically connected to the delay adjustment module; The delay adjustment module is configured to adjust the delay of the delay module; The phase detector is electrically connected to the delay adjustment module and is configured to detect the phases of any two sub-clocks and output a delay error of the two sub-clocks, and feed the delay error back to the delay adjustment module. The delay adjustment module adjusts the path delay of one or two sub-clocks based on the delay error in a direction of decreasing the delay error. The delay module, the delay adjustment module and the phase detection module form a feedback loop, so that the delay errors of all sub-clocks are smaller than the delay threshold.

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