Distributed systems, simulation systems and methods, high speed clock alignment systems and methods

Abstract

The application belongs to the technical field of data information transmission, and provides a distributed system, a simulation system and method, and a high-speed clock alignment system and method, wherein the high-speed clock alignment method comprises the following steps: obtaining a calibration low-frequency clock of a distributed system to be aligned; switching a clock source of the distributed system to be aligned to the calibration low-frequency clock; correcting path delays of all sub-clocks in a state where the clock source is the calibration low-frequency clock, so that all the sub-clocks are aligned; and switching the clock source from the low-frequency clock back to a high-frequency clock. The application can be applied to high-speed clock path delay alignment and can avoid the generation of a period sliding phenomenon.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of data information transmission, and relates to a distributed system, a simulation method and system, a high-speed clock alignment system and method. BACKGROUND

[0002] In a high-speed digital logic or digital-analog hybrid logic circuit, the clock is a very important core part in the system. When the clock is applied, considering the different positions of the clock receiving module in the structure, the clock source will pass through the distributed system to distribute the sub-clock to each part of the system, Figure 1 is a typical distributed system of clock tree established by buffer stage. The total clock (CLKs) of the clock source is generated through three levels of buffer stage to generate four sub-clocks (CLK1, CLK2, CLK3, CLK4) respectively distributed to each part of the system.

[0003] Figure 2 An application scenario of the distributed system applied to a timing logic system is shown. The clock source passes through the clock tree to distribute multiple sub-clocks to multiple timing logic modules of the timing logic system, such as Figure 2 As shown, the data driven by the sub-clocks CLK1 and CLK2 will continue to produce correlation between the output data DATA1 and DATA2 of the subsequent first timing logic module A and the second timing logic module B. The clock information carried by DATA1 and DATA2 respectively from CLK1 and CLK2 will be reflected in the input end of the combination timing logic module AB. For example, the data DATA3 produced by the third timing logic module C driven by the sub-clock CLK3 enters the fourth timing logic module D for logic processing driven by the sub-clock CLK4. The sub-clocks CLK3 and CLK4 with good setup time and hold time requirements are aligned.

[0004] Figure 3 An application scenario of the distributed system applied to a TX transmitter system is shown. The clock source passes through the clock tree to distribute multiple sub-clocks to multiple TX transmitters of the TX transmitter system, such as Figure 3 As shown, for the high-speed signal sending end TX (transmitter), there are usually multiple channels, for example, UCIE, PCIE, etc. The data path is driven by the clock to send data. If the clock is not aligned, it will cause inter-channel skew of data. These high-speed interface protocols have strict restrictions on the skew. Therefore, the sub-clock delay alignment of the distributed system is also required for such applications.

[0005] Although different applications in systems requiring clock distribution systems will have different clock alignment requirements (or simply alignment requirements), for example... Figure 3 High-speed protocols have varying tolerances for offsets; for example, some fixed-frequency systems, under certain constraints, may only require phase alignment, but absolute delay alignment offers the highest robustness. As system data transmission speeds increase and clocks become faster, the alignment requirements for absolute delay alignment of sub-clocks become increasingly stringent.

[0006] Figure 4 This illustrates clock delay path alignment methods commonly used in distributed systems in the prior art, such as... Figure 4 As shown, in a clock distribution system with a period of T, a delay adjustment module is added to the sub-clock distribution path to correct the phase difference. Taking sub-clocks CLKp and CLKq as an example, the clock delay path alignment method is explained. Assuming the clock delay difference is Δ, the sub-clock to be corrected is connected to the phase detector PD of CLKp and CLKq. The detection result of the phase detector is used to control the delay adjustment module to achieve the purpose of correcting the phase difference between sub-clocks CLKp and CLKq.

[0007] As technology advances, system clock frequencies are increasing, meaning the period T is becoming shorter. However, existing clock delay path alignment methods for distributed systems can only achieve "phase alignment," not absolute delay alignment, and therefore cannot reliably provide path delay alignment for high-speed clock systems.

[0008] Figure 5 The left side represents the two sub-clock phases before correction. Figure 5 The right side is based on Figure 4 The result after adjusting the clock path delay alignment method, from Figure 5 It is clear that when the clock exhibits periodic repetition, Figure 4 The clock path delay alignment method cannot distinguish between different clock edges (①, ②, ③). For example, Figure 5 The process will eventually align the lower edge ① with the upper edge ②. It can only achieve "phase alignment", not absolute delay alignment (where the time difference is an integer multiple of the period T).

[0009] Furthermore, the latency error of distributed systems is further exacerbated by limitations imposed by physical conditions, system resource consumption, cost efficiency, and other factors.

[0010] On the one hand, due to physical limitations, distributed systems cannot be reduced in a linear proportion;

[0011] On the other hand, modern systems, considering both power consumption and area, may make clock distribution systems complex and large, which can worsen delay errors.

[0012] When the maximum delay error (Δmax) in the system is comparable to the period T, or even much larger than one T, the period sliding phenomenon occurs, and the maximum delay error after the delay alignment is not only not reduced but also expanded to an integer multiple of the period.

[0013] Therefore, the demand for reliably providing path delay alignment for a high-speed clock system is an important issue to be solved in the industry. SUMMARY

[0014] In view of this, the present application provides a simulation method of a distributed system and a high-speed clock alignment method. One or more embodiments of the present application also relate to a distributed system, a simulation system and a high-speed clock alignment system to solve the technical defects in the prior art.

[0015] According to a first aspect of the present application, a simulation method of a distributed system is provided, the distributed system comprising a clock source and at least one buffer stage, the simulation method comprising:

[0016] a high-frequency simulation step of collecting a maximum delay error of a plurality of sub-clocks of the distributed system when the clock source is a high-frequency clock as a first high-frequency maximum delay error;

[0017] a clock frequency setting step of setting a low-frequency clock, the low-frequency period of the low-frequency clock being not less than a set multiple of the first high-frequency maximum delay error;

[0018] a clock switching step of switching the high-frequency clock of the clock source to the low-frequency clock;

[0019] a clock switching back step of switching the clock source from the low-frequency clock back to the high-frequency clock;

[0020] a clock switching back simulation step of collecting a delay error introduced by switching the clock source from the low-frequency clock back to the high-frequency clock as an introduced delay error;

[0021] an introduced error judgment step of judging whether the introduced delay error is less than a set percentage of the first high-frequency maximum delay error;

[0022] If the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, the simulation is ended, and a calibrated low-frequency clock is obtained, the low-frequency period of the calibrated low-frequency clock being not less than a set multiple of the first high-frequency maximum delay error and the introduced delay error being less than the set percentage of the first high-frequency maximum delay error;

[0023] If the introduced delay error is not less than a set percentage of the first high-frequency maximum delay error, the frequency of the low-frequency clock is increased under a constraint of being less than the frequency of the high-frequency clock, and the clock frequency setting step is returned to for repeated circulation until the introduced delay error is less than the set percentage of the first high-frequency maximum delay error to obtain the calibrated low-frequency clock.

[0024] In a possible implementation, the simulation method further includes:

[0025] A simulation database is constructed, and the simulation database stores system data of the distributed system, simulation data, and a mapping between the system data and the simulation data, the system data includes structure data representing the distributed system and a high-frequency clock, and the simulation data includes a first high-frequency maximum delay error and a calibrated low-frequency clock.

[0026] In a possible implementation, the set multiple is not less than 2, and the set percentage is not greater than 50%.

[0027] According to a second aspect of the present application, a high-speed clock alignment method is provided, including:

[0028] A calibrated low-frequency clock of the distributed system to be aligned is obtained by simulating the distributed system to be aligned through the simulation method;

[0029] A low-frequency clock switching step: switching the high-frequency clock of the clock source of the distributed system to be aligned to the calibrated low-frequency clock;

[0030] A low-frequency clock alignment step: correcting path delays of all sub-clocks in a state where the clock source is the calibrated low-frequency clock, so that all sub-clocks are aligned;

[0031] A high-frequency clock switching back step: switching the clock source from the calibrated low-frequency clock back to the high-frequency clock.

[0032] In a possible implementation, the high-frequency clock switching back step further includes:

[0033] A high-frequency error collecting step: collecting maximum delay errors of a plurality of sub-clocks of the clock source of the distributed system to be aligned after the clock source is switched back to the high-frequency clock as a second high-frequency maximum delay error;

[0034] A high-frequency error judging step: judging whether the second high-frequency maximum delay error is not more than a first delay error threshold;

[0035] If the second high-frequency maximum delay error is not more than the first delay error threshold, the alignment is completed;

[0036] If the second high-frequency maximum delay error is more than the first delay error threshold, a high-frequency clock alignment step is performed;

[0037] high frequency clock alignment step: correcting path delays of all sub-clocks so that all sub-clocks are aligned in the state that the clock source is the high frequency clock.

[0038] In a possible implementation, the first delay error threshold is 0.

[0039] In a possible implementation, the step of correcting path delays of all sub-clocks comprises:

[0040] phase detection step: performing phase detection on two sub-clocks to obtain a phase error;

[0041] phase error judgment step: judging whether the phase error is less than a phase threshold;

[0042] if the phase error is less than the phase threshold, path delays of the two sub-clocks are not adjusted;

[0043] if the phase error is not less than the phase threshold, path delays of one or two sub-clocks are adjusted towards a trend of decreasing the phase error, and the phase detection step is returned to.

[0044] According to a third aspect of the present application, a high speed clock alignment method is provided, comprising:

[0045] obtaining a distributed system with the highest similarity to the distributed system to be aligned from a simulation database constructed by a simulation method, and setting a low frequency period of a calibrated low frequency clock of the distributed system to be aligned to be not less than a low frequency period of a calibrated low frequency clock of the distributed system with the highest similarity;

[0046] low frequency clock switching step: switching a high frequency clock of a clock source of the distributed system to be aligned to a calibrated low frequency clock;

[0047] low frequency clock alignment step: correcting path delays of all sub-clocks so that all sub-clocks are aligned in the state that the clock source is the calibrated low frequency clock;

[0048] high frequency clock switching back step: switching the clock source from the calibrated low frequency clock back to the high frequency clock.

[0049] In a possible implementation, the high frequency clock switching back step further comprises:

[0050] high frequency error collection step: collecting maximum delay errors of a plurality of sub-clocks of the distributed system to be aligned after the clock source is switched back to the high frequency clock as a second high frequency maximum delay error;

[0051] high frequency error judgment step: judging whether the second high frequency maximum delay error exceeds the first delay error threshold;

[0052] If the second high-frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed.

[0053] If the second high-frequency maximum delay error exceeds the first delay error threshold, a high-frequency clock alignment step is performed.

[0054] The high-frequency clock alignment step: in the state of the high-frequency clock as the clock source, corrects the path delay of all sub-clocks so that all sub-clocks are aligned.

[0055] In a possible implementation, the high-frequency clock switching back step further comprises:

[0056] The high-frequency error collection step: collects the maximum delay error of a plurality of sub-clocks of the distributed system to be aligned after the clock source switches back to the high-frequency clock as the second high-frequency maximum delay error.

[0057] The first high-frequency error judgment step: judges whether the second high-frequency maximum delay error exceeds the first delay error threshold.

[0058] If the second high-frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed.

[0059] If the second high-frequency maximum delay error exceeds the first delay error threshold, a second high-frequency error judgment step is performed.

[0060] The second high-frequency error judgment step: judges whether the second high-frequency maximum delay error is less than a second delay error threshold, the second delay error threshold being greater than the first delay error threshold and not greater than 0.5 times the first high-frequency maximum delay error.

[0061] If the second high-frequency maximum delay error is less than the second delay error threshold, a high-frequency clock alignment step is performed.

[0062] The high-frequency clock alignment step: in the state of the high-frequency clock, corrects the path delay of all sub-clocks so that all sub-clocks are aligned.

[0063] If the second high-frequency maximum delay error is not less than the second delay error threshold, a medium-frequency clock switching step is performed.

[0064] The medium-frequency clock switching step: switches the clock source from the high-frequency clock to the medium-frequency clock, the medium-frequency period of the medium-frequency clock being less than the low-frequency period of the calibration low-frequency clock and greater than the high-frequency period of the high-frequency clock.

[0065] The medium-frequency clock alignment step: in the state of the medium-frequency clock, corrects the path delay of all sub-clocks so that all sub-clocks are aligned, and then performs the high-frequency clock switching back step.

[0066] In a possible implementation, the intermediate frequency clock alignment step further comprises:

[0067] The intermediate frequency maximum delay error collection step collects intermediate frequency maximum delay errors of the plurality of sub-clocks when the clock source is the intermediate frequency clock.

[0068] The intermediate frequency period judgment step judges whether the intermediate frequency period corresponding to the intermediate frequency clock is not less than a set multiple of the intermediate frequency maximum delay error.

[0069] If the intermediate frequency period is not less than the set multiple of the intermediate frequency maximum delay error, the intermediate frequency clock alignment step is executed.

[0070] If the intermediate frequency period is less than the set multiple of the intermediate frequency maximum delay error, the clock frequency reduction step is executed.

[0071] The clock frequency reduction step reduces the frequency of the intermediate frequency clock to a corresponding intermediate frequency period that is not less than a set multiple of the intermediate frequency maximum delay error, and then executes the intermediate frequency clock alignment step.

[0072] In a possible implementation, the step of correcting the path delay of all sub-clocks comprises:

[0073] The phase detection step detects the phase of the two sub-clocks to obtain a phase error.

[0074] The phase error judgment step judges whether the phase error is less than a phase threshold.

[0075] If the phase error is less than the phase threshold, the path delay of the two sub-clocks is not adjusted.

[0076] If the phase error is not less than the phase threshold, the path delay of one or two sub-clocks is adjusted towards the trend of reducing the phase error, and the phase detection step is returned.

[0077] According to a fourth aspect of the present application, a high-speed clock alignment method is provided, comprising:

[0078] Obtaining a distributed system with the highest similarity to the distributed system to be aligned from a simulation database constructed by a simulation method, and setting a low-frequency period of a calibrated low-frequency clock of the distributed system to be aligned to be not less than a low-frequency period of a calibrated low-frequency clock of the distributed system with the highest similarity.

[0079] The low-frequency clock switching step switches a high-frequency clock of the clock source of the distributed system to be aligned to the calibrated low-frequency clock.

[0080] The low-frequency clock alignment step corrects the path delay of all sub-clocks to align all sub-clocks when the clock source is the calibrated low-frequency clock.

[0081] a medium frequency clock switching step of switching the clock source from the low frequency clock to a medium frequency clock, the medium frequency clock having a frequency higher than that of the low frequency clock and lower than that of the high frequency clock;

[0082] a medium frequency clock alignment step of correcting path delays of all the sub-clocks so as to align all the sub-clocks when the clock source is the medium frequency clock;

[0083] a high frequency clock switching back step of switching the clock source from the medium frequency clock back to the high frequency clock.

[0084] In a possible implementation, the high frequency clock switching back step is further followed by:

[0085] a high frequency error collecting step of collecting a maximum delay error of a plurality of sub-clocks of the distributed system after the clock source is switched back to the high frequency clock as a second high frequency maximum delay error;

[0086] a high frequency error judging step of judging whether the second high frequency maximum delay error is not more than the first delay error threshold;

[0087] if the second high frequency maximum delay error is not more than the first delay error threshold, the alignment is completed;

[0088] if the second high frequency maximum delay error is more than the first delay error threshold, a high frequency clock alignment step is performed;

[0089] the high frequency clock alignment step of correcting path delays of all the sub-clocks so as to align all the sub-clocks when the clock source is the high frequency clock.

[0090] In a possible implementation, the high frequency clock switching back step is preceded by a plurality of medium frequency clock switching steps to the medium frequency clock alignment step, the medium frequency clock corresponding to the medium frequency clock switching step to be performed having a medium frequency period smaller than that of the last medium frequency clock switching step.

[0091] In a possible implementation, the medium frequency clock alignment step is further preceded by:

[0092] a medium frequency maximum delay error collecting step of collecting a medium frequency maximum delay error of a plurality of sub-clocks when the clock source is the medium frequency clock;

[0093] a medium frequency period judging step of judging whether a medium frequency period corresponding to the medium frequency clock is not smaller than a set multiple of the medium frequency maximum delay error;

[0094] if the medium frequency period is not smaller than the set multiple of the medium frequency maximum delay error, the medium frequency clock alignment step is performed;

[0095] if the intermediate frequency period is less than a set multiple of the maximum delay error of the intermediate frequency, then performing a step of reducing the clock frequency;

[0096] the step of reducing the clock frequency: reducing the frequency of the intermediate frequency clock to a corresponding intermediate frequency period not less than a set multiple of the maximum delay error of the intermediate frequency, and then performing the step of aligning the intermediate frequency clock.

[0097] In one possible implementation, the step of correcting the path delay of all sub-clocks comprises:

[0098] the step of phase detection: performing phase detection on the two sub-clocks to obtain a phase error;

[0099] the step of phase error judgment: judging whether the phase error is less than a phase threshold value;

[0100] if the phase error is less than the phase threshold value, then not adjusting the path delay of the two sub-clocks;

[0101] if the phase error is not less than the phase threshold value, then adjusting the path delay of one or two sub-clocks towards a trend of decreasing the phase error, and returning to the step of phase detection.

[0102] According to a fifth aspect of the present application, a simulation system of a distributed system is provided, comprising:

[0103] a high frequency error collection module configured to collect maximum delay errors of a plurality of sub-clocks of the distributed system when a clock source is a high frequency clock as first high frequency maximum delay errors;

[0104] a low frequency clock setting module configured to set a low frequency clock based on the first high frequency maximum delay errors collected by the high frequency error collection module, wherein a low frequency period of the low frequency clock is not less than a set multiple of the first high frequency maximum delay errors;

[0105] a clock switching module configured to switch the high frequency clock of the clock source to the low frequency clock set by the low frequency clock setting module;

[0106] a clock switching back module configured to switch the clock source from the low frequency clock back to the high frequency clock;

[0107] an introduced error collection module configured to collect a delay error introduced by the clock switching back module switching the clock source from the low frequency clock back to the high frequency clock as an introduced delay error;

[0108] an introduction error judging module configured to judge whether the introduction delay error collected by the introduction error collecting module is less than a set percentage of the first high-frequency maximum delay error collected by the high-frequency error collecting module; if the introduction delay error is less than the set percentage of the first high-frequency maximum delay error, jump to a low-frequency clock obtaining module; if the introduction delay error is not less than the set percentage of the first high-frequency maximum delay error, jump to a low-frequency increasing module;

[0109] a low-frequency increasing module configured to increase the low-frequency clock set by the low-frequency clock setting module under a constraint of a frequency of the high-frequency clock;

[0110] a low-frequency clock obtaining module configured to obtain a calibrated low-frequency clock, a low-frequency period of the calibrated low-frequency clock being not less than a set multiple of the first high-frequency maximum delay error and the introduction delay error being less than the set percentage of the first high-frequency maximum delay error.

[0111] In a possible implementation, the simulation system further comprises:

[0112] a simulation database, the simulation database storing system data of the distributed system, simulation data, and a mapping between the system data and the simulation data, the system data including structure data representing a constitution of the distributed system and a high-frequency clock, the simulation data including the first high-frequency maximum delay error and the calibrated low-frequency clock.

[0113] According to a sixth aspect of the present application, there is provided a high-speed clock alignment system, comprising:

[0114] a clock frequency adjusting module configured to switch a clock source of a distributed system to be aligned back and forth between a high-frequency clock and a calibrated low-frequency clock of the distributed system to be aligned obtained by the simulation system.

[0115] In a possible implementation, the high-speed clock alignment system further comprises a phase correction module configured to correct path delays of all sub-clocks when the clock frequency adjusting module switches the clock source to the calibrated low-frequency clock.

[0116] In a possible implementation, the phase correction module is further configured to correct path delays of all sub-clocks when the clock source is the high-frequency clock after the clock frequency adjusting module switches the clock source from the calibrated low-frequency clock back to the high-frequency clock.

[0117] In a possible implementation, the phase correction module comprises a delay module, a delay adjusting module, and a phase detector:

[0118] The delay module is arranged on a sub-clock path of the distributed system, and the delay module is electrically connected with the delay adjustment module;

[0119] The delay adjustment module is configured to adjust the delay of the delay module.

[0120] The phase detector is electrically connected with the delay adjustment module, and is configured to detect a phase of any two sub-clocks, output a delay error of the two sub-clocks, and feed back the delay error to the delay adjustment module, and the delay adjustment module adjusts a path delay of one or two sub-clocks based on the delay error in a direction in which the delay error decreases.

[0121] The delay module, the delay adjustment module and the phase detector form a feedback loop, so that the delay error of all sub-clocks is less than a delay threshold.

[0122] In a possible implementation, the phase detector is a phase discriminator.

[0123] In a possible implementation, the delay threshold is a phase discrimination accuracy of the phase discriminator.

[0124] In a possible implementation, the high-speed clock alignment system further comprises an emulation system.

[0125] According to a seventh aspect of the present application, a distributed system is provided, comprising a clock source and at least one buffer stage, the clock source generates a plurality of sub-clocks through the buffer stage, and the plurality of sub-clocks are configured to be clock-aligned through the high-speed clock alignment method.

[0126] In a possible implementation, the clock source is a programmable clock source.

[0127] In a possible implementation, the distributed system further comprises a phase correction module, and the phase correction module is configured to correct path delays of all sub-clocks.

[0128] In a possible implementation, the phase correction module comprises a delay module, a delay adjustment module and a phase detector.

[0129] The delay module is arranged on a sub-clock path of the distributed system, and the delay module is electrically connected with the delay adjustment module;

[0130] The delay adjustment module is configured to adjust the delay of the delay module.

[0131] The phase detector is electrically connected with the delay adjustment module, configured to detect phase outputs of any two sub-clocks, output delay errors of the two sub-clocks, and feed back the delay errors to the delay adjustment module, and the delay adjustment module adjusts path delays of one or two sub-clocks based on the delay errors to the trend of reducing the delay errors.

[0132] The delay module, the delay adjustment module and the phase detection module form a feedback loop, so that delay errors of all sub-clocks are less than a delay threshold.

[0133] The simulation method and system simulate a first high-frequency maximum delay error of a distributed system at a high-frequency clock, set a low-frequency period of a low-frequency clock to be not less than 2 times the first high-frequency maximum delay error, so that a phase difference under the low-frequency clock is always within an unambiguous range; then switch the clock source to the low-frequency clock and then switch back to the high-frequency clock, then simulate a delay error introduced by the clock switching, and finally when the introduced error is not less than 50%, the low-frequency clock is calibrated again, avoiding a period sliding phenomenon caused by too large delay error introduced by switching from the low-frequency to the high-frequency; the accuracy of calibrating the low-frequency clock is ensured from the low-frequency period and the delay error introduced by the clock switching, and the period sliding phenomenon is avoided.

[0134] The high-speed clock alignment system and method can simulate a distributed system to be aligned by using the simulation system or the simulation method, obtain a corresponding calibration low-frequency error, switch a clock source of the distributed system to be aligned from a high-frequency clock to a calibration low-frequency clock, set a low-frequency period of the calibration low-frequency clock to be not less than 2 times a first high-frequency maximum delay error of the distributed system to be aligned, so that a phase difference under the calibration low-frequency clock is always within an unambiguous range, then perform clock path delay alignment under the calibration low-frequency clock, and eliminate a baseband phase difference, thereby avoiding a period sliding phenomenon.

[0135] The high-speed clock alignment system and method can also obtain a calibration low-frequency clock of a distributed system most similar to the distributed system to be aligned from a simulation database. Although this way of obtaining the calibration low-frequency clock of the distributed system to be aligned is less accurate than the way of directly simulating the calibration low-frequency clock of the distributed system to be aligned, this way can be applied to a situation that cannot be simulated. When the distributed system to be aligned is highly similar to a distributed system in the simulation database, clock path delay alignment is performed under the similar calibration low-frequency clock, the period sliding phenomenon is prevented while the clock alignment is performed, the low-frequency clock can be switched to a medium-frequency clock, the high-frequency clock is switched back after the medium-frequency clock is aligned, the introduced error is reduced, and the period sliding phenomenon is prevented. When the distributed system to be aligned is less similar to a distributed system in the simulation database, the second high-frequency maximum delay error after the introduced delay error after the high-frequency clock is switched back from the similar calibration low-frequency clock is judged, and clock path delay alignment is performed under the high-frequency clock, the delay error caused by the similar calibration low-frequency clock is reduced, and the period sliding phenomenon is prevented.

[0136] The multiple sub-clocks of the distributed system are aligned through the high-speed clock alignment method, the problem of delay mismatch of the clock tree itself is solved based on the clock tree, and the path delay correction of the multiple sub-clocks is realized at high speed, reliably and accurately. BRIEF DESCRIPTION OF DRAWINGS

[0137] Figure 1 is a structural schematic diagram of an embodiment of a distributed system of a clock tree in the prior art;

[0138] Figure 2 is an application scenario schematic diagram of an embodiment of the distributed system applied to a timing logic system;

[0139] Figure 3 is an application scenario schematic diagram of another embodiment of the distributed system applied to a timing logic system;

[0140] Figure 4 is a schematic diagram of an embodiment of a clock delay path alignment method commonly used by the distributed system in the prior art;

[0141] Figure 5 is Figure 4 is a waveform schematic diagram of an embodiment of clock delay path alignment of the clock delay path alignment method;

[0142] Figure 6 is a flowchart schematic diagram of an embodiment of the simulation method;

[0143] Figure 7 is a flowchart schematic diagram of an embodiment of the high-speed clock alignment method;

[0144] Figure 8 is a waveform variation diagram of an embodiment of the high-speed clock alignment method of the present application;

[0145] Figure 9 is a flowchart diagram of a second embodiment of the high-speed clock alignment method of the present application;

[0146] Figure 10 is a flowchart diagram of a third embodiment of the high-speed clock alignment method of the present application;

[0147] Figure 11 is a flowchart diagram of a fourth embodiment of the high-speed clock alignment method of the present application;

[0148] Figure 12 is a block diagram of an embodiment of the simulation system of the present application;

[0149] Figure 13 is a diagram of an embodiment of the distributed system of the present application;

[0150] Figure 14 is a diagram of an embodiment of the high-speed clock alignment system of the present application;

[0151] wherein: A, a first sequential logic module; B, a second sequential logic module; AB, a combinational sequential logic module; C, a third sequential logic module; D, a fourth sequential logic module; PD, a phase detector; 1, a simulation system; 11, a high-frequency error collection module; 12, a low-frequency clock setting module; 13, a clock switching module; 14, a clock switching-back module; 15, an introduced error collection module; 16, an introduced error judgment module; 17, a low-frequency improvement module; 18, a low-frequency clock obtaining module; 19, a simulation database; 2, a distributed system; 21, a clock source; 22, a buffer stage; 221, a buffer; 3, a clock frequency adjustment module; 4, a phase correction module; 41, a delay module; 42, a delay adjustment module; 43, a switch matrix; 44, a phase detector; 10, a high-speed clock alignment system. DETAILED DESCRIPTION

[0152] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details set forth in this description. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application.

[0153] The terminology used in this disclosure of one or more embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure of one or more embodiments. As used in this disclosure and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0154] It should be understood that although the terms first, second, etc. can be used herein to describe various information, these terms are not intended to denote a particular order or hierarchy among the information. These terms are used merely for distinguishing between information of the same type. For example, a first entity discussed below could be termed a second entity without departing from the scope of this disclosure of one or more embodiments. As used herein, the term "if' can be interpreted to mean "when" or "upon" or "in response to determining" taking into account negation that can be associated with such term.

[0155] First, the noun terms related to the disclosure of one or more embodiments are explained.

[0156] UCIE: Unified Chiplet Interconnect Express, which is a general chiplet interconnect technology;

[0157] PCIE: Peripheral Component Interconnect Express, which is a high-speed serial computer expansion bus standard;

[0158] Periodic sliding: when the clock path delay error is too large, the phase detector (such as a digital phase detector or a phase frequency detector) cannot distinguish whether the phase difference falls within a single period or crosses multiple periods, resulting in a whole period misjudgment in the correction process.

[0159] The prior art aligns clock data based on data path through link training, which requires fixed data and a receiver, and is not applicable to cases without a receiver (such as Figure 2 ). In addition, the phase detection method in the prior art cannot distinguish different clock edges and can only achieve phase alignment. When the delay error is large, periodic sliding phenomenon is likely to occur.

[0160] Based on the technical problems of the prior art, the present application solves the problem of delay mismatch from the clock tree itself.

[0161] The present application can obtain a calibration low-frequency clock capable of realizing multiple sub-clock unambiguous phase detection by simulating the distributed system to be aligned; then, unambiguous clock path delay correction is performed under the calibration low-frequency clock, which avoids period sliding and eliminates large delay error or even realizes absolute delay alignment; the clock source is switched back to the high-frequency clock from the calibration low-frequency clock, and even if an error is introduced, the introduced error is very small, which can meet the clock alignment requirements of most distributed systems; even in the case of strict absolute alignment, the very small introduced error can be eliminated by performing clock path delay correction after switching back to the high-frequency clock.

[0162] The present application can also select the calibration low-frequency clock of the stored distributed system with the highest similarity to the distributed system to be aligned as the calibration low-frequency clock of the distributed system to be aligned based on the simulation database storing multiple distributed systems and their calibration low-frequency clocks. Although the accuracy of the calibration low-frequency clock of the distributed system to be aligned obtained by the similarity method may not be as good as that of the calibration low-frequency clock obtained by directly simulating the distributed system to be aligned due to the influence of the similarity, the present application can guarantee the reliability of the clock path delay alignment from one or more of the following aspects:

[0163] First, a low-frequency clock with a low-frequency period that is sufficiently larger than that of the calibration low-frequency clock of the distributed system with the highest similarity can be selected as the calibration low-frequency clock of the distributed system to be aligned;

[0164] Second, when the introduced delay error of the calibration low-frequency clock switching back to the high-frequency clock is small, the introduced delay error can be eliminated by clock path delay correction under the high-frequency clock;

[0165] Third, when the introduced delay error of the calibration low-frequency clock switching back to the high-frequency clock is large, the clock source can be switched back to the high-frequency clock after passing through the calibration low-frequency clock and correction and at least once intermediate-frequency clock and correction; the high-frequency clock, high-frequency clock correction, or switching to at least once intermediate-frequency clock and correction and then returning to the high-frequency clock can also be maintained by judging the maximum delay error after switching back to the high-frequency clock.

[0166] Figure 6 is a flowchart of an embodiment of the simulation method of the present application, as shown in Figure 6 The simulation method comprises:

[0167] Step S11, high-frequency simulation step: collect the maximum delay error of multiple sub-clocks of the distributed system when the clock source is a high-frequency clock as a first high-frequency maximum delay error;

[0168] Step S12, clock frequency setting step: setting a low frequency clock, a low frequency period of the low frequency clock is not less than a first high frequency maximum delay error of a set multiple, preferably, the set multiple is not less than 2;

[0169] Step S13, clock switching step: switching a high frequency clock of a clock source to a low frequency clock;

[0170] Step S14, clock switching back step: switching back the clock source from the low frequency clock to the high frequency clock;

[0171] Step S15, clock switching back simulation step: collecting a delay error introduced by switching back the clock source from the low frequency clock to the high frequency clock as an introduced delay error;

[0172] Step S16, introduced error judging step: judging whether the introduced delay error is less than a set percentage of the first high frequency maximum delay error, preferably, the set percentage is not more than 50%;

[0173] If the introduced delay error is less than the set percentage of the first high frequency maximum delay error, step S18 is performed: ending the simulation, obtaining a calibrated low frequency clock, a low frequency period of the calibrated low frequency clock is not less than the first high frequency maximum delay error of the set multiple and the introduced delay error is less than the set percentage of the first high frequency maximum delay error;

[0174] If the introduced delay error is not less than the set percentage of the first high frequency maximum delay error, step S17 is performed: improving the frequency of the low frequency clock under a constraint of less than the frequency of the high frequency clock, returning to the clock frequency setting step, repeating the cycle until the introduced delay error is less than the set percentage of the first high frequency maximum delay error to obtain the calibrated low frequency clock.

[0175] In one feasible embodiment of the present application, the simulation method further comprises:

[0176] constructing a simulation database, the simulation database storing system data of the distributed system, simulation data and mapping between the system data and the simulation data, the system data including structure data representing the distributed system and the high frequency clock, the simulation data including the first high frequency maximum delay error and the calibrated low frequency clock.

[0177] Figure 7 is a flowchart of one embodiment of the high speed clock alignment method of the present application, as Figure 7 shown, the high speed clock alignment method comprises:

[0178] Step S1, obtaining a first high frequency maximum delay error of a clock source of a distributed system to be aligned under a high frequency clock (as Figure 8The low-frequency clock is calibrated, and a low-frequency period of the calibrated low-frequency clock is not less than 2 times of the first high-frequency maximum delay error and introduces a delay error less than 50% of the first high-frequency maximum delay error; the calibrated low-frequency clock of the distributed system to be aligned can be obtained by simulating the distributed system to be aligned through a simulation method, can be obtained from a simulation database, and can be obtained from a calibrated low-frequency clock of a distributed system with the highest similarity to the distributed system to be aligned, or a low-frequency clock with a low-frequency period multiple (for example, much greater than 2 times, 5 times, 20 times, etc.) corresponding to a low-frequency period of the calibrated low-frequency clock of the distributed system with the highest similarity can be used as the calibrated low-frequency clock of the distributed system to be aligned; the similarity can be analyzed by combining one or more similarities of a structure parameter, a timing index and a dynamic response; the structure parameter includes one or more of a topology type, node distribution and hierarchy of the distributed system; the timing index includes clock skew comparison or / and jitter tolerance; and the dynamic response includes dynamic time warping or / and Euclidean distance.

[0179] In step S2, the high-frequency clock of the clock source of the distributed system to be aligned is switched to the calibrated low-frequency clock, and in the state of the calibrated low-frequency clock, a clock waveform diagram of two sub-clocks corresponding to the first high-frequency maximum delay error is as shown in FIG. 2. Figure 8

[0180] In step S3, the path delay of all sub-clocks is corrected in the state of the clock source being the calibrated low-frequency clock, so that all sub-clocks are aligned, and a clock waveform diagram of two sub-clocks in the state of the aligned calibrated low-frequency clock is as shown in FIG. 3. Figure 8

[0181] In step S4, the clock source is switched back to the high-frequency clock, and after the high-frequency clock is switched back, a clock waveform diagram of two sub-clocks is as shown in FIG. 4. Figure 8

[0182] The simulation method of the present application can be used to simulate the distributed system to be aligned, so that a calibrated low-frequency clock with a period not less than 2 times of the first high-frequency maximum delay error or even much greater than the maximum delay error can be obtained, so that the maximum phase difference of the maximum delay error after the calibrated low-frequency clock is switched is strictly limited within 180°, a conventional phase discriminator can accurately measure the phase difference within the range of-180° to 180°, and the multi-period error is not misjudged, so that the phase detection is unambiguous, the path delay of the clock is corrected, so that the phase difference of all clock paths is zero, and the accurate alignment is realized. When the high-frequency mode is switched back, the compensation value is directly applied to the high-frequency clock path, so that the path delay remains consistent with the low-frequency alignment state. The low-frequency correction has eliminated the baseband phase difference, and the correction amount inherited in the high-frequency mode ensures the initial phase alignment. ​​​

[0183] In addition, the low frequency period of the low frequency clock is not less than 2 times of the first high frequency maximum delay error, so that greater phase margin is provided, the phase discrimination process is ensured not to be disturbed, and the correction robustness is enhanced.

[0184] In the distributed system with steep clock edge, the delay on each sub-clock path is basically fixed, and after the above high speed clock alignment method, the delay change is small, so that each sub-clock is basically aligned.

[0185] However, in the distributed system with non-steep clock edge, the delay may change greatly when switching from the low frequency clock to the high frequency clock.

[0186] In addition, the delay of some circuits is not fixed at different frequencies, for example, the delay is adjusted when the low frequency clock is aligned, and then the absolute delay of some branches changes due to different clock frequencies when the high frequency clock is switched.

[0187] Furthermore, in the system with high precision requirement, the small delay error introduced by switching from the low frequency clock to the high frequency clock cannot be ignored, and has influence on the system performance.

[0188] To solve the above technical problems, the application further provides the following high speed clock alignment methods.

[0189] Figure 9 is a flowchart of a second embodiment of the high speed clock alignment method according to the application, as shown in the figure, the high speed clock alignment method comprises: Figure 9

[0190] Step S10, obtaining a calibration low frequency clock of a distributed system to be aligned;

[0191] Step S20, low frequency clock switching step: switching the clock source to the calibration low frequency clock;

[0192] Step S30, low frequency clock alignment step: correcting the path delay of all sub-clocks in the calibration low frequency clock state;

[0193] Step S40, high frequency clock switching step: switching the clock of the clock source back to the high frequency clock;

[0194] Step S50, high frequency error collection step: collecting the maximum delay error of the plurality of sub-clocks after the clock source of the distributed system to be aligned is switched back to the high frequency clock as the second high frequency maximum delay error;

[0195] Step S60, high frequency error collection step: high frequency error judgment step: judging whether the second high frequency maximum delay error is less than the first delay error threshold;

[0196] ​If the second high-frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed;

[0197] If the second high-frequency maximum delay error exceeds the first delay error threshold, step S70 is performed.

[0198] Step S70, high-frequency clock alignment step: in the state that the clock source is the high-frequency clock, the path delay of all sub-clocks is corrected so that all sub-clocks are aligned.

[0199] The high-speed clock alignment method eliminates the delay error introduced by frequency switching.

[0200] In the above embodiment, the first delay error threshold can be set to 0, realizing the absolute alignment of all sub-clocks of the distributed system.

[0201] Figure 10 is a flowchart of a third embodiment of the high-speed clock alignment method according to the present application, as shown in the figure, the high-speed clock alignment method comprises: Figure 10

[0202] Step S100, obtaining a calibration low-frequency clock of a distributed system to be aligned;

[0203] Step S200, low-frequency clock switching step: switching the clock source to the calibration low-frequency clock;

[0204] Step S300, low-frequency clock alignment step: in the state that the clock source is the calibration low-frequency clock, the path delay of all sub-clocks is corrected so that all sub-clocks are aligned;

[0205] Step S400, medium-frequency clock switching step: switching the clock source from the low-frequency clock to a medium-frequency clock, the frequency of the medium-frequency clock is higher than that of the low-frequency clock and lower than that of the high-frequency clock;

[0206] Step S500, medium-frequency clock alignment step: in the state that the clock source is the medium-frequency clock, the path delay of all sub-clocks is corrected so that all sub-clocks are aligned;

[0207] Step S600, high-frequency clock switching back step: switching the clock source from the medium-frequency clock back to the high-frequency clock.

[0208] In a feasible embodiment, step S600 is performed before step S400-step S500 is performed multiple times, and the medium-frequency period corresponding to the medium-frequency clock of the medium-frequency clock switching step to be performed is less than the medium-frequency period corresponding to the medium-frequency clock of the last medium-frequency clock switching step.

[0209] ​The high-speed clock alignment method converts the clock into high-frequency clock-low-frequency clock-medium-frequency clock-high-frequency clock, and eliminates the delay error introduced by the high-frequency clock-low-frequency clock through path delay correction under multiple different frequency clocks. The low-frequency clock is switched back to the high-frequency clock through the medium-frequency clock, which avoids introducing too large delay error when directly switching back to the high-frequency clock from the low-frequency clock, and eliminates the risk of period sliding when directly switching back to the working target high-frequency clock.

[0210] Generally, the delay error introduced by clock frequency switching is relatively low, and period sliding is generally not generated. However, in the case of extreme difference of circuit, the low-frequency clock switching back to the high-frequency clock may introduce larger delay error, and there is a risk of period sliding. In order to solve the technical problem, the following embodiments are provided:

[0211] Figure 11 is a flowchart of the fourth embodiment of the high-speed clock alignment method according to the application, as shown in Figure 11 The high-speed clock alignment method comprises the following steps:

[0212] In step S1000, a calibration low-frequency clock of a distributed system to be aligned is obtained.

[0213] In step S2000, a low-frequency clock switching step is performed, in which the clock source is switched to the calibration low-frequency clock.

[0214] In step S3000, a low-frequency clock alignment step is performed, in which the path delay of all sub-clocks is corrected under the condition that the clock source is the calibration low-frequency clock, so that all sub-clocks are aligned.

[0215] In step S4000, a high-frequency clock switching back step is performed, in which the clock source is switched back from the low-frequency clock to the high-frequency clock.

[0216] In step S5000, a high-frequency error collection step is performed, in which the maximum delay error of a plurality of sub-clocks after the clock source of the distributed system to be aligned is switched back to the high-frequency clock is collected as a second high-frequency maximum delay error.

[0217] In step S6000, a first high-frequency error judgment step is performed, in which it is judged whether the second high-frequency maximum delay error exceeds a first delay error threshold.

[0218] If the second high-frequency maximum delay error does not exceed the first delay error threshold, the alignment is completed.

[0219] If the second high-frequency maximum delay error exceeds the first delay error threshold, step S7000 is performed.

[0220] Step S7000, second high-frequency error judgment step: judging whether the second high-frequency maximum delay error is less than a second delay error threshold, the second delay error threshold being greater than the first delay error threshold and not greater than 0.5 times of the first high-frequency maximum delay error, for example, the alignment requirement is absolute delay alignment, the first delay error threshold is 0, and the second delay error threshold is 0.5 times of the first high-frequency maximum delay error;

[0221] If the second high-frequency maximum delay error is less than the second delay error threshold, step S7100 is performed.

[0222] Step S7100, high-frequency clock alignment step: in the high-frequency clock state, correcting the path delay of all sub-clocks so that all sub-clocks are aligned.

[0223] If the second high-frequency maximum delay error is not less than the second delay error threshold, step S7200 is performed.

[0224] Step S7200, intermediate-frequency clock switching step: switching the clock source from the high-frequency clock to the intermediate-frequency clock, the intermediate-frequency period of the intermediate-frequency clock being less than the low-frequency period of the nominal low-frequency clock and greater than the high-frequency period of the high-frequency clock.

[0225] Step S7210, intermediate-frequency maximum delay error collection step: collecting the intermediate-frequency maximum delay error of a plurality of sub-clocks when the clock source is the intermediate-frequency clock.

[0226] Step S7220, intermediate-frequency error judgment step: judging whether the intermediate-frequency maximum delay error exceeds the first delay error threshold.

[0227] If the intermediate-frequency maximum delay error exceeds the first delay error threshold, step S7230 is performed.

[0228] Step S7230, intermediate-frequency clock alignment step: in the intermediate-frequency clock state, correcting the path delay of all sub-clocks, and then performing step S7240.

[0229] Step S7240: switching the clock source from the intermediate-frequency clock back to the high-frequency clock.

[0230] If the intermediate-frequency maximum delay error does not exceed the first delay error threshold, step S7240 is performed.

[0231] In one feasible embodiment, the high-speed clock alignment method described above is performed multiple times, and the intermediate-frequency clock corresponding to the intermediate-frequency clock switching step to be performed is less than the intermediate-frequency period corresponding to the last intermediate-frequency clock switching step.

[0232] In one possible embodiment, in the above high-speed clock alignment method, if the intermediate frequency maximum delay error exceeds the first delay error threshold, step S7221 is performed.

[0233] In step S7221, an intermediate frequency period judgment step is performed to determine whether the intermediate frequency period is not less than twice the intermediate frequency maximum delay error.

[0234] If the intermediate frequency period is not less than twice the intermediate frequency maximum delay error, step S7230 is performed.

[0235] If the period is less than twice the intermediate frequency maximum delay error, step S7221 is performed.

[0236] In step S7221, a low clock frequency step is performed to reduce the frequency of the intermediate frequency clock to a corresponding intermediate frequency period that is not less than the intermediate frequency maximum delay error collected in step S7210, and then step S7230 is performed.

[0237] The above shows four embodiments of the high-speed clock alignment method of the present application, but the present application is not limited thereto and can be any combination of technical features in the above embodiments, for example, the fourth embodiment and the second embodiment are combined, steps S1000-S7240 are performed first, and then steps S50-S70 are performed; for another example, the third embodiment and the second embodiment are combined, steps S100-S600 are performed first, and then steps S50-S70 are performed.

[0238] In one possible embodiment, the steepness of the clock edge can be determined according to the slew rate or / and the edge slope, and different embodiments are used according to different steepness.

[0239] In one possible embodiment, the period of the low-frequency clock is much larger than twice the maximum delay error of the high-frequency clock, for example, it can be 5 times, 10 times, etc. of the maximum delay error, to improve reliability and reduce the influence of non-ideal factors in the actual environment.

[0240] In one specific embodiment, the high-speed clock alignment method of the present application is used to align three Figure 2 The sub-clocks of the timing logic system shown are aligned.

[0241] This step is performed on the three timing logic systems: the first high-frequency maximum delay error of the initial sub-clock is 500 ps, the working clock (high-frequency clock) fH=10G (period 100 ps), the working clock is switched to a 1M calibration low-frequency clock, the paths are corrected in the calibration low-frequency clock state, and the absolute delay alignment of the four sub-clocks in the calibration low-frequency state is achieved.

[0242] For the first timing logic system: after the clock source is directly switched from the calibration low-frequency clock 1M to the working clock 10G, the second high-frequency maximum delay error is 10ps, the path delay of each sub-clock is corrected under the 10G high-frequency clock, and the absolute delay alignment of the four sub-clocks is realized;

[0243] For the second timing logic system: the clock source is switched from the 1M calibration low-frequency clock to the 1G intermediate-frequency clock; the path delay of each sub-clock is corrected under the 1G intermediate-frequency clock state; the clock source is switched from the 1G intermediate-frequency clock to the 2G intermediate-frequency clock; the path delay of each sub-clock is corrected under the 2G intermediate-frequency clock state; the clock source is switched from the 2G to the 10G high-frequency clock, and the absolute delay alignment of the four sub-clocks is realized.

[0244] For the third timing logic system: after the clock source is directly switched from the 1M calibration low-frequency clock to the 10G, the second high-frequency maximum delay error is 300ps, which is more than 0.5 times of the first high-frequency maximum delay error; the clock source is switched from the high-frequency clock source to the 3G intermediate-frequency clock; the path delay of each sub-clock is corrected under the 3G intermediate-frequency clock state; the clock source is switched from the 3G to the 10G high-frequency clock, and the absolute delay alignment of the four sub-clocks is realized.

[0245] In the above embodiments, the step of correcting the path delay of all sub-clocks includes:

[0246] The phase detection step: the phase error is obtained by phase detection of two sub-clocks;

[0247] The phase error judgment step: whether the phase error is less than the phase threshold value;

[0248] If the phase error is less than the phase threshold value, the path delay of the two sub-clocks is not adjusted;

[0249] If the phase error is not less than the phase threshold value, the path delay of one or two sub-clocks is adjusted towards the trend of reducing the phase error, and the phase detection step is returned.

[0250] Figure 12 is a block diagram of an embodiment of the simulation system according to the present application, as shown in Figure 12 The simulation system 1 includes:

[0251] The high-frequency error acquisition module 11 is configured to acquire the maximum delay error of a plurality of sub-clocks of the distributed system 2 when the clock source 21 is a high-frequency clock as a first high-frequency maximum delay error;

[0252] The low-frequency clock setting module 12 is configured to set a low-frequency clock based on the first high-frequency maximum delay error collected by the high-frequency error collecting module 11, and the low-frequency period of the low-frequency clock is not less than the first high-frequency maximum delay error multiplied by a set multiple.

[0253] The clock switching module 13 is configured to switch the high-frequency clock of the clock source 21 to the low-frequency clock set by the low-frequency clock setting module 12.

[0254] The clock switching back module 14 is configured to switch the clock source 21 from the low-frequency clock back to the high-frequency clock.

[0255] The introduction error collecting module 15 is configured to collect a delay error introduced by the clock switching back module 14 when switching the clock source 21 from the low-frequency clock back to the high-frequency clock as an introduction delay error.

[0256] The introduction error judging module 16 is configured to judge whether the introduction delay error collected by the introduction error collecting module 15 is less than a set percentage of the first high-frequency maximum delay error collected by the high-frequency error collecting module 11; if the introduction delay error is less than the set percentage of the first high-frequency maximum delay error, jump to the low-frequency clock obtaining module 18; if the introduction delay error is not less than the set percentage of the first high-frequency maximum delay error, jump to the low-frequency increasing module 17.

[0257] The low-frequency increasing module 17 is configured to increase the low-frequency clock set by the low-frequency clock setting module 12 under the constraint of a frequency less than the high-frequency clock.

[0258] The low-frequency clock obtaining module 18 is configured to obtain a calibrated low-frequency clock, and the low-frequency period of the calibrated low-frequency clock is not less than the first high-frequency maximum delay error multiplied by a set multiple and the introduction delay error is less than the set percentage of the first high-frequency maximum delay error.

[0259] In one possible embodiment, the simulation system 1 further comprises:

[0260] The simulation database 19 stores system data of the distributed system 2, simulation data, and a mapping between the system data and the simulation data, the system data includes structure data representing the distributed system 2 and a high-frequency clock, and the simulation data includes the first high-frequency maximum delay error and the calibrated low-frequency clock.

[0261] In this specification, the distributed system 2 and the high-speed clock alignment system 10 are also involved, different distributed systems 2 adopt different configurations of the high-speed clock alignment system 10, which will be described in detail one by one in the following embodiments of the distributed system 2 and the high-speed clock alignment system 10.

[0262] The distributed system 2 of the present application can be Figures 1-4 The distributed system 2 of any of the application scenarios mentioned above is configured to perform clock alignment through the high-frequency clock alignment method of the present application.

[0263] In one possible embodiment, as shown in Figure 13 The distributed system 2 includes a clock source 21 and at least one buffer stage 22, which can include one or more buffers 221. The clock source 21 generates a plurality of sub-clocks through the buffer stage 22.

[0264] The distributed system 2 corresponding to this embodiment, as shown in Figure 14 The high-speed clock alignment system 10 of the present application includes a clock frequency adjustment module 3 and a phase correction module 4:

[0265] The clock frequency adjustment module 3 is configured to switch the clock source 21 of the distributed system 2 to be aligned between a high-frequency clock and a calibrated low-frequency clock of the distributed system to be aligned obtained through the simulation system 1.

[0266] The phase correction module 4 is configured to correct the path delay of all sub-clocks when the clock frequency adjustment module 3 switches the clock source 21 to the calibrated low-frequency clock.

[0267] In another possible embodiment, as shown in Figure 13 The distributed system 2 includes a clock source 21, at least one buffer stage 22, and a phase correction module 4.

[0268] The high-speed clock alignment system 10 of the distributed system 2 corresponding to this embodiment includes a clock frequency adjustment module 3.

[0269] In the above two embodiments, the clock frequency adjustment module 3 can be implemented by software or / and hardware; the phase correction module 4 can be implemented by hardware or a combination of hardware and software; and the simulation system 1 can be implemented by software or a combination of software and hardware.

[0270] In one possible embodiment, the clock source 21 of the distributed system 2 is a programmable clock source, and the clock frequency adjustment module 3 is a computer program that, when executed by the programmable clock source, realizes the switching of the clock source 21 between the high-frequency clock and the calibrated low-frequency clock.

[0271] In the above embodiments, the phase correction module 4 includes a delay module 41, a delay adjustment module 42, and a phase detector 44:

[0272] The delay module 41 is arranged on the path of the sub-clock, and the delay module 41 is electrically connected to the delay adjustment module 42.

[0273] The delay adjustment module 42 is configured to adjust the delay of the delay module 41;

[0274] The phase detector 44 is electrically connected with the delay adjustment module 42, configured to detect the phase of any two sub-clocks, output the delay error of the two sub-clocks, and feed back the delay error to the delay adjustment module 42, and the delay adjustment module 42 adjusts the path delay of one or two sub-clocks based on the delay error to the trend of reducing the delay error;

[0275] The delay module 41, the delay adjustment module 42 and the phase detection module form a feedback loop, so that the delay error of all sub-clocks is less than the delay threshold.

[0276] In the above embodiments, the phase correction module 4 can include multiple phase detectors 44, and each two sub-clocks correspond to one phase detector 44, but in order to save resources, reduce costs and facilitate miniaturization, the phase correction module 4 can include a switch matrix 43 and one phase detector 44, the switch matrix 43 is used to control the conduction and shutdown of the delay adjustment module 42 and the phase detector 44.

[0277] In a preferred embodiment, the phase detection module is a phase detector, and the delay threshold is the accuracy of the phase detector, which can be close to 0, and the theoretical value in the ideal state is 0.

[0278] In the above embodiments, the high-speed clock alignment system 10 can further include an emulation system 1.

[0279] In one application scenario, the emulation system 1 is implemented by software, which can be installed in the client (computer, mobile phone, etc.) in the form of APP; the distributed system 2 is a chip, and the distributed system 2 is composed of a clock source 21 and a buffer stage; the high-speed clock alignment system 10 is a circuit board, and the circuit board is provided with a clock frequency adjustment module 3 and a phase correction module 4.

[0280] In another application scenario, the distributed system 2 is a chip, and the distributed system 2 is composed of a programmable clock source, a buffer stage and a phase correction module 4; the emulation system 1 is implemented by software, and the high-speed clock system is composed of a clock frequency adjustment module 3, the clock frequency adjustment module 3 is implemented by software, and the software corresponding to the emulation system 1 and the software corresponding to the high-speed clock system can be installed in the client in the form of an APP.

[0281] The above-described embodiments of the application have several aspects, no single one of which is solely responsible for the application's desirable attributes. Without limiting the scope of the application as expressed by the claims that follow, some further embodiments make these aspects even more useful. Other embodiments can result in less desirable attributes.

[0282] It is noted that, for the foregoing methods embodiments, the steps have been presented in a particular order. However, alternative embodiments can perform the steps in a different order, or employ all the steps at the same time. Moreover, it is also possible that certain steps can be omitted, or other steps can be added, without departing from the scope of the embodiments described herein. Further, the steps need not all be performed, or need not be performed in the order described, for proper practice of the embodiments.

[0283] In the foregoing embodiments, the description of each embodiment has been presented for purposes of clarity and explanation, and is not necessarily intended to limit the embodiments to the description in the foregoing embodiments. Descriptions of the embodiments in this specification should not be construed as preferred embodiments, and the acts and modules involved are not necessarily essential to the embodiments.

[0284] The preferred embodiments of the present application disclosed above only serve to help explain the principles of the present application. Alternative embodiments are not described in detail because they are understood to be the same as the embodiments described above. Obviously, many modifications and changes can be made to the embodiments of the present application on the basis of the contents of the present application. The present application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of the present application, so that those skilled in the art can well understand and use the present application.

Claims

1. A method of simulating a distributed system, said distributed system comprising a clock source and at least one level of buffering, characterized in that, The method comprises: a high-frequency simulation step of collecting a maximum delay error of a plurality of sub-clocks of a distributed system when a clock source is a high-frequency clock as a first high-frequency maximum delay error; a clock frequency setting step of setting a low-frequency clock, a low-frequency period of the low-frequency clock being not less than a set multiple of the first high-frequency maximum delay error, the set multiple being not less than 2; a clock switching step of switching the high-frequency clock of the clock source to the low-frequency clock; a clock switching-back step of switching the clock source from the low-frequency clock back to the high-frequency clock; a clock switching-back simulation step of collecting a delay error introduced by switching the clock source from the low-frequency clock back to the high-frequency clock as an introduced delay error; an introduced error judging step of judging whether the introduced delay error is less than a set percentage of the first high-frequency maximum delay error; if the introduced delay error is less than the set percentage of the first high-frequency maximum delay error, ending the simulation to obtain a calibrated low-frequency clock, a low-frequency period of the calibrated low-frequency clock being not less than a set multiple of the first high-frequency maximum delay error and the introduced delay error being less than the set percentage of the first high-frequency maximum delay error, the set percentage being not more than 50%; if the introduced delay error is not less than the set percentage of the first high-frequency maximum delay error, increasing the frequency of the low-frequency clock under a constraint of being less than the frequency of the high-frequency clock, returning to the clock frequency setting step, and repeating the cycle until the introduced delay error is less than the set percentage of the first high-frequency maximum delay error to obtain the calibrated low-frequency clock.

2. The simulation method of a distributed system according to claim 1, characterized in that, The method comprises: constructing a simulation database, the simulation database storing system data of a distributed system, simulation data, and a mapping between the system data and the simulation data, the system data comprising structure data representing the distributed system and a high-frequency clock, and the simulation data comprising a first high-frequency maximum delay error and a calibrated low-frequency clock.

3. A high speed clock alignment method, characterized by, The method comprises: simulating a to-be-aligned distributed system by the simulation method of claim 1 to obtain a calibrated low-frequency clock of the to-be-aligned distributed system; a low-frequency clock switching step of switching a high-frequency clock of a clock source of the to-be-aligned distributed system to the calibrated low-frequency clock; a low-frequency clock alignment step of correcting path delays of all sub-clocks under a condition that the clock source is the calibrated low-frequency clock so that all the sub-clocks are aligned; a high-frequency clock switching-back step of switching the clock source from the calibrated low-frequency clock back to the high-frequency clock.

4. A high speed clock alignment method, characterized by, The method comprises: obtaining a distributed system with the highest similarity to a to-be-aligned distributed system from a simulation database constructed by the simulation method of claim 2, and setting a low-frequency period of a calibrated low-frequency clock of the to-be-aligned distributed system to be not less than a low-frequency period of a calibrated low-frequency clock of the distributed system with the highest similarity; a low-frequency clock switching step of switching a high-frequency clock of a clock source of the to-be-aligned distributed system to the calibrated low-frequency clock; a low-frequency clock alignment step of correcting path delays of all sub-clocks under a condition that the clock source is the calibrated low-frequency clock so that all the sub-clocks are aligned; a high-frequency clock switching-back step of switching the clock source from the calibrated low-frequency clock back to the high-frequency clock.

5. A high speed clock alignment method, characterized by, The method comprises: obtaining a distributed system with the highest similarity to the distributed system to be aligned from a simulation database constructed from the simulation method of claim 2, and setting a low-frequency period of a calibrated low-frequency clock of the distributed system to be aligned to be no less than a low-frequency period of a calibrated low-frequency clock of the distributed system with the highest similarity; a low-frequency clock switching step of switching a high-frequency clock of a clock source of the distributed system to be aligned to the calibrated low-frequency clock; a low-frequency clock alignment step of correcting path delays of all sub-clocks in a state where the clock source is the calibrated low-frequency clock, so that all the sub-clocks are aligned; a medium-frequency clock switching step of switching the clock source from the calibrated low-frequency clock to a medium-frequency clock, the medium-frequency clock having a frequency higher than that of the low-frequency clock and lower than that of the high-frequency clock; a medium-frequency clock alignment step of correcting path delays of all sub-clocks in a state where the clock source is the medium-frequency clock, so that all the sub-clocks are aligned; a high-frequency clock switching back step of switching the clock source from the medium-frequency clock back to the high-frequency clock.

6. The high speed clock alignment method of any of claims 3-5, wherein, The high-frequency clock switching back step further comprises: a high-frequency error collecting step of collecting maximum delay errors of a plurality of sub-clocks of the distributed system to be aligned after the clock source switches back to the high-frequency clock as a second high-frequency maximum delay error; a high-frequency error judging step of judging whether the second high-frequency maximum delay error is no more than a first delay error threshold value; if the second high-frequency maximum delay error is no more than the first delay error threshold value, the alignment is completed; if the second high-frequency maximum delay error is more than the first delay error threshold value, a high-frequency clock alignment step is performed; the high-frequency clock alignment step of correcting path delays of all sub-clocks in a state where the clock source is the high-frequency clock, so that all the sub-clocks are aligned.

7. The high speed clock alignment method of any of claims 3-5, wherein, The high-frequency clock switching back step further comprises: a high-frequency error collecting step of collecting maximum delay errors of a plurality of sub-clocks of the distributed system to be aligned after the clock source switches back to the high-frequency clock as a second high-frequency maximum delay error; a first high-frequency error judging step of judging whether the second high-frequency maximum delay error is no more than a first delay error threshold value; if the second high-frequency maximum delay error is no more than the first delay error threshold value, the alignment is completed; if the second high-frequency maximum delay error is more than the first delay error threshold value, a second high-frequency error judging step is performed; the second high-frequency error judging step of judging whether the second high-frequency maximum delay error is less than a second delay error threshold value, the second delay error threshold value being greater than the first delay error threshold value and no more than 0.5 times the first high-frequency maximum delay error; if the second high-frequency maximum delay error is less than the second delay error threshold value, a high-frequency clock alignment step is performed; the high-frequency clock alignment step of correcting path delays of all sub-clocks in a state where the clock source is the high-frequency clock, so that all the sub-clocks are aligned; if the second high-frequency maximum delay error is no less than the second delay error threshold value, a medium-frequency clock switching step is performed; the medium-frequency clock switching step of switching the clock source from the high-frequency clock to a medium-frequency clock, the medium-frequency clock having a medium-frequency period smaller than a low-frequency period of the calibrated low-frequency clock and greater than a high-frequency period of the high-frequency clock; The intermediate frequency clock alignment step corrects the path delay of all sub-clocks in the intermediate frequency clock state so that all sub-clocks are aligned, and then performs the high frequency clock switching back step.

8. The high speed clock alignment method of claim 7, wherein, The intermediate frequency clock alignment step further comprises: The intermediate frequency maximum delay error collection step collects the intermediate frequency maximum delay error of the plurality of sub-clocks when the clock source is the intermediate frequency clock. The intermediate frequency period judgment step judges whether the intermediate frequency period corresponding to the intermediate frequency clock is not less than the set multiple of the intermediate frequency maximum delay error. If the intermediate frequency period is not less than the set multiple of the intermediate frequency maximum delay error, the intermediate frequency clock alignment step is performed. If the intermediate frequency period is less than the set multiple of the intermediate frequency maximum delay error, the clock frequency reduction step is performed. The clock frequency reduction step reduces the frequency of the intermediate frequency clock to the corresponding intermediate frequency period not less than the set multiple of the intermediate frequency maximum delay error, and then performs the intermediate frequency clock alignment step.

9. The high speed clock alignment method of any of claims 3-5, wherein, The step of correcting the path delay of all sub-clocks comprises: The phase detection step detects the phase error of the two sub-clocks. The phase error judgment step judges whether the phase error is less than the phase threshold. If the phase error is less than the phase threshold, the path delay of the two sub-clocks is not adjusted. If the phase error is not less than the phase threshold, the path delay of one or two sub-clocks is adjusted towards the trend of reducing the phase error, and the phase detection step is returned.

10. The high speed clock alignment method of claim 5, wherein, The intermediate frequency clock switching step is performed multiple times before the high frequency clock switching back step, and the intermediate frequency period corresponding to the intermediate frequency clock of the performed intermediate frequency clock switching step is less than the intermediate frequency period corresponding to the intermediate frequency clock of the last intermediate frequency clock switching step.

11. A simulation system of a distributed system, characterized by It comprises: The high frequency error collection module is configured to collect the maximum delay error of the plurality of sub-clocks of the distributed system when the clock source is the high frequency clock as the first high frequency maximum delay error. The low frequency clock setting module is configured to set the low frequency clock based on the first high frequency maximum delay error collected by the high frequency error collection module, and the low frequency period of the low frequency clock is not less than the set multiple of the first high frequency maximum delay error, and the set multiple is not less than 2. The clock switching module is configured to switch the high frequency clock of the clock source to the low frequency clock set by the low frequency clock setting module. The clock switching back module is configured to switch the clock source from the low frequency clock to the high frequency clock. The introduction error collection module is configured to collect the delay error introduced by the clock switching back module when the clock source is switched from the low frequency clock to the high frequency clock as the introduction delay error. The introduction error judgment module is configured to judge whether the introduction delay error collected by the introduction error collection module is less than the set percentage of the first high frequency maximum delay error collected by the high frequency error collection module; if the introduction delay error is less than the set percentage of the first high frequency maximum delay error, jump to the low frequency clock obtaining module; if the introduction delay error is not less than the set percentage of the first high frequency maximum delay error, jump to the low frequency improvement module; the set percentage is not more than 50%. a low-frequency improving module configured to improve the low-frequency clock set by the low-frequency clock setting module under a constraint of a frequency less than that of the high-frequency clock; a low-frequency clock obtaining module configured to obtain a calibrated low-frequency clock, a low-frequency period of the calibrated low-frequency clock being not less than a set multiple of the first high-frequency maximum latency error and a latency error introduced being less than a set percentage of the first high-frequency maximum latency error.

12. The simulation system of a distributed system according to claim 11, characterized in that, Further comprising: a simulation database storing system data of the distributed system, simulation data, and a mapping between the system data and the simulation data, the system data including structure data representing a constitution of the distributed system and a high-frequency clock, and the simulation data including the first high-frequency maximum latency error and the calibrated low-frequency clock.

13. A high speed clock alignment system, characterized by, Comprising: a clock frequency adjusting module configured to switch the clock source of the distributed system to be aligned back and forth between the high-frequency clock and the calibrated low-frequency clock of the simulation system of claim 11 or 12.

14. The high speed clock alignment system of claim 13, wherein, Further comprising: a phase correction module configured to correct path latencies of all sub-clocks when the clock frequency adjusting module switches the clock source to the calibrated low-frequency clock.

15. The high speed clock alignment system of claim 14, wherein, The phase correction module is further configured to correct path latencies of all sub-clocks when the clock source is the high-frequency clock after the clock frequency adjusting module switches the clock source from the calibrated low-frequency clock back to the high-frequency clock.

16. The high speed clock alignment system of claim 14, wherein, The phase correction module comprises a latency module, a latency adjusting module, and a phase detector: The latency module is disposed on a sub-clock path of the distributed system, and the latency module is electrically connected with the latency adjusting module; The latency adjusting module is configured to adjust a latency of the latency module; The phase detector is electrically connected with the latency adjusting module and is configured to detect a phase of any two sub-clocks, output a latency error of the two sub-clocks, and feed back the latency error to the latency adjusting module, and the latency adjusting module adjusts a path latency of one or both of the sub-clocks based on the latency error in a direction of reducing the latency error; The latency module, the latency adjusting module, and the phase detector form a feedback loop, so that latency errors of all sub-clocks are less than a latency threshold.

17. The high speed clock alignment system of claim 16, wherein, The phase detector is a phase discriminator.

18. The high speed clock alignment system of claim 13, wherein, Further comprising: the simulation system of claim 11 or 12.

19. A distributed system, characterized by Comprising a clock source and at least one buffer stage, the clock source generating a plurality of sub-clocks through the buffer stage, and the plurality of sub-clocks being configured to be clock-aligned through the high-speed clock alignment method of any one of claims 3-10.

20. The distributed system of claim 19, wherein, The clock source is a programmable clock source.

21. The distributed system of claim 19, wherein, The distributed system further comprises a phase correction module configured to correct path latencies of all sub-clocks.

22. The distributed system of claim 21, wherein, The phase correction module comprises a latency module, a latency adjusting module, and a phase detector: The latency module is disposed on a sub-clock path, and the latency module is electrically connected with the latency adjusting module; The latency adjusting module is configured to adjust a latency of the latency module; The latency module, the latency adjusting module, and the phase detector form a feedback loop, so that latency errors of all sub-clocks are less than a latency threshold. The phase detector is electrically connected with the delay adjustment module, configured to detect phase outputs of any two sub-clocks, output delay errors of the two sub-clocks, and feed back the delay errors to the delay adjustment module, and the delay adjustment module adjusts path delays of one or two sub-clocks based on the delay errors in a trend of decreasing delay errors. The delay module, the delay adjustment module and the phase detection module form a feedback loop, so that delay errors of all sub-clocks are less than a delay threshold.

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