Display device

Abstract

The invention relates to a display device. The display device includes: first-first pixel circuits, first-second pixel circuits, first-third pixel circuits, and a first sensor circuit in a first row; a second-first pixel circuit, a second-second pixel circuit, a second-third pixel circuit, and a second sensor circuit in a second row; a third-first pixel circuit, a third-second pixel circuit, a third-third pixel circuit, and a third sensor circuit in a third row; a first-first pixel electrode in a first pixel row corresponding to the first row and connected to the first-first pixel circuit; a first sensor electrode in the first pixel row and connected to the first sensor circuit; a second sensor electrode in the first pixel row and connected to the second sensor circuit; a second-first pixel electrode in a second pixel row corresponding to the second row and connected to the second-first pixel circuit; and a third sensor electrode in a third pixel row corresponding to the third row and connected to the third sensor circuit.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the development of an information-oriented society, there is an increasing demand for display devices that display images in various ways. For example, display devices are used in a variety of electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart televisions. In display devices, because each pixel of a display panel includes a light-emitting element that can emit its own light, images can be displayed without the need for a backlight unit to provide light to the display panel.

[0003] A display device may include a display panel that displays an image, an optical sensor that detects light, a fingerprint sensor that detects a person's fingerprint, and an illumination sensor that detects ambient brightness. As electronic devices employing display devices diversify, it is appropriate to provide display devices in various designs. For example, a display device may expand a display area for displaying an image by removing a sensor device (such as a light sensor, a fingerprint sensor, or an illumination sensor) that is separately arranged in a non-display area. Summary of the Invention

[0004] Aspects of the present disclosure provide a display device capable of improving the resolution of pixels without increasing a mask process while maintaining the sensitivity of a fingerprint sensor, and capable of improving fingerprint sensitivity by reducing or minimizing a sensing error according to a contact angle of a finger.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0006] According to one or more embodiments, a display device includes: a first-first pixel circuit, a first-second pixel circuit, a first-third pixel circuit and a first sensor circuit, which are arranged sequentially in a first circuit row; a second-first pixel circuit, a second-second pixel circuit, a second-third pixel circuit and a second sensor circuit, which are arranged sequentially in a second circuit row after the first circuit row; a third-first pixel circuit, a third-second pixel circuit, a third-third pixel circuit and a third sensor circuit, which are arranged sequentially in a third circuit row after the second circuit row; a first-first pixel electrode, in a first pixel row corresponding to the first circuit row, and electrically connected to the first-first pixel circuit; a first sensor electrode, in the first pixel row, and electrically connected to the first sensor circuit; a second sensor electrode, in the first pixel row, and electrically connected to the second sensor circuit; a second-first pixel electrode, in a second pixel row corresponding to the second circuit row, and electrically connected to the second-first pixel circuit; and a third sensor electrode, in a third pixel row corresponding to the third circuit row, and electrically connected to the third sensor circuit.

[0007] The second sensor electrode may be spaced apart from the first sensor electrode in a first direction, wherein the third sensor electrode is spaced apart from the first sensor electrode in a second direction intersecting the first direction.

[0008] A gap between the first sensor electrode and the second sensor electrode may be substantially equal to a gap between the first sensor electrode and the third sensor electrode.

[0009] The display device may further include: a fourth-first pixel circuit, a fourth-second pixel circuit, a fourth-third pixel circuit and a fourth sensor circuit, arranged in a fourth circuit row after the third circuit row; and a fourth sensor electrode, in the third pixel row, and electrically connected to the fourth sensor circuit.

[0010] The fourth sensor electrode may be spaced apart from the third sensor electrode in the first direction and spaced apart from the second sensor electrode in the second direction.

[0011] A gap between the third sensor electrode and the fourth sensor electrode may be substantially equal to a gap between the second sensor electrode and the fourth sensor electrode.

[0012] The display device may further include a sensor connection electrode electrically connecting the first sensor circuit to the first sensor electrode.

[0013] The first-third pixel circuits may be between the first-first pixel electrodes and the first sensor circuit, wherein the sensor connection electrode overlaps the first-third pixel circuits.

[0014] The sensor connection electrode may be integrated in the same layer as the first sensor electrode.

[0015] The sensor connection electrode may be in a layer between the first sensor circuit and the first sensor electrode.

[0016] A width of each of the first-first pixel circuit, the first-second pixel circuit, and the first-third pixel circuit in the first direction may be greater than a width of the first sensor circuit in the first direction.

[0017] The first-first pixel circuit may include: a first transistor for controlling a driving current provided to the first-first pixel electrode; a second transistor for providing a data voltage to the first electrode of the first transistor; a third transistor for electrically connecting the second electrode of the first transistor to the gate electrode of the first transistor; and a fourth transistor for providing an initialization voltage to the gate electrode of the first transistor, wherein the first transistor and the second transistor include a silicon-based semiconductor region, and wherein the third transistor and the fourth transistor include an oxide-based semiconductor region.

[0018] The first sensor circuit may include: a first sensor transistor including a gate electrode electrically connected to the first sensor electrode; a second sensor transistor providing an initialization voltage to the gate electrode of the first sensor transistor; and a third sensor transistor electrically connecting the first sensor transistor to a readout line, wherein the first sensor transistor and the third sensor transistor include silicon-based semiconductor regions, and wherein the second sensor transistor includes an oxide-based semiconductor region.

[0019] According to one or more embodiments, a display device includes: a first-first pixel circuit, a first-second pixel circuit, a first-third pixel circuit, a first-fourth pixel circuit and a first sensor circuit, which are arranged sequentially in a first circuit row; a second-first pixel circuit, a second-second pixel circuit, a second-third pixel circuit, a second-fourth pixel circuit and a second sensor circuit, which are arranged sequentially in a second circuit row after the first circuit row; a first-first pixel electrode, in a first pixel row corresponding to the first circuit row, and electrically connected to the first-first pixel circuit; a first-second pixel electrode, in the first pixel row, and electrically connected to the first-second pixel circuit; a first-third pixel electrode, in the first pixel row, and electrically connected to the first-third pixel circuit; a first sensor electrode, in the first pixel row, and electrically connected to the first sensor circuit; and a second sensor electrode, in the first pixel row, and electrically connected to the second sensor circuit.

[0020] The first sensor electrode may be at least partially surrounded by the first-first pixel electrode, the first-second pixel electrode, and the first-third pixel electrode.

[0021] The display device may also include: a second-first pixel electrode, in a second pixel row corresponding to the second circuit row, and electrically connected to the second-first pixel circuit; a second-second pixel electrode, in the second pixel row, and electrically connected to the second-second pixel circuit; and a second-third pixel electrode, in the second pixel row, and electrically connected to the second-third pixel circuit.

[0022] The first sensor electrode and the second sensor electrode may overlap the first circuit row and not overlap the second circuit row.

[0023] The display device may also include: a third-first pixel circuit, a third-second pixel circuit, a third-third pixel circuit, a third-fourth pixel circuit and a third sensor circuit, which are arranged sequentially in a third circuit row after the second circuit row; a fourth-first pixel circuit, a fourth-second pixel circuit, a fourth-third pixel circuit, a fourth-fourth pixel circuit and a fourth sensor circuit, which are arranged sequentially in a fourth circuit row after the third circuit row; a third sensor electrode, in a third pixel row corresponding to the third circuit row, and electrically connected to the third sensor circuit; and a fourth sensor electrode, in the third pixel row, and electrically connected to the fourth sensor circuit.

[0024] The third sensor electrode and the fourth sensor electrode may overlap with the third circuit row and not overlap with the fourth circuit row.

[0025] A gap between the first sensor electrode and the second sensor electrode may be substantially equal to a gap between the first sensor electrode and the third sensor electrode.

[0026] According to a display device according to an embodiment, including a sensor circuit in which the gap in the first direction and the gap in the second direction are different and a sensor area in which the gap in the first direction and the gap in the second direction are substantially the same, it is possible to improve the resolution of pixels while maintaining the sensitivity of the fingerprint sensor without increasing the mask process, and it is also possible to improve the fingerprint sensitivity by reducing or minimizing the sensing error according to the contact angle of the finger.

[0027] However, aspects according to embodiments of the present disclosure are not limited to those described above, and various other aspects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0029] Figure 1 is a perspective view showing a display device according to one or more embodiments;

[0030] Figure 2 is a cross-sectional view illustrating a display device according to one or more embodiments;

[0031] Figure 3 is a plan view showing a display of a display device according to one or more embodiments;

[0032] Figure 4 is a block diagram illustrating a display panel and a display driver according to one or more embodiments;

[0033] Figure 5 is a plan view showing a pixel circuit and a sensor circuit of a display device according to one or more embodiments;

[0034] Figure 6 is a plan view of a pixel circuit and a sensor circuit located in a unit area in a display device according to one or more embodiments;

[0035] Figure 7 is a plan view illustrating an emission area and a sensor area in a display device according to one or more embodiments;

[0036] Figure 8 is a plan view showing a pixel circuit, a sensor circuit, a pixel electrode, an anode connecting electrode, a sensor electrode, and a sensor connecting electrode of a display device according to one or more embodiments;

[0037] Figure 9 is a circuit diagram illustrating a pixel of a display device according to one or more embodiments;

[0038] Figure 10 is a circuit diagram of a fingerprint sensor of a display device according to one or more embodiments;

[0039] Figure 11 is a layout diagram showing some layers of a pixel circuit and a sensor circuit of a display device according to one or more embodiments;

[0040] Figure 12 It shows Figure 11 Layout diagrams of some layers;

[0041] Figure 13 It shows Figure 11 Layout diagrams of some other layers;

[0042] Figure 14 is a layout diagram showing some other layers of a pixel circuit and a sensor circuit of a display device according to one or more embodiments;

[0043] Figure 15is a layout diagram showing some layers of a pixel circuit of a display device according to one or more embodiments;

[0044] Figure 16 It shows Figure 15 Layout diagrams of some layers;

[0045] Figure 17 It shows Figure 15 Layout diagrams of some other layers;

[0046] Figure 18 is a layout diagram showing some other layers of a pixel circuit of a display device according to one or more embodiments;

[0047] Figure 19 It is along Figures 15 to 18 A sectional view taken along line II';

[0048] Figure 20 is a layout diagram showing some layers of a sensor circuit of a display device according to one or more embodiments;

[0049] Figure 21 It shows Figure 20 Layout diagrams of some layers;

[0050] Figure 22 It shows Figure 20 Layout diagrams of some other layers;

[0051] Figure 23 is a layout diagram showing some other layers of a sensor circuit of a display device according to one or more embodiments;

[0052] Figure 24 It is along Figures 20 to 23 A sectional view taken along line II-II';

[0053] Figure 25 is a plan view showing a pixel circuit, a sensor circuit, a pixel electrode, an anode connecting electrode, a sensor electrode, and a sensor connecting electrode of a display device according to one or more other embodiments; and

[0054] Figure 26 It shows Figure 25 Cross-sectional view of the sensor electrode and sensor connection electrode. DETAILED DESCRIPTION

[0055] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of one or more devices or methods using the disclosure disclosed herein. However, it is apparent that various embodiments can be put into practice without these specific details or with one or more equivalent arrangements. In other cases, structures and devices are shown in block diagram form to avoid unnecessarily blurring the various embodiments. In addition, various embodiments can be different, but do not have to be exclusive or limit the present disclosure. For example, without departing from the present disclosure, the specific shape, configuration and characteristics of one or more embodiments can be used or implemented in other embodiments.

[0056] Unless otherwise indicated, the illustrated embodiments should be understood as providing features of varying details that may implement some of the ways in which the present disclosure may be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0057] The use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other characteristic, attribute, property, etc. of an element.

[0058] In addition, in the accompanying drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. When one or more embodiments can be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0059] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. For this purpose, the term “connected” may refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements.

[0060] In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of the rectangular coordinate system, and therefore, the X-axis, Y-axis, and Z-axis can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0061] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, ZZ, etc. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0062] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0063] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "down," "above," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein and thereby describe the relationship of one element to another element(s) as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the term "below" may encompass both above and below orientations. Additionally, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0064] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of the features, wholes, steps, operations, elements, components, and / or groups thereof set forth, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as terms of degree, and are therefore used to allow for inherent deviations in measurements, calculations, and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0065] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments disclosed herein should not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but should include deviations in shapes due to, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are not necessarily intended to be limiting.

[0066] As is customary in the art, some embodiments are described and shown in the accompanying drawings for functional blocks, units, parts and / or modules. It will be understood by those skilled in the art that these blocks, units, parts and / or modules are physically implemented by electrical circuits (or optical circuits) such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, parts and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit, part and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware for performing some functions and a processor for performing other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, without departing from the scope of this disclosure, each block, unit, part and / or module in some embodiments can be physically separated into two or more interactive and discrete blocks, units, parts and / or modules. Furthermore, the blocks, units, parts and / or modules of some embodiments may be physically combined into more complex blocks, units, parts and / or modules without departing from the scope of the present disclosure.

[0067] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0068] Hereinafter, detailed embodiments of the present disclosure are described with reference to the accompanying drawings.

[0069] Figure 1 is a perspective view illustrating a display device according to one or more embodiments.

[0070] refer to Figure 1The display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile personal computers (UMPCs), etc. For example, the display device 10 can be applied as a display for a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD).

[0071] The display device 10 may have a planar shape similar to a quadrilateral shape. For example, in a plan view, the display device 10 may have a shape similar to a quadrilateral shape having a short side in the X-axis direction and a long side in the Y-axis direction. The corner where the short side in the X-axis direction and the long side in the Y-axis direction intersect may be rounded to have a curvature (e.g., a predetermined curvature), or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to another polygonal shape, a circular shape, or an elliptical shape.

[0072] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power source (eg, a power supply unit) 500 .

[0073] The display panel 100 may include a main area MA and a sub-area SBA.

[0074] The main area MA may include a display area DA and a non-display area NDA located around the display area DA. The display area DA includes pixels for displaying an image. The display area DA may emit light from multiple emission areas or multiple opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining the emission area or the opening area, and a self-luminous element.

[0075] For example, the self-luminous element may include one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0076] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. In one or more embodiments, the non-display area NDA may include a gate driver that provides gate signals to gate lines and a fan-out line that connects the display driver 200 to the display area DA.

[0077] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include the display driver 200 and a pad portion connected to the circuit board 300. Alternatively, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0078] The display driver 200 may output signals and voltages for driving the display panel 100. The display driver 200 may provide data voltages to the data lines. The display driver 200 may provide power voltages to the power lines and may provide gate control signals to the gate driver. The display driver 200 may receive sensing signals through readout lines. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 through a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be located in the sub-area SBA and may overlap with the main area MA in the thickness direction (Z-axis direction) by bending the sub-area SBA. For another example, the display driver 200 may be mounted on the circuit board 300.

[0079] The circuit board 300 may be attached to the pad portion of the display panel 100 using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0080] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensor (e.g., a touch sensing unit) of the display panel 100. The touch driver 400 may provide a touch drive signal to the plurality of touch electrodes of the touch sensor and may sense the change in capacitance between the plurality of touch electrodes. For example, the touch drive signal may be a pulse signal having a frequency (e.g., a predetermined frequency). The touch driver 400 may calculate whether an input is present and may calculate input coordinates based on the change in capacitance between the plurality of touch electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0081] The power supply 500 may be located on the circuit board 300 to provide power voltage to the display driver 200 and the display panel 100. The power supply 500 may generate a driving voltage to provide it to a driving voltage line, and may generate a common voltage to provide it to a common electrode common to the light-emitting elements of multiple pixels. For example, the driving voltage may be a high potential voltage for driving the light-emitting element, and the common voltage may be a low potential voltage for driving the light-emitting element. The power supply 500 may generate an initialization voltage to provide it to an initialization voltage line, may generate a reference voltage to provide it to a reference voltage line, may generate a bias voltage to provide it to a bias voltage line, and may generate a reset voltage to provide it to a reset voltage line.

[0082] Figure 2 is a cross-sectional view illustrating a display device according to one or more embodiments.

[0083] refer to Figure 2 The display panel 100 may include a display unit (eg, a display unit) DU, a touch sensor TSU, and a color filter layer CFL. The display DU may include a substrate SUB, a transistor layer TFTL, a light emitting element layer EDL, and an encapsulation layer TFEL.

[0084] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0085] The transistor layer TFTL may be located on the substrate SUB. The transistor layer TFTL may include a plurality of transistors that constitute the pixels and the fingerprint sensor. The transistor layer TFTL may also include gate lines, data lines, power lines, readout lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines, and leads connecting the display driver 200 to the pad portion. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0086] The transistor layer TFTL may be located in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines, power lines, and readout lines of the transistor layer TFTL may be located in the display area DA. The gate control lines and fan-out lines of the transistor layer TFTL may be located in the non-display area NDA. Lead lines of the transistor layer TFTL may be located in the sub-area SBA.

[0087] The light-emitting element layer (EDL) may be located on the transistor layer (TFTL). The light-emitting element layer (EDL) may include light-emitting elements for the pixels, light-receiving elements for the fingerprint sensor, and a pixel-defining layer that defines the pixels and the fingerprint sensor. The light-emitting elements may emit light by being formed by sequentially stacking pixel electrodes, light-emitting layers, and common electrodes, and the light-receiving elements may receive light by being formed by sequentially stacking sensor electrodes, light-receiving layers, and common electrodes. The light-emitting elements and light-receiving elements of the light-emitting element layer (EDL) may be located in the display area (DA).

[0088] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a voltage (e.g., a predetermined voltage) through the transistor of the transistor layer TFTL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer, electrons may move to the organic light-emitting layer through the electron transport layer, and the holes and electrons may recombine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0089] For another example, the plurality of light emitting elements may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0090] The light receiving element can receive light and can convert light energy into an electrical signal. When the user's finger touches the display panel 100, the light emitted from the light emitting element can be reflected by the finger, and the light receiving element can receive the reflected light. The sensing signal of the fingerprint sensor that receives the light reflected by the ridge of the finger can be different from the sensing signal of the fingerprint sensor that receives the light reflected by the valley of the finger. The main processor can distinguish the difference between these sensing signals to generate sensing data, and based on the sensing data, the main processor can determine whether the ridge of the finger touches or whether the valley of the finger touches. Therefore, the display device 10 can recognize the pattern of the user's fingerprint based on the sensing data. For example, the light receiving element can be an organic photodiode, but is not limited to this.

[0091] The encapsulation layer TFEL may cover the top and side surfaces of the light emitting element layer EDL and may protect the light emitting element layer EDL. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EDL.

[0092] The touch sensor TSU may be located on the encapsulation layer TFEL. The touch sensor TSU may include a plurality of touch electrodes for capacitively sensing a user's touch, and touch lines connecting the plurality of touch electrodes to the touch driver 400. The plurality of touch electrodes of the touch sensor TSU may be located in a touch sensor area overlapping the display area DA. The touch lines of the touch sensor TSU may be located in a touch peripheral area overlapping the non-display area NDA. For example, the touch sensor TSU may sense a user's touch using a mutual capacitance method or a self-capacitance method.

[0093] For another example, the touch sensor TSU may be located on a separate substrate positioned on the display DU. In this case, the substrate supporting the touch sensor TSU may be a base member that packages the display DU.

[0094] A color filter layer (CFL) may be located on the touch sensor TSU. The color filter layer (CFL) may include multiple color filters corresponding to the multiple emission regions. Each color filter selectively transmits light of a corresponding wavelength and blocks or absorbs light of a different wavelength. The color filter layer (CFL) may absorb a portion of light from outside the display device 10 to reduce reflected light caused by the external light. Therefore, the color filter layer (CFL) may reduce or prevent color distortion caused by reflection of external light.

[0095] Since the color filter layer CFL is directly located on the touch sensor TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be relatively reduced.

[0096] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include the display driver 200 and a pad portion electrically connected to the circuit board 300.

[0097] Figure 3 is a plan view illustrating a display of a display device according to one or more embodiments. Figure 4 is a block diagram illustrating a display panel and a display driver according to one or more embodiments.

[0098] refer to Figure 3 and Figure 4 The display panel 100 may include a display area DA, a non-display area NDA, and a sub-area SBA. The display area DA may include pixels SP, a fingerprint sensor OPD, power lines VL, data lines DL, readout lines ROL, gate lines GL, and emission control lines EML.

[0099] Each of the plurality of pixels SP may be connected to a gate line GL, an emission control line EML, a data line DL, and a power line VL. Each of the pixels SP may include at least one transistor, a light emitting element, and a capacitor.

[0100] Each of the plurality of fingerprint sensors OPD may be connected to a gate line GL, a power line VL, and a readout line ROL. Each of the plurality of fingerprint sensors OPD may include at least one transistor and a light receiving element.

[0101] The gate lines GL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction. The gate lines GL may sequentially provide gate signals to the pixels SP and the fingerprint sensor OPD.

[0102] The emission control lines EML may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction. The emission control lines EML may sequentially provide emission signals to the pixels SP.

[0103] The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The data lines DL may provide a data voltage to the pixels SP. The data voltage may determine the brightness of each of the pixels SP.

[0104] The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The power lines VL may provide a power voltage to the pixel SP and the fingerprint sensor OPD. Here, the power voltage may be a driving voltage, a common voltage, an initialization voltage, a reference voltage, a bias voltage, or a reset voltage. The driving voltage may be a high potential voltage for driving the light-emitting element, and the common voltage may be a low potential voltage for driving the light-emitting element and the light-receiving element.

[0105] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, an emission control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0106] The fan-out line FL may extend from the display driver 200 to the display area DA. The fan-out line FL may provide a data voltage received from the display driver 200 to the data line DL, may provide a power voltage received from the display driver 200 to the power line VL, and may provide a sensing signal received from the readout line ROL to the display driver 200. Thus, the display driver 200 may drive the pixel SP and the fingerprint sensor OPD.

[0107] The first gate control line GSL1 may extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 may provide the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0108] The second gate control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 may provide the emission control signal ECS received from the display driver 200 to the emission control driver 620.

[0109] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad portion DP. The pad portion DP may be closer to one edge of the sub-area SBA than the display driver 200. The pad portion DP may be electrically connected to the circuit board 300 via an anisotropic conductive film (ACF).

[0110] The display driver 200 may include a timing controller 210 and a data driver 220 .

[0111] The timing controller 210 may receive digital video data DATA and timing signals from the circuit board 300. Based on the timing signals, the timing controller 210 may generate a data control signal DCS for controlling the operation timing of the data driver 220, a gate control signal GCS for controlling the operation timing of the gate driver 610, and an emission control signal ECS for controlling the operation timing of the emission control driver 620. The timing controller 210 may provide the gate control signal GCS to the gate driver 610 via a first gate control line GSL1. The timing controller 210 may provide the emission control signal ECS to the emission control driver 620 via a second gate control line GSL2. The timing controller 210 may provide the digital video data DATA and the data control signal DCS to the data driver 220.

[0112] The data driver 220 can convert the digital video data DATA into an analog data voltage and can provide the analog data voltage to the data line DL through the fan-out line FL. The gate signal of the gate driver 610 can select the pixel SP to which the data voltage is provided, and the selected pixel SP can receive the data voltage through the data line DL. The data driver 220 can provide the sensing signal received through the readout line ROL to the host processor.

[0113] The power supply 500 may be located on the circuit board 300 to provide power voltage to the display driver 200 and the display panel 100. The power supply 500 may generate a power voltage to be supplied to the power line VL, and may generate a common voltage to be supplied to a common electrode common to the pixel SP and the fingerprint sensor OPD. The power supply 500 may generate an initialization voltage to be supplied to an initialization voltage line, a reference voltage to be supplied to a reference voltage line, a bias voltage to be supplied to a bias voltage line, and a reset voltage to be supplied to a reset voltage line.

[0114] The gate driver 610 may be located on one side of the display area DA or on one side of the non-display area NDA. The emission control driver 620 may be located on the other side of the display area DA or on the other side of the non-display area NDA. However, the present disclosure is not limited thereto. As another example, the gate driver 610 and the emission control driver 620 may be located on either one side or the other side of the non-display area NDA.

[0115] The gate driver 610 may include a plurality of transistors that generate gate signals based on a gate control signal GCS. The emission control driver 620 may include a plurality of transistors that generate emission signals based on an emission control signal ECS. For example, the transistors of the gate driver 610 and the transistors of the emission control driver 620 may be formed in the same layer as the transistors of each pixel SP. The gate driver 610 may provide a gate signal to the gate line GL, and the emission control driver 620 may provide an emission signal to the emission control line EML.

[0116] Figure 5 is a plan view illustrating a pixel circuit and a sensor circuit of a display device according to one or more embodiments.

[0117] refer to Figure 5, a plurality of pixel circuits and a plurality of sensor circuits may be arranged along a plurality of rows and columns in the display area DA. For example, the pixel circuits and the sensor circuits may be arranged along a first circuit row CRW1, a second circuit row CRW2, a third circuit row CRW3, a fourth circuit row CRW4, a fifth circuit row CRW5, a sixth circuit row CRW6, a seventh circuit row CRW7, and an eighth circuit row CRW8, and a first circuit column CCL01, a second circuit column CCL02, a third circuit column CCL03, a fourth circuit column CCL04, a fifth circuit column CCL05, a sixth circuit column CCL06, a seventh circuit column CCL07, an eighth circuit column CCL08, a ninth circuit column CCL09, a tenth circuit column CCL10, an eleventh circuit column CCL11, a twelfth circuit column CCL12, a thirteenth circuit column CCL13, a fourteenth circuit column CCL14, a fifteenth circuit column CCL15, a sixteenth circuit column CCL16, a seventeenth circuit column CCL17, and an eighteenth circuit column CCL18. The pixel circuits and sensor circuits may be positioned in a corresponding ratio within the display area DA. The display area DA includes the pixel circuits and sensor circuits arranged in a corresponding ratio, and thus may include the pixels SP and the fingerprint sensor OPD positioned in the same layer. For example, the pixel circuits and sensor circuits may be positioned in an 8:1 ratio, but the present disclosure is not limited thereto. Thus, the display device 10 can improve the resolution of the pixels SP while maintaining the sensitivity of the fingerprint sensor OPD.

[0118] The first circuit row CRW1 may include an eleventh pixel circuit PC11, a twelfth pixel circuit PC12, a thirteenth pixel circuit PC13, a fourteenth pixel circuit PC14, a fifteenth pixel circuit PC15, a sixteenth pixel circuit PC16, a seventeenth pixel circuit PC17, an eighteenth pixel circuit PC18, a nineteenth pixel circuit PC19, a 1A pixel circuit PC1A, a 1B pixel circuit PC1B, a 1C pixel circuit PC1C, a 1D pixel circuit PC1D, a 1E pixel circuit PC1E, a 1F pixel circuit PC1F, and a 1G pixel circuit PC1G, as well as an eleventh sensor circuit SC11 and a twelfth sensor circuit SC12. The eleventh sensor circuit SC11 may be located between the fourteenth pixel circuit PC14 and the fifteenth pixel circuit PC15, and the twelfth sensor circuit SC12 may be located between the 1C pixel circuit PC1C and the 1D pixel circuit PC1D.

[0119] The second circuit row CRW2 may include a twenty-first pixel circuit PC21, a twenty-second pixel circuit PC22, a twenty-third pixel circuit PC23, a twenty-fourth pixel circuit PC24, a twenty-fifth pixel circuit PC25, a twenty-sixth pixel circuit PC26, a twenty-seventh pixel circuit PC27, a twenty-eighth pixel circuit PC28, a twenty-ninth pixel circuit PC29, a 2A pixel circuit PC2A, a 2B pixel circuit PC2B, a 2C pixel circuit PC2C, a 2D pixel circuit PC2D, a 2E pixel circuit PC2E, a 2F pixel circuit PC2F, and a 2G pixel circuit PC2G, as well as a twenty-first sensor circuit SC21 and a twenty-second sensor circuit SC22. The twenty-first sensor circuit SC21 may be located between the twenty-fourth pixel circuit PC24 and the twenty-fifth pixel circuit PC25, and the twenty-second sensor circuit SC22 may be located between the 2C pixel circuit PC2C and the 2D pixel circuit PC2D.

[0120] The third circuit row CRW3 may include a 31st pixel circuit PC31, a 32nd pixel circuit PC32, a 33rd pixel circuit PC33, a 34th pixel circuit PC34, a 35th pixel circuit PC35, a 36th pixel circuit PC36, a 37th pixel circuit PC37, a 38th pixel circuit PC38, a 39th pixel circuit PC39, a 3A pixel circuit PC3A, a 3B pixel circuit PC3B, a 3C pixel circuit PC3C, a 3D pixel circuit PC3D, a 3E pixel circuit PC3E, a 3F pixel circuit PC3F, and a 3G pixel circuit PC3G, as well as a 31st sensor circuit SC31 and a 32nd sensor circuit SC32. The 31st sensor circuit SC31 may be located between the 34th pixel circuit PC34 and the 35th pixel circuit PC35, and the 32nd sensor circuit SC32 may be located between the 3C pixel circuit PC3C and the 3D pixel circuit PC3D.

[0121] The fourth circuit row CRW4 may include a 41st pixel circuit PC41, a 42nd pixel circuit PC42, a 43rd pixel circuit PC43, a 44th pixel circuit PC44, a 45th pixel circuit PC45, a 46th pixel circuit PC46, a 47th pixel circuit PC47, a 48th pixel circuit PC48, a 49th pixel circuit PC49, a 4A pixel circuit PC4A, a 4B pixel circuit PC4B, a 4C pixel circuit PC4C, a 4D pixel circuit PC4D, a 4E pixel circuit PC4E, a 4F pixel circuit PC4F, and a 4G pixel circuit PC4G, as well as a 41st sensor circuit SC41 and a 42nd sensor circuit SC42. The 41st sensor circuit SC41 may be located between the 44th pixel circuit PC44 and the 45th pixel circuit PC45, and the 42nd sensor circuit SC42 may be located between the 4C pixel circuit PC4C and the 4D pixel circuit PC4D.

[0122] The fifth circuit row CRW5 may include a 51st pixel circuit PC51, a 52nd pixel circuit PC52, a 53rd pixel circuit PC53, a 54th pixel circuit PC54, a 55th pixel circuit PC55, a 56th pixel circuit PC56, a 57th pixel circuit PC57, a 58th pixel circuit PC58, a 59th pixel circuit PC59, a 5A pixel circuit PC5A, a 5B pixel circuit PC5B, a 5C pixel circuit PC5C, a 5D pixel circuit PC5D, a 5E pixel circuit PC5E, a 5F pixel circuit PC5F, and a 5G pixel circuit PC5G, as well as a 51st sensor circuit SC51 and a 52nd sensor circuit SC52. The 51st sensor circuit SC51 may be located between the 54th pixel circuit PC54 and the 55th pixel circuit PC55, and the 52nd sensor circuit SC52 may be located between the 5C pixel circuit PC5C and the 5D pixel circuit PC5D.

[0123] The sixth circuit row CRW6 may include a sixty-first pixel circuit PC61, a sixty-second pixel circuit PC62, a sixty-third pixel circuit PC63, a sixty-fourth pixel circuit PC64, a sixty-fifth pixel circuit PC65, a sixty-sixth pixel circuit PC66, a sixty-seventh pixel circuit PC67, a sixty-eighth pixel circuit PC68, a sixty-ninth pixel circuit PC69, a 6A pixel circuit PC6A, a 6B pixel circuit PC6B, a 6C pixel circuit PC6C, a 6D pixel circuit PC6D, a 6E pixel circuit PC6E, a 6F pixel circuit PC6F, and a 6G pixel circuit PC6G, as well as a sixty-first sensor circuit SC61 and a sixty-second sensor circuit SC62. The sixty-first sensor circuit SC61 may be located between the sixty-fourth pixel circuit PC64 and the sixty-fifth pixel circuit PC65, and the sixty-second sensor circuit SC62 may be located between the 6C pixel circuit PC6C and the 6D pixel circuit PC6D.

[0124] The seventh circuit row CRW7 may include a seventy-first pixel circuit PC71, a seventy-second pixel circuit PC72, a seventy-third pixel circuit PC73, a seventy-fourth pixel circuit PC74, a seventy-fifth pixel circuit PC75, a seventy-sixth pixel circuit PC76, a seventy-seventh pixel circuit PC77, a seventy-eighth pixel circuit PC78, a seventy-ninth pixel circuit PC79, a 7A pixel circuit PC7A, a 7B pixel circuit PC7B, a 7C pixel circuit PC7C, a 7D pixel circuit PC7D, a 7E pixel circuit PC7E, a 7F pixel circuit PC7F, and a 7G pixel circuit PC7G, as well as a seventy-first sensor circuit SC71 and a seventy-second sensor circuit SC72. The seventy-first sensor circuit SC71 may be located between the seventy-fourth pixel circuit PC74 and the seventy-fifth pixel circuit PC75, and the seventy-second sensor circuit SC72 may be located between the 7C pixel circuit PC7C and the 7D pixel circuit PC7D.

[0125] The eighth circuit row CRW8 may include an 81st pixel circuit PC81, ​​an 82nd pixel circuit PC82, an 83rd pixel circuit PC83, an 84th pixel circuit PC84, an 85th pixel circuit PC85, an 86th pixel circuit PC86, an 87th pixel circuit PC87, an 88th pixel circuit PC88, an 89th pixel circuit PC89, an 8A pixel circuit PC8A, an 8B pixel circuit PC8B, an 8C pixel circuit PC8C, an 8D pixel circuit PC8D, an 8E pixel circuit PC8E, an 8F pixel circuit PC8F, and an 8G pixel circuit PC8G, as well as an 81st sensor circuit SC81 and an 82nd sensor circuit SC82. The 81st sensor circuit SC81 may be located between the 84th pixel circuit PC84 and the 85th pixel circuit PC85, and the 82nd sensor circuit SC82 may be located between the 8C pixel circuit PC8C and the 8D pixel circuit PC8D.

[0126] Figure 6 is a plan view of a pixel circuit and a sensor circuit located in a unit area in a display device according to one or more embodiments.

[0127] refer to Figure 6 , the pixel circuits and sensor circuits can be positioned in a constant ratio within the display area DA. The pixel circuits can have the same size, and the sensor circuits can have the same size. The pixel circuits and sensor circuits can be positioned in an 8:1 ratio. For example, a unit area can include eight pixel circuits PC11, PC12, PC13, PC14, PC15, PC16, PC17, and PC18 and one sensor circuit SC11.

[0128] For example, if the Y-axis length of the unit area is "A," the Y-axis length of each of the eleventh pixel circuit PC11, the twelfth pixel circuit PC12, the thirteenth pixel circuit PC13, the fourteenth pixel circuit PC14, the fifteenth pixel circuit PC15, the sixteenth pixel circuit PC16, the seventeenth pixel circuit PC17, the eighteenth pixel circuit PC18, and the eleventh sensor circuit SC11 can be "A." If the X-axis length of the unit area is "B," the X-axis length of the eleventh pixel circuit PC11 is "B1," and the X-axis length of the eleventh sensor circuit SC11 is "B2," then "B = 8 × B1 + B2" can be satisfied. When the unit area is fixed, the number of pixel circuits can increase as the number of sensor circuits decreases, and the number of pixel circuits can decrease as the number of sensor circuits increases. Therefore, the display device 10 includes pixel circuits and sensor circuits positioned at a constant ratio, thereby improving the resolution of the pixels SP while maintaining the sensitivity of the fingerprint sensor OPD without increasing the mask process.

[0129] Figure 7 is a plan view illustrating an emission area and a sensor area in a display device according to one or more embodiments.

[0130] refer to Figure 7 The display area DA may include a first emission area EA1, a second emission area EA2, and a third emission area EA3, as well as a sensor area PDA. Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may emit light of a light-emitting element. For example, the first emission area EA1 may emit light of a first color, or red light, the second emission area EA2 may emit light of a second color, or green light, and the third emission area EA3 may emit light of a third color, or blue light, but is not limited thereto.

[0131] One unit pixel UP may present a white grayscale by including one first emission area EA1, two second emission areas EA2, and one third emission area EA3, but the configuration of the unit pixel UP is not limited thereto. The white grayscale may be presented by a combination of light emitted from one first emission area EA1, light emitted from two second emission areas EA2, and light emitted from one third emission area EA3.

[0132] The first, second, and third emission areas EA1, EA2, and EA3 may differ in size from one another. For example, the third emission area EA3 may be larger than the first emission area EA1, and the first emission area EA1 may be larger than the second emission area EA2. However, the present disclosure is not limited thereto. As another example, the first, second, and third emission areas EA1, EA2, and EA3 may be the same size.

[0133] The sensor area PDA may be surrounded by the first emission area EA1, the second emission area EA2, and the third emission area EA3. The sensor area PDA may be adjacent to the first emission area EA1 or the third emission area EA3 in the X-axis direction, and may be adjacent to the second emission area EA2 in the Y-axis direction. The sensor areas PDA may be spaced apart from each other, with at least one of the first emission area EA1, the second emission area EA2, and the third emission area EA3 interposed therebetween. The sensor area PDA may receive light reflected by a finger.

[0134] The first, second, and third emission areas EA1, EA2, and EA3 and the sensor area PDA may be arranged along a plurality of rows and columns. For example, the first emission area EA1, the second emission area EA2 and the third emission area EA3 and the sensor area PDA can be arranged along the first pixel row PRW1, the second pixel row PRW2, the third pixel row PRW3, the fourth pixel row PRW4, the fifth pixel row PRW5, the sixth pixel row PRW6, the seventh pixel row PRW7 and the eighth pixel row PRW8 and the first pixel column PCL01, the second pixel column PCL02, the third pixel column PCL03, the fourth pixel column PCL04, the fifth pixel column PCL05, the sixth pixel column PCL06, the seventh pixel column PCL07, the eighth pixel column PCL08, the ninth pixel column PCL09, the tenth pixel column PCL10, the eleventh pixel column PCL11, the twelfth pixel column PCL12, the thirteenth pixel column PCL13, the fourteenth pixel column PCL14, the fifteenth pixel column PCL16 and the sixteenth pixel column PCL16.

[0135] The first emission area EA1, the second emission area EA2, and the third emission area EA3, and the sensor area PDA may be located in the display area DA in corresponding proportions. The display area DA includes the first emission area EA1, the second emission area EA2, and the third emission area EA3, and the sensor area PDA positioned in corresponding proportions, and therefore may include pixels SP and fingerprint sensors OPD located in the same layer. The unit pixels UP and the fingerprint sensor OPD may be positioned in a 4:2 ratio, but the present disclosure is not limited thereto. For example, the area of ​​the first pixel row PRW1 and the second pixel row PRW2 and the first pixel column PCL01, the second pixel column PCL02, the third pixel column PCL03, the fourth pixel column PCL04, the fifth pixel column PCL05, the sixth pixel column PCL06, the seventh pixel column PCL07, and the eighth pixel column PCL08 may include four unit pixels UP and two fingerprint sensors OPD.

[0136] Multiple sensor areas PDA can be arranged with the same spacing L in the X-axis direction and the Y-axis direction. For example, the spacing L between adjacent sensor areas PDA in the X-axis direction can be substantially the same as the spacing L between adjacent sensor areas PDA in the Y-axis direction. The spacing in the X-axis direction and the spacing in the Y-axis direction of the sensor electrodes corresponding to the sensor areas PDA can be substantially the same. Therefore, in the display device 10, when sensing a user's fingerprint, fingerprint sensitivity can be improved by reducing or minimizing the sensing error depending on the contact angle of the finger.

[0137] Figure 7The first emission area EA1, the second emission area EA2, and the third emission area EA3 and the sensor area PDA may correspond to Figure 5 pixel circuit and sensor circuit. Figure 5 It can include 128 pixel circuits and 16 sensor circuits, and Figure 7 128 emission areas and 16 sensor areas may be included. For example, the sensor area PDA located in the first pixel row PRW1 and the second pixel column PCL02 may correspond to the eleventh sensor circuit SC11 located in the first circuit row CRW1 and the fifth circuit column CCL05. The sensor area PDA located in the first pixel row PRW1 and the sixth pixel column PCL06 may correspond to the twenty-first sensor circuit SC21 located in the second circuit row CRW2 and the fifth circuit column CCL05. The sensor area PDA located in the first pixel row PRW1 and the tenth pixel column PCL10 may correspond to the twelfth sensor circuit SC12 located in the first circuit row CRW1 and the fourteenth circuit column CCL14. The sensor area PDA located in the first pixel row PRW1 and the fourteenth pixel column PCL14 may correspond to the twenty-second sensor circuit SC22 located in the second circuit row CRW2 and the fourteenth circuit column CCL14.

[0138] The gap between the eleventh sensor circuit SC11 and the twelfth sensor circuit SC12, which are adjacent in the X-axis direction, and the gap between the eleventh sensor circuit SC11 and the twenty-first sensor circuit SC21, which are adjacent in the Y-axis direction, may be different. The eleventh sensor circuit SC11 and the twelfth sensor circuit SC12 may be spaced apart from each other in the X-axis direction with eight pixel circuits interposed therebetween, and the eleventh sensor circuit SC11 and the twenty-first sensor circuit SC21 may be directly adjacent to each other in the Y-axis direction. The display device 10 includes sensor connection electrodes that allow electrical connection between the sensor circuits and the light-receiving elements, which are spaced apart in plan view. Therefore, the display device 10 includes sensor circuits in which the gap in the X-axis direction and the gap in the Y-axis direction are different, and a sensor area PDA in which the gap L in the X-axis direction and the gap L in the Y-axis direction are substantially the same. This allows for improving the resolution of the pixels SP while maintaining the sensitivity of the fingerprint sensor OPD without increasing the masking process, and also allows for improving fingerprint sensitivity by reducing or minimizing sensing errors depending on the contact angle of the finger.

[0139] Figure 8 is a plan view illustrating a pixel circuit, a sensor circuit, a pixel electrode, an anode connecting electrode, a sensor electrode, and a sensor connecting electrode of a display device according to one or more embodiments.

[0140] refer to Figure 8, multiple pixel circuits and multiple sensor circuits can be arranged along multiple rows and columns in the display area DA. For example, the pixel circuits and sensor circuits can be arranged along the first circuit row CRW1 and the second circuit row CRW2 and the first circuit column CCL01, the second circuit column CCL02, the third circuit column CCL03, the fourth circuit column CCL04, the fifth circuit column CCL05, the sixth circuit column CCL06, the seventh circuit column CCL07, the eighth circuit column CCL08, and the ninth circuit column CCL09. The pixel circuits and sensor circuits can be located in the display area DA in corresponding proportions. The display area DA includes pixel circuits and sensor circuits positioned in corresponding proportions, and therefore can include pixels SP and fingerprint sensors OPD located in the same layer. For example, the pixel circuits and sensor circuits can be positioned in an 8:1 ratio, but the present disclosure is not limited thereto. Therefore, the display device 10 can improve the resolution of the pixels SP while maintaining the sensitivity of the fingerprint sensor OPD without increasing the mask process.

[0141] The first emission area EA1, the second emission area EA2, and the third emission area EA3, and the sensor area PDA may be arranged along a plurality of rows and columns. For example, the first emission area EA1, the second emission area EA2, and the third emission area EA3, and the sensor area PDA may be arranged along the first pixel row PRW1 and the second pixel row PRW2, and the first pixel column PCL01, the second pixel column PCL02, the third pixel column PCL03, the fourth pixel column PCL04, the fifth pixel column PCL05, the sixth pixel column PCL06, the seventh pixel column PCL07, and the eighth pixel column PCL08.

[0142] The first emission area EA1, the second emission area EA2, and the third emission area EA3, and the sensor area PDA may be located in the display area DA in corresponding proportions. The display area DA includes the first emission area EA1, the second emission area EA2, and the third emission area EA3, and the sensor area PDA positioned in corresponding proportions, and therefore may include pixels SP and fingerprint sensors OPD located in the same layer. The unit pixels UP and the fingerprint sensor OPD may be positioned in a 4:2 ratio, but the present disclosure is not limited thereto. For example, the area of ​​the first pixel row PRW1 and the second pixel row PRW2 and the first pixel column PCL01, the second pixel column PCL02, the third pixel column PCL03, the fourth pixel column PCL04, the fifth pixel column PCL05, the sixth pixel column PCL06, the seventh pixel column PCL07, and the eighth pixel column PCL08 may include four unit pixels UP and two fingerprint sensors OPD.

[0143] The four unit pixels UP may correspond to the eleventh pixel circuit PC11, the twelfth pixel circuit PC12, the thirteenth pixel circuit PC13, the fourteenth pixel circuit PC14, the fifteenth pixel circuit PC15, the sixteenth pixel circuit PC16, the seventeenth pixel circuit PC17, and the eighteenth pixel circuit PC18, and the twenty-first pixel circuit PC21, the twenty-second pixel circuit PC22, the twenty-third pixel circuit PC23, the twenty-fourth pixel circuit PC24, the twenty-fifth pixel circuit PC25, the twenty-sixth pixel circuit PC26, the twenty-seventh pixel circuit PC27, and the twenty-eighth pixel circuit PC28. The two fingerprint sensors OPD may correspond to the eleventh sensor circuit SC11 and the twenty-first sensor circuit SC21.

[0144] The eleventh pixel circuit PC11 may be electrically connected to the first pixel electrode AE1 located in the first pixel row PRW1 and the first pixel column PCL01 through the first anode connection electrode ANE1. The first anode connection electrode ANE1 may be formed integrally with the first pixel electrode AE1 in the same layer.

[0145] The twelfth pixel circuit PC12 may be electrically connected to the second pixel electrode AE2 located in the first pixel row PRW1 and the second pixel column PCL02 through the second anode connection electrode ANE2. The second anode connection electrode ANE2 may be formed integrally in the same layer as the second pixel electrode AE2.

[0146] The thirteenth pixel circuit PC13 may be electrically connected to the third pixel electrode AE3 located in the first pixel row PRW1 and the third pixel column PCL03 through the third anode connection electrode ANE3. The third anode connection electrode ANE3 may be formed integrally with the third pixel electrode AE3 in the same layer.

[0147] The fourteenth pixel circuit PC14 may be electrically connected to the second pixel electrode AE2 located in the first pixel row PRW1 and the fourth pixel column PCL04 through the second anode connection electrode ANE2. The second anode connection electrode ANE2 may be formed integrally with the second pixel electrode AE2 in the same layer.

[0148] The fifteenth pixel circuit PC15 can be electrically connected to the first pixel electrode AE1 located in the first pixel row PRW1 and the fifth pixel column PCL05 through the first anode connection electrode ANE1. The sixteenth pixel circuit PC16 can be electrically connected to the second pixel electrode AE2 located in the first pixel row PRW1 and the sixth pixel column PCL06 through the second anode connection electrode ANE2.

[0149] The seventeenth pixel circuit PC17 can be electrically connected to the third pixel electrode AE3 located in the first pixel row PRW1 and the seventh pixel column PCL07 through the third anode connection electrode ANE3. The eighteenth pixel circuit PC18 can be electrically connected to the second pixel electrode AE2 located in the first pixel row PRW1 and the eighth pixel column PCL08 through the second anode connection electrode ANE2.

[0150] The first pixel row PRW1 may include a first sub-row and a second sub-row. The second pixel electrode AE2 and the second emission area EA2 may be arranged in the first sub-row. The first pixel electrode AE1 and the third pixel electrode AE3 may be alternately arranged in the second sub-row. The first emission area EA1 and the third emission area EA3 may be alternately arranged in the second sub-row.

[0151] The eleventh sensor circuit SC11 can be electrically connected to the sensor electrode PE located in the first pixel row PRW1 and the second pixel column PCL02 via a sensor connection electrode PNE. The sensor connection electrode PNE can be formed integrally with the sensor electrode PE in the same layer. The eleventh sensor circuit SC11 and the sensor electrode PE can be spaced apart from each other, with the thirteenth pixel circuit PC13 and the fourteenth pixel circuit PC14 interposed therebetween. The sensor connection electrode PNE can overlap with the thirteenth pixel circuit PC13 and the fourteenth pixel circuit PC14. The sensor electrode PE can be adjacent to the first pixel electrode AE1 and the third pixel electrode AE3 in the X-axis direction, and can be adjacent to the second pixel electrode AE2 in the Y-axis direction.

[0152] The twenty-first sensor circuit SC21 can be electrically connected to the sensor electrode PE located in the first pixel row PRW1 and the sixth pixel column PCL06 via the sensor connection electrode PNE. The sensor connection electrode PNE can be formed integrally with the sensor electrode PE in the same layer. The sensor electrode PE located in the first pixel row PRW1 and the sixth pixel column PCL06 can overlap the sixteenth pixel circuit PC16. The twenty-first sensor circuit SC21 and the sensor electrode PE can be spaced apart from each other, with the fifteenth pixel circuit PC15 and the twenty-fifth pixel circuit PC25 interposed therebetween. The sensor connection electrode PNE can overlap the twenty-fifth pixel circuit PC25, the twenty-sixth pixel circuit PC26, the twenty-seventh pixel circuit PC27, the seventeenth pixel circuit PC17, and the sixteenth pixel circuit PC16.

[0153] The eleventh sensor circuit SC11 and the twenty-first sensor circuit SC21 may be adjacent to each other in the Y-axis direction, and the sensor electrodes PE electrically connected to each of the eleventh and second sensor circuits SC11 and SC21 may be spaced apart from each other in the X-axis direction, with a plurality of pixel circuits interposed therebetween. The sensor connection electrode PNE may electrically connect each of the eleventh and second sensor circuits SC11 and SC21 to the sensor electrodes PE spaced apart from each other in plan view. Thus, the display device 10 includes sensor circuits in which the gaps in the X-axis direction and the gaps in the Y-axis direction are different, and a sensor area PDA in which the gaps L in the X-axis direction and the gaps L in the Y-axis direction are substantially the same. This allows for improving the resolution of the pixels SP while maintaining the sensitivity of the fingerprint sensor OPD without increasing the mask process, and also improves fingerprint sensitivity by reducing or minimizing sensing errors depending on the contact angle of the finger.

[0154] Figure 8 Shown is located Figure 5 The pixel circuits and sensor circuits in the first circuit row CRW1 and the second circuit row CRW2 are located Figure 7 The connection relationship between the first pixel electrode AE1, the second pixel electrode AE2 and the third pixel electrode AE3 and the sensor electrode PE in the first pixel row PRW1 and the second pixel row PRW2. Figure 5 The pixel circuits and sensor circuits in the third circuit row CRW3, the fourth circuit row CRW4, the fifth circuit row CRW5, the sixth circuit row CRW6, the seventh circuit row CRW7 and the eighth circuit row CRW8 are located in the same manner as the pixel circuits and sensor circuits in the third circuit row CRW3, the fourth circuit row CRW4, the fifth circuit row CRW5, the sixth circuit row CRW6, the seventh circuit row CRW7 and the eighth circuit row Figure 7 The first pixel electrode AE1, the second pixel electrode AE2, the third pixel electrode AE3 and the sensor electrode PE in the third pixel row PRW3, the fourth pixel row PRW4, the fifth pixel row PRW5, the sixth pixel row PRW6, the seventh pixel row PRW7 and the eighth pixel row PRW8 may be electrically connected.

[0155] Figure 9 is a circuit diagram illustrating a pixel of a display device according to one or more embodiments.

[0156] refer to Figure 9 , the pixel SP can be connected to the first gate line GWL, the second gate line GCL, the third gate line GIL, the fourth gate line GBL, the emission control line EML, the data line DL, the driving voltage line VDL, the first initialization voltage line VIL1, the second initialization voltage line VIL2 and the low potential line VSL.

[0157] The pixel SP may include a light emitting element ED and a pixel circuit PC for driving the light emitting element ED. The pixel circuit PC may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, and an eighth transistor ST8, and a storage capacitor CST.

[0158] The first transistor ST1 may control the driving current supplied to the light emitting element ED. The first transistor ST1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor ST1 may be connected to the third node N3, the first electrode thereof may be connected to the first node N1, and the second electrode thereof may be connected to the second node N2. For example, the first electrode of the first transistor ST1 may be a source electrode, and the second electrode thereof may be a drain electrode, but the present disclosure is not limited thereto.

[0159] The first transistor ST1 may control a source-drain current Isd (hereinafter referred to as a "driving current") according to a data voltage applied to a gate electrode. The driving current Isd flowing through the channel of the first transistor ST1 may be proportional to the square of a difference between a threshold voltage Vth and a voltage Vsg between a source electrode and a gate electrode of the first transistor ST1 (e.g., Isd=k×(Vsg-Vth)). 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor ST1, Vsg is a source-gate voltage of the first transistor ST1, and Vth is a threshold voltage of the first transistor ST1.

[0160] The light-emitting element ED can emit light by receiving the driving current Isd. The emission amount or brightness of the light-emitting element ED can be proportional to the magnitude of the driving current Isd. The light-emitting element ED may include a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode. The first electrode of the light-emitting element ED may be connected to the fourth node N4. The first electrode of the light-emitting element ED may be connected to the second electrode of the sixth transistor ST6 and the first electrode of the seventh transistor ST7 through the fourth node N4. The second electrode of the light-emitting element ED may be connected to the low potential line VSL. For example, the first electrode of the light-emitting element ED may be an anode electrode or a pixel electrode, and the second electrode thereof may be a cathode electrode or a common electrode, but the present disclosure is not limited thereto.

[0161] The second transistor ST2 can be turned on by the first gate signal of the first gate line GWL to electrically connect the data line DL to the first node N1, which is the first electrode of the first transistor ST1. The second transistor ST2 can be turned on based on the first gate signal to provide a data voltage to the first node N1. The gate electrode of the second transistor ST2 can be connected to the first gate line GWL, its first electrode can be connected to the data line DL, and its second electrode can be connected to the first node N1. The second electrode of the second transistor ST2 can be connected to the first electrode of the first transistor ST1, the second electrode of the fifth transistor ST5, and the second electrode of the eighth transistor ST8 through the first node N1. For example, the first electrode of the second transistor ST2 can be a source electrode, and its second electrode can be a drain electrode, but the present disclosure is not limited to this.

[0162] The third transistor ST3 can be turned on by the second gate signal of the second gate line GCL to electrically connect the second node N2, which serves as the second electrode of the first transistor ST1, to the third node N3, which serves as the gate electrode of the first transistor ST1. The gate electrode of the third transistor ST3 can be connected to the second gate line GCL, its first electrode can be connected to the second node N2, and its second electrode can be connected to the third node N3. The first electrode of the third transistor ST3 can be connected to the second electrode of the first transistor ST1 and the first electrode of the sixth transistor ST6 via the second node N2. The second electrode of the third transistor ST3 can be connected to the gate electrode of the first transistor ST1, the first electrode of the fourth transistor ST4, and the first capacitor electrode of the storage capacitor CST via the third node N3. For example, the first electrode of the third transistor ST3 can be a drain electrode, and the second electrode can be a source electrode, but is not limited thereto.

[0163] The fourth transistor ST4 can be turned on by a third gate signal of the third gate line GIL to electrically connect the third node N3, which serves as the gate electrode of the first transistor ST1, to the first initialization voltage line VIL1. The fourth transistor ST4 can be turned on based on the third gate signal, thereby discharging the gate electrode of the first transistor ST1 to the first initialization voltage. The gate electrode of the fourth transistor ST4 can be connected to the third gate line GIL, its first electrode can be connected to the third node N3, and its second electrode can be connected to the first initialization voltage line VIL1. The first electrode of the fourth transistor ST4 can be connected to the gate electrode of the first transistor ST1, the second electrode of the third transistor ST3, and the first capacitor electrode of the storage capacitor CST through the third node N3. For example, the first electrode of the fourth transistor ST4 can be a drain electrode, and its second electrode can be a source electrode, but is not limited thereto.

[0164] The fifth transistor ST5 can be turned on by an emission signal of the emission control line EML to electrically connect the drive voltage line VDL to the first node N1, which is the first electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 can be connected to the emission control line EML, its first electrode can be connected to the drive voltage line VDL, and its second electrode can be connected to the first node N1. The second electrode of the fifth transistor ST5 can be electrically connected to the first electrode of the first transistor ST1, the second electrode of the second transistor ST2, and the second electrode of the eighth transistor ST8 through the first node N1. For example, the first electrode of the fifth transistor ST5 can be a source electrode, and its second electrode can be a drain electrode, but the present disclosure is not limited thereto.

[0165] The sixth transistor ST6 can be turned on by an emission signal from the emission control line EML to electrically connect the second node N2, which serves as the second electrode of the first transistor ST1, to the fourth node N4, which serves as the first electrode of the light-emitting element ED. The gate electrode of the sixth transistor ST6 can be connected to the emission control line EML, its first electrode can be connected to the second node N2, and its second electrode can be connected to the fourth node N4. The first electrode of the sixth transistor ST6 can be connected to the second electrode of the first transistor ST1 and the first electrode of the third transistor ST3 via the second node N2. The second electrode of the sixth transistor ST6 can be connected to the first electrode of the light-emitting element ED and the first electrode of the seventh transistor ST7 via the fourth node N4. For example, the first electrode of the sixth transistor ST6 can be a source electrode, and its second electrode can be a drain electrode, but the present disclosure is not limited thereto.

[0166] When all of the fifth transistor ST5 , the first transistor ST1 , and the sixth transistor ST6 are turned on, the driving current Isd may be supplied to the plurality of light emitting elements ED.

[0167] The seventh transistor ST7 can be turned on by the fourth gate signal of the fourth gate line GBL to electrically connect the second initialization voltage line VIL2 to the fourth node N4, which is the first electrode of the light-emitting element ED. By turning on the seventh transistor ST7 based on the fourth gate signal, the first electrode of the light-emitting element ED can be discharged to the second initialization voltage. The gate electrode of the seventh transistor ST7 can be connected to the fourth gate line GBL, the first electrode thereof can be connected to the fourth node N4, and the second electrode thereof can be connected to the second initialization voltage line VIL2. The first electrode of the seventh transistor ST7 can be connected to the first electrode of the light-emitting element ED and the second electrode of the sixth transistor ST6 via the fourth node N4.

[0168] The eighth transistor ST8 can be turned on by the fourth gate signal of the fourth gate line GBL to electrically connect the bias voltage line VBL to the first node N1 serving as the source electrode of the first transistor ST1. The eighth transistor ST8 can be turned on based on the fourth gate signal to provide a bias voltage to the first node N1. The eighth transistor ST8 can improve the hysteresis of the first transistor ST1 by providing a bias voltage to the source electrode of the first transistor ST1. The gate electrode of the eighth transistor ST8 can be connected to the fourth gate line GBL, its first electrode can be connected to the bias voltage line VBL, and its second electrode can be connected to the first node N1. The second electrode of the eighth transistor ST8 can be electrically connected to the first electrode of the first transistor ST1, the second electrode of the second transistor ST2, and the second electrode of the fifth transistor ST5 via the first node N1. For example, the first electrode of the eighth transistor ST8 can be a source electrode, and its second electrode can be a drain electrode, but the present disclosure is not limited thereto.

[0169] Each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may include a semiconductor region based on silicon. For example, each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may include a semiconductor region made of low-temperature polysilicon (LTPS). The semiconductor region made of low-temperature polysilicon may have high electron mobility and excellent conduction characteristics. Therefore, because the display device includes the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 having excellent conduction characteristics, it is possible to stably and efficiently drive a plurality of pixels SP.

[0170] Each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may correspond to a p-type transistor. For example, each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may output a current flowing into a first electrode to a second electrode based on a gate low voltage applied to the gate electrode.

[0171] Each of the third transistor ST3 and the fourth transistor ST4 may include an oxide-based semiconductor region. For example, each of the third transistor ST3 and the fourth transistor ST4 may have a coplanar structure in which the gate electrode is located on the oxide-based semiconductor region. Transistors having a coplanar structure may have excellent leakage current characteristics and may be driven at a low frequency, thereby reducing power consumption. Therefore, the display device may include the third transistor ST3 and the fourth transistor ST4 having excellent leakage current characteristics, thereby reducing or preventing leakage current flowing in the pixel SP and stably maintaining the voltage in the pixel SP.

[0172] Each of the third transistor ST3 and the fourth transistor ST4 may correspond to an n-type transistor. For example, each of the third transistor ST3 and the fourth transistor ST4 may output current flowing into the first electrode to the second electrode based on a gate high voltage applied to the gate electrode.

[0173] The storage capacitor CST may be connected between the third node N3, which is the gate electrode of the first transistor ST1, and the driving voltage line VDL. For example, a first capacitor electrode of the storage capacitor CST may be connected to the third node N3, and a second capacitor electrode of the storage capacitor CST may be connected to the driving voltage line VDL, thereby maintaining a potential difference between the driving voltage line VDL and the gate electrode of the first transistor ST1.

[0174] Figure 10 is a circuit diagram of a fingerprint sensor of a display device according to one or more embodiments.

[0175] refer to Figure 10 , the fingerprint sensor OPD may be connected to the first gate line GWL, the reset signal line GRL, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the readout line ROL.

[0176] The fingerprint sensor OPD may include a light receiving element PD and a sensor circuit SC for driving the light receiving element PD. The sensor circuit SC may include a first sensor transistor PT1, a second sensor transistor PT2, and a third sensor transistor PT3.

[0177] The first sensor transistor PT1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first sensor transistor PT1 may be connected to the sensor node NS, the first electrode thereof may be connected to the third sensor transistor PT3, and the second electrode thereof may be connected to the second initialization voltage line VIL2. The first sensor transistor PT1 may control a source-drain current Isd (hereinafter referred to as “sensing current”) based on the voltage of the sensor node NS which is the first electrode of the light receiving element PD. The sensing current Isd flowing through the channel of the first sensor transistor PT1 may be proportional to the square of the difference between the threshold voltage Vth and the voltage Vsg between the source and gate electrodes of the first sensor transistor PT1 (e.g., Isd=k'×(Vsg-Vth) 2 ). Here, k' is a proportionality coefficient determined by the structure and physical characteristics of the first sensor transistor PT1, Vsg is a source-gate voltage of the first sensor transistor PT1, and Vth is a threshold voltage of the first sensor transistor PT1. The first electrode of the first sensor transistor PT1 may be a source electrode, and the second electrode thereof may be a drain electrode, but the present disclosure is not limited thereto.

[0178] The second sensor transistor PT2 can be turned on by a reset signal from the reset signal line GRL, thereby discharging the sensor node NS to a first initialization voltage. The gate electrode of the second sensor transistor PT2 can be connected to the reset signal line GRL, its first electrode can be connected to the sensor node NS, and its second electrode can be connected to the first initialization voltage line VIL1. The first electrode of the second sensor transistor PT2 can be connected to the first electrode of the light receiving element PD and the gate electrode of the first sensor transistor PT1 via the sensor node NS. The first electrode of the second sensor transistor PT2 can be a drain electrode, and its second electrode can be a source electrode, but is not limited thereto.

[0179] The third sensor transistor PT3 can be turned on by a first gate signal from the first gate line GWL to electrically connect the first electrode of the first sensor transistor PT1 to the readout line ROL. The third sensor transistor PT3 may include a third-first sensor transistor PT3-1 and a third-second sensor transistor PT3-2 connected in series. The third-first sensor transistor PT3-1 and the third-second sensor transistor PT3-2 may be connected in series between the first electrode of the first sensor transistor PT1 and the readout line ROL. The gate electrode of the third-first sensor transistor PT3-1 and the gate electrode of the third-second sensor transistor PT3-2 may be integrally formed and electrically connected to the first gate line GWL. The first electrode of the third-first sensor transistor PT3-1 may be connected to the readout line ROL, and the second electrode of the third-second sensor transistor PT3-2 may be connected to the first electrode of the first sensor transistor PT1. The second electrode of the third-first sensor transistor PT3-1 and the first electrode of the third-second sensor transistor PT3-2 may be integrally formed. A first electrode of each of the third-first sensor transistor PT3 - 1 and the third-second sensor transistor PT3 - 2 may be a source electrode, and a second electrode thereof may be a drain electrode, but the present disclosure is not limited thereto.

[0180] The light receiving element PD can recognize the pattern of the user's fingerprint based on the light reflected from the user's finger. The first electrode of the light receiving element PD can be connected to the sensor node NS, which is the gate electrode of the first sensor transistor PT1, and the second electrode thereof can be connected to the low potential line VSL. The second electrode of the light receiving element PD can receive the low potential voltage from the low potential line VSL. For example, the first electrode of the light receiving element PD can be a sensor electrode, and the second electrode thereof can be a common electrode, but the present disclosure is not limited thereto.

[0181] When a user's finger touches the display panel 100, the light receiving element PD can receive light reflected by the ridges or valleys of the finger. Light output from the light-emitting element ED can be reflected by the ridges or valleys of the finger, and the reflected light can reach the light receiving element PD. The light receiving element PD can convert the energy of the light into an electrical signal (current or voltage) formed between the first electrode and the second electrode, and the converted electrical signal can flow from the light receiving element PD to the sensor node NS as a reverse bias current. For example, when the light receiving element PD receives light and an electric field is formed between the first electrode and the second electrode of the light receiving element PD, a current can flow through the light receiving element PD in proportion to the amount of light, and the voltage at the sensor node NS can increase. Therefore, when the light receiving element PD receives light, the voltage of the sensor node NS can increase, and the magnitude of the sensed current Isd (or source-drain current) of the first sensor transistor PT1 can decrease. The sensed current Isd of the first sensor transistor PT1 can be applied to the display driver 200 as a sense signal via the third sensor transistor PT3 and the readout line ROL.

[0182] Figure 11 is a layout diagram illustrating some layers of a pixel circuit and a sensor circuit of a display device according to one or more embodiments. Figure 11 A metal layer MTL of the display device, a first active layer ACTL1, a first gate layer GTL1, a second gate layer GTL2, a second active layer ACTL2, a third gate layer GTL3, and a first source metal layer SDL1 may be included. Figure 12 It shows Figure 11 Layout diagram of some layers. Figure 12 A metal layer MTL, a first active layer ACTL1, a first gate layer GTL1, and a second gate layer GTL2 of the display device may be included. Figure 13 It shows Figure 11 Layout diagrams of some other layers. Figure 13 A second active layer ACTL2 , a third gate layer GTL3 , and a first source metal layer SDL1 of the display device may be included. Figure 14 is a layout diagram illustrating some other layers of a pixel circuit and a sensor circuit of a display device according to one or more embodiments. Figure 14 A first source metal layer SDL1, a second source metal layer SDL2, and a third source metal layer of the display device may be included. Figure 15 is a layout diagram showing some layers of a pixel circuit of a display device according to one or more embodiments, and Figure 16 It shows Figure 15 Layout diagram of some layers. Figure 17 It shows Figure 15 Layout diagrams of some other layers, and Figure 18is a layout diagram illustrating some other layers of a pixel circuit of a display device according to one or more embodiments. Figures 15 to 18 Public Figures 11 to 14 The pixel circuit PC. Figure 19 It is along Figures 15 to 18 A cross-sectional view taken along line II'.

[0183] refer to Figures 11 to 19 The sensor circuit SC and the pixel circuit PC may be adjacent to each other in the X-axis direction. The sensor circuit SC may be connected to the first gate line GWL, the reset signal line GRL, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the readout line ROL. The pixel circuit PC may be connected to the first gate line GWL, the second gate line GCL, the third gate line GIL, the fourth gate line GBL, the emission control line EML, the data line DL, the drive voltage line VDL, the first initialization voltage line VIL1, and the second initialization voltage line VIL2.

[0184] The pixel circuit PC may include a first transistor ST1 , a second transistor ST2 , a third transistor ST3 , a fourth transistor ST4 , a fifth transistor ST5 , a sixth transistor ST6 , a seventh transistor ST7 , and an eighth transistor ST8 and a storage capacitor CST.

[0185] The first transistor ST1 may include a semiconductor region ACT1, a gate electrode GE1, a first electrode SE1, and a second electrode DE1. The semiconductor region ACT1, the first electrode SE1, and the second electrode DE1 of the first transistor ST1 may be located in the first active layer ACTL1, and the gate electrode GE1 of the first transistor ST1 may be located in the first gate layer GTL1. The gate electrode GE1 of the first transistor ST1 may be part of the first capacitor electrode CPE1 of the first gate layer GTL1 and may overlap with the semiconductor region ACT1 of the first transistor ST1. For example, the semiconductor region ACT1 of the first transistor ST1 may include low-temperature polycrystalline silicon (LTPS).

[0186] The first light blocking layer BML1 may be located in the metal layer MTL and may overlap with the first transistor ST1. The first light blocking layers BML1 of the plurality of pixels SP may be connected to each other, but the present disclosure is not limited thereto. The first light blocking layer BML1 may block light incident from a lower portion of the first transistor ST1.

[0187] The gate electrode GE1 of the first transistor ST1 may be electrically connected to the first electrode of the fourth transistor ST4 and the second electrode SE3 of the third transistor ST3 located in the second active layer ACTL2 via the second connection electrode CE2 of the first source metal layer SDL1. The first electrode SE1 of the first transistor ST1 may be electrically connected to the second electrode of the fifth transistor ST5 and the second electrode DE2 of the second transistor ST2 located in the first active layer ACTL1. The first electrode SE1 of the first transistor ST1 may be electrically connected to the second electrode of the eighth transistor ST8 located in the first active layer ACTL1 via the fourth connection electrode CE4 of the first source metal layer SDL1. The second electrode DE1 of the first transistor ST1 may be electrically connected to the first electrode DE3 of the third transistor ST3 located in the second active layer ACTL2 via the third connection electrode CE3 of the first source metal layer SDL1. The second electrode DE1 of the first transistor ST1 may be connected to the first electrode of the sixth transistor ST6 located in the first active layer ACTL1.

[0188] The second transistor ST2 may include a semiconductor region ACT2, a gate electrode GE2, a first electrode SE2, and a second electrode DE2. The semiconductor region ACT2, the first electrode SE2, and the second electrode DE2 of the second transistor ST2 may be located in the first active layer ACTL1, and the gate electrode GE2 of the second transistor ST2 may be located in the first gate layer GTL1. The gate electrode GE2 of the second transistor ST2 may be part of the first gate line GWL of the first gate layer GTL1 and may overlap with the semiconductor region ACT2 of the second transistor ST2. For example, the semiconductor region ACT2 of the second transistor ST2 may include low-temperature polycrystalline silicon (LTPS).

[0189] The first electrode SE2 of the second transistor ST2 may be electrically connected to the data line DL of the second source metal layer SDL2 through the first connection electrode CE1 of the first source metal layer SDL1. The second electrode DE2 of the second transistor ST2 may be connected to the first electrode SE1 of the first transistor ST1 and the second electrode of the fifth transistor ST5. The second electrode DE2 of the second transistor ST2 may be electrically connected to the second electrode of the eighth transistor ST8 through the fourth connection electrode CE4.

[0190] The third transistor ST3 may include a semiconductor region ACT3, a gate electrode GE3, a first electrode DE3, and a second electrode SE3. The semiconductor region ACT3, the first electrode DE3, and the second electrode SE3 of the third transistor ST3 may be located in the second active layer ACTL2, and the gate electrode GE3 of the third transistor ST3 may be located in the third gate layer GTL3. The gate electrode GE3 of the third transistor ST3 may be part of the second gate line GCL of the third gate layer GTL3 and may overlap with the semiconductor region ACT3 of the third transistor ST3. For example, the semiconductor region ACT3 of the third transistor ST3 may include an oxide.

[0191] The second light blocking layer BML2 may be located in the second gate layer GTL2 and may overlap the third transistor ST3 and the second gate line GCL. The second light blocking layer BML2 may block light incident from a lower portion of the third transistor ST3.

[0192] A first electrode DE3 of the third transistor ST3 may be electrically connected to a first electrode of the sixth transistor ST6 and a second electrode DE1 of the first transistor ST1 located in the first active layer ACTL1 via a third connection electrode CE3 of the first source metal layer SDL1. A second electrode SE3 of the third transistor ST3 may be electrically connected to a first electrode of the fourth transistor ST4 located in the second active layer ACTL2. A second electrode SE3 of the third transistor ST3 may be electrically connected to a gate electrode GE1 of the first transistor ST1 and a first capacitor electrode CPE1 located in the first gate layer GTL1 via a second connection electrode CE2 of the first source metal layer SDL1.

[0193] The fourth transistor ST4 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fourth transistor ST4 may be located in the second active layer ACTL2, and the gate electrode of the fourth transistor ST4 may be located in the third gate layer GTL3. The gate electrode of the fourth transistor ST4 may be part of the third gate line GIL of the third gate layer GTL3 and may overlap with the semiconductor region of the fourth transistor ST4. For example, the semiconductor region of the fourth transistor ST4 may include an oxide.

[0194] The second light blocking layer BML2 may be located in the second gate layer GTL2 and may overlap the fourth transistor ST4 and the third gate line GIL. The second light blocking layer BML2 may block light incident from a lower portion of the fourth transistor ST4.

[0195] A first electrode of the fourth transistor ST4 may be electrically connected to the second electrode SE3 of the third transistor ST3 and may be electrically connected to the gate electrode GE1 of the first transistor ST1 through the second connection electrode CE2. A second electrode of the fourth transistor ST4 may be connected to the first portion VIL1a of the first initialization voltage line VIL1 of the first source metal layer SDL1.

[0196] The fifth transistor ST5 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the fifth transistor ST5 may be located in the first active layer ACTL1, and the gate electrode of the fifth transistor ST5 may be located in the first gate layer GTL1. The gate electrode of the fifth transistor ST5 may be part of the emission control line EML of the first gate layer GTL1 and may overlap with the semiconductor region of the fifth transistor ST5. For example, the semiconductor region of the fifth transistor ST5 may include low-temperature polysilicon (LTPS).

[0197] A first electrode of the fifth transistor ST5 may be connected to a first portion VDLa of a driving voltage line VDL of the first source metal layer SDL1. The first portion VDLa of the driving voltage line VDL may be connected to a second portion VDLb of a driving voltage line VDL of the second source metal layer SDL2, and may provide a driving voltage to the first electrode of the fifth transistor ST5. A second electrode of the fifth transistor ST5 may be connected to the first electrode SE1 of the first transistor ST1 and the second electrode DE2 of the second transistor ST2. The second electrode of the fifth transistor ST5 may be electrically connected to the second electrode of the eighth transistor ST8 via a fourth connection electrode CE4.

[0198] The sixth transistor ST6 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the sixth transistor ST6 may be located in the first active layer ACTL1, and the gate electrode of the sixth transistor ST6 may be located in the first gate layer GTL1. The gate electrode of the sixth transistor ST6 may be part of the emission control line EML and may overlap with the semiconductor region of the sixth transistor ST6. For example, the semiconductor region of the sixth transistor ST6 may include low-temperature polysilicon (LTPS).

[0199] A first electrode of the sixth transistor ST6 may be connected to the second electrode DE1 of the first transistor ST1 and may be electrically connected to the first electrode DE3 of the third transistor ST3 via the third connection electrode CE3. A second electrode of the sixth transistor ST6 may be connected to the first electrode of the seventh transistor ST7 located in the first active layer ACTL1 and may be electrically connected to the first electrode of the light emitting element ED via the fifth connection electrode CE5 of the first source metal layer SDL1 and the sixth connection electrode CE6 of the second source metal layer SDL2.

[0200] The seventh transistor ST7 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the seventh transistor ST7 may be located in the first active layer ACTL1, and the gate electrode of the seventh transistor ST7 may be located in the first gate layer GTL1. The gate electrode of the seventh transistor ST7 may be part of the fourth gate line GBL of the first gate layer GTL1 and may overlap with the semiconductor region of the seventh transistor ST7. For example, the semiconductor region of the seventh transistor ST7 may include low-temperature polysilicon (LTPS).

[0201] A first electrode of the seventh transistor ST7 may be connected to the second electrode of the sixth transistor ST6 and may be electrically connected to the first electrode of the light emitting element ED through the fifth and sixth connection electrodes CE5 and CE6. A second electrode of the seventh transistor ST7 may be connected to a first portion VIL2a of a second initialization voltage line VIL2 located in the first source metal layer SDL1.

[0202] The eighth transistor ST8 may include a semiconductor region, a gate electrode, a first electrode, and a second electrode. The semiconductor region, the first electrode, and the second electrode of the eighth transistor ST8 may be located in the first active layer ACTL1, and the gate electrode of the eighth transistor ST8 may be located in the first gate layer GTL1. The gate electrode of the eighth transistor ST8 may be part of the fourth gate line GBL of the first gate layer GTL1 and may overlap with the semiconductor region of the eighth transistor ST8. For example, the semiconductor region of the eighth transistor ST8 may include low-temperature polycrystalline silicon (LTPS).

[0203] A first electrode of the eighth transistor ST8 may be connected to the bias voltage line VBL of the first source metal layer SDL1, and a second electrode of the eighth transistor ST8 may be electrically connected to the first electrode SE1 of the first transistor ST1, the second electrode DE2 of the second transistor ST2, and the second electrode of the fifth transistor ST5 through the fourth connection electrode CE4.

[0204] The storage capacitor CST may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may overlap each other. The first capacitor electrode CPE1 of the storage capacitor CST may be located in the first gate layer GTL1, and the second capacitor electrode CPE2 may be located in the second gate layer GTL2. The first capacitor electrode CPE1 of the storage capacitor CST may include the gate electrode GE1 of the first transistor ST1, and the second capacitor electrode CPE2 may be connected to the first portion VDLa of the driving voltage line VDL.

[0205] exist Figure 19 In the embodiment, the display panel 100 may include a substrate SUB, a metal layer MTL, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a second gate layer GTL2, a first interlayer insulating layer ILD1, a second active layer ACTL2, a third gate insulating layer GI3, a third gate layer GTL3, a second interlayer insulating layer ILD2, a first source metal layer SDL1, a first passivation layer PAS1, a second source metal layer SDL2, a second passivation layer PAS2, a third passivation layer PAS3, a planarization layer OC, a pixel defining layer PDL, a light emitting element ED and an encapsulation layer TFEL.

[0206] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. For another example, the substrate SUB may include a glass material or a metal material.

[0207] The metal layer MTL may be positioned on the substrate SUB and may include a first light blocking layer BML1.

[0208] The buffer layer BF may be located on the metal layer MTL and the substrate SUB. For example, the buffer layer BF may include an inorganic layer capable of reducing or preventing the penetration of air or moisture. For example, the buffer layer BF may include a plurality of inorganic layers alternately stacked.

[0209] The first active layer ACTL1 may be located on the buffer layer BF. The first active layer ACTL1 may include a silicon-based material. For example, the first active layer ACTL1 may be formed of low-temperature polycrystalline silicon (LTPS). The first active layer ACTL1 may include a semiconductor region ACT1, a first electrode SE1, and a second electrode DE1 of the first transistor ST1, and a semiconductor region ACT2, a first electrode SE2, and a second electrode DE2 of the second transistor ST2.

[0210] The first gate insulating layer GI1 may be on the first active layer ACTL1. The first gate insulating layer GI1 may insulate the first active layer ACTL1 from the first gate layer GTL1.

[0211] The first gate layer GTL1 may be located on the first gate insulating layer GI1. The first gate layer GTL1 may include a gate electrode GE1 of the first transistor ST1, a gate electrode GE2 of the second transistor ST2, a first capacitor electrode CPE1, and a first gate line GWL. The gate electrode GE1 of the first transistor ST1 may be part of the first capacitor electrode CPE1.

[0212] The second gate insulating layer GI2 may be located on the first gate layer GTL1 and may insulate the first gate layer GTL1 from the second gate layer GTL2.

[0213] The second gate layer GTL2 may be located on the second gate insulating layer GI2. The second gate layer GTL2 may include a second capacitor electrode CPE2 and a second light blocking layer BML2. The second capacitor electrode CPE2 may overlap the first capacitor electrode CPE1.

[0214] The first interlayer insulating layer ILD1 may be on the second gate layer GTL2 . The first interlayer insulating layer ILD1 may insulate the second gate layer GTL2 from the second active layer ACTL2 .

[0215] The second active layer ACTL2 may be located on the first interlayer insulating layer ILD1. The second active layer ACTL2 may include an oxide-based material. The second active layer ACTL2 may include a semiconductor region ACT3 of the third transistor ST3, a first electrode DE3, and a second electrode SE3.

[0216] The third gate insulating layer GI3 may be on the second active layer ACTL2. The third gate insulating layer GI3 may insulate the second active layer ACTL2 from the third gate layer GTL3.

[0217] The third gate layer GTL3 may be positioned on the third gate insulating layer GI3 . The third gate layer GTL3 may include the second gate line GCL and the gate electrode GE3 of the third transistor ST3 .

[0218] The second interlayer insulating layer ILD2 may be located on the third gate layer GTL3 . The second interlayer insulating layer ILD2 may insulate the third gate layer GTL3 from the first source metal layer SDL1 .

[0219] The first source metal layer SDL1 may be positioned on the second interlayer insulating layer ILD2 , and may include first, second, and third connection electrodes CE1 , CE2 , and CE3 , and a first portion VDLa of the driving voltage line VDL.

[0220] The first passivation layer PAS1 may be on the first source metal layer SDL1. The first passivation layer PAS1 may insulate the first source metal layer SDL1 from the second source metal layer SDL2.

[0221] The second source metal layer SDL2 may be positioned on the first passivation layer PAS1. The second source metal layer SDL2 may include the second portion VDLb of the driving voltage line VDL and the data line DL.

[0222] The second passivation layer PAS2 may be on the second source metal layer SDL2. The second passivation layer PAS2 may insulate the second source metal layer SDL2 from the third source metal layer.

[0223] The third passivation layer PAS3 may be located on the second passivation layer PAS2 and the third source metal layer. A planarization layer OC may be located on the third passivation layer PAS3. The planarization layer OC may planarize the top of the transistor layer TFTL. The planarization layer OC may include an organic insulating material such as polyimide (PI).

[0224] The pixel defining layer PDL may be located on the planarization layer OC. The pixel defining layer PDL may define a plurality of emission areas EA. The pixel defining layer PDL may include an organic insulating material such as polyimide (PI).

[0225] The light-emitting element ED may include a pixel electrode AE, a light-emitting layer EL, and a common electrode CAT. The pixel electrode AE ​​may be located on the planarization layer OC. The pixel electrode AE ​​may overlap one of a plurality of emission areas EA defined by the pixel-defining layer PDL. The pixel electrode AE ​​may receive a driving current from the pixel circuit PC of the pixel SP.

[0226] The light-emitting layer EL may be located on the pixel electrode AE. For example, the light-emitting layer EL may be an organic light-emitting layer made of an organic material, but is not limited thereto. In the case where the light-emitting layer EL is an organic light-emitting layer, when the pixel circuit PC of the pixel SP applies a voltage (e.g., a predetermined voltage) to the pixel electrode AE ​​and the common electrode CAT receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer, respectively, and the holes and electrons may recombine with each other in the light-emitting layer EL to emit light.

[0227] The common electrode CAT may be disposed on the light-emitting layer EL. For example, the common electrode CAT may be fabricated in the form of an electrode common to all pixels SP, rather than being specific to each pixel SP. The common electrode CAT may be located on the light-emitting layer EL in the plurality of emission areas EA, and may be located on the pixel-defining layer PDL in areas other than the emission area EA.

[0228] The encapsulation layer TFEL may be located on the common electrode CAT to cover the plurality of light-emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to reduce or prevent oxygen or moisture from penetrating into the plurality of light-emitting elements ED. The encapsulation layer TFEL may include at least one organic layer to protect the plurality of light-emitting elements ED from impurities such as dust.

[0229] Figure 20 is a layout diagram illustrating some layers of a sensor circuit of a display device according to one or more embodiments. Figure 20 A metal layer MTL of the display device, a first active layer ACTL1, a first gate layer GTL1, a second gate layer GTL2, a second active layer ACTL2, a third gate layer GTL3, and a first source metal layer SDL1 may be included. Figure 21 It shows Figure 20 Layout diagram of some layers. Figure 21 A metal layer MTL, a first active layer ACTL1, a first gate layer GTL1, and a second gate layer GTL2 of the display device may be included. Figure 22 It shows Figure 20 Layout diagrams of some other layers. Figure 22 A second active layer ACTL2 , a third gate layer GTL3 , and a first source metal layer SDL1 of the display device may be included. Figure 23 is a layout diagram illustrating some other layers of a sensor circuit of a display device according to one or more embodiments. Figure 23 A first source metal layer SDL1, a second source metal layer SDL2, and a third source metal layer SDL3 of the display device may be included. Figures 20 to 23 Public Figures 11 to 14 The sensor circuit SC. Figure 24 It is along Figures 20 to 23 A sectional view taken along line II-II'.

[0230] refer to Figures 20 to 24 , the fingerprint sensor OPD may be connected to the first gate line GWL, the reset signal line GRL, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and the readout line ROL.

[0231] The first gate line GWL may be located in the first gate layer GTL1 and may extend in the X-axis direction. The first gate line GWL may provide a first gate signal to the third sensor transistor PT3.

[0232] The reset signal line GRL may be located in the third gate layer GTL3 and may extend in the X-axis direction. The reset signal line GRL may provide a reset signal to the gate electrode PGE2 of the second sensor transistor PT2.

[0233] The first initialization voltage line VIL1 may provide a first initialization voltage to the second electrode PSE2 of the second sensor transistor PT2. The first initialization voltage line VIL1 may include a first portion VIL1a, a second portion VIL1b, and a third portion VIL1c.

[0234] A first portion VIL1a of the first initialization voltage line VIL1 may be located in the first source metal layer SDL1 and may extend in the X-axis direction. The first portion VIL1a of the first initialization voltage line VIL1 may be connected to the second electrode PSE2 of the second sensor transistor PT2 in the second active layer ACTL2.

[0235] The second portion VIL1b of the first initialization voltage line VIL1 may be located in the second source metal layer SDL2 and may extend in the Y-axis direction. The second portion VIL1b of the first initialization voltage line VIL1 may be connected between the first portion VIL1a and the third portion VIL1c of the first initialization voltage line VIL1.

[0236] The third portion VIL1c of the first initialization voltage line VIL1 may be located in the third source metal layer SDL3 and may be connected to the second portion VIL1b of the first initialization voltage line VIL1. The third portion VIL1c of the first initialization voltage line VIL1 may overlap with the second portion VIL1b and the readout line ROL. The third portion VIL1c of the first initialization voltage line VIL1 may shield an upper portion of the readout line ROL.

[0237] The second initialization voltage line VIL2 may provide a second initialization voltage to the second electrode PDE1 of the first sensor transistor PT1. The second initialization voltage line VIL2 may include a first portion VIL2a and a second portion VIL2b.

[0238] A first portion VIL2a of the second initialization voltage line VIL2 may be located in the first source metal layer SDL1 and may extend in the X-axis direction. A second portion VIL2b of the second initialization voltage line VIL2 may extend from the first portion VIL2a in the Y-axis direction. The second portion VIL2b of the second initialization voltage line VIL2 may be connected to the second electrode PDE1 of the first sensor transistor PT1 located in the first active layer ACTL1.

[0239] The fingerprint sensor OPD may include first, second, and third sensor transistors PT1, PT2, and PT3, and a light receiving element PD.

[0240] The first sensor transistor PT1 may include a semiconductor region PACT1, a gate electrode PGE1, a first electrode PSE1, and a second electrode PDE1. The semiconductor region PACT1, the first electrode PSE1, and the second electrode PDE1 of the first sensor transistor PT1 may be located in the first active layer ACTL1, and the gate electrode PGE1 of the first sensor transistor PT1 may be located in the first gate layer GTL1. The gate electrode PGE1 of the first sensor transistor PT1 may overlap with the semiconductor region PACT1 of the first sensor transistor PT1. The semiconductor region PACT1 of the first sensor transistor PT1 may include a silicon-based material. For example, the semiconductor region PACT1 of the first sensor transistor PT1 may include low-temperature polysilicon (LTPS).

[0241] The gate electrode PGE1 of the first sensor transistor PT1 may be electrically connected to the sensor electrode PE of the light receiving element PD through the first sensor node electrode NSE1, the second sensor node electrode NSE2, and the third sensor node electrode NSE3. The first sensor node electrode NSE1 may be located in the first source metal layer SDL1 and may be connected to the gate electrode PGE1 of the first sensor transistor PT1. The second sensor node electrode NSE2 may be located in the second source metal layer SDL2 and may be connected to the first sensor node electrode NSE1. The third sensor node electrode NSE3 may be located in the third source metal layer SDL3 and electrically connect the second sensor node electrode NSE2 and the sensor electrode PE. The first sensor node electrode NSE1, the second sensor node electrode NSE2, and the third sensor node electrode NSE3 may correspond to Figure 10 The gate electrode PGE1 of the first sensor transistor PT1 may be electrically connected to the first electrode PDE2 of the second sensor transistor PT2 located in the second active layer ACTL2 through the first sensor node electrode NSE1.

[0242] The first electrode PSE1 of the first sensor transistor PT1 may be electrically connected to the readout line ROL through the third sensor transistor PT3. The first electrode PSE1 of the first sensor transistor PT1 may be connected to the second electrode PDE3-2 of the third-second sensor transistor PT3-2. The second electrode PDE1 of the first sensor transistor PT1 may be connected to the second portion VIL2b of the second initialization voltage line VIL2.

[0243] The second sensor transistor PT2 may include a semiconductor region PACT2, a gate electrode PGE2, a first electrode PDE2, and a second electrode PSE2. The semiconductor region PACT2, the first electrode PDE2, and the second electrode PSE2 of the second sensor transistor PT2 may be located in the second active layer ACTL2, and the gate electrode PGE2 of the second sensor transistor PT2 may be located in the third gate layer GTL3. The gate electrode PGE2 of the second sensor transistor PT2 may receive a reset signal from a reset signal line GRL of the third gate layer GTL3 and may overlap with the semiconductor region PACT2 of the second sensor transistor PT2. For example, the semiconductor region PACT2 of the second sensor transistor PT2 may include an oxide-based material.

[0244] The second light blocking layer BML2 may be located in the second gate layer GTL2 and may overlap the second sensor transistor PT2 and the reset signal line GRL. The second light blocking layer BML2 may block light incident from a lower portion of the second sensor transistor PT2.

[0245] A first electrode PDE2 of the second sensor transistor PT2 may be electrically connected to the gate electrode PGE1 of the first sensor transistor PT1 via the first sensor node electrode NSE1. The first electrode PDE2 of the second sensor transistor PT2 may be electrically connected to the sensor electrode PE of the light receiving element PD via the first sensor node electrode NSE1, the second sensor node electrode NSE2, and the third sensor node electrode NSE3. A second electrode PSE2 of the second sensor transistor PT2 may be connected to the first portion VIL1a of the first initialization voltage line VIL1.

[0246] The third sensor transistor PT3 may include a third-first sensor transistor PT3-1 and a third-second sensor transistor PT3-2 connected in series. The third-first sensor transistor PT3-1 may include a semiconductor region PACT3-1, a gate electrode PGE3-1, a first electrode PSE3-1, and a second electrode PDE3-1. The semiconductor region PACT3-1, the first electrode PSE3-1, and the second electrode PDE3-1 of the third-first sensor transistor PT3-1 may be located in the first active layer ACTL1, and the gate electrode PGE3-1 thereof may be located in the first gate layer GTL1. The gate electrode PGE3-1 of the third-first sensor transistor PT3-1 may overlap with the semiconductor region PACT3-1 of the third-first sensor transistor PT3-1. The semiconductor region PACT3-1 of the third-first sensor transistor PT3-1 may include low-temperature polycrystalline silicon (LTPS). The gate electrode PGE3-1 of the third-first sensor transistor PT3-1 may be part of an extension extending from the first gate line GWL in a direction opposite to the Y-axis direction.

[0247] A first electrode PSE3-1 of the third-first sensor transistor PT3-1 may be electrically connected to a readout line ROL of the second source metal layer SDL2 via a readout electrode ROE of the first source metal layer SDL1. The readout line ROL may extend in the Y-axis direction and may provide a sensing signal to the display driver 200. A second electrode PDE3-1 of the third-first sensor transistor PT3-1 may be connected to a first electrode PSE3-2 of the third-second sensor transistor PT3-2.

[0248] The third-second sensor transistor PT3-2 may include a semiconductor region PACT3-2, a gate electrode PGE3-2, a first electrode PSE3-2, and a second electrode PDE3-2. The semiconductor region PACT3-2, the first electrode PSE3-2, and the second electrode PDE3-2 of the third-second sensor transistor PT3-2 may be located in the first active layer ACTL1, and the gate electrode PGE3-2 thereof may be located in the first gate layer GTL1. The gate electrode PGE3-2 of the third-second sensor transistor PT3-2 may overlap with the semiconductor region PACT3-2 of the third-second sensor transistor PT3-2. The semiconductor region PACT3-2 of the third-second sensor transistor PT3-2 may include low-temperature polycrystalline silicon (LTPS). The gate electrode PGE3-2 of the third-second sensor transistor PT3-2 may be part of the first gate line GWL. The second electrode PDE3-2 of the third-second sensor transistor PT3-2 may be connected to the first electrode PSE1 of the first sensor transistor PT1.

[0249] exist Figure 24In the embodiment, the display panel 100 may include a substrate SUB, a metal layer MTL, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a second gate layer GTL2, a first interlayer insulating layer ILD1, a second active layer ACTL2, a third gate insulating layer GI3, a third gate layer GTL3, a second interlayer insulating layer ILD2, a first source metal layer SDL1, a first passivation layer PAS1, a second source metal layer SDL2, a second passivation layer PAS2, a third source metal layer SDL3, a third passivation layer PAS3, a planarization layer OC, a pixel defining layer PDL, a light receiving element PD and an encapsulation layer TFEL.

[0250] The pixel defining layer PDL may be located on the planarization layer OC. The pixel defining layer PDL may define the sensor area PDA. The pixel defining layer PDL may include an organic insulating material such as polyimide (PI).

[0251] The light receiving element PD may be located on the planarization layer OC. The light receiving element PD of each of the plurality of fingerprint sensors OPD may include a sensor electrode PE, a light receiving layer RCL, and a common electrode CAT. The sensor electrode PE may be located on the planarization layer OC and may be located in the same layer as the pixel electrode AE ​​of the pixel SP. The sensor electrode PE may overlap one of the plurality of sensor areas PDA defined by the pixel defining layer PDL.

[0252] The light receiving layer RCL may be located on the sensor electrode PE. When a user's finger touches the display panel 100, the light receiving layer RCL may receive light reflected by the ridges or valleys of the finger. Light output from the light emitting element ED may be reflected by the ridges or valleys of the finger, and the reflected light may reach the light receiving layer RCL. The light receiving element PD may convert the energy of the light into an electrical signal (current or voltage) formed between the sensor electrode PE and the common electrode CAT, and the converted electrical signal may flow from the light receiving element PD to the sensor node NS as a reverse bias current. For example, when the light receiving element PD receives light and an electric field is formed between the common electrode CAT of the light receiving element PD and the sensor electrode PE, a current may flow through the light receiving element PD in proportion to the amount of light, and the voltage at the sensor node NS may increase. Therefore, when the light receiving element PD receives light, the voltage at the sensor node NS may increase, and the magnitude of the sensed current (or source-drain current) of the first sensor transistor PT1 may decrease. The sensed current of the first sensor transistor PT1 may be applied to the display driver 200 as a sense signal via the third sensor transistor PT3 and the readout line ROL.

[0253] The common electrode CAT may be located on the light receiving layer RCL. For example, the common electrode CAT may be implemented as an electrode common to all fingerprint sensors OPD, rather than being dedicated to each of the fingerprint sensors OPD. The common electrode CAT may be located on the light receiving layer RCL in the plurality of sensor areas PDA, and may be located on the pixel defining layer PDL in areas other than the plurality of sensor areas PDA.

[0254] Figure 25 is a plan view showing a pixel circuit, a sensor circuit, a pixel electrode, an anode connection electrode, a sensor electrode, and a sensor connection electrode of a display device according to one or more other embodiments, and Figure 26 It shows Figure 25 Cross-sectional view of the sensor electrode and sensor connection electrode. Figure 25 and Figure 26 Display devices and Figure 8 The display device of is different in configurations of the anode connection electrode and the sensor connection electrode, so that the same configurations as those described above will be briefly described or omitted.

[0255] refer to Figure 25 and Figure 26 The four unit pixels UP may correspond to the eleventh pixel circuit PC11, the twelfth pixel circuit PC12, the thirteenth pixel circuit PC13, the fourteenth pixel circuit PC14, the fifteenth pixel circuit PC15, the sixteenth pixel circuit PC16, the seventeenth pixel circuit PC17, and the eighteenth pixel circuit PC18, and the twenty-first pixel circuit PC21, the twenty-second pixel circuit PC22, the twenty-third pixel circuit PC23, the twenty-fourth pixel circuit PC24, the twenty-fifth pixel circuit PC25, the twenty-sixth pixel circuit PC26, the twenty-seventh pixel circuit PC27, and the twenty-eighth pixel circuit PC28. The two fingerprint sensors OPD may correspond to the eleventh sensor circuit SC11 and the twenty-first sensor circuit SC21.

[0256] The eleventh pixel circuit PC11 can be electrically connected to the first pixel electrode AE1 located in the first pixel row PRW1 and the first pixel column PCL01 via the first anode connection electrode ANE1. The first anode connection electrode ANE1 can be located in an auxiliary metal layer between the first pixel electrode AE1 and the eleventh pixel circuit PC11. The auxiliary metal layer can be located on the third passivation layer PAS3. The auxiliary metal layer may include a transparent conductive material and can transmit light. For example, the auxiliary metal layer may include an electrode or line located in a transmissive portion of the display panel 100 that overlaps with the camera or sensor.

[0257] The twelfth pixel circuit PC12 may be electrically connected to the second pixel electrode AE2 located in the first pixel row PRW1 and the second pixel column PCL02 through the second anode connection electrode ANE2. The second anode connection electrode ANE2 may be located in the auxiliary metal layer between the second pixel electrode AE2 and the twelfth pixel circuit PC12.

[0258] The thirteenth pixel circuit PC13 may be electrically connected to the third pixel electrode AE3 located in the first pixel row PRW1 and the third pixel column PCL03 through the third anode connection electrode ANE3. The third anode connection electrode ANE3 may be located in the auxiliary metal layer between the third pixel electrode AE3 and the thirteenth pixel circuit PC13.

[0259] The eleventh sensor circuit SC11 may be electrically connected to the sensor electrode PE located in the first pixel row PRW1 and the second pixel column PCL02 through a sensor connection electrode PNE. The sensor connection electrode PNE may be located in an auxiliary metal layer between the sensor electrode PE and the eleventh sensor circuit SC11.

Claims

1. Display devices, including: A first-first pixel circuit, a first-second pixel circuit, a first-third pixel circuit, and a first sensor circuit are sequentially arranged in a first circuit row; A second-first pixel circuit, a second-second pixel circuit, a second-third pixel circuit, and a second sensor circuit are sequentially arranged in a second circuit row following the first circuit row; a third-first pixel circuit, a third-second pixel circuit, a third-third pixel circuit, and a third sensor circuit, sequentially arranged in a third circuit row following the second circuit row; a first-first pixel electrode in a first pixel row corresponding to the first circuit row and electrically connected to the first-first pixel circuit; a first sensor electrode in the first row of pixels and electrically connected to the first sensor circuit; a second sensor electrode in the first row of pixels and electrically connected to the second sensor circuit; a second-first pixel electrode in a second pixel row corresponding to the second circuit row and electrically connected to the second-first pixel circuit; as well as The third sensor electrode is in a third pixel row corresponding to the third circuit row and is electrically connected to the third sensor circuit.

2. The display device according to claim 1, wherein the second sensor electrode is spaced apart from the first sensor electrode in a first direction, and The third sensor electrode is spaced apart from the first sensor electrode in a second direction intersecting with the first direction.

3. The display device according to claim 2, wherein A gap between the first sensor electrode and the second sensor electrode is equal to a gap between the first sensor electrode and the third sensor electrode.

4. The display device according to claim 2, further comprising: a fourth-first pixel circuit, a fourth-second pixel circuit, a fourth-third pixel circuit, and a fourth sensor circuit, arranged in a fourth circuit row following the third circuit row; as well as A fourth sensor electrode is in the third pixel row and is electrically connected to the fourth sensor circuit.

5. The display device according to claim 4, wherein The fourth sensor electrode is spaced apart from the third sensor electrode in the first direction, and is spaced apart from the second sensor electrode in the second direction. The display device according to claim 4 , wherein: A gap between the third sensor electrode and the fourth sensor electrode is equal to a gap between the second sensor electrode and the fourth sensor electrode. 7 . The display device according to claim 1 , further comprising a sensor connection electrode electrically connecting the first sensor circuit to the first sensor electrode.

8. The display device according to claim 7, wherein The first-third pixel circuit is between the first-first pixel electrode and the first sensor circuit, and The sensor connection electrode overlaps with the first to third pixel circuits.

9. The display device according to claim 7, wherein The sensor connection electrode is integrated in the same layer as the first sensor electrode.

10. The display device according to claim 7, wherein The sensor connection electrode is in a layer between the first sensor circuit and the first sensor electrode.

11. The display device according to claim 1, wherein A width of each of the first-first pixel circuit, the first-second pixel circuit, and the first-third pixel circuit in the first direction is greater than a width of the first sensor circuit in the first direction.

12. The display device according to claim 1, wherein The first-first pixel circuit includes: a first transistor, configured to control a driving current provided to the first-first pixel electrode; a second transistor, configured to provide a data voltage to the first electrode of the first transistor; a third transistor for electrically connecting the second electrode of the first transistor to the gate electrode of the first transistor; and a fourth transistor, configured to provide an initialization voltage to the gate electrode of the first transistor, wherein the first transistor and the second transistor include silicon-based semiconductor regions, and The third transistor and the fourth transistor include oxide-based semiconductor regions.

13. The display device according to claim 1, wherein The first sensor circuit comprises: a first sensor transistor comprising a gate electrode electrically connected to the first sensor electrode; a second sensor transistor that supplies an initialization voltage to the gate electrode of the first sensor transistor; and a third sensor transistor electrically connecting the first sensor transistor to a readout line, wherein the first sensor transistor and the third sensor transistor include silicon-based semiconductor regions, and The second sensor transistor includes an oxide-based semiconductor region.

14. Display devices, including: A first-first pixel circuit, a first-second pixel circuit, a first-third pixel circuit, a first-fourth pixel circuit, and a first sensor circuit are sequentially arranged in a first circuit row; A second-first pixel circuit, a second-second pixel circuit, a second-third pixel circuit, a second-fourth pixel circuit, and a second sensor circuit are sequentially arranged in a second circuit row following the first circuit row; a first-first pixel electrode in a first pixel row corresponding to the first circuit row and electrically connected to the first-first pixel circuit; first-second pixel electrodes in the first pixel row and electrically connected to the first-second pixel circuits; first to third pixel electrodes in the first pixel row and electrically connected to the first to third pixel circuits; a first sensor electrode in the first row of pixels and electrically connected to the first sensor circuit; as well as A second sensor electrode is in the first pixel row and is electrically connected to the second sensor circuit.

15. The display device according to claim 14, wherein The first sensor electrode is at least partially surrounded by the first-first pixel electrode, the first-second pixel electrode, and the first-third pixel electrode.

16. The display device according to claim 14, further comprising: a second-first pixel electrode in a second pixel row corresponding to the second circuit row and electrically connected to the second-first pixel circuit; a second-second pixel electrode in the second pixel row and electrically connected to the second-second pixel circuit; as well as The second-third pixel electrodes are in the second pixel row and are electrically connected to the second-third pixel circuits.

17. The display device according to claim 14, wherein: The first sensor electrode and the second sensor electrode overlap with the first circuit row and do not overlap with the second circuit row.

18. The display device according to claim 14, further comprising: a third-first pixel circuit, a third-second pixel circuit, a third-third pixel circuit, a third-fourth pixel circuit, and a third sensor circuit, which are sequentially arranged in a third circuit row following the second circuit row; a fourth-first pixel circuit, a fourth-second pixel circuit, a fourth-third pixel circuit, a fourth-fourth pixel circuit, and a fourth sensor circuit, which are sequentially arranged in a fourth circuit row following the third circuit row; a third sensor electrode in a third pixel row corresponding to the third circuit row and electrically connected to the third sensor circuit; as well as A fourth sensor electrode is in the third pixel row and is electrically connected to the fourth sensor circuit.

19. The display device according to claim 18, wherein The third sensor electrode and the fourth sensor electrode overlap with the third circuit row and do not overlap with the fourth circuit row.

20. The display device according to claim 18, wherein A gap between the first sensor electrode and the second sensor electrode is equal to a gap between the first sensor electrode and the third sensor electrode.

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