Row and column driving circuit system applied to digital driving micro display

Abstract

The invention relates to a row and column driving circuit system applied to a digital driving micro display. In the circuit system, a pixel array of a micro-display is divided into two or four pixel arrays, and each pixel array is respectively provided with a row driver and a column driver, so that the driving control of the micro-display is realized; the triggers in each row drive and each column drive are all fully static clock drive triggers. Compared with the prior art, the driving circuit has the advantages of reducing power consumption, improving driving stability and reliability and the like.

Description

Technical Field

[0001] The present invention relates to a row and column driving circuit, in particular to a row and column driving circuit system applied to a digital drive micro display. Background Art

[0002] Currently, with the development of display technology, VR / AR technology is gradually becoming a hot topic in the future. In recent years, in order to adapt to the needs of near-eye display, the performance parameters of display devices have increased rapidly, such as resolution, refresh rate, grayscale, etc. Traditional display driving methods all use analog driving methods, and the row and column driving circuits are also designed for analog driving methods. In order to meet high resolution, the circuit needs to add more triggers, which makes the wires too long during the layout drawing process. In order to achieve higher grayscale, a higher-bit digital-to-analog converter circuit (DAC) has to be used to control the pixel circuit.

[0003] In order to achieve grayscale display of pixels, traditional row and column drive circuits require DAC circuits, and the circuit structure is too complex; high-performance displays have too many pixels, and direct control leads to long layout and wiring, increasing transmission delays; and the high-bit DAC speed is too slow to meet the refresh rate requirements.

[0004] For example, patent publication CN102622965A discloses a silicon-based microdisplay driver circuit, in which a row driver generates the strobe signals required by the pixel driver circuit array, and a column driver generates the data signals required by the pixel driver circuit array. This driver circuit can be modularized, simplifying the design process; however, achieving high resolution requires an increased number of driver triggers, resulting in excessive power consumption.

[0005] In summary, the current row and column driving circuit system is heavy, and in order to achieve high resolution, the power consumption is too high; and in low-power scenarios, the existing driving circuit is difficult to achieve long-term stable display of the display device, and there are insufficient driving stability and reliability. Summary of the Invention

[0006] The purpose of the present invention is to overcome the defects of the prior art and provide a row and column driving circuit system for a digitally driven micro display.

[0007] The purpose of the present invention can be achieved by the following technical solutions:

[0008] According to one aspect of the present invention, a row and column driving circuit system for a digitally driven microdisplay is provided, in which the pixel array of the microdisplay is divided into two or four pixel arrays, and each pixel array is respectively configured with a row driver and a column driver, thereby realizing the drive control of the microdisplay; the triggers in each row driver and each column driver use a fully static clock drive trigger.

[0009] As a preferred technical solution, the column driving circuit includes a primary circuit, a secondary circuit and a tertiary circuit;

[0010] The first-level circuit is a column serial shift enable circuit, which includes a buffer and a shift register. The shift chain in the shift register consists of 32 edge-triggered D flip-flops, which shift on the rising edge of the shift clock signal to generate the latch clock signal of the flip-flop array.

[0011] The secondary circuit is a flip-flop array that uses a 240-bit data bus for parallel input and latches 32 sets of 240-bit data on the rising edge of the shift register output signal.

[0012] The three-stage circuit is a data latch circuit, including a trigger array and a buffer. When the second-stage circuit inputs a row of pixel data, the third-stage circuit generates a first enable signal to latch the data on all column data registers into the D trigger. The Q and inverted Q outputs of the D trigger drive the bit line and inverted bit line respectively through the buffer.

[0013] The input signals of the column driver include: COL_START, SCLKN, RSTN, DATA[239:0], G1, LRN and LSN[2:0], which are respectively the shift start signal, the low-level effective shift clock signal, the low-level effective reset signal, the 240-bit parallel data input signal, the first enable signal, the low-level effective clear signal and the low-level effective set signal of the 3-bit bus; the shift start signal is input by the clear terminal of the column serial shift circuit trigger; in the column driver, when LRN is 0, the bit line is set to 0; when the 3-bit LSN are all 0, the circuit enters the full-screen test mode and sets the RGB pixel data in the latch to 1; during normal display, LSN needs to be connected to the high level 1, and LSN has a higher priority than LRN; RSTN is the global reset signal, which sets the shift register data to 0.

[0014] As a preferred technical solution, the row driver is used to decode the address line into a row signal WL. The row driver circuit includes a shift register, a trigger, a decoder, a WOE register and a buffer.

[0015] The input signals of the row driver include: RD[1:0], SCLK, RSTN, G2, WOE and HSN; respectively, they are the row address input signal, serial clock signal, reset signal, second enable signal, write enable signal and high level selection signal;

[0016] The working process of the row driver circuit is divided into a decoding process and a driving process; its specific working process includes: the unused 2 bits of the control signal differential pair CTP or CTN are used to generate 11-bit row address data through a shift register; the row address signal is latched to the row latch through the G2 signal, and G2 is a rising edge sensitive signal; after three-level decoding, 1280 decoded row signals RN[1279:0] are output, and a valid row write signal is output when WOE is high; the HSN signals of all rows are connected together, and when HSN is low, the WL signals of all rows are set to 1, at this time all rows are turned on; when HSN is high, the circuit works normally; RSTN is a global reset signal, which is connected to the column reset signal to set all row address registers to 0; RD[1:0] generates 11-bit row address data through 6 SCLK shift registers, where RD[1] is filled with the odd bits of the address data RD_DATA in sequence through shift register, and RD[0] is filled with the even bits of the address data RD_DATA in sequence through shift register.

[0017] As a preferred technical solution, the fully static clock driven trigger includes a master latch and a slave latch.

[0018] As a preferred technical solution, the master latch is composed of six NMOS transistors N1-N6 and six PMOS transistors P1-P6. P1 and N1 form an inverter structure, which is used to convert the input signal D into an inverted signal DN.

[0019] The structure of the master latch is specifically as follows: the input signal D is connected to the gates of N4 and P3; the inverted signal DN is connected to the gates of N5 and P6; the transistors N2, N3, P4, and P5 form a latch structure in which the inverters are connected end to end, wherein the sources of P4 and P5 are connected to the power supply; the sources of N2 and N3 are connected to the drains of N4 and N5 respectively; the drains of N2 and N3 are grounded; the gate of transistor N6 is connected to the clock, and the source and drain of N6 are connected to the sources of N2 and N3 respectively; the gate of transistor P2 is connected to the clock, the source of P2 is connected to the power supply voltage, and the drain of P2 is connected to the sources of P3 and P6; the drain of P3 is connected to N2 and P4, forming the output of the inverter structure, and the drain of P6 is connected to N3 and P5, forming the output of the inverter structure; in the latch structure of the master latch, the node on the side of P5 and N3 is selected as the node E; the node on the side of P4 and N2 is selected as the node EN; and virtual ground lines VS1 and VS2 are set at N2 and N3 respectively;

[0020] The slave latch is composed of six NMOS transistors N7-N12 and six PMOS transistors P7-P12; the structure of the slave latch is a complementary symmetrical structure of the master latch structure; transistors N8, N9, P10, and P11 form a latch structure in which inverters are connected end to end; in the latch structure of the slave latch, the nodes on the P10 and N8 sides are selected as node F; the nodes on the P11 and N9 sides are selected as node FN; and virtual power lines VD1 and VD2 are set at P7 and P9 respectively.

[0021] As a preferred technical solution, when the input signal D flips from 0 to 1 at CLK=0, the working process of the fully static clock-driven trigger includes:

[0022] Before D flips, in the master latch, node E is connected to GND through N3 and N5, and node EN is connected to VDD through P2 and P3;

[0023] After D flips, in the master latch, P3 is turned off, P6 is turned on, E is charged to VDD through P2 and P6, and node EN is discharged to GND through the feedback circuit N2 and N4;

[0024] During the entire low-level period of the clock in this process, in the slave latch, P8 is turned on. Regardless of whether P7 or P9 is turned on, the balancing transistor P8 maintains the voltages at VD1 and VD2 at the voltage of VDD; thus, node F is maintained at a low level through N8, and node FN is maintained at a high level through P11.

[0025] When the rising edge of CLK arrives, P2 and P8 are turned off, and N6 and N11 are turned on. At this time, no matter whether N4 or N5 is in the on state, N6 keeps the voltage at VS1 and VS2 at 0V, so that node EN is maintained at a low level through N2, and node E is maintained at a high level through P5; P2 is turned off, and new data flips cannot be written to the main internal nodes through P3; the high level E will turn on the N10 node and turn off the P9 node, so that the node FN can be discharged to GND without competition, and then P10 and P12 are turned on, and the node F is charged to VDD through P7 and P10, and Q is charged to VDD through P12.

[0026] As a preferred technical solution, when the input signal D remains at logic 1 in the next preset clock cycle, the working process of the fully static clock-driven trigger is as follows:

[0027] When CLK=0, in the master latch, node EN is maintained at a low level through N2 and N4, and node E is maintained at a high level through P5 and P2 and P6. In the slave latch, node F is maintained at a high level through P7 and P10, and node FN is maintained at a low level through N9.

[0028] When CLK=1, in the master latch, node EN is maintained at a low level through N2 and N4, and node E is maintained at a high level through P5. In the slave latch, node F is maintained at a high level through P7 and P10, and node FN is maintained at a low level through N9, N10, and N11. When D remains unchanged, there is no redundant charging, discharging or floating of the internal nodes.

[0029] As a preferred technical solution, when the input signal D flips from 1 to 0 at CLK=0, the working process of the fully static clock-driven trigger is:

[0030] Before D flips, in the master latch, node E is maintained at a high level through P5, P2, and P6, while node EN is maintained at a low level through N2 and N4;

[0031] After D flips, in the master latch, P6 is turned off, P3 is turned on, node EN is charged to VDD through P2 and P3, and then N3 is turned on, and node E is discharged to 0V through N3 and N5;

[0032] During the entire low clock period in this process, in the slave latch, node F is connected to the virtual power line VD1 through P10, and node FN is connected to GND through N9.

[0033] When the rising edge of CLK arrives, in the master latch, node E is connected to VS2 through N3, and node EN is maintained at a high level through P4. Since P2 is turned off, the new data will not affect node E or EN; in the slave latch, P7 is turned off, P9 is turned on, node F is discharged to 0V through N7 and N11, and node N of F is charged to VDD through P9 and P11, and then N12 is turned on, and the low-level logic is written to Q.

[0034] As a preferred technical solution, when the input signal D remains at logic 1 in the next preset clock cycle, the working process of the fully static clock-driven trigger is as follows:

[0035] When CLK=0, in the master latch, node E is maintained at a low level through N3 and N5, while node EN is maintained at a high level through P4 and P2 and P3; in the slave latch, node F is maintained at a low level through N8, and node FN is connected to VDD through P9 and P11.

[0036] When CLK=1, in the master latch, node E is connected to the virtual ground through N3, and node EN is maintained at VDD through P4. In the slave latch, node F is maintained at 0V through N8, N7, and N11, and node FN is connected to VDD through P9 and P11. Internal nodes have a DC path to VDD or GND at any time, and there is no redundant charging and discharging.

[0037] As a preferred technical solution, when the row and column drive circuit system is working, the timing needs to meet the preset timing requirements: the CLK and DATA signals in the external input signal of the interface have a 90° phase difference, and the rising edge of SCLK only samples the even bits of the DATA signal. If an odd bit is mistakenly sampled, the external CLK signal is inverted.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] 1. In the present invention, the triggers in each row driver and each column driver use a fully static clock to drive the trigger, avoiding leakage and timing drift, solving the power consumption problem caused by too many triggers, and significantly reducing power consumption. In low-power scenarios (such as wearable device micro-displays), it ensures long-term stable display and improves driving stability and reliability.

[0040] 2. In the present invention, the pixel array is split, each equipped with row and column drivers, adapted to high-resolution micro-displays; the split-screen drive method reduces the problem of excessively long drive lines and heavy loads; and because a digital drive method is adopted, the circuit is simplified, and no DAC is required to convert digital quantities into analog quantities, saving the area cost of the circuit.

[0041] 3. In the present invention, the column drive circuit includes a first-level circuit, a second-level circuit and a third-level circuit; the first-level column serial shift circuit is synchronized with the clock through a 32-level D flip-flop, accurately controls the data shift rhythm, and adapts to high-speed serial input; the second-level 240-bit parallel latch breaks through the serial transmission bottleneck and meets the large data throughput of high-resolution micro-displays; the third-level latch and buffer output realizes seamless connection from data latch to drive, ensures the stability of the bit line drive current, solves the problem of uneven brightness of pixels at the edge of the micro-display panel, and improves display uniformity; and through the grouped shift input of the three-level circuit, it solves the problem of insufficient speed under large data volume, and meets the driving requirements when facing large data volume under high-resolution conditions.

[0042] 4. In the present invention, when the input signal D flips from 0 to 1 at CLK=0, the charging process of node E and the discharging process of EN in the master latch accurately match the clock timing to ensure that the data is stably latched at the clock edge; the slave latch maintains the power supply level through the balance tube (P8) to avoid glitch interference during clock switching and ensure that the row or column drive signal of the micro display panel is clean.

[0043] 5. In the present invention, when the input signal D remains in the logic 1 state in the next preset clock cycle, the master-slave latch nodes are charged and discharged without redundant power consumption, thereby reducing dynamic power consumption; and the DC path ensures the stability of the electrical level, avoiding the noise introduced by floating nodes, thereby improving the purity of the dark state image in low-brightness display scenarios.

[0044] 6. In the present invention, when the input signal D flips from 1 to 0 at CLK=0, the master latch turns off P6 and turns on P3 to achieve low-noise switching of data reverse latching, which is suitable for high-contrast switching of micro-display images; the slave latch ensures that the output Q accurately follows the data flip through the discharge link of node F and the charging link of node FN, solving the problem of asynchronous row or column drive of traditional triggers.

[0045] 7. In the present invention, when the input signal D remains in the logic 0 state in the next preset clock cycle, it is always connected to VDD / GND through the internal node, eliminating the risk of floating and avoiding display abnormalities caused by electromagnetic interference in high-reliability scenarios; and there is no redundant charging and discharging design, which is suitable for high-frequency refresh micro-displays and extends the service life of the circuit.

[0046] 8. In the present invention, the 90° phase difference between CLK and DATA and the SCLK sampling bit rule are used to enforce external signal synchronization constraints and resolve timing conflicts during collaborative driving of multiple chips. Through the external CLK inversion mechanism, the timing deviations of different data sources are compatible, and diversified image inputs are adapted, thereby improving system-level compatibility and simplifying terminal device design. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Schematic diagram of the overall structure of the row and column circuit of the present invention;

[0048] Figure 2 is a schematic diagram of a column driving circuit in the present invention;

[0049] Figure 3 is a schematic diagram of a row driving circuit in the present invention;

[0050] Figure 4a A circuit diagram of a master latch in a fully static clock-driven flip-flop in the present invention;

[0051] Figure 4b A circuit diagram of a slave latch in a fully static clock-driven flip-flop in the present invention;

[0052] Figure 5a Schematic diagram of the working state of the fully static clock-driven trigger when CLK is 0 and D is 1 in the present invention;

[0053] Figure 5b Schematic diagram of the working state of the fully static clock-driven trigger when CLK is 1 and D is 1 in the present invention;

[0054] Figure 5c Schematic diagram of the working state of the fully static clock-driven trigger when CLK is 0 and D is 0 in the present invention;

[0055] Figure 5dSchematic diagram of the working state of the fully static clock-driven trigger when CLK is 1 and D is 0 in the present invention;

[0056] Figure 6 This is a signal timing diagram that meets the preset timing requirements in the present invention. DETAILED DESCRIPTION

[0057] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0058] Example 1

[0059] In this embodiment, a row and column driving circuit system for digitally driving a micro display is used, such as Figure 1 As shown, in the circuit system, the pixel array of the micro display is divided into two pixel arrays, pixel array_A and pixel array_B;

[0060] The system also includes row drive circuits and column drive circuits. The row and column drive circuits are divided into two groups, namely row drive_A, row drive_B, column drive_A, and column drive_B. Row drive_A and column drive_A control pixel array_A; row drive_B and column drive_B control pixel array_B, thereby realizing the drive control of the micro display; the triggers in each row drive and each column drive use a fully static clock to drive the trigger.

[0061] In this embodiment, each pixel array includes 2560*3 (RGB)*1280 pixel units.

[0062] The structure of a single row driver circuit is as follows Figure 2 As shown in Figure 1, the column driver circuit input signals include COL_START, SCLKN, RSTN, DATA[239:0], G1, LRN, and LSN[2:0]. The column driver circuit is divided into three stages:

[0063] The first stage is the column serial shift enable circuit. The shift chain consists of 32 EDFFs, which shift on the rising edge of the SCLK signal to generate the latch clock signal for the flip-flop (DFF) array. COL_START is the shift start signal, connected to the clear terminal of the column serial shift circuit flip-flop;

[0064] The second stage is a flip-flop array, which uses a 240-bit data bus for parallel input and latches 32 groups of 240-bit data on the rising edge of the 32 shift register outputs;

[0065] The third stage is the data latch circuit. When the flip-flop array is ready for a row of pixel data, G1 (rising edge active) is generated, latching the data in all column data registers into the DFF. The Q and QN outputs of the DFF drive the BN / BLN lines, respectively, through a buffer. LRN is the DFF clear signal. When LRN is low, BL is set to "0" for fast clearing. When LSN[2:0] is "0," the RGB pixel data in the data latch DFF can be set to "1" for full-screen testing. For normal display, LSN must be connected to a high level "1" and has priority over LRN. RSTN is the global reset signal, setting the shift register data to "0."

[0066] The structure diagram of a single row driver circuit is as follows Figure 3 As shown. The function of the row driver circuit is to decode the address line into the row signal WL. The row driver circuit works in two steps: decoding and driving. Decoding: The display resolution is 2560*(3)*2560, and it is driven by two sets of identical row driver circuits, each with 211 row addresses. The unused 2 bits of the control signal differential pair CTP / CTN generate 11-bit row address data through the shift register; the row address signal is latched into the row latch through the G2 signal, and G2 is a rising edge sensitive signal. After three levels of decoding, 1280 decoded row signals RN[1279:0] are output. When WOE is high, a valid row write signal is output. The HSN signals of all rows are connected together. When HSN is low, the WL signals of all rows are set to "1", turning on all rows; when HSN is high, the circuit works normally. RSTN is the global reset signal, which is connected to the column reset signal and sets all row address registers to "0". RD[1:0] generates 11-bit row address data after 6 SCLK shift registers. RD[1] generates the (11 / 9 / 7 / 5 / 3 / 1)-bit address signal of RD_DATA[12:0], and RD[0] generates the (10 / 8 / 6 / 4 / 2 / 0)-bit address signal of RD_DATA[12:0].

[0067] The system's internal triggers and registers all use fully static clock-driven triggers to reduce power consumption. The fully static clock-driven trigger structure is as follows: Figure 4a and 4b As shown. The low power trigger is divided into a master latch and a slave latch. The master latch is as shown Figure 4aAs shown, it consists of 6 NMOS transistors and 6 PMOS transistors. P1 and N1 form an inverter structure to convert the input signal D into an inverted signal DN. The input signal D is connected to the gates of N4 and P3. DN is connected to the gates of N5 and P6. Transistors N2, N3, P4, and P5 form a latch structure in which the inverters are connected end to end, where the sources of P4 and P5 are connected to the power supply. The sources of N2 and N3 are connected to the drains of N4 and N5 respectively. The drains of N2 and N3 are grounded. The gate of transistor N6 is connected to the clock, and the source and drain are connected to the sources of N2 and N3 respectively. The gate of transistor P2 is connected to the clock, the source is connected to the power supply voltage, and the drain is connected to the sources of P3 and P6. The drain of P3 is connected to N2 and P4 to form the output of the inverter structure, and the drain of P6 is connected to N3 and P5 to form the output of the inverting structure. From the latch structure as shown Figure 4b As shown, it is a complementary symmetrical structure of the main latch structure, which is detailed in the figure and will not be described in detail here.

[0068] The working state and principle of the low-power trigger are shown in Figure 5. The details are as follows:

[0069] If D flips from 0 to 1 when CLK=0:

[0070] Before D flips, the main stage status is as follows Figure 5c As shown, node E is connected to GND through N3 and N5, and node EN is connected to VDD through P2 and P3;

[0071] After D flips, the main stage status is as follows Figure 5a As shown in FIG, P3 is turned off, P6 is turned on, E is charged to VDD through P2 and P6, and EN is discharged to GND through the feedback circuit N2 and N4.

[0072] During the entire low clock period, the slave status is as follows: Figure 5a As shown, P8 is turned on. Regardless of whether P7 or P9 is turned on, the balancing transistor P8 keeps VD1 and VD2 at the voltage of VDD. Therefore, node F is maintained at a low level through N8, and node FN is maintained at a high level through P11.

[0073] When the CLK rising edge arrives, P2 and P8 are turned off, and N6 and N11 are turned on. At this time, the switching state of the transistors in the trigger is as follows: Figure 5b As shown in the figure, no matter whether N4 or N5 is in the on state, N6 keeps VS1 and VS2 at 0V, so EN is maintained at a low level through N2, and E is maintained at a high level through P5. P2 is turned off, and new data flips cannot be written to the main internal nodes through P3; the high level E will open the N10 node and close the P9 node, so FN can be discharged to GND without competition, and then P10 and P12 are opened, F is charged to VDD through P7 and P10, and Q is charged to VDD through P12.

[0074] It can be seen that there is no competing current during the flipping process, and there are no more than three stacking paths.

[0075] If D remains at logic 1 for the next clock cycle:

[0076] When CLK=0, the main stage will Figure 5a As shown, the slave level Figure 5b That is, the master node EN is maintained at a low level through N2 and N4, the node E is maintained at a high level through P5, P2 and P6, while the slave node F is maintained at a high level through P7 and P10, and the node FN is maintained at a low level through N9.

[0077] When CLK=1, the main circuit state will be as follows Figure 5b As shown, the master's EN is maintained low through N2 and N4, and E is maintained high through P5. The slave's F is maintained high through P7 and P10, and FN is maintained low through N9, N10, and N11. When D remains unchanged, there is no redundant charging or discharging of internal nodes, and no floating.

[0078] If D flips from 1 to 0 when CLK=0:

[0079] Before D flip, the main state is as follows Figure 5a As shown, node E is maintained at a high level through P5, P2, and P6, while node EN is maintained at a low level through N2 and N4;

[0080] After D flips, the main stage status is as follows Figure 5c As shown in the figure, P6 is turned off, P3 is turned on, EN is charged to VDD through P2 and P3, and then N3 is turned on, and E is discharged to 0V through N3 and N5.

[0081] During the entire low clock period, the slave stage Figure 5c As shown, node F is connected to the virtual power line VD1 through P10, and node FN is connected to GND through N9.

[0082] After the rising edge of CLK arrives, the trigger state is as follows Figure 5d As shown, E is connected to the virtual ground VS2 through N3, and EN is maintained at a high point through P4. Since P2 is turned off, the new data will not affect E and EN; in the slave stage, P7 is turned off, P9 is turned on, F is discharged to 0V through N7 and N11, and FN is charged to VDD through P9 and P11, and then N12 is turned on to write the low-level logic to Q.

[0083] Similarly, there is no competition in the data flipping process, and there is no overly long stacked charge and discharge path.

[0084] If D remains at a low level in the next clock cycle:

[0085] When CLK=0, the switching state of the main transistor will be as follows Figure 5d As shown, node E is maintained at a low level through N3 and N5, while node EN is maintained at a high level through P4, P2 and P3;

[0086] At this time, Figure 5c As shown, node F is maintained at a low level through N8, while node FN is connected to VDD through P9 and P11.

[0087] When CLK=1, the switching state of the transistor in the trigger is as follows: Figure 5d As shown, E is connected to virtual ground via N3, EN is maintained at VDD via P4, F is maintained at 0V via N8, N7, and N11, and FN is connected to VDD via P9 and P11. Internal nodes in the SC2FF always have a DC path to VDD or GND, and there is no redundant charging or discharging.

[0088] The entire system needs to meet certain timing requirements when working. To ensure the normal operation of subsequent circuits, the external input signal of the interface must ensure that the CLK and DATA signals have a 90° phase difference, and at the same time, it must ensure that the SCLK rising edge samples the even bits of the DATA signal. If an odd bit is sampled, the external CLK signal needs to be inverted. The normal working timing of the row and column is as follows Figure 6 shown.

[0089] To sum up, in this solution, the triggers in each row driver and each column driver use a fully static clock to drive the trigger, avoiding leakage and timing drift, solving the power consumption problem caused by too many triggers, and significantly reducing power consumption. In low-power scenarios (such as wearable device micro-displays), it ensures long-term stable display and improves driving stability and reliability.

[0090] Example 2

[0091] In this embodiment, a row and column driving circuit system for a digitally driven microdisplay is used. In this circuit system, the pixel array of the microdisplay is divided into four pixel arrays, and each pixel array is respectively configured with a row driver and a column driver, thereby realizing the drive control of the microdisplay; the triggers in each row driver and each column driver use a fully static clock drive trigger.

[0092] The rest of the implementation process is the same as Example 1.

[0093] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A row and column driving circuit system for a digitally driven microdisplay, characterized in that: In this circuit system, the pixel array of the microdisplay is divided into two or four pixel arrays, and each pixel array is respectively configured with a row driver and a column driver, thereby realizing the drive control of the microdisplay; the triggers in each row driver and each column driver are all driven by a fully static clock.

2. The row and column driving circuit system for a digitally driven micro display according to claim 1, characterized in that: The column driving circuit includes a primary circuit, a secondary circuit and a tertiary circuit; The first-level circuit is a column serial shift enable circuit, including a buffer and a shift register. The shift chain in the shift register is composed of 32 edge-triggered D flip-flops, which shift on the rising edge of the shift clock signal to generate a latch clock signal for the flip-flop array; The secondary circuit is a flip-flop array, which uses a 240-bit data bus for parallel input and latches 32 groups of 240-bit data at the rising edge of the output signal of the shift register; The three-stage circuit is a data latch circuit, including a trigger array and a buffer; when the second-stage circuit inputs a row of pixel data, the third-stage circuit generates a first enable signal to latch the data on all column data registers into the D trigger; The Q and inverted Q outputs of the D flip-flop drive the bit line and inverted bit line respectively through the buffer; The column driver input signals include: COL_START, SCLKN, RSTN, DATA[239:0], G1, LRN and LSN[2:0], which are respectively a shift start signal, a low-level effective shift clock signal, a low-level effective reset signal, a 240-bit parallel data input signal, a first enable signal, a low-level effective clear signal and a low-level effective set signal of the 3-bit bus; the shift start signal is input by the clear terminal of the column serial shift circuit trigger; in the column driver, when LRN is 0, the bit line is set to 0; when all 3 LSNs are 0, the circuit enters a full-screen test mode and uniformly sets the RGB pixel data in the latch to 1; during normal display, LSN needs to be connected to a high level 1, and LSN has a higher priority than LRN; RSTN is a global reset signal, which sets the shift register data to 0.

3. The row and column driving circuit system for a digitally driven micro display according to claim 1, characterized in that: The row driver is used to decode the address line into a row signal WL, and the row driver circuit includes a shift register, a trigger, a decoder, a WOE register and a buffer; The input signals of the row driver include: RD[1:0], SCLK, RSTN, G2, WOE and HSN; which are row address input signal, serial clock signal, reset signal, second enable signal, write enable signal and high level selection signal respectively; The working process of the row driver circuit is divided into a decoding process and a driving process; its specific working process includes: the unused 2 bits of the control signal differential pair CTP or CTN are used to generate 11-bit row address data through a shift register; the row address signal is latched to the row latch through the G2 signal, and G2 is a rising edge sensitive signal; after three-level decoding, 1280 decoded row signals RN[1279:0] are output, and a valid row write signal is output when WOE is high; the HSN signals of all rows are connected together, and when HSN is low, the WL signals of all rows are set to 1, at this time all rows are turned on; when HSN is high, the circuit works normally; RSTN is a global reset signal, which is connected to the column reset signal to set all row address registers to 0; RD[1:0] generates 11-bit row address data through 6 SCLK shift registers, where RD[1] is filled with the odd bits of the address data RD_DATA in sequence through shift register, and RD[0] is filled with the even bits of the address data RD_DATA in sequence through shift register.

4. The row and column driving circuit system for a digitally driven micro display according to claim 1, characterized in that: The fully static clock driven trigger comprises a master latch and a slave latch.

5. The row and column driving circuit system for a digitally driven micro display according to claim 4, characterized in that: The master latch is composed of six NMOS transistors N1-N6 and six PMOS transistors P1-P6. P1 and N1 form an inverter structure, which is used to convert the input signal D into an inverted signal DN. The structure of the master latch is as follows: the input signal D is connected to the gates of N4 and P3; the inverted signal DN is connected to the gates of N5 and P6; the transistors N2, N3, P4, and P5 form a latch structure with inverters connected end to end, wherein the sources of P4 and P5 are connected to the power supply; the sources of N2 and N3 are connected to the drains of N4 and N5 respectively; the drains of N2 and N3 are grounded; the gate of transistor N6 is connected to the clock, and the source and drain of N6 are connected to the sources of N2 and N3 respectively; The gate of transistor P2 is connected to the clock, the source of P2 is connected to the power supply voltage, and the drain of P2 is connected to the sources of P3 and P6; the drain of P3 is connected to N2 and P4, forming the output of the inverter structure, and the drain of P6 is connected to N3 and P5, forming the output of the inverter structure; in the latch structure of the master latch, the node on the side of P5 and N3 is selected as the node E; the node on the side of P4 and N2 is selected as the node EN; and virtual ground lines VS1 and VS2 are respectively provided at N2 and N3; The slave latch is composed of six NMOS transistors N7-N12 and six PMOS transistors P7-P12; the structure of the slave latch is a complementary symmetrical structure of the master latch structure; transistors N8, N9, P10, and P11 constitute a latch structure in which inverters are connected end to end; in the latch structure of the slave latch, the nodes on the P10 and N8 sides are selected as node F; the nodes on the P11 and N9 sides are selected as node FN; and virtual power lines VD1 and VD2 are respectively provided at P7 and P9.

6. The row and column driving circuit system for a digitally driven micro display according to claim 5, characterized in that: When the input signal D flips from 0 to 1 at CLK=0, the working process of the fully static clock-driven trigger includes: Before D flips, in the master latch, node E is connected to GND through N3 and N5, and node EN is connected to VDD through P2 and P3; After D flips, in the master latch, P3 is turned off, P6 is turned on, E is charged to VDD through P2 and P6, and node EN is discharged to GND through the feedback circuit N2 and N4; During the entire low-level period of the clock in this process, in the slave latch, P8 is turned on. Regardless of whether P7 or P9 is turned on, the balancing transistor P8 maintains the voltages at VD1 and VD2 at the voltage of VDD; thus, node F is maintained at a low level through N8, and node FN is maintained at a high level through P11. When the rising edge of CLK arrives, P2 and P8 are turned off, and N6 and N11 are turned on. At this time, no matter whether N4 or N5 is in the on state, N6 keeps the voltage at VS1 and VS2 at 0V, so that node EN is maintained at a low level through N2, and node E is maintained at a high level through P5; P2 is turned off, and new data flips cannot be written to the main internal nodes through P3; the high level E will turn on the N10 node and turn off the P9 node, so that the node FN can be discharged to GND without competition, and then P10 and P12 are turned on, and the node F is charged to VDD through P7 and P10, and Q is charged to VDD through P12.

7. The row and column driving circuit system for a digitally driven micro display according to claim 5, characterized in that: When the input signal D remains at logic 1 in the next preset clock cycle, the working process of the fully static clock-driven trigger is as follows: When CLK=0, in the master latch, node EN is maintained at a low level through N2 and N4, and node E is maintained at a high level through P5 and P2 and P6. In the slave latch, node F is maintained at a high level through P7 and P10, and node FN is maintained at a low level through N9. When CLK=1, in the master latch, node EN is maintained at a low level through N2 and N4, and node E is maintained at a high level through P5. In the slave latch, node F is maintained at a high level through P7 and P10, and node FN is maintained at a low level through N9, N10, and N11. When D remains unchanged, there is no redundant charging, discharging or floating of the internal nodes.

8. The row and column driving circuit system for a digitally driven micro display according to claim 5, characterized in that: When the input signal D flips from 1 to 0 at CLK=0, the working process of the fully static clock-driven trigger is as follows: Before D flips, in the master latch, node E is maintained at a high level through P5, P2, and P6, while node EN is maintained at a low level through N2 and N4; After D flips, in the master latch, P6 is turned off, P3 is turned on, node EN is charged to VDD through P2 and P3, and then N3 is turned on, and node E is discharged to 0V through N3 and N5; During the entire low clock period in this process, in the slave latch, node F is connected to the virtual power line VD1 through P10, and node FN is connected to GND through N9; When the rising edge of CLK arrives, in the master latch, node E is connected to VS2 through N3, and node EN is maintained at a high level through P4. Since P2 is turned off, the new data will not affect node E or EN; in the slave latch, P7 is turned off, P9 is turned on, node F is discharged to 0V through N7 and N11, and node N of F is charged to VDD through P9 and P11, and then N12 is turned on, and the low-level logic is written to Q.

9. The row and column driving circuit system for a digitally driven micro display according to claim 5, characterized in that: When the input signal D remains at logic 1 in the next preset clock cycle, the working process of the fully static clock-driven trigger is as follows: When CLK=0, in the master latch, node E is maintained at a low level through N3 and N5, while node EN is maintained at a high level through P4, P2, and P3; in the slave latch, node F is maintained at a low level through N8, and node FN is connected to VDD through P9 and P11; When CLK=1, in the master latch, node E is connected to the virtual ground through N3, and node EN is maintained at VDD through P4. In the slave latch, node F is maintained at 0V through N8, N7, and N11, and node FN is connected to VDD through P9 and P11. Internal nodes have a DC path to VDD or GND at any time, and there is no redundant charging and discharging.

10. The row and column driving circuit system for a digitally driven micro display according to claim 1, characterized in that: When the row and column driving circuit system is working, the timing needs to meet the preset timing requirements: the CLK and DATA signals in the external input signal of the interface have a 90° phase difference, and the rising edge of SCLK only samples the even bits of the DATA signal. If an odd bit is mistakenly sampled, the external CLK signal is inverted.

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