Display panel and display device

Abstract

The invention relates to a display panel and a display device. The area of a channel region of an anode reset transistor of a first sub-pixel is designed to be larger than that of a channel region of an anode reset transistor of a second sub-pixel; the parasitic capacitance of the anode reset transistor of the first sub-pixel is larger than the parasitic capacitance of the anode reset transistor of the second sub-pixel, so that after the anode of the light-emitting element of each sub-pixel is reset, the reset voltage of the anode of the light-emitting element of the anode reset transistor of the first sub-pixel is larger than the reset voltage of the anode of the light-emitting element of the second sub-pixel. The reset voltage is higher than the reset voltage of the anode of the light-emitting element of the anode reset transistor of the second sub-pixel, so that the response time from charging to turning on of the light-emitting element of the first sub-pixel is shortened, the light-emitting brightness of the light-emitting element of the first sub-pixel is improved, the sub-pixels are enabled to be turned on at the same time, and the color cast and smear phenomena are effectively improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, the application of display panels is becoming more and more extensive, and users have higher and higher requirements for the display quality of display panels.

[0003] However, the display panel in the related art has color cast and smear problems, resulting in poor display effects. Summary of the Invention

[0004] Based on this, it is necessary to provide a display panel and a display device that can help improve the color shift and streaking problem and enhance the display effect of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0006] a plurality of sub-pixels, each sub-pixel comprising a pixel circuit and a light-emitting element electrically connected;

[0007] The pixel circuit includes an anode reset transistor, a first electrode of the anode reset transistor is electrically connected to the first reset signal line, and a second electrode of the anode reset transistor is electrically connected to the anode of the light emitting element;

[0008] The plurality of sub-pixels include at least a first sub-pixel and a second sub-pixel, wherein a color of the first sub-pixel is different from a color of the second sub-pixel;

[0009] The area of ​​the channel region of the anode reset transistor of the first sub-pixel is S1, and the area of ​​the channel region of the anode reset transistor of the second sub-pixel is S2, wherein S1>S2.

[0010] In a second aspect, an embodiment of the present application further provides a display device, which includes the display panel provided in the first aspect.

[0011] The above-mentioned display panel and display device are designed to have a channel region area of ​​the anode reset transistor of the first sub-pixel larger than the channel region area of ​​the anode reset transistor of the second sub-pixel, so that the parasitic capacitance of the anode reset transistor of the first sub-pixel is larger than the parasitic capacitance of the anode reset transistor of the second sub-pixel. Consequently, after the anode of the light-emitting element of each sub-pixel is reset, the reset voltage of the anode of the light-emitting element of the anode reset transistor of the first sub-pixel is higher than the reset voltage of the anode of the light-emitting element of the anode reset transistor of the second sub-pixel. This shortens the response time from charging to ignition of the light-emitting element of the first sub-pixel, improves the luminance of the light-emitting element of the first sub-pixel, and enables each sub-pixel to be illuminated nearly simultaneously, thereby effectively improving color shift and smearing. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 is a schematic structural diagram of a display panel in one embodiment;

[0014] Figure 2 is a schematic structural diagram of a sub-pixel in one embodiment;

[0015] Figure 3 is a schematic structural diagram of a sub-pixel in another embodiment;

[0016] Figure 4 Schematic diagram comparing the structures of the first sub-pixel and the second sub-pixel in one embodiment;

[0017] Figure 5 is a schematic diagram comparing the structures of the first sub-pixel and the second sub-pixel in another embodiment;

[0018] Figure 6 is a schematic diagram comparing the structures of the first sub-pixel and the second sub-pixel in another embodiment;

[0019] Figure 7 1 is a schematic diagram of a circuit structure of a pixel circuit in one embodiment;

[0020] Figure 8 FIG1 is a schematic diagram comparing anode reset transistors of a first sub-pixel and a second sub-pixel in one embodiment;

[0021] Figure 9 is a schematic diagram comparing the anode reset transistors of the first sub-pixel and the second sub-pixel in another embodiment;

[0022] Figure 10 is a schematic diagram comparing the anode reset transistors of the first sub-pixel and the second sub-pixel in another embodiment;

[0023] Figure 11 is a schematic structural diagram of a first gate electrode of an anode reset transistor of a first sub-pixel in one embodiment;

[0024] Figure 12 FIG1 is a schematic structural diagram of a first active portion of an anode reset transistor of a first sub-pixel in one embodiment;

[0025] Figure 13is a schematic diagram comparing the anode reset transistors of the first sub-pixel and the second sub-pixel in another embodiment;

[0026] Figure 14 is a schematic diagram comparing the anode reset transistors of the first sub-pixel and the second sub-pixel in another embodiment;

[0027] Figure 15 A schematic diagram of a partial film layer structure of a display panel in one embodiment;

[0028] Figure 16 A schematic diagram of a timing sequence of some driving signals of a display panel in one embodiment;

[0029] Figure 17 is a structural schematic diagram of a display panel in another embodiment;

[0030] Figure 18 FIG. 1 is a schematic structural diagram of a display device in an embodiment. DETAILED DESCRIPTION

[0031] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0033] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, when a layer is referred to as being "under" another layer, it can be directly under or one or more intervening elements may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening elements may also be present.

[0034] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0035] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0036] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately," "approximately," or "substantially" can mean within one or more standard deviations, and is not limited here.

[0037] Furthermore, in the specification, the phrase “planar distribution diagram” refers to a drawing when the target portion is viewed from above, and the phrase “cross-sectional diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0038] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0039] As mentioned in the background technology section, the display quality requirements for display panels are getting higher and higher. In the related art, when the display panel switches from a black state to a display image, color deviation and smearing problems may occur, thereby resulting in poor display effects of the display panel.

[0040] The inventors have discovered that display panels typically include multiple color sub-pixels, such as red, blue, and green, each illuminated by a different color light-emitting element. Because these different color light-emitting elements use different luminescent materials, they exhibit inconsistent performance at low grayscales. The low-grayscale performance of these light-emitting elements is primarily influenced by the charge of their anodes. Specifically, different color light-emitting elements require different voltages to activate their anodes.

[0041] On the one hand, different turn-on voltages result in different charging times for different-colored light-emitting elements. For example, the turn-on voltage for a green light-emitting element is higher than that for a red light-emitting element, and the turn-on voltage for a green light-emitting element is also higher than that for a blue light-emitting element. Consequently, when switching between screens, the charging time for the red and green light-emitting elements is longer than that for the blue light-emitting elements. This results in a longer response time for the red and green light-emitting elements than for the blue light-emitting elements, leading to blurred or residual images at the edges of the screen, a phenomenon known as smearing.

[0042] On the other hand, the difference in turn-on voltage will also cause the brightness of the first frame of the different light-emitting elements (i.e., the first frame brightness) to be lower than the desired target brightness value. For example, when the display panel switches from black state to the target image, if the turn-on voltage of the red / green light-emitting element is higher than that of the blue light-emitting element, the response time from the first frame charging to the turn-on time is longer. As a result, at the same time point when the blue light-emitting element has already charged to the target brightness, the first frame brightness of the red / green light-emitting element is lower than its target brightness, thereby lowering the overall first frame brightness of the display panel and causing color shift in the first frame of the display panel.

[0043] Based on the above issues, the inventors further discovered that by designing the channel area of ​​the anode reset transistors connected to the anodes of the light-emitting elements of different sub-pixels with different sizes, they can obtain anode reset transistors with different parasitic capacitances. After resetting the anodes of the light-emitting elements, they can provide different coupling voltages to the anodes of the light-emitting elements. In this way, the reset voltage of the anodes of the light-emitting elements can be changed, thereby achieving the purpose of changing the response time from charging to ignition of the light-emitting elements of different sub-pixels, thereby effectively improving color shift and smearing.

[0044] Based on this, the inventors further developed the technical solutions of the embodiments of the present application. The display panel provided in the embodiments of the present application includes a plurality of sub-pixels, each of which includes a pixel circuit electrically connected to a light-emitting element; the pixel circuit includes an anode reset transistor, a first electrode of the anode reset transistor electrically connected to a first reset signal line, and a second electrode of the anode reset transistor electrically connected to an anode of the light-emitting element; the plurality of sub-pixels includes at least a first sub-pixel and a second sub-pixel, the color of the first sub-pixel being different from the color of the second sub-pixel; the channel region of the anode reset transistor of the first sub-pixel has an area S1, and the channel region of the anode reset transistor of the second sub-pixel has an area S2, where S1>S2. By adopting the above technical solution, the area of ​​the channel region of the anode reset transistor of the first sub-pixel is designed to be larger than the area of ​​the channel region of the anode reset transistor of the second sub-pixel, so that the parasitic capacitance of the anode reset transistor of the first sub-pixel is larger than the parasitic capacitance of the anode reset transistor of the second sub-pixel. Therefore, after the anode of the light-emitting element of each sub-pixel is reset, the reset voltage of the anode of the light-emitting element of the anode reset transistor of the first sub-pixel will be higher than the reset voltage of the anode of the light-emitting element of the anode reset transistor of the second sub-pixel. In this way, the response time from charging to lighting of the light-emitting element of the first sub-pixel is shortened, the luminance of the light-emitting element of the first sub-pixel is improved, and each sub-pixel is turned on almost simultaneously, thereby effectively improving color shift and smearing.

[0045] The above is the core concept of this application. The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0046] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present application is shown in FIG. Figure 2 A schematic diagram of the structure of a sub-pixel provided in an embodiment of the present application. Figure 3 A schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of the present application.

[0047] Combine Figure 1 and Figure 2 As shown, in an exemplary embodiment, a display panel 10 is provided. The display panel 10 includes a plurality of sub-pixels 100 . The sub-pixels 100 include a pixel circuit 110 and a light-emitting element D that are electrically connected.

[0048] The display panel 10 provided in this embodiment may be an organic light emitting diode (OLED) display panel. The display panel 10 may include a plurality of sub-pixels 100. The plurality of sub-pixels 100 may be as follows: Figure 1 As shown, they are arranged in an array on the display panel 10, and can also be arranged in other ways, which is not limited in the embodiment of the present application. The multiple sub-pixels 100 arranged on the display panel 10 can be sub-pixels of multiple different colors, for example, at least red sub-pixels, green sub-pixels and blue sub-pixels. In other embodiments, white sub-pixels and cyan sub-pixels can also be included, which can be set according to the actual display technology and is not limited. In the embodiment of the present application, as Figure 1 As shown in FIG, the explanation is given by taking the display panel 10 as an example in which a plurality of red sub-pixels R, green sub-pixels G and blue sub-pixels B are arranged in an array. Figure 1 As shown, the embodiments of the present application are all illustrated by taking the orthographic projection shape of a sub-pixel 100 onto the light-emitting surface of the display panel 10 as a strip. In specific implementation, the shape of the sub-pixel 100 includes but is not limited to this shape and can be designed according to actual needs.

[0049] like Figure 2As shown, the sub-pixel 100 of this embodiment includes a pixel circuit 110 and a light-emitting element D that are electrically connected. The light-emitting element D may be an organic light-emitting diode. The pixel circuit 110 is configured to transmit a light-emitting driving current to the light-emitting element D under the action of a signal from a driving signal line (such as a scan line, a data line, a voltage signal line, etc., not shown in the figure) on the display panel 10, thereby providing a driving current for the light-emitting element D to emit light.

[0050] Reference Figure 3 In an exemplary embodiment, the pixel circuit 110 includes an anode reset transistor T7 , a first electrode of the anode reset transistor T7 is electrically connected to the first reset signal line Vref, and a second electrode of the anode reset transistor T7 is electrically connected to the anode of the light emitting element D.

[0051] Specifically, the anode reset transistor T7 is used to reset the anode of the light-emitting element D connected thereto under the control of its gate enable level. A first electrode of the anode reset transistor T7 is used to receive a reset signal transmitted on a first reset signal line Vref. The anode reset transistor T7 is turned on in response to the gate enable level and resets the anode of the light-emitting element D through the reset signal.

[0052] It can be understood that after the anode of the light emitting element D is reset, the reset voltage of the anode of the light emitting element D will be changed, that is, Figure 3 The node voltage of the N4 node.

[0053] In an exemplary embodiment, the plurality of sub-pixels 100 includes at least a first sub-pixel and a second sub-pixel, and the color of the first sub-pixel is different from the color of the second sub-pixel.

[0054] It can be understood that the light-emitting elements D in the first and second sub-pixels use different luminescent materials, and thus can emit light of different colors when driven by the pixel circuit 110. Furthermore, due to the influence of the anode charge of the light-emitting element D, the anodes of the light-emitting elements D of different colors in the first and second sub-pixels must be charged to different turn-on voltages when emitting light. Accordingly, the turn-on voltage of the light-emitting element in the first sub-pixel can be higher than that of the light-emitting element in the second sub-pixel, or lower than that of the light-emitting element in the second sub-pixel.

[0055] The embodiments of the present application are explained by taking the example that the turn-on voltage of the light-emitting element of the first sub-pixel is higher than the turn-on voltage of the light-emitting element of the second sub-pixel. Figure 1, the first sub-pixel may be a red sub-pixel R or a green sub-pixel G, and the second sub-pixel may be a blue sub-pixel B. Furthermore, when the first sub-pixel is a green sub-pixel G, the second sub-pixel may also be a red sub-pixel R. In an exemplary embodiment, the light-emitting element D in the first sub-pixel may be a red light-emitting element or a green light-emitting element, and the light-emitting element in the second sub-pixel may be a blue light-emitting element.

[0056] In an exemplary embodiment, referring to Figure 2 The area of ​​the channel region of the anode reset transistor T7 of the first sub-pixel is S1, and the area of ​​the channel region of the anode reset transistor T7 of the second sub-pixel is S2, wherein S1>S2.

[0057] From the perspective of transistor structure, parasitic capacitance is mainly composed of gate capacitance, gate-source capacitance and gate-drain capacitance. The size of these capacitances is closely related to the size of the channel region. There is a positive correlation between the area of ​​the channel region and the size of its parasitic capacitance. When the area of ​​the channel region increases, the parasitic capacitance will also increase accordingly.

[0058] Specifically, since the area S1 of the channel region of the anode reset transistor T7 of the first sub-pixel is larger than the area S2 of the channel region of the anode reset transistor T7 of the second sub-pixel, the parasitic capacitance C1 of the anode reset transistor T7 of the first sub-pixel can be larger than the parasitic capacitance C2 of the anode reset transistor T7 of the second sub-pixel.

[0059] It should be noted that the anode reset transistor T7 included in the pixel circuit 110 in this embodiment is described using a P-type transistor as an example. When the transistor is selected as a P-type transistor, the P-type transistor is turned on when its gate is at a low level and is turned off when its gate is at a high level. It is understood that after the reset signal transmitted on the first reset signal line Vref completes the anode reset of the light-emitting elements D of the first and second sub-pixels, the gate of the anode reset transistor T7 switches from an enabled level to a disabled level (high level). This generates a coupling voltage at the anode of the light-emitting element D, i.e., the N4 node, through the influence of the parasitic capacitance of the anode reset transistor T7, thereby increasing the reset voltage at the anode of the light-emitting element D.

[0060] Among them, if the parasitic capacitance C1 of the anode reset transistor T7 of the first sub-pixel generates a coupling voltage V1 on the anode of the light-emitting element D of the first sub-pixel, and the parasitic capacitance C2 of the anode reset transistor T7 of the second sub-pixel generates a coupling voltage V2 on the anode of the light-emitting element D of the second sub-pixel, since C1>C2, V1>V2.

[0061] With this design, after the anode reset is completed, the reset voltage of the anode of the light-emitting element D of the first sub-pixel can be made higher than the reset voltage of the anode of the light-emitting element D of the second sub-pixel, thereby shortening the response time from charging to turning on the light-emitting element of the first sub-pixel, improving the luminous brightness of the light-emitting element of the first sub-pixel, and making each sub-pixel turn on almost at the same time, thereby effectively improving color cast and ghosting.

[0062] In an exemplary embodiment, referring to Figures 1 to 3 When the light emitting control signal is switched from the non-enable level to the enable level, the anode voltage of the light emitting element D of the first sub-pixel is higher than the anode voltage of the light emitting element D of the second sub-pixel.

[0063] Specifically, the light-emission control signal is input to the light-emission control transistor in the pixel circuit 110. When the light-emission control signal switches from a non-enable level to an enable level, the sub-pixel 100 is controlled to enter a light-emission phase. It can be understood that, when the sub-pixel 100 enters the light-emission phase, the anode voltage of the light-emitting element D of the first sub-pixel is higher than the anode voltage of the light-emitting element D of the second sub-pixel due to the different designs of the channel regions of the anode reset transistors of the different sub-pixels.

[0064] Such a design can raise the anode voltage of the first sub-pixel with a higher turn-on voltage of the light-emitting element, shorten the response time from charging to turning on of the light-emitting element of the first sub-pixel, and make the time points when the light-emitting elements of the first sub-pixel and the second sub-pixel are charged to the target brightness close, thereby improving the overall brightness of the first frame of the display panel and improving the color deviation problem of the first frame of the display panel.

[0065] Figure 4 A schematic diagram of the structure of some sub-pixels in a display panel provided in an embodiment of the present application.

[0066] In an exemplary embodiment, please refer to Figure 4 The display panel 10 further includes: a first scanning signal line Scan1 and a second scanning signal line Scan2; the first scanning signal line Scan1 is electrically connected to the gate of the anode reset transistor T7 of the first sub-pixel 100A, and is used to provide a first scanning signal to the anode reset transistor T7 of the first sub-pixel 100A; the second scanning signal line Scan2 is electrically connected to the gate of the anode reset transistor T7 of the second sub-pixel 100B, and is used to provide a second scanning signal to the anode reset transistor T7 of the second sub-pixel 100B.

[0067] The anode reset transistor T7 of the first sub-pixel 100A is configured to respond to the enable level of the first scanning signal transmitted on the first scanning signal line Scan1 and reset the anode of the light-emitting element D connected thereto via the reset signal transmitted on the first reset signal line Vref connected thereto at its first electrode. The anode reset transistor T7 of the second sub-pixel 100B is configured to respond to the enable level of the second scanning signal transmitted on the second scanning signal line Scan2 and reset the anode of the light-emitting element D connected thereto via the reset signal transmitted on the first reset signal line Vref connected thereto at its first electrode.

[0068] Exemplarily, a voltage value of a first scanning signal transmitted on the first scanning signal line Scan1 is different from a voltage value of a second scanning signal transmitted on the second scanning signal line Scan2 .

[0069] It can be understood that the first sub-pixel 100A and the second sub-pixel 100B corresponding to different colors use scanning signals with different voltage values ​​as the gate drive signal of the anode reset transistor T7. After the gate of the anode reset transistor T7 jumps from the enable level to the non-enable level (high level), the parasitic capacitance of the anode reset transistor T7 is affected, thereby generating different coupling voltages on the anodes of the light-emitting elements D of the first sub-pixel 100A and the second sub-pixel 100B, that is, the N4 node. This achieves the purpose of changing the reset voltage of the anodes of the light-emitting elements D of the sub-pixels of different colors, so that the sub-pixels are illuminated almost simultaneously, thereby improving the color shift and smearing phenomenon.

[0070] In an exemplary embodiment, please refer to Figure 4 The turn-on voltage of the light-emitting element D of the first sub-pixel 100A is higher than the turn-on voltage of the light-emitting element D of the second sub-pixel 100B, and the high-level voltage value of the first scanning signal is greater than the high-level voltage value of the second scanning signal.

[0071] Specifically, to achieve the goal of having the high-level voltage value of the first scan signal be greater than the high-level voltage value of the second scan signal, the high-level voltage value of the first scan signal transmitted on the first scan signal line Scan1 may be increased, the high-level voltage value of the second scan signal transmitted on the second scan signal line Scan2 may be decreased, or the high-level voltage values ​​of both scan signal lines may be changed simultaneously. It should be noted that since the anode reset transistor T7 in this embodiment is described as a P-type transistor, the above voltage value adjustment only applies to the high-level voltage value; the low-level voltage value does not need to be adjusted.

[0072] With such a design, after the anode reset is completed, the voltage value of the anode of the light-emitting element D of the first sub-pixel 100A coupled to the anode via the parasitic capacitance of the anode reset transistor T7 by the first scanning signal will be further greater than the voltage value of the anode of the light-emitting element D of the second sub-pixel 100B coupled to the anode via the parasitic capacitance of the anode reset transistor T7 by the second scanning signal. This makes the reset voltage of the anode of the light-emitting element D of the first sub-pixel 100A higher than the reset voltage of the anode of the light-emitting element D of the second sub-pixel 100B, thereby shortening the response time from charging to turning on the light-emitting element D of the first sub-pixel 100A, improving the luminous brightness of the light-emitting element D of the first sub-pixel 100A, and making each sub-pixel turn on almost simultaneously, thereby effectively improving color shift and smearing.

[0073] Figure 5 A schematic diagram of the structure of some sub-pixels in a display panel provided in an embodiment of the present application.

[0074] In an exemplary embodiment, please refer to Figure 5 The pixel circuit further includes a driving transistor T1, a first electrode of the driving transistor T1 being electrically connected to the anode of the light-emitting element D, wherein the width-to-length ratio of the channel region of the driving transistor T1 of the first sub-pixel 100A is N1, and the width-to-length ratio of the channel region of the driving transistor T1 of the second sub-pixel 100B is N2, wherein N1<N2.

[0075] The driving transistor T1 is used to generate a light-emitting drive current to drive the light-emitting element in the sub-pixel. When the gate voltage of the driving transistor T1 changes, it can be turned on or off based on the gate voltage, thereby allowing or preventing current from flowing from its first electrode to its second electrode, thereby controlling the brightness of the light-emitting element.

[0076] Understandably, in OLED (organic light-emitting diode) display technology, different color sub-pixels (red, green, and blue) require different drive currents due to the different properties of their luminescent materials. For example, the blue light-emitting element has the largest equivalent capacitance, which means that a higher voltage is required to achieve the same brightness level at the same current density. Consequently, the blue light-emitting element requires a higher drive current to ensure that it can be turned on simultaneously with the red and green light-emitting elements and achieve the same brightness level.

[0077] Specifically, according to the driving current I of the driving transistor OLEDAs can be seen from the expression formula, its current density is closely related to the aspect ratio (W / L) of the driving transistor. Adjusting the aspect ratio of the driving transistor is a very effective way to increase the luminous drive current flowing through the blue light-emitting element. In the embodiment of the present application, the second sub-pixel 100B is a blue sub-pixel. Therefore, the aspect ratio of the driving transistor T1 in the second sub-pixel 100B can be designed to be larger than that of other sub-pixels to provide a larger luminous drive current, ensuring that the sub-pixels of each color are illuminated nearly simultaneously, achieving good white balance and brightness consistency across the display panel.

[0078] It should be noted that since the blue sub-pixel has a lower turn-on voltage than other color sub-pixels, increasing the aspect ratio of its driving transistor alone can increase the driving current and improve its luminous brightness, but it may also cause its first frame brightness under low grayscale lighting to be much higher than that of other sub-pixels. However, in the embodiment of the present application, by combining the design of different channel area sizes for the anode reset transistors of different sub-pixels and the design of different high-level voltage values ​​for the gate drive signal connected to the anode reset transistor, it is possible to improve the color cast problem of the first frame of the image while increasing the driving current of the blue sub-pixel to improve its luminous brightness, thereby improving the overall display effect of the display panel.

[0079] For example, the method of achieving N1<N2 is not limited. It can be to increase the width W of the channel region of the driving transistor of the second sub-pixel, or to reduce the length L of the channel region of the driving transistor of the second sub-pixel. It can also be to increase the width W of the channel region of the driving transistor of the second sub-pixel while reducing the length L of the channel region of the driving transistor of the second sub-pixel.

[0080] Figure 6 A schematic diagram of the structure of some sub-pixels in a display panel provided in an embodiment of the present application.

[0081] In an exemplary embodiment, please refer to Figure 6 The pixel circuit further includes a light-emitting control transistor T6, a first electrode of the light-emitting control transistor T6 is electrically connected to the first electrode of the driving transistor T1, a second electrode of the light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element D, and a cathode of the light-emitting element D is electrically connected to the second power signal line; wherein, an area of ​​a channel region of the light-emitting control transistor T6 of the first sub-pixel 100A is S3, and an area of ​​a channel region of the light-emitting control transistor T6 of the second sub-pixel 100B is S4, wherein S3<S4.

[0082] The light-emission control transistor T6 is used to control the duration of the light-emitting element D's light-emission phase, that is, the duration of the light-emitting phase. When the light-emission control transistor T6 is turned on by the light-emission control signal connected to its gate, a light-emission drive current flows through the light-emission element D, causing it to emit light. When the light-emission control transistor T6 is turned off, the light-emission drive current flow path is cut off, and the light-emission element D stops emitting light. By precisely controlling the timing of the light-emission control transistor T6, the actual light-emission duration of the sub-pixel can be determined, thereby adjusting the display brightness and optimizing power consumption at low refresh rates.

[0083] Based on the above description, there is a positive correlation between the area of ​​the channel region and the magnitude of the parasitic capacitance of the transistor. When the area of ​​the channel region increases, the parasitic capacitance will also increase accordingly.

[0084] Furthermore, since the area S3 of the channel region of the light-emitting control transistor T6 of the first sub-pixel 100A is larger than the area S4 of the channel region of the light-emitting control transistor T6 of the second sub-pixel 100B, the parasitic capacitance C3 of the light-emitting control transistor T6 of the first sub-pixel 100A can be larger than the parasitic capacitance C4 of the light-emitting control transistor T6 of the second sub-pixel 100B.

[0085] In this embodiment, the light-emission control transistor T6 is also described using a P-type transistor as an example. It will be appreciated that when the light-emission control signal switches from a non-enable level to an enable level (low level), controlling the sub-pixel to enter the light-emitting stage, the low level, through the influence of the parasitic capacitance of the light-emission control transistor T6, generates a coupling voltage on the anode of the light-emitting element D, i.e., node N4, thereby lowering the reset voltage of the anode of the light-emitting element D. Due to the different designs of the channel areas of the light-emission control transistors T6 in the different sub-pixels, the anode voltage of the light-emitting element D in the second sub-pixel 100B is lower due to the larger parasitic capacitance, resulting in a higher anode voltage of the light-emitting element D in the first sub-pixel 100A than in the second sub-pixel 100B.

[0086] Such a design can lower the anode voltage of the second sub-pixel whose light-emitting element has a lower turn-on voltage, extend the response time of the second sub-pixel's light-emitting element from charging to turning on, and make the time points when the light-emitting elements of the first sub-pixel and the second sub-pixel are charged to the target brightness close, thereby improving the overall brightness of the first frame of the display panel and improving the color deviation problem of the first frame of the display panel.

[0087] In an exemplary embodiment, please refer to Figure 6The display panel 10 also includes: a first light-emitting control signal line EM1 and a second light-emitting control signal line EM2; the first light-emitting control signal line EM1 is electrically connected to the gate of the light-emitting control transistor T6 of the first sub-pixel 100A, and is used to provide a first light-emitting control signal to the light-emitting control transistor T6 of the first sub-pixel 100A; the second light-emitting control signal line EM2 is electrically connected to the gate of the light-emitting control transistor T6 of the second sub-pixel 100B, and is used to provide a second light-emitting control signal to the light-emitting control transistor T6 of the second sub-pixel 100B.

[0088] The light-emitting control transistor T6 of the first sub-pixel 100A is configured to respond to the enable level of the first light-emitting control signal transmitted on the first light-emitting control signal line EM1 and flow a light-emitting drive current to the light-emitting element D of the first sub-pixel 100A, thereby causing the light-emitting element to emit light. The light-emitting control transistor T6 of the second sub-pixel 100B is configured to respond to the enable level of the second light-emitting control signal transmitted on the second light-emitting control signal line EM2 and flow a light-emitting drive current to the light-emitting element D of the second sub-pixel 100B, thereby causing the light-emitting element to emit light.

[0089] Exemplarily, a voltage value of the first light emitting control signal transmitted on the first light emitting control signal line EM1 is different from a voltage value of the second light emitting control signal transmitted on the second light emitting control signal line EM2 .

[0090] It can be understood that, corresponding to the first sub-pixel 100A and the second sub-pixel 100B of different colors, light-emitting control signals with different voltage values ​​are used as the gate drive signal of the light-emitting control transistor T6. This can cause the gate of the light-emitting control transistor T6 to jump from the non-enabled level to the enabled level (low level). Then, through the influence of the parasitic capacitance of the light-emitting control transistor T6, different coupling voltages are generated on the anodes of the light-emitting elements D of the first sub-pixel 100A and the second sub-pixel 100B, i.e., the N4 node. This achieves the purpose of changing the reset voltage of the anodes of the light-emitting elements D of the sub-pixels of different colors, so that the sub-pixels are illuminated almost simultaneously, thereby improving the color shift and smearing phenomenon.

[0091] In an exemplary embodiment, please refer to Figure 6 The turn-on voltage of the light-emitting element D of the first sub-pixel 100A is higher than the turn-on voltage of the light-emitting element D of the second sub-pixel 100B, and the low-level voltage value of the first light-emitting control signal is greater than the low-level voltage value of the second light-emitting control signal.

[0092] Specifically, in order to achieve the purpose of the low-level voltage value of the first light-emitting control signal being greater than the low-level voltage value of the second light-emitting control signal, the low-level voltage value of the first light-emitting control signal transmitted on the first light-emitting control signal line EM1 can be increased, or the low-level voltage value of the second light-emitting control signal transmitted on the second light-emitting control signal line EM2 can be reduced, or the low-level voltage values ​​on the above two light-emitting control signal lines can be changed at the same time.

[0093] With this design, when the light-emitting control signal switches from the non-enable level to the enable level (low level) and controls the sub-pixel to enter the light-emitting stage, the voltage value of the anode of the light-emitting element D of the first sub-pixel 100A coupled to the parasitic capacitance of the light-emitting control transistor T6 by the first light-emitting control signal will be lower than the voltage value of the anode of the light-emitting element D of the second sub-pixel 100B coupled to the parasitic capacitance of the light-emitting control transistor T6 by the second light-emitting control signal. As a result, the reset voltage of the anode of the light-emitting element D of the first sub-pixel 100A is higher than the reset voltage of the anode of the light-emitting element D of the second sub-pixel 100B, thereby extending the response time from charging to turning on the light-emitting element D of the second sub-pixel 100B, so that all sub-pixels turn on almost simultaneously, indirectly improving the light-emitting brightness of the light-emitting element D of the first sub-pixel 100A, and thus effectively improving color shift and smearing.

[0094] Figure 7 This is a schematic diagram of the circuit structure of a pixel circuit in a first sub-pixel provided in an embodiment of the present application. Figure 7 The pixel circuit may further include a second light emitting control transistor T2, a data writing transistor T3, a gate reset transistor T4, and a threshold compensation transistor T5.

[0095] The second emission control transistor T2 and the first emission control transistor T6 are connected in series between the first power signal terminal VDD and the light-emitting element D, respectively, and are electrically connected to the first power signal terminal VDD and the anode of the light-emitting element D. The cathode of the light-emitting element 20 is electrically connected to the second power signal terminal VSS, thereby providing a light-emitting signal to the light-emitting element D during the light-emitting phase. The first power signal terminal VDD can be connected to a first power signal line (not shown) in the display panel to receive a first voltage signal. The second power signal terminal VSS can be connected to a second power signal line (not shown) in the display panel to receive a second voltage signal. The first and second voltage signals have different levels, and the first voltage signal can be set to be greater than the second voltage signal. The gates of the second emission control transistor T2 and the first emission control transistor T6 can be connected to the same emission control signal line, receiving the same emission control signal for enable control. This helps reduce the number of signal lines in the display panel, improve the display panel's transmittance, or increase the wiring space of the display panel.

[0096] A first electrode of the data write transistor T3 is connected to the data voltage signal terminal DATA, and a second electrode of the data write transistor T3 is connected to the second electrode of the drive transistor T1. The data voltage signal terminal DATA can be connected to a data line (not shown) in the display panel to receive a data voltage signal on the data line. The gate of the data write transistor T3 can be used to receive a data write enable signal, which can be a first scan signal. When the gate of the data write transistor T3 is in a conductive state in response to the first scan signal, it is used to transmit the data voltage signal at the data voltage signal terminal DATA to the second electrode of the drive transistor T1, thereby providing the data voltage signal to the drive transistor T1.

[0097] The first electrode of the gate reset transistor T4 can be electrically connected to the first reset signal line Vref, and the second electrode is electrically connected to the gate of the driving transistor T1. The gate reset transistor T4 is used to reset the gate of the driving transistor T1 to which it is connected, under the control of its gate enable level. The first electrode of the gate reset transistor T4 is used to receive the reset signal transmitted on the first reset signal line Vref. In response to the gate enable level, the gate reset transistor T4 is in the on state and resets the gate of the driving transistor T1 via the reset signal, thereby facilitating the conduction of the driving transistor T1 after the reset operation is completed.

[0098] It should be noted that, in this embodiment, when the gate reset transistor T4 and the anode reset transistor T7 play a reset role, the input terminals of the two can be commonly connected to the first reset signal line Vref to provide the same reset signal to reset the gate of the driving transistor T1 and the anode of the light-emitting element D. In specific implementation, the structure of the input terminal of the reset transistor is not limited to this. The input terminals of the gate reset transistor T4 and the anode reset transistor T7 can also be connected to different reset signal lines and reset respectively by reset signals of different voltage values. This embodiment does not make specific limitations here.

[0099] The first and second electrodes of the threshold compensation transistor T5 are electrically connected to the gate and drain of the drive transistor T1, respectively. During the threshold compensation phase of the data writing phase, this transistor short-circuits the gate and drain of the drive transistor T1, forming a diode connection structure. This extracts and stores the threshold voltage of the drive transistor T1, ensuring that the drive current is unaffected by individual differences in threshold voltage or drift caused by long-term use, so that the current is only related to the data voltage. It can be understood that the threshold compensation transistor T5 is used to address the problem of threshold voltage drift in the drive transistor, thereby improving the stability and uniformity of the display.

[0100] It can be understood that this embodiment is only an example of the module structure that the pixel circuit 110 may include. In specific implementation, the connection structure between the pixel circuit 110 and the light-emitting element D includes but is not limited to this, and may also include other connection structures. It can be understood by referring to the connection structure of the pixel circuit in the organic light-emitting display panel in the related art. This embodiment does not make specific limitations here.

[0101] In an exemplary embodiment, the channel regions of the anode reset transistor T7 and the emission control transistor T6 are both rectangular in shape. It should be understood that the following embodiments use the rectangular shape of the channel regions of the anode reset transistor T7 and the emission control transistor T6 as an example to clearly explain that the area of ​​the channel region is the product of its width and length. In specific implementations, the shape of the channel region is not limited to this. The shape of the channel region may also include other shapes. Reference may be made to other shapes in the related art for understanding, and this embodiment does not limit this.

[0102] Figure 8 A schematic diagram of a partial layout structure of a display panel provided in an embodiment of the present application; Figure 9 A schematic diagram of the partial layout structure of another display panel provided in an embodiment of the present application.

[0103] Exemplarily, the film layer structure of the display panel may include at least a first metal layer M1, a second metal layer M2, a third metal layer M3, an active layer POLY, etc. The partial layout structure diagram of the display panel provided in this application only shows the portion including the first metal layer M1 and the active layer POLY. Among them, the first metal layer M1 can be used to make the scanning signal lines and light control signal lines in the display panel, as well as the gates of various transistors. The active layer POLY can be used to make the active portion or source / drain of each transistor. The second metal layer M2, not shown in the figure, can be used to make the data lines, power signal lines, and the source / drain of each transistor in the display panel, and the third metal layer M3 can be used to make the reset signal line in the display panel. In other embodiments, the film layer structure of the display panel may also include a fourth metal layer, and at least one of the data line, power signal line, and reset signal line may also be located in the fourth metal layer to effectively reduce the signal line density in the single-layer metal film structure, reduce signal crosstalk, and help reduce the projected area of ​​the overall structure of the pixel circuit on the substrate, thereby increasing the pixel density of the display panel.

[0104] It should be noted that the above-mentioned partial layout structure diagrams of the display panel are only explained by taking the arrangement of two sub-pixels (the first sub-pixel 100A and the second sub-pixel 100B) as an example. During specific implementation, the design can be based on the actual arrangement.

[0105] In an exemplary embodiment, please refer to Figures 8 to 10 The anode reset transistor T7 includes a first active portion T1P, a first gate T1G, a first source T1S, and a first drain T1D. Along a first direction X, in the first subpixel 100A, the length of the first gate T1G of the anode reset transistor T7 is A1; in the second subpixel 100B, the length of the first gate T1G of the anode reset transistor T7 is A2. Along a second direction Y, in the first subpixel 100A, the length of the first active portion T1P of the anode reset transistor T7 is B1; in the second subpixel 100B, the length of the first active portion of the anode reset transistor T7 is B2. The direction from the first source T1S to the first drain T1D in a direction parallel to the light-emitting surface of the display panel is the first direction X, and the second direction Y intersects the first direction X. The figure illustrates an example where the first direction X and the second direction Y are perpendicular to each other in a direction parallel to the light-emitting surface of the display panel.

[0106] It can be understood that the area of ​​the channel region of the anode reset transistor T7 in this embodiment can be represented by the product of the width and length of the channel region, and the width of the channel region can be represented by the length of the first active portion T1P, and the length of the channel region can be represented by the length of the first gate T1G. Figures 8 to 10 In the first subpixel 100A, the area S1 of the channel region of the anode reset transistor T7 is the product of the length A1 of the first gate electrode T1G of the anode reset transistor T7 and the length B1 of the first active portion T1P. In the second subpixel 100B, the area of ​​the channel region of the anode reset transistor T7 is the product of the length A2 of the first gate electrode T1G of the anode reset transistor T7 and the length B2 of the first active portion T1P.

[0107] Reference Figure 8 , A1=A2, B1>B2 can be set, that is, the lengths of the first gates T1G of the anode reset transistors T7 of the two sub-pixels are equal, and the length of the first active portion T1P of the anode reset transistor T7 in the first sub-pixel 100A is greater than the length of the first active portion T1P of the anode reset transistor T7 in the second sub-pixel 100B, so that the area of ​​the channel region of the anode reset transistor T7 in the first sub-pixel 100A is greater than the area of ​​the channel region of the anode reset transistor T7 in the second sub-pixel 100B.

[0108] Or, refer to Figure 9, it can be set that A1>A2, B1=B2, that is, the lengths of the first active portions T1P of the anode reset transistors T7 of the two sub-pixels are equal, and the length of the first gate T1G of the anode reset transistor T7 in the first sub-pixel 100A is greater than the length of the first gate T1G of the anode reset transistor T7 in the second sub-pixel 100B, so that the area of ​​the channel region of the anode reset transistor T7 in the first sub-pixel 100A is greater than the area of ​​the channel region of the anode reset transistor T7 in the second sub-pixel 100B.

[0109] Or, refer to Figure 10 , it can be set that A1>A2, B1>B2, that is, the length of the first gate T1G of the anode reset transistor T7 in the first sub-pixel 100A is greater than the length of the first gate T1G of the anode reset transistor T7 in the second sub-pixel 100B, and the length of the first active portion T1P of the anode reset transistor T7 in the first sub-pixel 100A is greater than the length of the first active portion T1P of the anode reset transistor T7 in the second sub-pixel 100B, so that the area of ​​the channel region of the anode reset transistor T7 in the first sub-pixel 100A is greater than the area of ​​the channel region of the anode reset transistor T7 in the second sub-pixel 100B.

[0110] In the above-described manner, it is preferably set to A1>A2 and B1>B2, so that the channel area of ​​the anode reset transistor T7 in the first sub-pixel 100A is larger than the channel area of ​​the anode reset transistor T7 in the second sub-pixel 100B. It can be understood that when the length of the first gate T1G and the length of the first active portion T1P are simultaneously increased, not only can the area of ​​the channel region be increased, but the ratio of the increase can also be controlled to minimize the change in the width-to-length ratio of the transistor channel region, thereby preventing excessive changes in the width-to-length ratio from causing changes in other performance parameters of other transistors.

[0111] It can be understood that in order to change the channel area of ​​the transistor by changing the length of the first gate T1G and the first active portion T1P of the transistor, the length of the first gate T1G and / or the first active portion T1P of the transistor can also be designed in different shapes.

[0112] In an exemplary embodiment, referring to Figures 11 to 13The first gate T1G includes a first gate sub-portion T1G1, and the first gate sub-portion T1G1 is used to overlap with the first active portion T1P; the first active portion T1P includes a first active sub-portion T1P1, and the first active sub-portion T1P1 is used to overlap with the first gate T1G; along the first direction X, in the first sub-pixel 100A, the length of the first gate sub-portion T1G1 of the anode reset transistor T7 is C1; in the second sub-pixel 100B, the length of the first gate sub-portion T1G1 of the anode reset transistor T7 is C2; along the second direction Y, in the first sub-pixel 100A, the length of the first active sub-portion T1P1 of the anode reset transistor T7 is D1; ​​in the second sub-pixel 100B, the length of the first active sub-portion of the anode reset transistor T7 is D2.

[0113] It can be understood that the area of ​​the channel region of the anode reset transistor T7 in this embodiment can be represented by the product of the width and length of the channel region, and the width of the channel region can be represented by the length of the first active sub-portion T1P1, and the length of the channel region can be represented by the length of the first gate sub-portion T1G1. Figures 11 to 13 In the first subpixel 100A, the area S1 of the channel region of the anode reset transistor T7 is the product of the length C1 of the first gate subportion T1G1 of the anode reset transistor T7 and the length D1 of the first active subportion T1P1. In the second subpixel 100B, the area of ​​the channel region of the anode reset transistor T7 is the product of the length C2 of the first gate subportion T1G1 of the anode reset transistor T7 and the length D2 of the first active subportion.

[0114] Reference Figure 13 In order to make the area of ​​the channel region of the anode reset transistor T7 in the first sub-pixel 100A larger than the area of ​​the channel region of the anode reset transistor T7 in the second sub-pixel 100B, at least one of the following relationships must be satisfied:

[0115] Item 1: C1>C2;

[0116] Second item: D1>D2.

[0117] It can be understood that it is possible to set C1>C2, that is, the lengths of the first active sub-portions T1P1 of the anode reset transistors T7 of the two sub-pixels are equal. It is also possible to set D1>D2, that is, the lengths of the first gate sub-portions T1G1 of the anode reset transistors T7 of the two sub-pixels are equal. It is also possible to set C1>C2 and D1>D2, that is, Figure 13In the manner shown, the lengths of the first gate sub-portion T1G1 and the first active sub-portion T1P1 of the anode reset transistor T7 in the first sub-pixel 100A are simultaneously enlarged, which not only achieves the purpose of increasing the area of ​​the channel region, but also controls the enlargement ratio of the two so that the width-to-length ratio of the channel region of the transistor does not change much, thereby avoiding excessive changes in the width-to-length ratio that may cause changes in other performance parameters of other transistors.

[0118] In an exemplary embodiment, please refer to Figures 11 to 13 The first gate T1G further includes a second gate subportion T1G2, which does not overlap with the first active portion T1P. The first active portion T1P includes a second active subportion T1P2, which does not overlap with the first gate T1G. Along the first direction X, in the first subpixel 100A, the second gate subportion T1G2 of the anode reset transistor T7 has a length of C3; in the second subpixel 100B, the second gate subportion T1G2 of the anode reset transistor T7 has a length of C4. Along the second direction Y, in the first subpixel 100A, the second active subportion T1P2 of the anode reset transistor T7 has a length of D3; in the second subpixel 100B, the second active subportion T1P2 of the anode reset transistor T7 has a length of D4.

[0119] It can be understood that in the original design, in the first sub-pixel 100A, the length D1 of the first active sub-portion T1P1 of the anode reset transistor T7 can be equal to the length D3 of its second active sub-portion T1P2. In the second sub-pixel 100B, the length D2 of the first active sub-portion T1P1 of the anode reset transistor T7 can be equal to the length D4 of its first active sub-portion T1P1. In actual product design, D3 and D4 will be equal in length. Furthermore, in the improvement process, in order to achieve C1>C2, it can be as follows Figure 13 In the example shown, only C1 is increased, but only C2 can be decreased, or C1 can be increased while C2 is decreased.

[0120] Similarly, in the original design, in the first sub-pixel 100A, the length C1 of the first gate sub-portion T1G1 of the anode reset transistor T7 can be equal to the length C3 of its second gate sub-portion T1G2. In the second sub-pixel 100B, the length C2 of the first gate sub-portion T1G1 of the anode reset transistor T7 can be equal to the length C4 of its second gate sub-portion T1G2. In the actual product design, C3 and C4 will be equal in length. Furthermore, in the improvement process, in order to achieve D1>D2, it can be as follows Figure 13 In the example shown, only D1 is increased, but only D2 may be decreased, or D1 may be increased while D2 is decreased.

[0121] For example, Figure 14As shown, in this embodiment, in order to make the area of ​​the channel region of the anode reset transistor T7 in the first sub-pixel 100A larger than the area of ​​the channel region of the anode reset transistor T7 in the second sub-pixel 100B, it can be set as follows: C1>C3=C4>C2, D1>D2=D3=D4.

[0122] It can be understood that the first gate T1G is designed with a gradient distribution (C1>C3=C4>C2), and the first active sub-portion T1P is also differentiated (D1>D2). This effectively ensures that the channel area of ​​the anode reset transistor T7 in the first sub-pixel 100A is larger than the channel area of ​​the anode reset transistor T7 in the second sub-pixel 100B. Secondly, the first active sub-portion T1P is designed with a uniform length (D2=D3=D4) to maximize the consistency of carrier transport characteristics in non-overlapping active regions, thereby avoiding differences in threshold voltage shift caused by uneven etching. Furthermore, the uniform design of the non-overlapping regions effectively reduces the complexity of mask design and improves production yield.

[0123] For example, the method for achieving an area of ​​the channel region of the light emitting control transistor T6 of the first sub-pixel 100A being smaller than an area of ​​the channel region of the light emitting control transistor T6 of the second sub-pixel 100B may refer to the solution adopted in the above embodiment to achieve an area of ​​the channel region of the anode reset transistor T7 in the first sub-pixel 100A being larger than an area of ​​the channel region of the anode reset transistor T7 in the second sub-pixel 100B.

[0124] In an exemplary embodiment, the light emission control transistor includes a second active portion, a second gate, a second source, and a second drain. The second gate includes a third gate sub-portion, the third gate sub-portion overlaps with the second active portion; the second active portion includes a third active sub-portion, the third active sub-portion overlaps with the second gate; along the first direction, in the first sub-pixel, the length of the third gate sub-portion of the light emission control transistor is C5; in the second sub-pixel, the length of the third gate sub-portion of the light emission control transistor is C6; along the second direction, in the first sub-pixel, the length of the third active sub-portion of the light emission control transistor is D5; in the second sub-pixel, the length of the third active sub-portion of the light emission control transistor is D6; the second gate also includes a fourth gate sub-portion, the third gate sub-portion overlaps with the second active portion; The fourth gate sub-portion does not overlap with the second active portion; the second active portion includes a fourth active sub-portion, and the fourth active sub-portion does not overlap with the second gate; along the first direction, in the first sub-pixel, the length of the fourth gate sub-portion of the light-emitting control transistor is C7; in the second sub-pixel, the length of the fourth gate sub-portion of the light-emitting control transistor is C8; along the second direction, in the first sub-pixel, the length of the fourth active sub-portion of the light-emitting control transistor is D7; in the second sub-pixel, the length of the fourth active sub-portion of the light-emitting control transistor is D8; wherein, C5>C7=C8>C6, D5>D6=D7=D8.

[0125] It can be understood that the specific dimensions of the width-to-length ratio and area of ​​the channel region involved in the above-mentioned multiple embodiments, as well as the specific voltage values ​​adjusted to the corresponding signals transmitted on each driving signal line, can be comprehensively set based on the goal of making each sub-pixel light up almost at the same time, and are not limited to the specific values ​​described in a single embodiment.

[0126] Figure 15 A schematic diagram of a partial layout structure of a display panel provided in a specific embodiment; Figure 16 A timing diagram of part of driving signals in a display panel provided in a specific embodiment; Figure 17 The figure is a schematic structural diagram of a display panel provided in a specific embodiment.

[0127] In a specific embodiment, Figure 17 As shown, the display panel 10 includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes a pixel circuit and a light-emitting element D that are electrically connected. Figure 7 As shown, Figure 15 for Figure 7 The schematic diagram of the local layout structure corresponding to the pixel circuit shown in FIG. Figure 16 for Figure 7 The timing diagram of some driving signals corresponding to the pixel circuit shown is shown.

[0128] In this embodiment, when the turn-on voltage of the light-emitting element D of the first sub-pixel 100A is higher than the turn-on voltage of the light-emitting element D of the second sub-pixel 100B, the first sub-pixel 100A can be a red sub-pixel R and a green sub-pixel G, and the second sub-pixel 100B can be a blue sub-pixel B.

[0129] First, it is designed that the channel area of ​​the anode reset transistor T7 of the first sub-pixel 100A is S1, and the channel area of ​​the anode reset transistor T7 of the second sub-pixel is S2, wherein S1>S2. Figure 15 , the areas of the active layer and the first metal layer corresponding to the channel region of the anode reset transistor T7 of the first sub-pixel 100A can be increased, and at the same time, the width of the first metal layer corresponding to the channel region of the anode reset transistor T7 of the second sub-pixel 100B can be reduced (equivalent to the channel region length L) to achieve S1>S2.

[0130] It is also designed that the channel area of ​​the light emitting control transistor T6 of the first sub-pixel 100A is S3, and the channel area of ​​the light emitting control transistor T6 of the second sub-pixel 100B is S4, wherein S3<S4. Figure 15, the areas of the active layer and the first metal layer corresponding to the channel region of the light-emitting control transistor T6 of the second sub-pixel 100B can be increased, and at the same time, the width of the first metal layer corresponding to the channel region of the light-emitting control transistor T6 of the first sub-pixel 100A can be reduced (equivalent to the channel region length L) to achieve S3<S4.

[0131] Secondly, the first scanning signal line Scan1 is electrically connected to the gate of the anode reset transistor T7 of the first sub-pixel 100A, and is used to provide a first scanning signal to the anode reset transistor T7 of the first sub-pixel 100A; the second scanning signal line Scan2 is electrically connected to the gate of the anode reset transistor T7 of the second sub-pixel 100B, and is used to provide a second scanning signal to the anode reset transistor T7 of the second sub-pixel 100B. Accordingly, the high-level voltage value of the first scanning signal is designed to be greater than the high-level voltage value of the second scanning signal. For example, in an example, Figure 16 As shown, the high-level voltage value of the first scanning signal can be raised to +7V, and the high-level voltage value of the second scanning signal can be lowered to +5V to achieve that the high-level voltage value of the first scanning signal is greater than the high-level voltage value of the second scanning signal.

[0132] Next, the first light-emitting control signal line EM1 is electrically connected to the gate of the light-emitting control transistor T6 of the first sub-pixel 100A, and is used to provide a first light-emitting control signal to the light-emitting control transistor T6 of the first sub-pixel 100A; the second light-emitting control signal line EM2 is electrically connected to the gate of the light-emitting control transistor T6 of the second sub-pixel 100B, and is used to provide a second light-emitting control signal to the light-emitting control transistor T6 of the second sub-pixel 100B. Accordingly, the low-level voltage value of the first light-emitting control signal is designed to be greater than the low-level voltage value of the second light-emitting control signal. For example, in an example, Figure 16 As shown, the low-level voltage value of the first light-emitting control signal can be raised to -5V, and the low-level voltage value of the second light-emitting control signal can be lowered to -7V, so that the low-level voltage value of the first light-emitting control signal is greater than the low-level voltage value of the second light-emitting control signal.

[0133] For example, referring to Figure 17To optimize the wiring layout, multiple red sub-pixels R and green sub-pixels G can be arranged in the same pixel row, and alternately arranged with the pixel row where multiple blue sub-pixels B are located. Specifically, EM circuit 1 is used to electrically connect to the first light-emitting control signal line EM1 to generate a first light-emitting control signal to the red sub-pixels R and green sub-pixels G. Scan circuit 1 is used to electrically connect to the first scan signal line Scan1 to generate a first scan signal to the red sub-pixels R and green sub-pixels G. EM circuit 2 is used to electrically connect to the second light-emitting control signal line EM2 to generate a second light-emitting control signal to the blue sub-pixels B. Scan circuit 2 is used to electrically connect to the second scan signal line Scan2 to generate a second scan signal to the blue sub-pixels B.

[0134] In this embodiment, by designing the channel regions of the transistors with different dimensions and differentially adjusting the voltage value of the gate drive signal of the control transistor, when the light-emitting control signal is switched from the non-enable level to the enable level, the anode voltage of the light-emitting element D of the first sub-pixel can be made higher than the anode voltage of the light-emitting element D of the second sub-pixel, thereby shortening the response time from charging to lighting of the light-emitting element of the first sub-pixel, improving the light-emitting brightness of the light-emitting element of the first sub-pixel, and making each sub-pixel light up almost simultaneously, thereby effectively improving color shift and smearing.

[0135] Based on the same application concept, an embodiment of the present application also provides a display device. Figure 18 This is a schematic diagram of the structure of the display device 20 provided in an embodiment of the present application, as shown in FIG. Figure 18 As shown, the display device 20 includes the display panel 10 in any of the above embodiments. Figure 18 As shown, the display device 20 includes a display panel 10. Therefore, the display device 20 also has the beneficial effects of the display panel 10 in the above embodiment. The similarities can be understood by referring to the above explanation of the display panel 10, which will not be repeated below.

[0136] The display device 20 provided in the embodiment of the present application can be Figure 18 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of this application do not specifically limit this.

[0137] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0138] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A display panel, characterized in that: include: a plurality of sub-pixels, each sub-pixel comprising a pixel circuit and a light-emitting element electrically connected; The pixel circuit includes an anode reset transistor, a first electrode of the anode reset transistor is electrically connected to the first reset signal line, and a second electrode of the anode reset transistor is electrically connected to the anode of the light emitting element; The plurality of sub-pixels include at least a first sub-pixel and a second sub-pixel, and a color of the first sub-pixel is different from a color of the second sub-pixel; The area of ​​the channel region of the anode reset transistor of the first sub-pixel is S1, and the area of ​​the channel region of the anode reset transistor of the second sub-pixel is S2, wherein S1>S2.

2. The display panel according to claim 1, wherein: When the light emitting control signal is switched from the non-enable level to the enable level, the anode voltage of the light emitting element of the first sub-pixel is higher than the anode voltage of the light emitting element of the second sub-pixel.

3. The display panel according to claim 1, wherein: Also includes: a first scanning signal line and a second scanning signal line; The first scanning signal line is electrically connected to the gate of the anode reset transistor of the first sub-pixel, and is used to provide a first scanning signal to the anode reset transistor of the first sub-pixel; The second scanning signal line is electrically connected to the gate of the anode reset transistor of the second sub-pixel, and is used to provide a second scanning signal to the anode reset transistor of the second sub-pixel; The voltage value of the first scanning signal is different from the voltage value of the second scanning signal.

4. The display panel according to claim 3, wherein: The turn-on voltage of the light-emitting element of the first sub-pixel is higher than the turn-on voltage of the light-emitting element of the second sub-pixel, and the high-level voltage value of the first scanning signal is greater than the high-level voltage value of the second scanning signal.

5. The display panel according to claim 1, wherein: The pixel circuit further includes a driving transistor, wherein a first electrode of the driving transistor is electrically connected to an anode of the light emitting element; The width-to-length ratio of the channel region of the driving transistor of the first sub-pixel is N1, and the width-to-length ratio of the channel region of the driving transistor of the second sub-pixel is N2, wherein N1<N2.

6. The display panel according to claim 5, wherein: The pixel circuit further includes a light emitting control transistor, wherein a first electrode of the light emitting control transistor is electrically connected to a first electrode of the driving transistor, a second electrode of the light emitting control transistor is electrically connected to an anode of the light emitting element, and a cathode of the light emitting element is electrically connected to a second power signal line; The area of ​​the channel region of the light emitting control transistor of the first sub-pixel is S3, and the area of ​​the channel region of the light emitting control transistor of the second sub-pixel is S4, wherein S3<S4.

7. The display panel according to claim 6, wherein: Also includes: a first light-emitting control signal line and a second light-emitting control signal line; The first light emitting control signal line is electrically connected to the gate of the light emitting control transistor of the first sub-pixel, and is used to provide a first light emitting control signal to the light emitting control transistor of the first sub-pixel; The second light emitting control signal line is electrically connected to the gate of the light emitting control transistor of the second sub-pixel, and is used to provide a second light emitting control signal to the light emitting control transistor of the second sub-pixel; The voltage value of the first light-emitting control signal is different from the voltage value of the second light-emitting control signal.

8. The display panel according to claim 7, wherein: The turn-on voltage of the light-emitting element of the first sub-pixel is higher than the turn-on voltage of the light-emitting element of the second sub-pixel, and the low-level voltage value of the first light-emitting control signal is greater than the low-level voltage value of the second light-emitting control signal.

9. The display panel according to claim 6, wherein: The channel regions of the anode reset transistor and the light emission control transistor are both rectangular in shape.

10. The display panel according to claim 9, wherein: The anode reset transistor includes a first active portion, a first gate, a first source and a first drain; Along the first direction, in the first sub-pixel, the length of the first gate of the anode reset transistor is A1; in the second sub-pixel, the length of the first gate of the anode reset transistor is A2; Along the second direction, in the first sub-pixel, the length of the first active portion of the anode reset transistor is B1; in the second sub-pixel, the length of the first active portion of the anode reset transistor is B2; A1=A2, B1>B2; or A1>A2,B1=B2;or A1>A2, B1>B2; Wherein, in a direction parallel to the light emitting surface of the display panel, the direction from the first source electrode to the first drain electrode is a first direction, and the second direction intersects with the first direction.

11. The display panel according to claim 10, wherein: The first gate includes a first gate sub-portion, the first gate sub-portion overlaps with the first active portion; the first active portion includes a first active sub-portion, the first active sub-portion overlaps with the first gate; Along the first direction, in the first sub-pixel, the length of the first gate sub-portion of the anode reset transistor is C1; in the second sub-pixel, the length of the first gate sub-portion of the anode reset transistor is C2; Along the second direction, in the first sub-pixel, the length of the first active sub-portion of the anode reset transistor is D1; ​​in the second sub-pixel, the length of the first active sub-portion of the anode reset transistor is D2; At least one of the following relations must be satisfied: Item 1: C1>C2; Second item: D1>D2.

12. The display panel according to claim 11, wherein: The first gate further includes a second gate sub-portion, the second gate sub-portion does not overlap with the first active portion; the first active portion includes a second active sub-portion, the second active sub-portion does not overlap with the first gate; Along the first direction, in the first sub-pixel, the length of the second gate sub-portion of the anode reset transistor is C3; In the second sub-pixel, the length of the second gate sub-portion of the anode reset transistor is C4; Along the second direction, in the first sub-pixel, the length of the second active sub-portion of the anode reset transistor is D3; in the second sub-pixel, the length of the second active sub-portion of the anode reset transistor is D4; Among them, C1>C3=C4>C2, D1>D2=D3=D4.

13. The display panel according to claim 1, wherein: The light-emitting element in the first sub-pixel is a red light-emitting element or a green light-emitting element, and the light-emitting element in the second sub-pixel is a blue light-emitting element.

14. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 13.

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