Display device

Abstract

A display device. The display device comprises a pixel array, a time schedule controller and a source driver. The pixel array has a plurality of liquid crystal pixels and a plurality of self-luminous pixels. The time schedule controller receives display data to provide driving mode data and pixel gray scale data, and the driving mode data is based on the configuration positions of the liquid crystal pixels and the self-luminous pixels. The source driver is coupled between the pixel array and the time schedule controller and receives the driving mode data and the pixel gray scale data so as to provide a plurality of liquid crystal source voltages and a plurality of spontaneous light source voltages based on the driving mode data and the pixel gray scale data.

Description

Technical Field

[0001] The present invention relates to a display device, and in particular to a display device having the same function as the display device. Background Art

[0002] Currently, the main types of display panels include liquid crystal display (LCD) panels, micro light emitting diode (uLED) panels, and organic light emitting diode (OLED) panels. Each panel requires a different driving method. If different panels are to be driven on the same display device to realize a display screen with spliced ​​heterogeneous panels, source drivers corresponding to the respective types of panels are required to drive them. This increases the number of source driver chips and causes an increase in overall hardware costs. Summary of the Invention

[0003] The present invention provides a display device in which a source driver can provide a liquid crystal source voltage with alternating polarity over time to liquid crystal pixels and provide a self-luminous pixel source voltage with fixed polarity to self-luminous pixels, thereby improving the versatility of the source driver, simplifying the implementation architecture, and reducing the overall hardware cost of the display device.

[0004] The display device of the present invention includes a pixel array, a timing controller, and a source driver. The pixel array has a plurality of liquid crystal pixels and a plurality of self-luminous pixels. The timing controller receives display data to provide drive mode data and pixel grayscale data, wherein the drive mode data is based on the configuration positions of the liquid crystal pixels and the self-luminous pixels. The source driver is coupled between the pixel array and the timing controller, and receives the drive mode data and the pixel grayscale data to provide a plurality of liquid crystal source voltages and a plurality of self-luminous source voltages based on the drive mode data and the pixel grayscale data. The liquid crystal source voltage is provided to the liquid crystal pixels and its voltage polarity relative to a common voltage varies over time, while the self-luminous source voltage is provided to the self-luminous pixels and its voltage polarity relative to the common voltage does not vary over time.

[0005] Based on the above, the display device of the embodiment of the present invention can simplify the hardware circuit implementation of the display device, reduce the number of source driver chips / timing controllers, and thereby reduce the overall cost of the display device, because the source driver can determine the positions of the liquid crystal pixels and the self-luminous pixels based on the driving mode data, and then provide the liquid crystal source voltage or the self-luminous source voltage accordingly.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A FIG. 1 is a system diagram of a display device according to an embodiment of the present invention.

[0008] Figure 1B FIG. 1 is a waveform diagram of a liquid crystal source voltage according to an embodiment of the present invention.

[0009] Figure 1C FIG. 1 is a waveform diagram of a liquid crystal source voltage according to an embodiment of the present invention.

[0010] Figure 2 FIG. 1 is a data diagram of source driver data of a single frame according to an embodiment of the present invention.

[0011] Figure 3 FIG. 1 is a schematic diagram of field definitions of driving mode data according to an embodiment of the present invention.

[0012] Figure 4 FIG. 1 is a system diagram of a source driver according to an embodiment of the present invention.

[0013] Figure 5 FIG. 1 is a system diagram of a source channel according to an embodiment of the present invention.

[0014] Figure 6 FIG. 1 is a schematic diagram of an application of a display device according to an embodiment of the present invention.

[0015] Figure 7 FIG. 4 is a schematic diagram of an application of a display device according to another embodiment of the present invention.

[0016] Description of reference numerals:

[0017] 100: Display device

[0018] 110: Timing controller

[0019] 120, 120a: Source driver

[0020] 130: Pixel array

[0021] 410: Decoding circuit

[0022] 420, 420a, 430: Source channel

[0023] AGND: Ground voltage

[0024] BK, DMS_1, DMS_2, BAC, EOL, Setting, DATA REG +DATA GAMMA , BKPOL: Data Packet

[0025] BLM: Backlight Module

[0026] CH_NUM: Channel number field

[0027] CH_SEL: Channel start field

[0028] DAC1: First Digital-to-Analog Converter

[0029] DAC2: Second digital-to-analog converter

[0030] DATA_pixel1 to DATA_pixel4: sub-pixel data

[0031] DATAdis: Display data

[0032] DATA RGB : Pixel grayscale data\data packet

[0033] DMS: Drive Mode Data

[0034] DPX: Liquid Crystal Pixel

[0035] EN:Enable field

[0036] EPX: Self-luminous pixels

[0037] LSR1: First level converter

[0038] LSR2: Second level converter

[0039] Lsrc: source line

[0040] Lsrc1: first source line

[0041] Lsrc2: second source line

[0042] MUX: Multiplexing circuit

[0043] NAVDD: Negative system voltage

[0044] PAVDD: positive system voltage

[0045] POL: Data packet\polarity data

[0046] SB1, SB2, SB4: Transparent substrate

[0047] SB3: Flexible substrate

[0048] Sdm1, Sdm2: drive mode signals

[0049] SW1: First switch

[0050] SW2: Second switch

[0051] SW3: The third switch

[0052] SW4: The fourth switch

[0053] SW POL : Polarity switch signal

[0054] VCOM: common voltage

[0055] Vsoutd: liquid crystal source voltage

[0056] Vsoute: self-luminous source voltage DETAILED DESCRIPTION

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as idealized or overly formal unless explicitly defined as such herein.

[0058] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a "first element," "component," "region," "layer," or "portion" discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0059] The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and / or "including" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, components and / or parts, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, components and / or combinations thereof.

[0060] Figure 1A FIG. 1 is a system diagram of a display device according to an embodiment of the present invention. Figure 1B FIG. 1 is a waveform diagram of a liquid crystal source voltage according to an embodiment of the present invention. Figure 1CFIG1 is a waveform diagram of a liquid crystal source voltage according to an embodiment of the present invention. Figures 1A to 1C In this embodiment, the display device 100 includes a timing controller 110 , a source driver 120 , and a pixel array 130 , wherein the source driver 120 is coupled between the pixel array 130 and the timing controller 110 .

[0061] The pixel array 130 has a plurality of liquid crystal pixels DPX, a plurality of self-luminous pixels EPX, and a plurality of source lines Lsrc coupled to the liquid crystal pixels DPX and the self-luminous pixels EPX. The timing controller 110 receives the display data DATAdis to provide the driving mode data DMS and the pixel grayscale data DATA RGB , wherein the driving mode data DMS is provided based on the distribution positions of the liquid crystal pixels DPX and the self-luminous pixels EPX, and the distribution positions of the liquid crystal pixels DPX and the self-luminous pixels EPX can be stored in the timing controller 110 or in other storage devices (not shown) in the display device 100, but the embodiments of the present invention are not limited thereto.

[0062] The source driver 120 receives the driving mode data DMS and the pixel grayscale data DATA RGB , based on the driving mode data DMS and the pixel grayscale data DATA RGB A plurality of liquid crystal source voltages Vsoutd and a plurality of self-luminous source voltages Vsoute are provided, wherein the liquid crystal source voltage Vsoutd is provided to the liquid crystal pixel DPX and its voltage polarity relative to the common voltage VCOM changes over time, and the self-luminous source voltage Vsoute is provided to the self-luminous pixel EPX and its voltage polarity relative to the common voltage VCOM does not change over time.

[0063] According to the above, the source driver 120 can determine the position of the liquid crystal pixel DPX and the self-luminous pixel EPX based on the driving mode data DMS, and then control each source channel (such as Figure 4 The source channels 420 and 430 shown provide a liquid crystal source voltage Vsoutd or a self-luminous source voltage Vsoute, thereby simplifying the implementation of the hardware circuit, reducing the number of source driver chips / timing controllers, and lowering costs.

[0064] In other words, in this embodiment, the output of the timing controller 110 carries a setting code (i.e., the driving mode data DMS), which controls the state of the output pins of the source driver 120. Therefore, when the display device 100 is powered on (Power On), each chip / channel of the source driver 120 can be determined to drive the liquid crystal pixel DPX / self-luminous pixel EPX.

[0065] In the embodiment of the present invention, the self-luminous pixel EPX may include at least one micro light emitting diode (uLED) pixel and / or at least one organic light emitting diode (OLED) pixel, but the embodiment of the present invention is not limited thereto.

[0066] In this embodiment, each source line Lsrc is shown to be coupled to multiple liquid crystal pixels DPX or coupled to multiple self-luminous pixels EPX, but in the embodiment of the present invention, each source line Lsrc can be coupled to multiple liquid crystal pixels DPX and self-luminous pixels EPX in any arrangement, but the embodiment of the present invention is not limited to this.

[0067] Figure 2 This is a data diagram of source driver data of a single frame according to an embodiment of the present invention. Figure 1A and Figure 2 In this embodiment, the source driver data of a single frame is shown, and the source driver data is transmitted using, for example, an integrated-stream protocol (ISP). Figure 2 As shown, the source driver data includes the first to last line data (Line Data), setting line data, and vertical blank line data.

[0068] The data structure of the first to last row of data is roughly the same, and is encapsulated with data packets BK, DMS_1, DMS_2, BAC, POL, DATA RGB and EOL, wherein the data packets DMS_1 and DMS_2 constitute the driving mode data DMS, and the data packet DATA RGB Transmit pixel grayscale data DATA RGB , and the data packet POL transmits polarity data POL. The setting line data package has data packets BK, BAC, Setting, DATA REG +DATA GAMMA The vertical blank line data package includes data packets BK, BAC, BKPOL and EOL.

[0069] According to the integrated streaming protocol, one data packet consists of 9 bits. Before each row of data is logged, it will first input data packets BK, BAC, POL, etc., display data (such as pixel grayscale data DATA RGB ) After logging in, the data packet EOL will be input, indicating the end of a line. The data packets BK and BAC are fixed data, and the data packet POL is divided into POL=+ and POL=-, indicating the flipping mode of the data in this line. After the input of the effective display signal of each screen is completed, the setting line data (i.e. data packets BK, BAC, Setting, DATA REG+DATA GAMMA and EOL) to set the registers in the source driver (such as 120). Then, vertical blank line data (i.e., data packets BK, BAC, BKPOL, and EOL) are input line by line to control the blanking area display.

[0070] In this embodiment, the driving mode data DMS is composed of, for example, two data packets. However, the driving mode data DMS may also be composed of one data packet or three or more data packets, depending on the circuit design and not limited to this embodiment of the present invention. Furthermore, the driving mode data DMS in each row of data determines the arrangement of different driving modes for each column of liquid crystal pixels DPX / self-luminous pixels EPX in the pixel array 130. In other words, it determines the driving mode of each source channel of the source driver 120 when driving each column of liquid crystal pixels DPX / self-luminous pixels EPX in the pixel array 130.

[0071] Figure 3 This is a schematic diagram of the field definition of the driving mode data according to an embodiment of the present invention. Figure 1A 、 Figure 2 and Figure 3 In this embodiment, the driving mode data DMS is composed of data packets DMS_1 and DMS_2, for example, and the driving mode data DMS includes an enable field EN (e.g., including bit [0] of the data packet DMS_1), a channel number field CH_NUM (e.g., including bits [4:1] of the data packet DMS_1), and a channel start field CH_SEL (e.g., including bits [7:5] of the data packet DMS_1 and bits [7:0] of the data packet DMS_2).

[0072] The enable field EN is used to determine the drive mode for the row corresponding to the row data in the pixel array 130. Specifically, it determines whether the source line Lsrc (corresponding to the source channel) in each row of pixels is coupled to the self-luminous pixel EPX. Furthermore, if the source line Lsrc (corresponding to the source channel) in the corresponding row is not coupled to the self-luminous pixel EPX, the enable field EN may be 0, indicating that all pixels in the corresponding row are liquid crystal pixels DPX and can therefore be driven only in the liquid crystal drive mode. If the source line Lsrc in the corresponding row is coupled to the self-luminous pixel EPX, the enable field EN may be 1, indicating that some pixels are liquid crystal pixels DPX and therefore need to be driven in the micro light emitting diode (uLED) / organic light emitting diode (OLED) drive mode.

[0073] The channel number field CH_NUM indicates the number of source channels coupled to the self-luminous pixel EPX in the corresponding row. For example, the maximum value that can be determined by bit [4:1] of the data packet DMS_1 is 3. n, where n = 2 4 The channel start field CH_SEL indicates the starting position of the source channel coupled to the self-emitting pixel EPX in the corresponding row. In the embodiment of the present invention, the packet setting method of the channel number field CH_NUM and the channel start field CH_SEL can be determined according to the circuit design, and the embodiment of the present invention is not limited to this definition method.

[0074] Based on the above, by adding the driving mode data DMS to the source driver data output by the timing controller 110, the source driver 120 can identify whether there are source channels coupled to the self-luminous pixels EPX in the source line Lsrc and their number, so that the source driver 120 can switch the driving mode when the corresponding source channel is output.

[0075] Figure 4 This is a schematic diagram of a source driver system according to an embodiment of the present invention. Figure 1A 、 Figures 2 to 4 In this embodiment, the source driver 120 is, for example, a source driver 120a, and the source driver 120a includes a decoding circuit 410 and a plurality of source channels (such as 420 and 430). The decoding circuit 410 receives the driving mode data DMS and the pixel grayscale data DATA. RGB and polarity data POL (eg data transmitted by the data packet POL) to provide a plurality of sub-pixel data (eg DATA_pixel1 to DATA_pixel4), a plurality of driving mode signals (eg Sdm1 to Sdm2), and a polarity switch signal SW POL .

[0076] The source channels (such as 420 and 430) are coupled to the decoding circuit 410. Each source channel 420 and 430 receives two consecutive sub-pixel data (i.e., a pair of sub-pixel data) from the sub-pixel data DATA_pixel1 to DATA_pixel4, receives a corresponding one of the driving mode signals (such as Sdm1 to Sdm2) and the polarity switch signal SW. POL , to provide a pair of liquid crystal source voltages Vsoutd or a pair of self-luminous source voltages Vsoute.

[0077] For example, the source channel 420 receives sub-pixel data DATA_pixel1 (corresponding to the first sub-pixel data) and DATA_pixel2 (corresponding to the second sub-pixel data), receives the driving mode signal Sdm1 (corresponding to the first driving mode signal) and the polarity switch signal SW POL , to provide a pair of liquid crystal source voltages Vsoutd or a pair of self-luminous source voltages Vsoute.

[0078] Figure 5This is a schematic diagram of a source channel system according to an embodiment of the present invention. Figure 1A 、 Figures 2 to 5 In this embodiment, source channel 420 is used as an example for illustration. Other source channels (such as 430) can refer to the example of source channel 420, but the present invention is not limited thereto. For example, source channel 420a is used as an example. Source channel 420 includes a first switch SW1, a second switch SW2, a first level shifter LSR1, a second level shifter LSR2, a multiplexer circuit MUX, a first digital-to-analog converter DAC1, a second digital-to-analog converter DAC2, a third switch SW3, and a fourth switch SW4.

[0079] The first switch SW1 has a first terminal for receiving the first sub-pixel data DATA_pixel1, a second terminal for receiving the sub-pixel data DATA_pixel2, and a second terminal for receiving the polarity switch signal SW POL The second switch SW2 has a first end for receiving the sub-pixel data DATA_pixel2, a second end for receiving the sub-pixel data DATA_pixel1, and a control end for receiving the polarity switch signal SW POL control end and output end.

[0080] The first level shifter LSR1 includes an input terminal coupled to the output terminal of the first switch SW1, a positive power terminal receiving the positive system voltage PAVDD, a negative power terminal receiving the ground voltage AGND, and an output terminal. The second level shifter LSR2 includes an input terminal coupled to the output terminal of the second switch SW2, a positive power terminal, a negative power terminal receiving the ground voltage AGND, and an output terminal. The multiplexer circuit MUX includes a first input terminal receiving the negative system voltage NAVDD, a second input terminal receiving the positive system voltage PAVDD, a control terminal receiving the drive mode signal Sdm1, and an output terminal coupled to the positive power terminal of the second level shifter LSR2.

[0081] The first digital-to-analog converter DAC1 has an input terminal coupled to the output terminal of the first level converter LSR1, and an output terminal. The second digital-to-analog converter DAC2 has an input terminal coupled to the output terminal of the second level converter LSR2, and an output terminal. The third switch SW3 has an input terminal coupled to the output terminal of the first digital-to-analog converter DAC1, a control terminal that receives a polarity switch signal SWPOL, a first output terminal coupled to the first source line Lsrc1, and a second output terminal coupled to the second source line Lsrc2. The fourth switch SW4 has an input terminal coupled to the output terminal of the second digital-to-analog converter DAC2, a first output terminal coupled to the second source line Lsrc2, and a second output terminal coupled to the first source line Lsrc1.

[0082] In this embodiment, the first level shifter LSR1 and the second level shifter LSR2 are designed to perform in-phase logic level shifting when receiving the positive system voltage PAVDD, and to perform inverting logic level shifting when receiving the negative system voltage NAVDD.

[0083] Therefore, when used to drive the liquid crystal pixel DPX, the driving mode signal Sdm1 controls the multiplexer circuit MUX to provide the negative system voltage NAVDD to the second level converter LSR2, so that the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 alternately convert the sub-pixel data DATA_pixel1 and DATA_pixel2 into positive and negative voltages (e.g., Figure 1B As shown), a pair of liquid crystal source voltages Vsoutd whose voltage polarity varies with time are provided to the first source line Lsrc1 and the second source line Lsrc2; on the contrary, when used to drive the self-luminous pixel EPX, the driving mode signal Sdm1 controls the multiplexing circuit MUX to provide the positive system voltage PAVDD to the second potential converter LSR2, so that the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 alternately convert each of the sub-pixel data DATA_pixel1 and DATA_pixel2 into a voltage with only positive polarity (as shown). Figure 1C As shown), a pair of self-luminous source voltages Vsoute whose voltage polarity does not change with time are provided to the first source line Lsrc1 and the second source line Lsrc2.

[0084] In the embodiment of the present invention, the polarity switch signal SW POL The sub-pixel data DATA_pixel1 and DATA_pixel2 may be periodically switched to be alternately provided to the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2 .

[0085] In the embodiment of the present invention, the first source line Lsrc1 and the second source line Lsrc2 may be two adjacent source lines Lsrc, but the embodiment of the present invention is not limited thereto.

[0086] According to the above, the source channel 420a of the source driver (such as 120a) has a switching circuit inside, and the driving voltage of the output pin can be switched between the self-luminous source voltage Vsoute and the liquid crystal source voltage Vsoutd by setting the multiplexer circuit MUX. That is, the source driver 120a (or the source channel 420a) can be applied to the source line Lsrc to be coupled to the liquid crystal pixel DPX and the self-luminous pixel EPX at the same time. Therefore, there is no need to design circuits for the liquid crystal pixel DPX and the self-luminous pixel EPX respectively, which can simplify the circuit design and reduce hardware costs.

[0087] Figure 6 This is a schematic diagram of an application of a display device according to an embodiment of the present invention. Figure 1A and Figure 6 In this embodiment, the display device 100 is applied to a folding screen, for example. By combining the liquid crystal pixels DPX and the self-luminous pixels EPX, the width of the splicing seam can be reduced, and the visual display can be more complete.

[0088] In this embodiment, a flexible substrate SB3 connects transparent substrates SB1 and SB2. Liquid crystal pixels DPX can be arranged on the transparent substrates SB1 and SB2, and self-luminous pixels EPX can be arranged on the flexible substrate SB3 to serve as the joints between the liquid crystal pixels DPX. Therefore, compared to folding screens made with fully self-luminous pixels EPX (such as micro light-emitting diode (uLED) pixels and / or organic light-emitting diode (OLED) pixels), folding screens that use fully self-luminous pixels EPX as the joints between the liquid crystal pixels DPX can reduce production costs.

[0089] Figure 7 This is a schematic diagram of an application of a display device according to another embodiment of the present invention. Figure 1A and Figure 7 In this embodiment, the display device 100 is used, for example, in a liquid crystal television. Liquid crystal pixels DPX may be disposed on one side of a transparent substrate SB4, while self-luminous pixels EPX and a backlight module BLM may be disposed on the other side of the transparent substrate SB4 relative to the liquid crystal pixels DPX. The self-luminous pixels EPX may be disposed near an edge of the transparent substrate SB4, but the present invention is not limited thereto.

[0090] Since the atmosphere effects of currently available flat-screen TVs all require the installation of additional light strips and controllers to project the TV scene onto the back of the TV, by adopting the heterogeneous splicing effect of the display device 100 of the present invention, the connected parts of the self-luminous pixels EPX are mounted on the back of the flat-screen TV, which can achieve accurate colors consistent with the display screen without the need for additional controllers and light strips.

[0091] In summary, the display device of the embodiment of the present invention can simplify the hardware circuit implementation of the display device, reduce the number of source driver chips / timing controllers, and thereby reduce the overall cost of the display device, because the source driver can determine the positions of liquid crystal pixels and self-luminous pixels based on the driving mode data and then provide the liquid crystal source voltage or the self-luminous source voltage accordingly.

[0092] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A display device comprising: a pixel array having a plurality of liquid crystal pixels and a plurality of self-luminous pixels; A timing controller receives display data to provide driving mode data and pixel grayscale data, wherein the driving mode data is based on an arrangement position of the liquid crystal pixels and the self-luminous pixels; as well as A source driver is coupled between the pixel array and the timing controller and receives the driving mode data and the pixel grayscale data to provide a plurality of liquid crystal source voltages and a plurality of self-luminous source voltages based on the driving mode data and the pixel grayscale data, wherein the liquid crystal source voltage is provided to the liquid crystal pixels and a voltage polarity relative to a common voltage varies with time, and the self-luminous source voltage is provided to the self-luminous pixels and a voltage polarity relative to the common voltage does not vary with time.

2. A display device as described in claim 1, wherein the driving mode data includes an enable field, a channel number field, and a channel start field, wherein the enable field is used to determine a driving mode of a corresponding row in the pixel array, the channel number field represents a number of the self-luminous pixels in the corresponding row, and the channel start field represents a starting position of the self-luminous pixels in the corresponding row.

3. The display device as claimed in claim 1 , wherein the source driver comprises: a decoding circuit receiving the driving mode data, the pixel grayscale data, and polarity data to provide a plurality of sub-pixel data, a plurality of driving mode signals, and a polarity switch signal; as well as A plurality of source channels are coupled to the decoding circuit, and each of the source channels receives a first sub-pixel data and a second sub-pixel data of the sub-pixel data, receives a first driving mode signal of the driving mode signals, and the polarity switch signal to provide a pair of the liquid crystal source voltages or the self-luminous source voltages.

4. The display device as claimed in claim 3, wherein each of the source channels comprises: a first switch having a first end for receiving the first sub-pixel data, a second end for receiving the second sub-pixel data, a control end for receiving the polarity switch signal, and an output end; a second switch having a first end for receiving the second sub-pixel data, a second end for receiving the first sub-pixel data, a control end for receiving the polarity switch signal, and an output end; a first potential converter having an input terminal coupled to the output terminal of the first switch, a positive power terminal receiving a positive system voltage, a negative power terminal receiving a ground voltage, and an output terminal; a second potential converter having an input terminal coupled to the output terminal of the second switch, a positive power terminal, a negative power terminal receiving the ground voltage, and an output terminal; a multiplexer circuit having a first input terminal receiving a negative system voltage, a second input terminal receiving the positive system voltage, a control terminal receiving the first driving mode signal, and an output terminal coupled to the positive power terminal of the second potential converter; a first digital-to-analog converter having an input terminal coupled to the output terminal of the first level converter and an output terminal; a second digital-to-analog converter having an input terminal coupled to the output terminal of the second level converter, and an output terminal; a third switch having an input terminal coupled to the output terminal of the first digital-to-analog converter, a control terminal receiving the polarity switch signal, a first output terminal coupled to a first source line, and a second output terminal coupled to a second source line; as well as a fourth switch having an input terminal coupled to the output terminal of the second digital-to-analog converter, a first output terminal coupled to the second source line, and a second output terminal coupled to the first source line, The first source line and the second source line are used to receive the pair of liquid crystal source voltages or the self-luminous source voltages. 5 . The display device as claimed in claim 3 , wherein the driving mode data, the pixel grayscale data and the polarity data are packaged in a row of data. The display device as claimed in claim 5 , wherein the row data is transmitted via an integrated streaming protocol. 7 . The display device as claimed in claim 1 , wherein the self-luminous pixels comprise at least one micro light emitting diode pixel and / or at least one organic light emitting diode pixel.

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