A memory repair system based on multiple parallel BISR chains

Abstract

The application relates to the field of integrated circuit repair technology, in particular to a storage repair system based on multiple parallel BISR chains, which sets state information for each target register chain, so that a control unit can determine a current register chain according to the state information of each target register chain, reads corresponding compressed repair data in a nonvolatile memory by the current register chain, and changes the current register chain when the current register chain needs to decompress the received compressed sub-data, so that multiple target register chains can read the compressed repair data in parallel. Compared with the situation that the existing technology needs to wait for the repair of one register chain to be completed before repairing another register chain in the scheme of using multiple register chains, the storage repair efficiency can be effectively improved.

Description

A storage repair system based on multiple parallel BISR chains Technical Field

[0001] This invention relates to the field of integrated circuit repair technology, and in particular to a memory repair system based on multiple parallel BISR chains. Background Technology

[0002] With the rapid development of emerging applications such as artificial intelligence, big data, and the Internet of Things, and the continuous advancement of manufacturing processes, chips need to process increasingly larger amounts of data, leading to a greater proportion of on-chip memory. The increasing chip area and number of on-chip memory units result in a higher probability of defects in these units, posing challenges to chip yield and cost. To improve chip yield, repair solutions for on-chip memory are needed, including adding redundant arrays, adding built-in self-analysis circuitry for the on-chip memory, and adding non-volatile memory for storing and retrieving repair data analyzed by the built-in self-analysis circuitry.

[0003] When the built-in self-test (BST) detects a defect within the memory, if the memory has a redundant array, the built-in self-analysis circuitry analyzes the data to determine suitable repair data. This data is then used to select an appropriate redundant array to replace the defective row or column, thus repairing the memory. After the BST analysis is complete, the analyzed repair data is updated in the Built-in Self-Repair Register (BISR) chain. The BISR chain is connected to the controller of the on-chip non-volatile memory. By shifting the BISR chain, the repair data can be stored directly or compressed into the on-chip non-volatile memory.

[0004] In existing technologies, there are typically two types of BISR registers: external and internal, corresponding to parallel and serial repair memories, respectively. Updating repair data from the built-in self-analyzing circuit to the external BISR register is relatively simple and fast, accomplished through parallel sampling between registers, generally requiring only one to two clock cycles. However, updating repair data from the built-in self-analyzing circuit to the internal BISR register requires serial shifting, and the number of clock cycles required is proportional to the length of the internal BISR chain.

[0005] However, when using a parallel strategy to repair memory, the external BISR register requires relatively complex control logic. When there are many on-chip memories, each on-chip memory needs to have a corresponding external BISR register and control logic, which leads to an excessively large chip area. In order to simplify the control logic, the existing technology usually uses a serial strategy to repair memory. However, when there are many on-chip memories, the chain length of the formed BISR will also be long, resulting in a long memory repair time, and even causing the chip's system power-on time to fail to meet the expected requirements.

[0006] Therefore, improving the efficiency of memory repair in chips has become an urgent problem to be solved. Summary of the Invention

[0007] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0008] A storage repair system based on multiple parallel BISR chains, the system comprising: P repair modules and corresponding target register chains, non-volatile memory and corresponding control units, wherein the non-volatile memory stores compressed repair data corresponding to each target register chain, and P is a positive integer.

[0009] For any given target register chain, the target register chain determines its state information based on its own repair state and read state. The repair state is initially unrepaired, and the read state is initially requested to read.

[0010] When the current register chain does not exist, the control unit determines the current register chain from the target register chains whose status information meets the conditions.

[0011] When a current register chain exists, the control unit sends the compressed repair data corresponding to the current register chain from the non-volatile memory to the current register chain in the form of sub-data. The compressed repair data includes several sub-data, which may be uncompressed or compressed.

[0012] If the current register link receives uncompressed sub-data, it continues reading the next sub-data.

[0013] If the current register link receives compressed sub-data, then stop reading the next sub-data, decompress the latest received compressed sub-data, determine that the current register link's read state is stopped, and change the current register link to the target register link.

[0014] For any target register chain, if the target register chain has finished decompressing the latest received compressed sub-data, then the read status of the target register chain is determined to be a request read status.

[0015] If the target register link receives all the sub-data in the compressed repair data corresponding to the target register link, and the latest received compressed data has been decompressed, then the repair status of the target register link is determined to be repaired.

[0016] When all target register chains are in the repaired state, the repair of P repair modules is complete.

[0017] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the storage repair system based on multiple parallel BISR chains provided by the present invention achieves considerable technological progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0018] This invention sets status information for each target register chain, enabling the control unit to determine the current register chain based on the status information of each target register chain. The current register chain reads the corresponding compressed repair data from the non-volatile memory. When the current register chain needs to decompress the received compressed sub-data, the current register chain is changed, allowing multiple target register chains to read compressed repair data in parallel. Compared to the existing technology that uses multiple register chains and requires waiting for one register chain to be repaired before another register chain can be repaired, this invention effectively improves storage repair efficiency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 is a schematic diagram of the structure of a storage repair system based on a multi-morphological BISR chain provided in Embodiment 1 of the present invention;

[0021] Figure 2 is a schematic flowchart of a storage repair system based on multiple parallel BISR chains provided in Embodiment 2 of the present invention;

[0022] Figure 3 is a schematic diagram of a storage repair system based on multiple parallel BISR chains provided in Embodiment 2 of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] This embodiment provides a storage repair system based on a multi-morphological BISR chain. The system includes: M repair modules, non-volatile memory, and control units corresponding to the non-volatile memory. Each repair module corresponds to a first selector, and M is a positive integer.

[0025] The m-th repair module a m It contains N(m) storage units, in a m In the i-th storage unit b i There is a corresponding external register c i b i There are also corresponding repair types, which include serial and parallel types, when b i When the corresponding repair type is serial, b i Including on-chip register d i m is an integer in the range [1, M], and i is an integer in the range [1, N(m)].

[0026] In a m In the middle, when b i When it is a parallel type, b i With c i connect;

[0027] When b i When the data is of serial type, if i=1, then c i d i The input terminals are all connected to a m The corresponding output of the first selector is connected; if i ≠ 1, then c i d i The input terminals are all connected to c i-1 Connect the output terminal;

[0028] When b i When it is a parallel type, if i=1, then c i The input terminal and a m The corresponding output of the first selector is connected; if i ≠ 1, then c i The input terminal and c i-1 Connect the output terminal;

[0029] When i = N(m), if m ≠ M, then c i The output terminals are respectively connected to a m The first input terminal of the corresponding first selector and a m+1 The second input terminal of the corresponding first selector is connected; if m = M, then c i The output terminals are respectively connected to a m The first input terminal of the corresponding first selector is connected to the input terminal of the control unit;

[0030] When m=1, a m The second input terminal of the corresponding first selector is connected to the output terminal of the control unit;

[0031] When each of the first selectors selects the first input terminal, M first off-chip register chains are formed by the several off-chip registers contained in the M repair modules. The first off-chip register chains are used to support the repair of each memory unit in the corresponding repair module.

[0032] The repair module can be controlled by a Memory Built-in Self Test Controller (MBIST Controller). Each repair module can correspond to a separate MBIST Controller. Each repair module contains several memory cells, and the memory cells contained in any repair module can be configured by the implementer. The non-volatile memory can use an electrically fusible fuse (eFuse). Unlike on-chip registers and off-chip registers, non-volatile memory can retain data without an external power supply. The control unit corresponding to the non-volatile memory can be used to configure the selection status of each first selector and configure the clock frequency, thereby configuring the serial shift time of each repair module.

[0033] Specifically, the number of memory cells contained in each repair module can be different, and the repair type of the memory cells contained can be different. The repair type can include serial type and parallel type, and the on-chip register can be used to support the repair of serial type memory cells.

[0034] In a m In the middle, when b i When it is a parallel type, b i With c i Connection, c i Directly through b i The port will send the repair data to b i .

[0035] When b i When it is a serial type, d i The repair data needs to be obtained by sequentially inserting the data bit by bit. If i=1, then c i d i The input terminals are all connected to a m The output terminals of the corresponding first selectors are connected, that is, the input terminals of c1 and d1 are both connected to the output terminals of the first selectors corresponding to their respective repair modules. If i≠1, then c i d i The input terminals are all connected to c i-1 The output terminal is connected, that is, c i d i The input terminals of each are connected to the output terminals of the previous external register.

[0036] When b i When it is a parallel type, if i=1, then ci The input terminal and a m The output of the corresponding first selector is connected, that is, the input of c1 is connected to the output of the first selector corresponding to the repair module. If i≠1, then c i The input terminal and c i-1 The output terminal is connected, that is, c i The input terminals of each are connected to the output terminals of the preceding external register, thus forming a m The external register chain.

[0037] When i = N(m), it means c i For the last storage unit of the corresponding repair module, if m≠M, then c i The output terminals are respectively connected to a m The first input terminal of the corresponding first selector and a m+1 The second input terminal of the corresponding first selector is connected, that is, when c i When the repair module is not the last repair module, c i Connect c to the first input terminal of the first selector corresponding to the current repair module and the second input terminal of the first selector corresponding to the next repair module, respectively. If m=M, then c i The output terminals are respectively connected to a m The first input terminal of the corresponding first selector is connected to the input terminal of the control unit, that is, when c i When the repair module is the last repair module, c i Each is connected to the first input terminal of the first selector corresponding to its respective repair module and the input terminal of the control unit of the non-volatile memory.

[0038] When m=1, it means a m For the first repair module, a m The second input terminal of the corresponding first selector is connected to the output terminal of the control unit; that is, the second input terminal of the first selector corresponding to the first repair module is connected to the output terminal of the control unit.

[0039] When all first selectors activate the first input, M first off-chip register chains are formed by the various off-chip registers contained in the M repair modules. The identifier of the first input can be 1, and correspondingly, the identifier of the second input can be 0. When all first selectors activate the first input, for any repair module, the input of the first storage unit in the repair module receives the data from the output of the last storage unit in the repair module. That is, the repair module only serially transmits the repair data in its contained off-chip registers, without needing repair data outside the repair module. Thus, each repair module corresponds to a first off-chip register chain.

[0040] Referring to Figure 1, which is a schematic diagram of a storage repair system based on a multi-morphological BISR chain provided in Embodiment 1 of the present invention, the schematic diagram uses two repair modules, each containing three storage units, as an example. For ease of distinction, the two repair modules are labeled as repair module 1 and repair module 2, respectively. The three storage units contained in repair module 1 are storage unit 11, storage unit 12, and storage unit 13, where storage unit 12 is of parallel type and storage unit 11 and storage unit 13 are of serial type. The three storage units contained in repair module 2 are storage unit 21, storage unit 22, and storage unit 23, where storage unit 22 is of serial type and storage unit 21 and storage unit 23 are of parallel type.

[0041] The first external register chain is used to support the repair of each memory unit in the corresponding repair module. When the memory unit in the repair module needs to be repaired, a single repair module performs serial transmission of repair data through its corresponding first external register chain. It can be known that if the sum of the chain lengths of the various external registers included in the first external register chain is L, then the repair module can complete the serial transmission after serially shifting L bits through its corresponding first external register chain.

[0042] In one specific implementation, the on-chip register includes an input terminal, a clock port, and a reset port, wherein the reset port is used to initialize the state of the corresponding on-chip register;

[0043] When repairing any serial-type memory cell, the on-chip register corresponding to that memory cell receives a clock signal through the clock port and transmits the repair data bit by bit according to the clock signal.

[0044] The clock port can be used to receive clock signals provided by the control unit of the non-volatile memory, thereby controlling the shift time interval of the on-chip registers.

[0045] In one specific implementation, when b i When it is a parallel type, b i Including the input end;

[0046] When repairing any parallel type of memory cell, the memory cell receives repair data through its included inputs.

[0047] Among them, the parallel type storage unit can directly receive the repair data through the input terminal without shifting and serializing. That is, the input terminal bit width of the parallel type storage unit is the same as the sum of the repair data bit width and the repair enable flag bit width.

[0048] In one specific implementation, the on-chip register further includes an output terminal, and each serial-type memory cell corresponds to a second selector;

[0049] Accordingly, when b i When the type is serial, if i ≠ 1 and b i-1 The corresponding repair type is serial, then c i d i The input terminals are all connected to b i-1 Connect the output terminal of the corresponding second selector;

[0050] When b i When it is a parallel type, if i≠1 and b i-1 The corresponding repair type is serial, then c i The input terminal and b i-1 Connect the output terminal of the corresponding second selector;

[0051] When b i When it is a serial type, c i The output terminal and b i The first input terminal of the corresponding second selector is connected, d i The output terminal and b i The second input terminal of the corresponding second selector is connected.

[0052] The second selector can be used to select the output of the external register and the output of the internal register.

[0053] In one specific implementation, when it is necessary to perform a path test on the on-chip register, each second selector is selected to activate its second input terminal.

[0054] In the testing phase, in order to test the path of the on-chip registers, this embodiment selects the second input terminal through the second selector. That is, the output of the on-chip register of the current memory cell is sent to the next memory cell through the second selector, instead of the output of the off-chip register of the current memory cell. This allows the validity of each on-chip register to be determined during the path testing phase.

[0055] In one specific implementation, when all the first selectors select the second input, a second off-chip register chain is formed by all off-chip registers. The second off-chip register chain is used to support the non-volatile memory in recording the repair data of each off-chip register.

[0056] When all the first selectors select the second input terminal, a second off-chip register chain is formed by all the off-chip registers included in each repair module. This second off-chip register chain is used to perform serial shifting when the non-volatile memory has not yet stored the repair data of each memory cell, so as to directly or compress the repair data of each off-chip register into the non-volatile memory.

[0057] In one specific implementation, each memory cell has a built-in self-analysis circuit, which is used to analyze the repair data of the corresponding memory cell and send the repair data of the corresponding memory cell to the off-chip register of the corresponding memory cell.

[0058] For any repair module, the chain length corresponding to the repair module is determined based on the total bit width of the repair data in each storage unit contained in the repair module.

[0059] The repair time of the repair module is determined based on the chain length corresponding to the repair module and the preset clock period;

[0060] The maximum repair time among all repair modules is used as the overall repair time.

[0061] Based on the total time consumption and the preset time consumption threshold, determine the repair module to which each storage unit belongs.

[0062] When the first external register chain is used to repair the memory unit, the overall time is the maximum repair time of each first external register chain. When the overall time is less than the preset time threshold, the overall memory repair time can be considered to meet the expectations, and the current repair module division method can be used for repair. When the overall time is greater than or equal to the preset time threshold, the overall memory repair time can be considered to exceed the expectations, and the memory units contained in the repair module need to be adjusted. The adjustment method can include adding a repair module or adjusting the memory units in the repair module to other repair modules. The implementer can determine the adjustment method of each repair module according to the actual situation.

[0063] In one specific implementation, each repair module corresponds to a shift counter;

[0064] For any repair module, the bit width of the shift counter corresponding to the repair module is determined according to the chain length corresponding to the repair module;

[0065] The area increase is determined based on the bit width of the shift counter corresponding to each repair module.

[0066] Based on the increase in area and the preset increase threshold, the repair module to which each storage unit belongs is determined.

[0067] When the first external register chain is used to repair the memory cell, additional control logic needs to be added to the repair module, which increases the chip area. The increase in chip area is mainly related to the bit width of the shift counter.

[0068] When the increase in area is greater than or equal to the preset increase threshold, it can be considered that the increase in area exceeds expectations, and the storage units contained in each repair module need to be adjusted. When the increase in area is less than the preset increase threshold, it can be considered that the increase in area meets expectations, and the current repair module division method can be used for repair.

[0069] In one embodiment, the division method of the repair module is determined in conjunction with the overall time consumption and the area increase. If only the overall time consumption is considered, it is obvious that the overall time consumption of a single storage unit as a repair module is the lowest. If only the area increase is considered, it is obvious that the area increase is the lowest when all storage units are treated as a repair module. Only when the overall time consumption is less than a preset time consumption threshold and the area increase is less than a preset increase threshold can a reasonable repair module division method be obtained.

[0070] In this first embodiment, the memory cells in the chip are divided into multiple repair modules. Each repair module contains several off-chip registers, forming multiple first off-chip register chains. When repairing the memory cells in the chip, repair can be performed simultaneously through multiple first off-chip register chains. The repair time of the chip memory cells is determined based on the maximum chain length of each first off-chip register chain. Compared with the prior art, where the repair time of the chip memory cells is determined by the sum of the chain lengths of all off-chip registers, this greatly reduces the memory repair time and improves the memory repair efficiency. Furthermore, during the memory repair process, the memory cells can be repaired in parallel or serial mode, and the memory repair can be compatible with memory cells of different repair types.

[0071] This embodiment 2 provides a storage repair system based on multiple parallel BISR chains. The system includes: P repair modules and corresponding target register chains, non-volatile memory and corresponding control units, wherein the non-volatile memory stores compressed repair data corresponding to each target register chain, and P is a positive integer;

[0072] For any target register chain, the target register chain determines its status information based on its repair status and read status. The repair status is initially unrepaired, and the read status is initially requested to be read.

[0073] When the current register chain does not exist, the control unit determines the current register chain from the target register chains whose status information meets the conditions.

[0074] When a current register chain exists, the control unit sends the compressed repair data corresponding to the current register chain from the non-volatile memory to the current register chain in the form of sub-data. The compressed repair data includes several sub-data, which are either uncompressed or compressed sub-data.

[0075] If the current register link receives uncompressed sub-data, continue reading the next sub-data;

[0076] If the current register link receives compressed sub-data, then stop reading the next sub-data, decompress the latest received compressed sub-data, determine that the current register link's read state is stopped, and change the current register link to the target register link;

[0077] For any target register chain, if the target register chain has finished decompressing the latest received compressed sub-data, then the read status of the target register chain is determined to be a read request status.

[0078] If the target register link receives all the sub-data in the compressed repair data corresponding to the target register chain, and the latest received compressed data has been decompressed, then the repair status of the target register chain is determined to be repaired.

[0079] When all target register chains are in the repaired state, the repair of P repair modules is complete.

[0080] The target register chain supports the repair of each storage unit in the corresponding repair module. When a storage unit in the repair module needs to be repaired, a single repair module serially transmits repair data through its corresponding target register chain. In this embodiment, the target register chain is stored in non-volatile memory in compressed form, which is represented by compressed repair data. The repair data is binary data. When any data bit in the repair data is 1, it indicates that the array corresponding to that data bit needs to be repaired; when any data bit in the repair data is 0, it indicates that the array corresponding to that data bit does not need to be repaired. In this embodiment, the compression method specifically involves compressing the repair data bit by bit. Data is sent to non-volatile memory. If the current data bit is 1, it is sent to non-volatile memory as uncompressed sub-data. If the current data bit is 0, the number of consecutive 0 data bits is counted, and the count result is sent to non-volatile memory as compressed sub-data. For W consecutive 0 data bits, only log2W bits of compressed sub-data are needed to store them in non-volatile memory, effectively saving storage space in non-volatile memory. Since the number of fault arrays in a chip is usually not too large, otherwise it would be considered a waste chip, the compression method in this embodiment can usually achieve a high compression ratio.

[0081] Referring to Figure 2, it is a schematic diagram of a storage repair system based on multiple parallel BISR chains provided in Embodiment 2 of the present invention, where Y represents that the corresponding condition is met and N represents that the corresponding condition is not met.

[0082] Specifically, when the current register chain receives compressed sub-data, it needs to decompress the compressed sub-data by decrementing a counter. It can be seen that for compressed sub-data with a width of log2W bits, it takes W clock cycles to complete the decompression. During these W clock cycles used for decompression, the current register chain will not continue to receive sub-data. Therefore, in order to improve the repair efficiency, this embodiment changes the current register chain to the target register chain when the current register chain decompresses the latest received compressed sub-data. After the change, there may be a situation where the current register chain does not exist. The control unit needs to determine the new current register chain from each target register chain that meets the status information conditions. However, the target register chain corresponding to the previous current register chain cannot be determined as the current register chain again when it is in the process of decompression.

[0083] In one specific implementation, the status information includes a busy status and an idle status;

[0084] The target register chain determines its status information based on its repair and read status, including:

[0085] If the repair status of the target register chain is unrepaired and the read status of the target register chain is requested to be read, then the status information of the target register chain is determined to be busy.

[0086] Otherwise, determine that the target register chain is in an idle state.

[0087] The busy state indicates that the corresponding target register chain needs to read the corresponding compressed repair data from non-volatile memory, while the idle state indicates that the corresponding target register chain does not need to read the corresponding compressed repair data from non-volatile memory.

[0088] Specifically, when the repair status of any target register chain is unrepaired and the read status of the target register chain is stopped, the status information of the target register chain is idle.

[0089] When the repair status of any target register chain is repaired, the status information of that target register chain is also idle.

[0090] In one specific implementation, the step of determining the current register chain from among the target register chains whose status information satisfies the conditions when no current register chain exists includes:

[0091] When the current register chain does not exist, the control unit determines the current register chain from the target register chains whose status information is busy.

[0092] Since the busy state indicates that the corresponding target register chain needs to read the corresponding compressed repair data from non-volatile memory, the current register chain is determined from each target register chain whose status information is busy.

[0093] In one specific implementation, the step of determining the current register chain from among the target register chains whose status information is busy when no current register chain exists includes:

[0094] When there is no current register chain, the control unit arbitrates a target register chain from each target register chain whose status information is busy, according to a preset priority, to serve as the current register chain.

[0095] Since all target register chains need to be repaired when the repair is completed, there is no need to set special priorities. In this embodiment, the preset priority order can be set according to the identifier of the target register chain, that is, the first target register chain has the highest priority and the last target register chain has the lowest priority.

[0096] It should be noted that implementers may choose other arbitration methods, such as polling arbitration, depending on the actual situation. Regardless of the arbitration method used to determine the current register chain, it is within the protection scope of this embodiment.

[0097] In one specific implementation, the p-th repair module f p It contains S(p) storage units, in f p In the middle, the g-th storage unit h g There is a corresponding off-chip register k g h g There are also corresponding repair types, which include serial and parallel types, when h g When the corresponding repair type is serial, h g Including on-chip registers g When h g When the corresponding repair type is parallel, p is an integer in the range [1, P] and g is an integer in the range [1, S(p)].

[0098] In f p In the middle, by f p The S(p) off-chip registers form the p-th destination register chain, where, when h g When it is a parallel type, k g with hg connect;

[0099] When h g When the data is of serial type, if g=1, then k g l g The input terminals are all connected to the output terminals of the control unit. If g≠1, then k g l g The input terminals are all connected to k g-1 Connect the output terminal;

[0100] When h g When it is a parallel type, if g=1, then k g The input terminal is connected to the output terminal of the control unit. If g≠1, then k g The input terminal and k g-1 Connect the output terminal;

[0101] When g = S(p), k g The output terminal is connected to the input terminal of the control unit.

[0102] Each repair module can be controlled by a control unit. Each repair module contains several storage units. The storage units contained in any repair module can be configured by the implementer. Non-volatile memory can use an electrically fusible fuse (eFuse). Unlike on-chip registers and off-chip registers, non-volatile memory can retain data without an external power supply. The control unit corresponding to the non-volatile memory can also be used to configure the clock frequency and thus configure the serial shift time of each repair module.

[0103] Specifically, the number of memory cells contained in each repair module can be different, and the repair type of the memory cells contained can be different. The repair type can include serial type and parallel type, and the on-chip register can be used to support the repair of serial type memory cells.

[0104] In f p In the middle, when h g When it is a parallel type, k g with h g Connection, k g Directly via h g The port will send the repair data to h g When h g When it is a serial type, l g The repair data needs to be obtained by sequentially inserting the data bit by bit.

[0105] Referring to Figure 3, which is a schematic diagram of a storage repair system based on multiple parallel BISR chains provided in Embodiment 2 of the present invention, the schematic diagram uses two repair modules, each containing three storage units, as an example. For ease of distinction, the two repair modules are labeled as repair module 3 and repair module 4, respectively. The three storage units contained in repair module 3 are storage unit 31, storage unit 32, and storage unit 33, respectively. Storage unit 32 is of parallel type, and storage unit 31 and storage unit 33 are of serial type. The three storage units contained in repair module 4 are storage unit 41, storage unit 42, and storage unit 43, respectively. Storage unit 42 is of serial type, and storage unit 41 and storage unit 43 are of parallel type.

[0106] In one specific implementation, the on-chip register includes an input terminal, a clock port, and a reset port, wherein the reset port is used to initialize the state of the corresponding on-chip register;

[0107] When repairing any serial-type memory cell, the on-chip register corresponding to that memory cell receives a clock signal through the clock port and transmits the repair data bit by bit according to the clock signal.

[0108] The clock port can be used to receive clock signals provided by the control unit of the non-volatile memory, thereby controlling the shift time interval of the on-chip registers.

[0109] In one specific implementation, when h g When it is a parallel type, h g Including the input end;

[0110] When repairing any parallel type of memory cell, the memory cell receives repair data through its included inputs.

[0111] Among them, the parallel type storage unit can directly receive the repair data through the input terminal without shifting and serializing. That is, the input terminal bit width of the parallel type storage unit is the same as the sum of the repair data bit width and the repair enable flag bit width.

[0112] In one specific implementation, the on-chip register further includes an output terminal, and each serial-type memory cell corresponds to a second selector;

[0113] Accordingly, when h g When it is a serial type, if g≠1 and h g-1 The corresponding repair type is serial, then k g l g The input terminals are all connected to h g-1 Connect the output terminal of the corresponding second selector;

[0114] When hg When it is a parallel type, if g≠1 and h g-1 The corresponding repair type is serial, then k g The input terminal and h g-1 Connect the output terminal of the corresponding second selector;

[0115] When h g When it is a serial type, k g The output terminal and h g The first input terminal of the corresponding second selector is connected, l g The output terminal and h g The second input terminal of the corresponding second selector is connected.

[0116] The second selector can be used to select the output of the external register and the output of the internal register. When the second selector selects the second input terminal, the path test of the internal register can be performed. That is, the output of the internal register of the current memory cell is sent to the next memory cell through the second selector, instead of the output of the external register of the current memory cell. Thus, the validity of each internal register can be determined during the path test phase.

[0117] It should be noted that the multi-form BISR chain provided in Embodiment 1 and the multiple parallel BISR chains provided in Embodiment 2 can coexist in one MBIST repair system. For example, the target register chain in Embodiment 2 can contain multiple repair sub-modules, and each repair sub-module corresponds to a first external register chain.

[0118] In this second embodiment, status information is set for each target register chain, so that the control unit can determine the current register chain based on the status information of each target register chain. The current register chain reads the corresponding compressed repair data from the non-volatile memory. When the current register chain needs to decompress the received compressed sub-data, the current register chain is changed, so that multiple target register chains can read compressed repair data in parallel. Compared with the existing technology that uses multiple register chains and requires waiting for one register chain to be repaired before another register chain can be repaired, this can effectively improve the storage repair efficiency.

[0119] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A storage repair system based on multiple parallel BISR chains, characterized in that, The system includes: P repair modules and corresponding target register chains, non-volatile memory and corresponding control units, wherein the non-volatile memory stores compressed repair data corresponding to each target register chain, and P is a positive integer; for any target register chain, the target register chain determines its status information based on its own repair status and read status, with the initial repair status being unrepaired and the initial read status being a request to read; when the current register chain does not exist, the control unit determines the current register chain from among the target register chains whose status information meets the conditions; when the current register chain exists, the control unit sends the compressed repair data corresponding to the current register chain from the non-volatile memory in a sub-data manner, wherein the compressed repair data includes several sub-data, and the sub-data belongs to uncompressed sub-data or already compressed sub-data. Compress sub-data; if the current register link receives uncompressed sub-data, continue reading the next sub-data; if the current register link receives compressed sub-data, stop reading the next sub-data, decompress the latest received compressed sub-data, determine the current register chain's read state as stopped reading, and change the current register chain to the target register chain; for any target register chain, if the target register chain has completely decompressed the latest received compressed sub-data, determine the target register chain's read state as requested reading; if the target register link receives all sub-data in the compressed repair data corresponding to the target register chain, and the latest received compressed data has been completely decompressed, determine the target register chain's repair state as repaired; when the repair states corresponding to all target register chains are all in the repaired state, the repair of P repair modules is completed.

2. The storage repair system based on multiple parallel BISR chains according to claim 1, characterized in that, The status information includes a busy status and an idle status; the target register chain determines its status information based on its repair status and read status, including: if the repair status of the target register chain is unrepaired and the read status of the target register chain is requested to read, then the status information of the target register chain is determined to be busy; otherwise, the status information of the target register chain is determined to be idle.

3. The storage repair system based on multiple parallel BISR chains according to claim 2, characterized in that, The step of determining the current register chain from the target register chains whose status information meets the conditions when there is no current register chain includes: determining the current register chain from the target register chains whose status information is busy when there is no current register chain.

4. The storage repair system based on multiple parallel BISR chains according to claim 3, characterized in that, The step of determining the current register chain from among the target register chains whose status information is busy when there is no current register chain includes: when there is no current register chain, the control unit arbitrates a target register chain as the current register chain from among the target register chains whose status information is busy according to a preset priority.

5. The storage repair system based on multiple parallel BISR chains according to claim 1, characterized in that, The p-th repair module f p It contains S(p) storage units, in f p In the middle, the g-th storage unit h g There is a corresponding off-chip register k g h g There are also corresponding repair types, which include serial and parallel types, when h g When the corresponding repair type is serial, h g Including on-chip registers g p is an integer in the range [1, P], and g is an integer in the range [1, S(p)]; in f p In the middle, by f p The S(p) off-chip registers form the p-th destination register chain, where, when h g When it is a parallel type, k g with h g Connection; when h g When the data type is serial, if g=1, then k g l g The input terminals are all connected to the output terminals of the control unit. If g≠1, then k g l g The input terminals are all connected to k g-1 The output terminal is connected; when h g When it is a parallel type, if g=1, then k g The input terminal is connected to the output terminal of the control unit. If g≠1, then k g The input terminal and k g-1 The output terminal is connected; when g = S(p), k g The output terminal is connected to the input terminal of the control unit.

6. The storage repair system based on multiple parallel BISR chains according to claim 5, characterized in that, The on-chip register includes an input terminal, a clock port, and a reset port. The reset port is used to initialize the state of the corresponding on-chip register. When repairing any serial-type memory cell, the on-chip register corresponding to that memory cell receives a clock signal through the clock port and transmits the repair data bit by bit according to the clock signal.

7. The storage repair system based on multiple parallel BISR chains according to claim 5, characterized in that, When h g When it is a parallel type, h g Includes input terminals; when repairing any parallel type of storage unit, that storage unit receives repair data through its included input terminals.

8. The storage repair system based on multiple parallel BISR chains according to claim 6, characterized in that, The on-chip register also includes an output terminal, and each serial-type memory cell corresponds to a second selector; correspondingly, when h g When it is a serial type, if g≠1 and h g-1 The corresponding repair type is serial, then k g l g The input terminals are all connected to h g-1 The corresponding output of the second selector is connected; when h g When it is a parallel type, if g≠1 and h g-1 The corresponding repair type is serial, then k g The input terminal and h g-1 The corresponding output of the second selector is connected; when h g When it is a serial type, k g The output terminal and h g The first input terminal of the corresponding second selector is connected, l g The output terminal and h g The second input terminal of the corresponding second selector is connected.

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