Chip piezoresistor and electronic equipment

Abstract

The invention discloses a chip varistor and electronic equipment, and a voltage-sensitive ceramic main body of the chip varistor comprises a first material layer and a second material layer. The first material layer and the second material layer are stacked, and an inner electrode is arranged between the adjacent first material layer and second material layer. The first material layer and the second material layer are made of different ceramic materials, and potential gradient difference is formed between the adjacent first material layer and second material layer. When the first material layer, the second material layer and the cover plate structure in the chip varistor disclosed by the invention are stacked, at least three inner electrodes can be arranged in the chip varistor. A potential gradient layer exists between every two adjacent inner electrodes in the three inner electrodes, namely at least two potential gradient layers are formed by the three inner electrodes. And when the two potential gradient layers are overlapped, the surge response range of the chip piezoresistor is enlarged, so that the chip piezoresistor can cope with large-range surges, and the chip piezoresistor is prevented from being damaged due to surge impact.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to a chip varistor and electronic equipment. Background Art

[0002] Chip varistors are commonly found in electronic devices today. Compared to traditional overcurrent and overvoltage protection components, chip varistors offer advantages such as fast response, compact size, light weight, and low power consumption. However, in some electronic devices, chip varistors may be exposed to a wide range of surges, such as current and voltage surges. For example, multilayer varistors can be subject to voltage surges ranging from 10V to 2.8kV.

[0003] Chip varistors in related technologies mostly use a single base material. Due to the limitation of the single material, the chip varistor can usually only respond to a single current surge or voltage surge, or the surge range it responds to is fixed. When the surge range exceeds the surge response range of the chip varistor, long-term use may cause the chip varistor to overheat or even burn out and be damaged, affecting the reliability of electronic equipment. Summary of the Invention

[0004] The embodiments of the present application disclose a chip varistor and an electronic device for improving the surge protection range of the chip varistor.

[0005] To achieve the above objectives, in a first aspect, the present application discloses a chip varistor, comprising:

[0006] A varistor ceramic body, the varistor ceramic body comprising a first material layer and a second material layer, the first material layer and the second material layer being stacked along a thickness direction of the varistor ceramic body, the first material layer and the second material layer being made of different ceramic materials so as to form a potential gradient difference between adjacent first material layers and second material layers;

[0007] a cover plate structure, the cover plate structure comprising an upper cover plate and a lower cover plate, wherein along the thickness direction of the piezoresistive ceramic body, the upper cover plate is located on the upper side of the first material layer, and the lower cover plate is located on the lower side of the second material layer;

[0008] Two external electrodes, the two external electrodes are respectively arranged at two ends of the piezoresistive ceramic body and the cover plate structure along the length direction of the piezoresistive ceramic body;

[0009] There are at least three internal electrodes, and along the thickness direction of the varistor ceramic body, an internal electrode is provided between the upper cover plate and the first material layer, between the lower cover plate and the second material layer, and between the first material layer and the second material layer. Each of the internal electrodes extends along the length direction of the varistor ceramic body so that one end of each of the internal electrodes is alternately connected to the external electrode.

[0010] As an optional implementation manner, the potential gradient difference between adjacent first material layers and second material layers is ΔE, and the ΔE satisfies: 100 V / mm≤ΔE≤500 V / mm.

[0011] As an optional implementation manner, the dielectric constant of the first material layer is ε1, and the dielectric constant of the second material layer is ε2, satisfying: ε1 / ε2≥1.5, or, ε2 / ε1≥1.5.

[0012] As an optional implementation, the bismuth content of the first material layer is a1, the bismuth content of the second material layer adjacent to the first material layer is a2, the difference between a1 and a2 is Δa, and Δa satisfies: Δa≥1wt%.

[0013] As an optional embodiment, the adjacent first material layer and the second material layer both contain multiple additives, the number of types of the additives in the first material layer is S1, the number of types of the additives in the second material layer is S2, the difference between S1 and S2 is ΔS, and ΔS satisfies: ΔS≥2.

[0014] As an optional embodiment, the upper cover plate is made of ceramic material, and the ceramic material of the upper cover plate is the same as or different from that of the first material layer and / or the second material layer; and / or,

[0015] The lower cover plate is made of ceramic material, and the ceramic material of the lower cover plate is the same as or different from that of the first material layer and / or the second material layer.

[0016] As an optional embodiment, when the ceramic material of the upper cover plate is different from that of the first material layer and / or the second material layer, the inner electrode is provided between the upper cover plate and the piezoresistive ceramic body along the thickness direction of the piezoresistive ceramic body; and / or,

[0017] When the ceramic material of the lower cover plate and the first material layer and / or the second material layer is different, the inner electrode is provided between the lower cover plate and the varistor ceramic body.

[0018] As an optional embodiment, the pressure-sensitive ceramic body further includes at least two first material layers, at least two second material layers, and at least two third material layers;

[0019] Along the thickness direction of the varistor ceramic body, the first material layer, the second material layer and the third material layer are sequentially arranged to construct a combined material layer, and the two combined material layers are stacked; or,

[0020] Along the thickness direction of the varistor ceramic body, the two first material layers and the two second material layers are alternately arranged, and the two third material layers are respectively located at the outermost sides of the varistor ceramic body.

[0021] As an optional embodiment, when the first material layer, the second material layer and the third material layer are arranged sequentially along the thickness direction of the varistor ceramic body, the potential gradients of the first material layer, the second material layer and the third material layer change sequentially, and / or the dielectric constants of the first material layer, the second material layer and the third material layer change sequentially.

[0022] In a second aspect, the present application further discloses an electronic device, comprising:

[0023] The chip varistor as described in the first aspect.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] The present application discloses a chip varistor and an electronic device. The chip varistor includes a varistor ceramic body, a cover plate structure, an external electrode, and an internal electrode. The varistor ceramic body includes a first material layer and a second material layer, and the first material layer and the second material layer are stacked along the thickness direction of the varistor ceramic body, and the ceramic materials of the first material layer and the second material layer are different, so that a potential gradient difference is formed between adjacent first material layers and second material layers. The upper cover plate of the cover plate structure is arranged on the first material layer, and the lower cover plate is arranged under the second material layer. The internal electrode is arranged between the adjacent first material layer and second material layer, the upper cover plate and the first material layer, and the lower cover plate and the second material layer. In the chip varistor disclosed in the present application, since the adjacent first material layer and the second material layer are made of different ceramic materials, a potential gradient difference can be formed between adjacent material layers. In this way, a potential gradient layer is formed between two adjacent inner electrodes among the three inner electrodes, that is, the three inner electrodes form at least two potential gradient layers. Among them, since a group of potential gradient layers can respond to surges within a certain range, when the two potential gradient layers are superimposed, the chip varistor increases the surge response range, so that the chip varistor can cope with larger current surges or voltage surges, avoiding the chip varistor from being damaged due to exceeding the surge range, and improving the service life of the chip varistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 A schematic structural diagram of a chip varistor disclosed in an embodiment of the present application;

[0028] Figure 2 Schematic diagram of the first internal structure of the chip varistor disclosed in the embodiment of the present application;

[0029] Figure 3 This is a schematic diagram of the second internal structure of the chip varistor disclosed in the embodiment of the present application;

[0030] Figure 4 This is a schematic diagram of the third internal structure of the chip varistor disclosed in the embodiments of the present application;

[0031] Figure 5 This is a schematic diagram of the fourth internal structure of the chip varistor disclosed in the embodiments of the present application;

[0032] Figure 6 This is a schematic diagram of the fifth internal structure of the chip varistor disclosed in the embodiments of the present application;

[0033] Figure 7 This is a schematic diagram of the sixth internal structure of the chip varistor disclosed in the embodiments of the present application;

[0034] Figure 8 Schematic diagram of the seventh internal structure of the chip varistor disclosed in the embodiments of the present application;

[0035] Figure 9 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application.

[0036] Description of reference numerals:

[0037] 100. Chip varistor; 1. Varistor ceramic body; 1a. Composite material layer; 11. First material layer; 12. Second material layer; 13. Third material layer; 2. External electrode; 3. Internal electrode; 41. Upper cover; 42. Lower cover;

[0038] 200. Electronic equipment; 201. Circuit board. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0040] In this application, terms such as "upper," "lower," "inner," and "outer" indicate positions or locations based on those shown in the accompanying drawings. These terms are intended to better describe this application and its embodiments and are not intended to limit the devices, elements, or components indicated to specific positions, or to their construction or operation in a specific position.

[0041] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to indicate a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0042] Furthermore, the terms "installed," "disposed," "equipped with," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0043] Furthermore, the terms "first," "second," etc., are primarily used to distinguish between different devices, elements, or components (which may or may not be of the same type and configuration), and are not intended to indicate or imply the relative importance or quantity of the devices, elements, or components indicated. Unless otherwise specified, "plurality" means two or more.

[0044] Chip varistors are commonly found in electronic devices, providing overvoltage protection, lightning protection, surge current suppression, spike pulse absorption, amplitude limiting, high-voltage arc extinguishing, noise reduction, and semiconductor component protection. Compared to traditional overcurrent and overvoltage protection components, chip varistors offer advantages such as fast response, small size, light weight, and low power consumption. However, in some electronic devices, chip varistors may be exposed to wide-range surges, such as current surges and voltage surges. Taking voltage surges as an example, multilayer varistors are typically subject to voltage surges ranging from 10V to 2.8kV.

[0045] The chip varistors in the related art mostly use a single material base material, such as a single zinc oxide (ZnO) as the base material system, and adjust the number of layers of the zinc oxide substrate by stacking to optimize its performance. However, due to the limitation of its material singleness, the homogeneous structure leads to a fixed potential gradient (for example, the potential gradient is 200V / mm-400V / mm), resulting in the chip varistor usually only being able to respond to a single current surge or voltage surge, or the surge range of its response is fixed. When the surge range exceeds the surge response range of the chip varistor, such as in the case of wide-range surge impact in high-power scenarios such as new energy, power systems, and 5G base stations, long-term use may cause the chip varistor to overheat or even burn out and be damaged, affecting the reliability of electronic equipment.

[0046] Based on this, the present application discloses a chip varistor. Through the stacking and structural design of different ceramic material layers, a multi-layer potential gradient is formed inside the chip varistor, thereby expanding the surge protection range and improving the service life of the chip varistor.

[0047] The technical solution of the present application will be further described below with reference to the embodiments and drawings.

[0048] First, please refer to Figures 1 to 3 The present application discloses a chip varistor 100, which includes a varistor ceramic body 1, an external electrode 2, an internal electrode 3 and a cover plate structure. The varistor ceramic body 1 includes a first material layer 11 and a second material layer 12, which are stacked along the thickness direction of the varistor ceramic body 1. The ceramic materials of the first material layer 11 and the second material layer 12 are different, so that a potential gradient difference is formed between the adjacent first material layers 11 and second material layers 12. The cover plate structure includes an upper cover plate 41 and a lower cover plate 42. Along the thickness direction of the varistor ceramic body, the upper cover plate 41 is arranged above the first material layer 11, and the lower cover plate 42 is arranged below the second material layer 12. The two external electrodes 2 are respectively arranged at the two ends of the varistor ceramic body 1 and the cover plate structure along the length direction. There are at least three internal electrodes 3. Along the thickness direction of the varistor ceramic body 1, an internal electrode 3 is provided between the upper cover plate 41 and the first material layer 11, between the lower cover plate 42 and the second material layer 12, and between the first material layer 11 and the second material layer 12. Each internal electrode 3 extends along the length direction of the varistor ceramic body 1 so that one end of each internal electrode 3 is alternately connected to the external electrode 2.

[0049] Because the ceramic materials between the adjacent first material layers 11 and second material layers 12 are different, a potential gradient can be formed between two adjacent internal electrodes 3. Therefore, when there are at least three internal electrodes 3 in the varistor ceramic body 1, at least two layers of potential gradient can be formed. When the two layers of potential gradient are superimposed, the chip varistor 100 increases its surge response range, allowing it to handle larger current surges or voltage surges, preventing the chip varistor 100 from being damaged by surges exceeding the surge range, and thus extending the service life of the chip varistor 100.

[0050] For example, Figure 2 As shown, in the thickness direction of the varistor ceramic body 1, the lower cover plate 42 is located at the bottom, and then the second material layer 12, the first material layer 11 and the upper cover plate 41 are arranged in sequence from bottom to top.

[0051] Optionally, the upper cover plate 41 is made of the same material as the second material layer 12 , and the lower cover plate 42 is made of the same material as the second material layer 12 .

[0052] For example, Figure 3 As shown, in the thickness direction of the varistor ceramic body 1, the first material layer 11 is located at the bottom, and then the second material layer 12, the first material layer 11, and the second material layer 12 are arranged in sequence from bottom to top, and the internal electrode 3 is provided between the adjacent first material layer 11 and the second material layer 12. It can be understood that the first material layer 11 and the second material layer 12 are not limited to the bottom position. For example, the second material layer 12 can also be located at the bottom, and then the second material layer 12, the first material layer 11, the second material layer 12, and the first material layer 11 are arranged in sequence from bottom to top.

[0053] Optionally, the first material layer 11 may be a multi-layer structure, and the second material layer 12 may be a multi-layer structure, and the multi-layer first material layer 11 and the multi-layer second material layer 12 are alternately arranged in sequence.

[0054] It is understood that when multiple first material layers 11 and multiple second material layers 12 are alternately arranged, the number of internal electrodes 3 increases accordingly, forming multiple sets of potential gradient differences. For example, when there are two or more first material layers 11 and two or more second material layers 12, the number of internal electrodes 3 can be four or more, as long as one internal electrode 3 is located between adjacent first material layers 11 and second material layers 12.

[0055] Optionally, the first material layer 11 and the second material layer 12 may use pressure-sensitive ceramic materials such as silicon carbide, titanium dioxide, strontium titanate or zinc oxide as a base material, which is not specifically limited in this application.

[0056] It should be noted that in Figure 2In the example, the direction indicated by X is the length direction of the varistor ceramic body 1, and the direction indicated by Y is the thickness direction of the varistor ceramic body 1. Of course, the above directions are only examples.

[0057] In some embodiments, the potential gradient difference between adjacent first material layers 11 and second material layers 12 is ΔE, and ΔE satisfies: 100 V / mm≤ΔE≤500 V / mm.

[0058] For example, ΔE may be 100V / mm-150V / mm, 150V / mm-200V / mm, 200V / mm-250V / mm, 250V / mm-300V / mm, 300V / mm-350V / mm, 350V / mm-400V / mm, 400V / mm-450V / mm, 450V / mm-500V / mm, etc. For example, ΔE may be 100 V / mm, 125 V / mm, 150 V / mm, 175 V / mm, 200 V / mm, 225 V / mm, 250 V / mm, 275 V / mm, 300 V / mm, 325 V / mm, 350 V / mm, 375 V / mm, 400 V / mm, 425 V / mm, 450 V / mm, 475 V / mm, or 500 V / mm, etc.

[0059] In the chip varistor 100 disclosed in the present application, since a larger surge protection range is required, the potential gradient difference between the two adjacent first material layers 11 and the second material layers 12 needs to be larger. On the one hand, if ΔE < 100V / mm, the potential gradient difference between the two adjacent first material layers 11 and the second material layers 12 is small. When two layers of potential gradient are formed between the two first material layers 11 and the two second material layers 12, although the surge protection range is larger than that of the existing chip varistor. However, in some application scenarios with a greater demand for surge protection, such as industrial power supplies and new energy vehicles, its surge protection capability is still relatively weak. On the other hand, it is also necessary to avoid excessive potential gradients between the adjacent first material layers 11 and the second material layers 12. If ΔE > 500V / mm, it may cause excessive differences in electrical properties between the adjacent first material layers 11 and the second material layers 12, affecting electrical performance parameters such as current flow capacity and leakage current between the material layers, and thus may affect the overall electrical performance of the chip varistor 100.

[0060] Therefore, when setting the potential gradient difference between two adjacent material layers, it is necessary to consider not only the effectiveness of the surge protection range formed by the potential gradient difference between the material layers in different application scenarios, but also the electrical properties between the material layers. In other words, the chip varistor 100 disclosed in this application can not only achieve a wide range of surge protection, but also maintain good electrical properties such as current carrying capacity and leakage current.

[0061] It is understandable that when the first material layer 11 and the second material layer 12 are provided, the potential gradient of the first material layer 11 may be greater than the potential gradient of the second material layer 12 , or the potential gradient of the second material layer 12 may be greater than the potential gradient of the first material layer 11 .

[0062] In some embodiments, the dielectric constant of the first material layer 11 is ε1, and the dielectric constant of the second material layer 12 is ε2, satisfying: ε1 / ε2≥1.5, or ε2 / ε1≥1.5.

[0063] It can be understood that when ε1 / ε2≥1.5, that is, the dielectric constant of the first material layer 11 is greater than the dielectric constant of the second material layer 12, and when ε2 / ε1≥1.5, that is, the dielectric constant of the second material layer 12 is greater than the dielectric constant of the first material layer 11.

[0064] It should be noted that the dielectric constants of the first material layer 11 and the second material layer 12 are related to their potential gradients.

[0065] When the dielectric constant ratio between the first material layer 11 and the second material layer 12 increases, the potential gradient difference between the first material layer 11 and the second material layer 12 increases accordingly. In other words, the greater the ratio between the first material layer 11 and the second material layer 12, the greater the potential gradient difference between the first material layer 11 and the second material layer 12.

[0066] Therefore, when ε1 / ε2 ≥ 1.5 or ε2 / ε1 ≥ 1.5, the potential gradient difference between the adjacent first material layer 11 and the second material layer 12 is relatively large. Thus, when a multi-layer potential gradient is formed within the chip varistor 100, the surge protection range formed by the multi-layer potential gradient difference is larger, which is beneficial for improving the surge protection range of the chip varistor 100.

[0067] In some embodiments, the bismuth content of the first material layer 11 is a1, the bismuth content of the second material layer 12 adjacent to the first material layer 11 is a2, the difference between a1 and a2 is Δa, and Δa satisfies: Δa≥1wt%.

[0068] For example, the main material components of the first material layer 11 may include bismuth oxide, manganese carbonate, chromium oxide, silver nitrate, magnesium oxide, etc., and the main material components of the second material layer 12 may include bismuth oxide, cobalt trioxide, chromium oxide, antimony oxide, etc.

[0069] It is understandable that bismuth, as an important doping element in varistor, easily affects the electrical properties of the material layer in the varistor.

[0070] For example, when the bismuth content in the first material layer 11 and the bismuth content in the second material layer 12 form a difference Δa, the potential gradient difference between the first material layer 11 and the second material layer 12 is affected. When Δa ≥ 1wt%, the potential gradient difference between the first material layer 11 and the second material layer 12 can be 100V / mm or above. That is, when the first material layer 11 and the second material layer 12 are doped with different contents of bismuth, so that the bismuth content difference Δa between the first material layer 11 and the second material layer 12 is ≥ 1wt%, a larger potential gradient difference can be formed between the first material layer 11 and the second material layer 12. Furthermore, when a multi-layer potential gradient is formed in the chip varistor 100, it is beneficial to increase the surge protection range of the chip varistor 100.

[0071] On the contrary, if Δa<1 wt %, the potential gradient difference between the adjacent first material layer 11 and second material layer 12 is small. When multiple layers of potential gradients are formed in the chip varistor 100 , it is difficult to form a large surge protection range.

[0072] In some embodiments, the adjacent first material layer 11 and the second material layer 12 both contain multiple additives. The number of types of additives in the first material layer 11 is S1, and the number of types of additives in the second material layer 12 is S2. The difference between S1 and S2 is ΔS, and ΔS satisfies: ΔS≥2.

[0073] When forming the first material layer 11 and the second material layer 12, the types and quantities of additives added to the first material layer 11 and the second material layer 12 are controlled respectively to change the electrical properties of the first material layer 11 and the second material layer 12. For example, electrical performance parameters such as potential gradient and dielectric constant can be adjusted so that an effective potential gradient difference is formed between adjacent first material layers 11 and second material layers 12. When multiple layers of first material layers 11 and second material layers 12 form the chip varistor 100, the multiple layers of potential gradients are superimposed to form a larger surge protection range.

[0074] It is understandable that the number of types of additives in the first material layer 11 may be greater than the number of types of additives in the second material layer 12 , or the number of types of additives in the second material layer 12 may be greater than the number of types of additives in the first material layer 11 .

[0075] Optionally, the additive may include one or more of bismuth oxide, manganese oxide, cadmium oxide, antimony oxide, nickel oxide, silicon oxide, aluminum oxide, gallium oxide, titanium oxide, zirconium oxide, boron oxide, titanium oxide, indium oxide, yttrium oxide, silver oxide, praseodymium oxide, etc., which are not specifically limited in this application.

[0076] For example, when the additive types in the first material layer 11 are bismuth oxide, manganese oxide, cadmium oxide, antimony oxide, nickel oxide, silicon oxide, aluminum oxide, gallium oxide, and titanium oxide, the additive types in the second material layer 12 may be bismuth oxide, manganese oxide, cadmium oxide, antimony oxide, gallium oxide, and titanium oxide.

[0077] In some embodiments, the thickness of the first material layer 11 is different from the thickness of the adjacent second material layer 12 .

[0078] It will be appreciated that the unit of the potential gradient may be V / mm.

[0079] For example, if the first material layer 11 and the second material layer 12 are in the same electric field and the voltage is the same, if the potential gradients between the first material layer 11 and the second material layer 12 are different, the thicknesses between the first material layer 11 and the second material layer 12 will be different. In other words, controlling the thickness difference between the first material layer 11 and the second material layer 12 also helps control the potential gradient difference between the first material layer 11 and the second material layer 12, thereby increasing the surge protection range of the chip varistor 100.

[0080] For some examples, see Figure 4 The upper cover plate 41 may be made of ceramic material, and the ceramic material of the upper cover plate 41 and the first material layer 11 and / or the second material layer 12 may be the same as or different from that of the first material layer 11 and / or the second material layer 12 .

[0081] It can be understood that when multiple layers of first material layers 11 and multiple layers of second material layers 12 are alternately arranged in sequence, the material layer located on the upper side of the varistor ceramic body 1 in the thickness direction of the varistor ceramic body 1 can be the first material layer 11 or the second material layer 12.

[0082] In one example, when the first material layer 11 is located on the upper side of the varistor ceramic body 1, the upper cover plate 41 is made of the same ceramic material as the first material layer 11, and the upper cover plate 41 is made of a different ceramic material from the second material layer 12; or, when the second material layer 12 is located on the upper side of the varistor ceramic body 1, the upper cover plate 41 is made of the same ceramic material as the second material layer 12, and the upper cover plate 41 is made of a different ceramic material from the first material layer 11. The upper cover plate 41 can only serve as a protective function to protect the upper side of the varistor ceramic body 1 to protect the structure of the chip varistor 100.

[0083] In another example, when the first material layer 11 is located on the upper side of the varistor ceramic body 1, the ceramic material of the upper cover plate 41 is different from that of the first material layer 11, and the ceramic material of the upper cover plate 41 is the same as that of the second material layer 12; or, when the second material layer 12 is located on the upper side of the varistor ceramic body 1, the ceramic material of the upper cover plate 41 is different from that of the second material layer 12, and the ceramic material of the upper cover plate 41 is the same as that of the first material layer 11. In other words, when the upper cover plate 41 is different from the first material layer 11 or the second material layer 12 adjacent to it, a potential gradient difference can be formed between the upper cover plate 41 and the first material layer 11 or the second material layer 12. In this way, the number of layers of the potential gradient in the chip varistor 100 can be increased, which is beneficial to expanding the surge protection range of the chip varistor 100.

[0084] In another example, the ceramic materials of the upper cover plate 41 and the first material layer 11 and the second material layer 12 are different. When the upper cover plate 41 is arranged adjacent to the first material layer 11 or the second material layer 12, a potential gradient difference can be formed between the upper cover plate 41 and the first material layer 11 or the second material layer 12. In this way, the number of layers of the potential gradient in the chip varistor 100 can be increased, which is beneficial to expanding the surge protection range of the chip varistor 100.

[0085] Alternatively, see Figure 4 The lower cover plate 42 may be made of ceramic material, and the ceramic material of the lower cover plate 42 and the first material layer 11 and / or the second material layer 12 may be the same as or different from that of the first material layer 11 and / or the second material layer 12 .

[0086] It can be understood that when multiple layers of first material layers 11 and multiple layers of second material layers 12 are alternately arranged in sequence, the material layer located on the lower side of the varistor ceramic body 1 in the thickness direction of the varistor ceramic body 1 can be the first material layer 11 or the second material layer 12.

[0087] In one example, when the first material layer 11 is located on the lower side of the varistor ceramic body 1, the lower cover plate 42 is made of the same ceramic material as the first material layer 11, and the ceramic material of the lower cover plate 42 is different from that of the second material layer 12; or, when the second material layer 12 is located on the lower side of the varistor ceramic body 1, the lower cover plate 42 is made of the same ceramic material as the second material layer 12, and the ceramic material of the lower cover plate 42 is different from that of the first material layer 11. The lower cover plate 42 can serve as a protective function to protect the lower side of the varistor ceramic body 1 so as to protect the structure of the chip varistor 100.

[0088] In another example, when the first material layer 11 is located on the lower side of the varistor ceramic body 1, the ceramic material of the lower cover plate 42 is different from that of the first material layer 11, and the ceramic material of the lower cover plate 42 is the same as that of the second material layer 12; or, when the second material layer 12 is located on the lower side of the varistor ceramic body 1, the ceramic material of the lower cover plate 42 is different from that of the second material layer 12, and the ceramic material of the lower cover plate 42 is the same as that of the first material layer 11. In other words, when the material of the lower cover plate 42 and its adjacent first material layer 11 or second material layer 12 is different, a potential gradient difference can be formed between the lower cover plate 42 and the first material layer 11 or the second material layer 12. In this way, the number of layers of the potential gradient in the chip varistor 100 can be increased, which is beneficial to expanding the surge protection range of the chip varistor 100.

[0089] In another example, the ceramic materials of the lower cover plate 42 and the first material layer 11 and the second material layer 12 are different. When the lower cover plate 42 is arranged adjacent to the first material layer 11 or the second material layer 12, a potential gradient difference can be formed between the lower cover plate 42 and the first material layer 11 or the second material layer 12. In this way, the number of layers of the potential gradient in the chip varistor 100 can be increased, which is beneficial to expanding the surge protection range of the chip varistor 100.

[0090] Optionally, when the ceramic materials of the upper cover plate 41 and the first material layer 11 and / or the second material layer 12 are different, an internal electrode 3 is provided between the upper cover plate 41 and the varistor ceramic body 1 along the thickness direction of the varistor ceramic body 1 .

[0091] For example, the upper cover plate 41, the lower cover plate 42, the first material layer 11, and the second material layer 12 may be arranged in a manner such that, along the thickness direction of the varistor ceramic body 1, from top to bottom, they may be the upper cover plate 41, the first material layer 11, the second material layer 12, the first material layer 11, the second material layer 12, and the lower cover plate 42, respectively. The upper cover plate 41 and the first material layer 11 are made of different ceramic materials, and an internal electrode 3 may be provided between the upper cover plate 41 and the adjacent first material layer 11. In this way, at least four internal electrodes 3 are provided in the chip varistor 100, and a potential gradient is formed between each pair of the internal electrodes 3, thereby forming a three-layer potential gradient in the chip varistor 100. Therefore, when the ceramic materials of the upper cover plate 41 and the adjacent first material layer 11 or second material layer 12 are different, by arranging the inner electrode 3 between the upper cover plate 41 and the first material layer 11 or the second material layer 12, another layer of potential gradient difference can be formed in the chip varistor 100 to expand the surge protection range of the chip varistor 100.

[0092] Optionally, when the ceramic material of the lower cover plate 42 is different from that of the first material layer 11 and / or the second material layer 12 , an internal electrode 3 is provided between the lower cover plate 42 and the varistor ceramic body 1 along the thickness direction of the varistor ceramic body 1 .

[0093] In one example, the upper cover plate 41, the lower cover plate 42, the first material layer 11, and the second material layer 12 may be arranged in such a manner that, along the thickness direction of the varistor ceramic body 1, from top to bottom, they may be the upper cover plate 41, the first material layer 11, the second material layer 12, the first material layer 11, the second material layer 12, and the lower cover plate 42, respectively. The lower cover plate 42 and the first material layer 11 are made of different ceramic materials, and an internal electrode 3 may be arranged between the lower cover plate 42 and the adjacent first material layer 11. In this way, at least four internal electrodes 3 are provided in the chip varistor 100, and a potential gradient is formed between the two internal electrodes 3, thereby forming a three-layer potential gradient in the chip varistor 100. Therefore, when the ceramic materials of the lower cover plate 42 and the first material layer 11 or the second material layer 12 adjacent to it are different, by arranging the inner electrode 3 between the upper cover plate 41 and the first material layer 11 or the second material layer 12, another layer of potential gradient can be formed in the chip varistor 100 to expand the surge protection range of the chip varistor 100.

[0094] In another example, along the thickness direction of the varistor ceramic body 1, from top to bottom, they can be respectively an upper cover plate 41, a first material layer 11, a second material layer 12, a first material layer 11, a second material layer 12 and a lower cover plate 42. When the ceramic materials of the upper cover plate 41 and the first material layer 11, and the lower cover plate 42 and the second material layer 12 are different, an internal electrode 3 is provided between the upper cover plate 41 and the first material layer 11, an internal electrode 3 is provided between the lower cover plate 42 and the second material layer 12, and an internal electrode 3 is also provided between the adjacent first material layer 11 and the second material layer 12. At least four layers of potential gradient are formed between the five internal electrodes 3. This is beneficial to increase the surge protection range of the chip varistor 100.

[0095] In some embodiments, the varistor ceramic body 1 also includes at least two first material layers 11, at least two second material layers 12 and at least two third material layers 13. Along the thickness direction of the varistor ceramic body 1, the first material layer 11, the second material layer 12 and the third material layer 13 are arranged in sequence to construct a combined material layer 1a, and the two combined material layers 1a are stacked.

[0096] For example, see Figure 5 When the two combined material layers 1a are stacked, that is, along the thickness direction of the varistor ceramic body 1, the first material layer 11, the second material layer 12, the third material layer 13, the first material layer 11, the second material layer 12, and the third material layer 13 can be arranged in sequence. In this way, by providing internal electrodes 3 between the layers, at least four layers of potential gradient can be formed. It can be seen that by providing the third material layer 13, the number of layers of potential gradient is increased, which is beneficial for increasing the surge protection range of the chip varistor 100.

[0097] It can be understood that, along the thickness direction of the varistor ceramic body 1, an upper cover plate 41 and a lower cover plate 42 can be respectively provided on the outermost sides of the two composite material layers 1a.

[0098] In other embodiments, see Figure 6 Along the thickness direction of the varistor ceramic body 1 , the two third material layers 13 are respectively located at the outermost sides of the varistor ceramic body 1 .

[0099] In other words, the material layers within the chip varistor 100 can be arranged in a pattern of: third material layer 13, first material layer 11, second material layer 12, first material layer 11, second material layer 12, and third material layer 13. By providing internal electrodes 3 between the layers, at least four layers of potential gradient can be formed. Thus, by providing the third material layer 13, the number of layers of potential gradient can be increased, thereby increasing the surge protection range of the chip varistor 100.

[0100] In some embodiments, when the first material layer 11, the second material layer 12 and the third material layer 13 are arranged sequentially along the thickness direction of the varistor ceramic body 1, the potential gradients of the first material layer 11, the second material layer 12 and the third material layer 13 change sequentially, or the dielectric constants of the first material layer 11, the second material layer 12 and the third material layer 13 change sequentially.

[0101] For example, when the first material layer 11, the second material layer 12, and the third material layer 13 form a composite material layer 1a, and the two composite material layers 1a are stacked, the potential gradient from the first material layer 11 to the third material layer 13 can decrease or increase in sequence. When the chip varistor 100 receives a surge from low to high, the first material layer 11 to the third material layer 13 can respond step by step according to the change in potential gradient. The absorbed surge energy can be released step by step from the third material layer 13 to the first material layer 11. This helps expand the surge protection range of the chip varistor 100.

[0102] It should be noted that the dielectric constant of the material layer is generally negatively correlated with its potential gradient, that is, when the potential gradient of the material layer increases, its dielectric constant generally decreases. When the potential gradients of the first material layer 11, the second material layer 12, and the third material layer 13 increase successively, their dielectric constants generally decrease successively. On the contrary, when the potential gradients of the first material layer 11, the second material layer 12, and the third material layer 13 decrease successively, their dielectric constants generally increase successively.

[0103] In order to facilitate a further understanding of the solution of the present application, two embodiments and related experimental data are described below.

[0104] Example 1:

[0105] The first material layer 11 is indicated by A, the second material layer 12 is indicated by B, the third material layer 13 is indicated by C, and the upper cover plate 41 and the lower cover plate 42 are both indicated by D.

[0106] See Figure 7 Two first material layers 11, two second material layers 12, and two third material layers 13 are sequentially arranged to form a stacked combination of ABCABC. A cover plate 41 and a lower cover plate 42 are then placed on either side of this stacked combination, forming a stacked combination of DABCABCD. Considering that the electrical properties of the chip varistor 100 may need to be adjusted to achieve the desired application in actual products, an additional first material layer 11 can be placed between CD to form a stacked combination of DABCABCAD. The corresponding parameters of each material layer are shown in Table 1 below:

[0107] Table 1

[0108] Material Potential gradient V / mm Dielectric constant A 800 500 B 500 800 C 200 1200

[0109] The structure comparison of the homogeneous zinc oxide (ZnO) using the solution of the present application and the related art is shown in Table 2 below:

[0110] Table 2

[0111] Test items Example 1 Multilayer heterogeneous material structure Comparative Example 1 Homogeneous structure Varistor voltage V1mA 10V-100V (adjustable) Fixed value (such as 50V, 80V) Flow capacity IP 1000A 500A Leakage current IL 0.1μA 0.5μA

[0112] It can be concluded from Table 1 and Table 2 above that, by adopting the solution of the present application, a multi-layer heterogeneous material structure is formed in the chip varistor 100, so that a multi-layer potential gradient difference is formed in the chip varistor 100 in sequence, and the varistor voltage of the chip varistor 100 can be adjusted within the range of 10V-100V. Compared with the homogeneous structure in Comparative Example 1, its current capacity is increased by 500A, and the leakage current is reduced by 0.4μA.

[0113] Example 2:

[0114] The first material layer 11 is indicated by A, the second material layer 12 is indicated by B, and the third material layer 13 is indicated by C.

[0115] See Figure 8 When the first material layer 11, the second material layer 12, and the third material layer 13 are sequentially arranged to form a combined material layer 1a, and when two combined material layers 1a are stacked on top of each other, the two combined material layers 1a can share the third material layer 13, that is, a stacked combination of ABCBA can be formed. The corresponding parameters of each material layer are shown in Table 3 below:

[0116] Table 3

[0117] Material Potential gradient V / mm Dielectric constant A 120 1000 B 300 600 C 600 300

[0118] The structure comparison of the homogeneous zinc oxide (ZnO) using the solution of the present application and the related art is shown in Table 4 below:

[0119] Table 4

[0120] Test items Example 2 Multilayer heterogeneous material structure Comparative Example 2 Homogeneous structure Varistor voltage V1mA 10V-50V (adjustable) Fixed value (such as 20V, 30V) Flow capacity IP 500A 200A

[0121] It can be concluded from Table 1 and Table 2 above that the solution of the present application forms a multi-layer heterogeneous material structure in the chip varistor 100, so that a multi-layer potential gradient difference is formed in the chip varistor 100 in sequence, so that the varistor voltage of the chip varistor 100 can be adjusted within the range of 10V to 50V, and its current capacity is improved by 300A compared with the homogeneous structure in Comparative Example 2.

[0122] It can be seen that the chip varistor 100 disclosed in the present application can absorb small surges by using low potential gradient differences and absorb large surges by using high potential gradient differences by setting multiple layers of potential gradient differences, so that the surge protection range of the chip varistor 100 can be expanded to 10V-3KV.

[0123] In different application scenarios, the potential gradients of the first material layer 11, the second material layer 12, the third material layer 13, the upper cover plate 41, and the lower cover plate 42 can be controlled to form a multi-layer potential gradient structure that changes sequentially to meet the surge protection requirements in different application scenarios, as shown in Table 5 below:

[0124] Table 5

[0125]

[0126] The chip varistor 100 disclosed in the present application has an improved effect in dispersing the current path and reducing local heat accumulation in the chip varistor 100, as shown in Table 6 below:

[0127] Table 6

[0128]

[0129] It can be seen that the current carrying capacity of the chip varistor 100 disclosed in the present application is improved by 50%-100%. The homogeneous structure of the comparative example suffered breakdown damage at a current of 10KA, while the heterogeneous stacked structure in the chip varistor of the embodiment did not fail at a current of 20KA. Moreover, compared with the failure mode of the comparative example, when the comparative example fails, the edge of the electrode at the center is burned, while in the embodiment, because it can evenly disperse energy from the low potential gradient layer to the high potential gradient layer, so as to avoid the failure of the chip varistor of the embodiment at high current, the heat dissipation effect is also improved, which reduces the probability of damage to the chip varistor 100, which is conducive to improving the service life of the product.

[0130] In a second aspect, the present application further discloses an electronic device 200 , comprising the chip varistor 100 disclosed in the first aspect.

[0131] That is, when the chip varistor 100 is set as an electronic component in the electronic device 200, since the chip varistor 100 has a better protection effect against a larger range of surges, the electronic device can be set in a scenario where a larger range of surge impacts may occur, which is conducive to expanding the application scenarios of the electronic device.

[0132] Understandably, see Figure 9 Taking the electronic device 200 as a mobile phone as an example, when the chip varistor 100 is set in the electronic device 200, the chip varistor 100 can be set on the circuit board 201 of the electronic device 200.

[0133] Optionally, the electronic device 200 may be a mobile phone, a tablet computer, an industrial power supply, a head unit of a new energy vehicle, etc., which is not specifically limited in this application.

[0134] The above is a detailed introduction to the chip varistor and electronic device disclosed in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the chip varistor and electronic device of the present application and its core ideas. At the same time, for those skilled in the art, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A chip varistor, characterized in that: include: A varistor ceramic body, the varistor ceramic body comprising a first material layer and a second material layer, the first material layer and the second material layer being stacked along a thickness direction of the varistor ceramic body, the first material layer and the second material layer being made of different ceramic materials so as to form a potential gradient difference between adjacent first material layers and second material layers; a cover plate structure, the cover plate structure comprising an upper cover plate and a lower cover plate, wherein along the thickness direction of the piezoresistive ceramic body, the upper cover plate is located on the upper side of the first material layer, and the lower cover plate is located on the lower side of the second material layer; Two external electrodes, the two external electrodes are respectively arranged at two ends of the piezoresistive ceramic body and the cover plate structure along the length direction of the piezoresistive ceramic body; There are at least three internal electrodes, and along the thickness direction of the varistor ceramic body, an internal electrode is provided between the upper cover plate and the first material layer, between the lower cover plate and the second material layer, and between the first material layer and the second material layer. Each of the internal electrodes extends along the length direction of the varistor ceramic body so that one end of each of the internal electrodes is alternately connected to the external electrode.

2. The chip varistor according to claim 1, characterized in that: The potential gradient difference between the adjacent first material layer and the second material layer is ΔE, and the ΔE satisfies: 100 V / mm≤ΔE≤500 V / mm.

3. The chip varistor according to claim 1, characterized in that The dielectric constant of the first material layer is ε1, and the dielectric constant of the second material layer is ε2, satisfying: ε1 / ε2≥1.5, or ε2 / ε1≥1.

5.

4. The chip varistor according to claim 1, characterized in that The bismuth content of the first material layer is a1, the bismuth content of the second material layer adjacent to the first material layer is a2, the difference between a1 and a2 is Δa, and Δa satisfies: Δa≥1wt%.

5. The chip varistor according to claim 1, characterized in that: The adjacent first material layer and second material layer both contain multiple additives. The number of types of the additives in the first material layer is S1, and the number of types of the additives in the second material layer is S2. The difference between S1 and S2 is ΔS, and ΔS satisfies: ΔS≥2.

6. The chip varistor according to any one of claims 1 to 5, characterized in that: The thickness of the first material layer is different from the thickness of the adjacent second material layer.

7. The chip varistor according to any one of claims 1 to 5, characterized in that: The upper cover plate is made of ceramic material, and the ceramic material of the upper cover plate is the same as or different from that of the first material layer and / or the second material layer; and / or, The lower cover plate is made of ceramic material, and the ceramic material of the lower cover plate is the same as or different from that of the first material layer and / or the second material layer.

8. The chip varistor according to claim 7, characterized in that: When the upper cover plate and the first material layer and / or the second material layer are made of different ceramic materials, the inner electrode is provided between the upper cover plate and the piezoresistive ceramic body along the thickness direction of the piezoresistive ceramic body; and / or, When the ceramic material of the lower cover plate and the first material layer and / or the second material layer is different, the inner electrode is provided between the lower cover plate and the varistor ceramic body.

9. The chip varistor according to any one of claims 1 to 5, characterized in that: The pressure-sensitive ceramic body includes at least two first material layers, at least two second material layers and at least two third material layers; Along the thickness direction of the varistor ceramic body, the first material layer, the second material layer and the third material layer are sequentially arranged to construct a combined material layer, and the two combined material layers are stacked; or, Along the thickness direction of the varistor ceramic body, the two first material layers and the two second material layers are alternately arranged, and the two third material layers are respectively located at the outermost sides of the varistor ceramic body.

10. The chip varistor according to claim 9, characterized in that: When the first material layer, the second material layer and the third material layer are arranged sequentially along the thickness direction of the varistor ceramic body, the potential gradients of the first material layer, the second material layer and the third material layer change sequentially, and / or the dielectric constants of the first material layer, the second material layer and the third material layer change sequentially.

11. An electronic device, characterized in that: include: The chip varistor according to any one of claims 1 to 10.

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