Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device is provided with a first isolation groove, a second isolation groove and a third isolation groove with different opening sizes, and insulating materials filled in the first isolation groove, the second isolation groove and the third isolation groove are correspondingly adjusted according to the different opening sizes. Therefore, the diversity of the trench isolation structure in the semiconductor device is realized, so that different trench isolation structures can be correspondingly adopted according to different isolation regions, and the application flexibility of the trench isolation structure is improved; moreover, the preparation difficulty of each trench isolation structure is simplified, and the production efficiency of the semiconductor device is improved.

Description

[0001] This invention is a divisional application of the invention with application number "201910690252.4", application date "July 29, 2019", and application name "Semiconductor device and its formation method". Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Art

[0003] As semiconductor device sizes continue to shrink and their integration increases, an isolation structure buried in the substrate, namely a trench isolation structure, has been introduced. The trench isolation structure has a high isolation effect and is conducive to reducing the spacing between device units.

[0004] For example, a trench isolation structure is usually formed in the substrate to define an active area, and then various device units (for example, transistors) can be further prepared based on the defined active area. At this time, the device units in different active areas can be separated from each other by the trench isolation structure to avoid mutual interference between different device units.

[0005] Currently, a plurality of trench isolation structures are usually provided in a semiconductor device. However, the existing trench isolation structures are usually simple in structure, and the structures of the trench isolation structures are usually the same even if they are applied to different isolation regions. Summary of the Invention

[0006] An object of the present invention is to provide a semiconductor device, so as to apply a diversified trench isolation structure to the semiconductor device.

[0007] In order to solve the above technical problems, the present invention provides a semiconductor device, comprising:

[0008] a substrate, wherein a second isolation trench is formed in the substrate, and the second isolation trench is filled with a first insulating material and at least a portion of an electrically conductive layer;

[0009] In the second isolation trench, the first insulating material covers the inner wall of the second isolation trench and defines a gap, and a portion of the electrically conductive layer formed in the second isolation trench is located above the gap.

[0010] In order to solve the above technical problems, the present invention further provides a semiconductor device, comprising:

[0011] A substrate, wherein a second isolation trench and a third isolation trench are formed in the substrate, the opening sizes of which increase successively; wherein,

[0012] The second isolation trench is filled with a first insulating material, a second insulating material and at least a portion of an electrically conductive layer;

[0013] The third isolation trench is sequentially filled with the first insulating material, the second insulating material and the third insulating material;

[0014] In a direction perpendicular to the substrate, a bottom of the second insulating material in the second isolation trench is higher than a bottom of the second insulating material in the third isolation trench.

[0015] In order to solve the above technical problems, the present invention further provides a semiconductor device, comprising:

[0016] A substrate, wherein a second isolation trench and a third isolation trench are formed in the substrate, the opening sizes of which increase successively; wherein,

[0017] The second isolation trench is filled with a first insulating material, a second insulating material and at least a portion of an electrically conductive layer; and

[0018] The third isolation trench is sequentially filled with the first insulating material, the second insulating material and the third insulating material;

[0019] There is a height difference between the bottom position of the second insulating material in the second isolation trench and the bottom position of the second isolation trench, and there is a predetermined thickness value between the bottom position of the second insulating material in the third isolation trench and the bottom position of the third isolation trench, and the height difference is greater than the predetermined thickness value.

[0020] In the semiconductor device provided by the present invention, the insulating materials filled in the first isolation trench, the second isolation trench, and the third isolation trench are adjusted accordingly based on the different opening sizes of the first isolation trench, the second isolation trench, and the third isolation trench. In this way, the diversity of the trench isolation structure in the semiconductor device is achieved, so that different trench isolation structures can be used according to different isolation areas, thereby improving the application flexibility of the trench isolation structure. For example, for a trench isolation structure that also accommodates an electrically conductive layer, a second trench isolation structure with a larger opening size can be used to accommodate the electrically conductive layer. In addition, for the isolation trenches with different opening sizes provided by the present invention, by adjusting their insulating materials accordingly, the difficulty of preparing each trench isolation structure can be further simplified.

[0021] In an optional solution, a gap may be formed in the second trench isolation structure, which can correspondingly improve the parasitic capacitance between the electrically conductive layer and the substrate.

[0022] In a further solution, an ion implantation region may be formed in a portion of the substrate adjacent to the first isolation trench and the second isolation trench, so as to improve leakage current of the semiconductor device by utilizing the ion implantation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1a Schematic diagram of the structure of the semiconductor device in the first embodiment of the present invention;

[0024] Figure 1b Schematic diagram of the structure of the semiconductor device in the second embodiment of the present invention;

[0025] Figure 1c Schematic diagram of the structure of the semiconductor device in the third embodiment of the present invention;

[0026] Figure 1d Schematic diagram of the structure of the semiconductor device in the fourth embodiment of the present invention;

[0027] Figure 2 is a top view of a semiconductor device in one embodiment of the present invention;

[0028] Figure 3 is a schematic flow chart of a method for forming a semiconductor device in one embodiment of the present invention;

[0029] Figure 4a to Figure 4g FIG. 1 is a structural diagram of a method for forming a semiconductor device during its preparation process in one embodiment of the present invention.

[0030] The accompanying drawings are numerals as follows:

[0031] 100-substrate;

[0032] 110 - first isolation trench;

[0033] 120 - second isolation trench;

[0034] 121-gap;

[0035] 130-third isolation trench;

[0036] 210-first insulating material;

[0037] 220- second insulating material;

[0038] 230- third insulating material;

[0039] 300-word line;

[0040] 300a-word line trench;

[0041] 300b-covering layer;

[0042] 400-mask layer;

[0043] AA-active area;

[0044] AA1-first active area;

[0045] AA2-second active area;

[0046] AA3-third active area;

[0047] D-predetermined thickness value;

[0048] H1 - first height position;

[0049] H2 - second height position. DETAILED DESCRIPTION

[0050] The semiconductor device and its formation method proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0051] Example 1

[0052] Figure 1a FIG. 1 is a schematic structural diagram of a semiconductor device in a first embodiment of the present invention. Figure 1a As shown, the semiconductor structure in this embodiment includes: a first isolation trench 110, a second isolation trench 120, and a third isolation trench 130 with increasing opening sizes. Specifically, the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 are all formed in a substrate 100.

[0053] like Figure 1a As shown, in this embodiment, the first isolation trench 110 is filled with a first insulating material 210 to form a first trench isolation structure. The second isolation trench 120 is sequentially filled with the first insulating material 210 and the second insulating material 220 to form a second trench isolation structure. Furthermore, the third isolation trench 130 is sequentially filled with the first insulating material 210, the second insulating material 220, and the third insulating material 230 to form a third trench isolation structure.

[0054] The first insulating material 210 includes, for example, silicon oxide, the second insulating material 220 includes, for example, silicon nitride, and the third insulating material 230 includes, for example, silicon oxide.

[0055] That is, based on the different opening sizes between the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130, the insulating materials filled in the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 can be further adjusted to form first, second, and third trench isolation structures with different structures. In this way, different trench isolation structures can be provided corresponding to different isolation regions in the semiconductor device, achieving flexibility in the application of the trench isolation structure and reducing the difficulty in fabricating the trench isolation structure in the semiconductor device.

[0056] Continue to refer Figure 1a As shown, in the second isolation trench 120 , the first insulating material 210 covers the inner wall of the second isolation trench 120 and defines a gap 121 .

[0057] In this embodiment, the opening size of the second isolation trench 120 gradually decreases from top to bottom. When the first insulating material 210 covers the inner wall of the second isolation trench 120, the first insulating material 210 covering the trench sidewalls can gradually approach each other from top to bottom, thereby defining the gap 121 at the bottom of the second isolation trench 120. For example, the second isolation trench 120 has a first sidewall and a second sidewall that are opposite to each other. In this case, the portion of the first insulating material 210 covering the first sidewall and the second sidewall gradually approaches each other from top to bottom, thereby forming the gap 121.

[0058] Furthermore, in the second isolation trench 120, the top opening of the gap 121 can be directly closed by the first insulating material 210, and the second insulating material 220 can be formed above the gap 121 without contacting the gap 121. Alternatively, as in this embodiment, the top opening of the gap 121 can also be closed by the second insulating material 220 located above the gap 121. In this way, the gap 121 can be defined by the insulating material in the second isolation trench 120.

[0059] As described above, the opening size of the second isolation trench 120 in this embodiment gradually decreases from top to bottom. Furthermore, the slope of the trench sidewalls below the slit 121 in the second isolation trench 120 can be greater than or equal to the slope of the trench sidewalls above the slit 121. That is, the trench sidewalls near the bottom of the second isolation trench 120 are more vertical than the trench sidewalls near the top. This makes it easier for the first insulating material 210 to form the slit 121 in the bottom of the second isolation trench 120 when depositing the first insulating material 210.

[0060] Continue to refer Figure 1a As shown, in the third isolation trench 130 , the first insulating material 210 and the second insulating material 220 both conformally cover the sidewalls and bottom walls of the third isolation trench 130 , and the third insulating material 230 fills the space in the third isolation trench 130 defined by the second insulating material 220 .

[0061] Furthermore, the first insulating material 210 in the third isolation trench 130 has a predetermined thickness D in a direction perpendicular to the trench sidewalls. The maximum opening dimension of the first isolation trench 110 is less than or equal to twice the predetermined thickness (2*D), the maximum opening dimension of the second isolation trench 120 is greater than or equal to twice the predetermined thickness (2*D), and the maximum opening dimension of the third isolation trench 130 is, for example, greater than or equal to three times the predetermined thickness (3*D).

[0062] Specifically, since the maximum opening size of the first isolation trench 110 is less than or equal to 2 times the predetermined thickness value, based on this, when the deposition process is performed to simultaneously deposit the first insulating material 210 on the first isolation trench 110, the second isolation trench 120 and the third isolation trench 130, the first insulating material 210 deposited in the first isolation trench 110 can fill the first isolation trench 110, and the first insulating material 210 deposited in the second isolation trench 120 and the third isolation trench 130 can cover the inner walls of the second isolation trench 120 and the third isolation trench 130.

[0063] In this embodiment, the top opening size of the second isolation trench 120 is larger than twice the predetermined thickness value (2*D), and the bottom opening size of the second isolation trench 120 can be closer to twice the predetermined thickness value (for example, equal to twice the predetermined thickness value; or slightly smaller than twice the predetermined thickness value; or slightly larger than twice the predetermined thickness value). In this case, the first insulating material 210 in the second isolation trench 120 is easily close to each other at the bottom of the second isolation trench 120 and defines the gap 121.

[0064] Continue to refer Figure 1a As shown, in this embodiment, the depths of the second isolation trench 120 and the third isolation trench 130 are both greater than the depth of the first isolation trench 110. Specifically, the depth H2 at which the second isolation trench 120 and the third isolation trench 130 extend in the substrate 100 is lower than the depth H1 at which the first isolation trench 110 extends in the substrate 100.

[0065] Furthermore, the bottom of the gap 121 in the second isolation trench 120 is further lower than the bottom of the first isolation trench 110. In this embodiment, the bottom of the gap 121 in the second isolation trench 120 is between the first height position H1 and the second height position H2, and the top of the gap 121 is higher than the first height position H1. Of course, in other embodiments, the gap 121 in the second isolation trench 120 can also be completely between the first height position H1 and the second height position H2 (i.e., the top of the gap 121 is lower than the first height position H1).

[0066] It should be noted that, in this embodiment, the opening size of the second isolation trench 120 gradually decreases from top to bottom, and the bottom size of the second isolation trench 120 is close to 2 times the predetermined thickness value, and the depth of the second isolation trench 120 is also relatively large, so that the gap 121 is easily formed, and the formed gap 121 can be close to the bottom of the second isolation trench 120.

[0067] Continue to refer Figure 1a As shown, the semiconductor device further includes, for example, an electrically conductive layer buried in the substrate 100 (the electrically conductive layer being, for example, a word line 300 in a memory device). The electrically conductive layer is at least partially formed in the second isolation trench 120 and is located above at least a portion of the second insulating material 220 in the second isolation trench 120. Accordingly, the electrically conductive layer is located above the gap 121. In this embodiment, since the second isolation trench 120 has a relatively large depth, the isolation performance of the second trench isolation structure with respect to the electrically conductive layer can be improved. Furthermore, since the gap 121 is also formed in the second trench isolation structure, it is also beneficial to improve the parasitic capacitance between the electrically conductive layer and the substrate 100.

[0068] It should be appreciated that the isolation trenches with different opening sizes as described above can be applied to a variety of semiconductor devices. In this embodiment, the semiconductor device is a memory as an example for explanation.

[0069] Figure 2 FIG. 1 is a top view of a semiconductor device in one embodiment of the present invention. Figure 2 As shown, the semiconductor device is a memory, such as a dynamic random access memory (DRAM), wherein the memory has a plurality of active areas AA, each of which extends along a first direction (Z direction).

[0070] In this embodiment, the second isolation trench 120 is spaced between the active areas AA that are most adjacent in the first direction (Z direction). Figure 2In the memory shown, the first active area AA1 and the third active area AA3 , which are most adjacent to each other in the first direction (Z direction), are separated from each other by the second isolation trench 120 .

[0071] Furthermore, the first isolation trench 110 is spaced between the most adjacent active areas AA in the second direction (X direction). The second direction (X direction) intersects with the first direction (Z direction). For example, Figure 2 In the memory shown, the first active area AA1 and the second active area AA2 that are most adjacent in the second direction (X direction) are separated from each other by the first isolation trench 110; and the second active area AA2 and the third active area AA3 that are most adjacent in the second direction (X direction) can also be separated from each other by the first isolation trench 110.

[0072] It can be understood that, in this embodiment, Figure 1a The structure diagram of aa' in is Figure 2 Schematic diagram of the cross section in the aa' direction, Figure 1a The structural diagram of bb' is Figure 2 Schematic diagram of the cross section in the bb' direction, and Figure 2 The top view of the cc' portion is not shown.

[0073] Continue to combine Figure 1a and Figure 2 As shown, the memory further includes a word line 300, which is buried in the substrate 100 and extends along the second direction (X direction) so that the word line 300 intersects the corresponding active area AA, and the word line 300 also has a portion formed in the isolation area.

[0074] In this embodiment, the word line 300 is at least partially formed in the second isolation trench 120 and constitutes a first word line portion, and the portion of the word line 300 formed in the active area AA constitutes a second word line portion. Furthermore, the first word line portion is located above at least a portion of the second insulating material 220 in the second isolation trench 120.

[0075] That is, in the second isolation trench 120, the first insulating material 210 covers the side walls of the second isolation trench 120 and defines the gap 121, the second insulating material 220 closes the top opening of the gap 121 and is located above the gap 121, and the first word line portion is located above at least a portion of the second insulating material 220 in the second isolation trench 120, then the first word line portion is correspondingly located above the gap 121.

[0076] It should be noted that, in this embodiment Figure 1aThe figure schematically shows that the second insulating material 220 in the second isolation trench 120 is located between the first word line portion and the gap 121. However, when the top opening of the second isolation trench 120 is large, the second insulating material may be further present in the region near the top of the second isolation trench 120. The second insulating material near the top of the second isolation trench 120 is located between the first word line portion and the first insulating material 210.

[0077] It should also be noted that in this embodiment, when the semiconductor device is a memory device, different trench isolation structures can be used in different isolation regions. For example, the most adjacent active areas AA in the second direction (X direction) can be separated from each other by a second trench isolation structure having a larger opening size than the first trench isolation structure. In this case, a portion of the word line 300 can be accommodated in the second trench isolation structure, preventing the first word line portion formed in the second trench isolation structure from contacting the adjacent active area AA. Furthermore, in this embodiment, the second trench isolation structure can also have a greater depth, thereby improving the isolation effect between the first word line portion formed in the second trench isolation structure and the adjacent active area AA. In addition, a gap 121 is formed in the second trench isolation structure, which can effectively reduce the parasitic capacitance between the word line 300 and the substrate 100, thereby improving the performance of the memory device.

[0078] In this embodiment, the word line 300 is formed in a word line trench, and the top of the word line 300 is lower than the top of the word line trench. Furthermore, a capping layer 300b is filled in the portion of the word line trench above the word line 300 to cover the word line 300. The capping layer 300b is made of, for example, silicon nitride.

[0079] Furthermore, the semiconductor device may further include a device cell region and a peripheral region located outside the device cell region. Furthermore, the device cell region and the peripheral region may be separated by the third isolation trench 130 . That is, the device cell region and the peripheral region may be separated from each other by the third isolation trench 130 having a larger opening size, thereby improving the isolation effect between the device cell region and the peripheral region.

[0080] In this embodiment, the device unit area is the storage area of ​​the memory (a plurality of active areas AA are distributed in the storage area), and the peripheral area (not shown in the figure) is located outside the storage area.

[0081] In an optional solution, an ion implantation region (not shown) is further formed in the portion of the substrate 100 bordering the first isolation trench 110 and the second isolation trench 120 to improve leakage current in the semiconductor device. That is, the ion implantation region is formed in the substrate 100 surrounding the first isolation trench 110 and the second isolation trench 120. In this embodiment, an ion implantation region may also be formed in the portion of the substrate 100 bordering the third isolation trench 130.

[0082] Specifically, the insulating material in the isolation trench is generally prone to attracting charges. This charged insulating material generates an electric field, which in turn causes the substrate near the isolation trench to invert under the influence of the electric field, thereby causing leakage current. Based on this, an ion implantation region is formed in the substrate 100 near the isolation trench, making the portion of the substrate where the ion implantation region is formed less susceptible to inversion, thereby suppressing leakage current.

[0083] Furthermore, the substrate 100 and the ion implantation region may both be of the first conductivity type, and the ion doping concentration of the ion implantation region is higher than the ion doping concentration of the substrate 100. That is, the substrate 100 and the ion implantation region may both be of P type or N type, for example.

[0084] In a specific embodiment, for example, a transistor of the second conductivity type is formed in a region of the substrate 100 adjacent to the first isolation trench 110 and / or the second isolation trench 120. In this case, the first isolation trench 110 and / or the second isolation trench 120 can easily capture charges of the second conductivity type, which can easily cause the adjacent substrate to be inverted when no ion implantation region is provided.

[0085] The following further explains the semiconductor device in this embodiment using a memory device as an example. In this embodiment, a memory transistor is formed in the active area AA, and a first isolation trench 110 and a second isolation trench 120 are formed around the active area AA. The first isolation trench 110 filled with an insulating material further constitutes a first trench isolation structure, and the second isolation trench 120 filled with an insulating material further constitutes a second trench isolation structure.

[0086] In this embodiment, the substrate 100 is of the first conductivity type, and the memory transistor formed in the active area AA is of the second conductivity type. Based on this, the ion implantation region formed around the first isolation trench 110 and the second isolation trench 120 can be of the first conductivity type. In this embodiment, the first conductivity type is, for example, P-type, the second conductivity type is, for example, N-type, and the dopant ions in the ion implantation region may include boron ions.

[0087] Specifically, when no ion implantation region is provided around the first isolation trench 110 and the second isolation trench 120, the second conductivity type of charge in the second conductivity type storage transistor is easily captured by the first trench isolation structure and the second trench isolation structure, causing the first trench isolation structure and the second trench isolation structure to exhibit the second conductivity type. In this case, the second conductivity type trench isolation structure can easily cause the first conductivity type substrate adjacent to it to be inverted, thereby causing leakage current.

[0088] However, in this embodiment, an ion implantation region is provided on the periphery of the first isolation trench 110 and the second isolation trench 120. Thus, even if the first trench isolation structure and the second trench isolation structure capture charges, since an ion implantation region is formed in the substrate bordering the first isolation trench 110 and the second isolation trench 120, the substrate in this region is not easily inverted, that is, the inversion of the substrate near the first isolation trench 110 and the second isolation trench 120 is suppressed, thereby alleviating the leakage current phenomenon of the semiconductor device.

[0089] Example 2

[0090] The difference from the first embodiment is that in this embodiment, no gaps are formed in the first insulating material of the second isolation trench, that is, the first insulating material densely covers the inner wall of the second isolation trench.

[0091] Figure 1b FIG. 1 is a schematic structural diagram of a semiconductor device in a second embodiment of the present invention, as shown in FIG. Figure 1b As shown, in the second isolation trench 120 , the first insulating material 210 covers the bottom wall and sidewalls of the second isolation trench 120 , and the second insulating material 220 is formed on the first insulating material 210 .

[0092] The first insulating material 210 in the third isolation trench 130 has a predetermined thickness D in a direction perpendicular to the trench sidewalls. It will be appreciated that the predetermined thickness D of the first insulating material is the thickness of the first insulating material when it is deposited. Therefore, the thickness of the first insulating material 210 in the second isolation trench 120 in a direction perpendicular to the trench sidewalls is also close to or equal to the predetermined thickness D. Furthermore, the height of the first insulating material 210 in the second isolation trench 120 covering the bottom wall of the second isolation trench is also less than twice the predetermined thickness (e.g., the height is close to or equal to the predetermined thickness D).

[0093] Continue to refer Figure 1b As shown, in this embodiment, the portion of the electrically conductive layer (eg, the word line 300 in the memory) formed in the second isolation trench 120 is also located above at least a portion of the second insulating material 220 .

[0094] Example 3

[0095] The difference from the second embodiment is that, in this embodiment, the first insulating material in the second isolation trench covers the bottom wall of the second isolation trench to a height greater than or equal to twice the predetermined thickness.

[0096] Figure 1c FIG. 1 is a schematic structural diagram of a semiconductor device in a third embodiment of the present invention, as shown in FIG. Figure 1c As shown, in the second isolation trench 120, the portion of the first insulating material 210 covering the trench sidewall gradually approaches from top to bottom until they are closed to each other, and the height difference △H between the starting position where the first insulating material 210 is closed to the bottom position of the second isolation trench 120 is greater than or equal to 2 times the predetermined thickness value.

[0097] Example 4

[0098] Similar to the first embodiment, the second isolation trench of this embodiment is filled with a first insulating material, and a gap is also formed in the center of the first insulating material of the second isolation trench. However, unlike the first embodiment, the second isolation trench of this embodiment is not provided with the second insulating material, at least in the region corresponding to the electrically conductive layer.

[0099] Figure 1d FIG. 1 is a schematic structural diagram of a semiconductor device in a fourth embodiment of the present invention, as shown in FIG. Figure 1d As shown, the second isolation trench 120 is filled with the first insulating material 210. In the second isolation trench 120, the first insulating material 210 covers the inner wall of the second isolation trench 120 and defines a gap 121. Furthermore, the portion of the electrically conductive layer (e.g., the memory word line 300) formed in the second isolation trench 120 is located above the gap 121 in the second isolation trench 120.

[0100] The second insulating material may not be disposed between the electrically conductive layer and the slit 121. In this embodiment, the bottom of the electrically conductive layer closes the top opening of the slit 121, that is, the electrically conductive layer is in direct contact with the slit 121. Furthermore, the conductive material of the electrically conductive layer may be present in the slit 121.

[0101] Based on the semiconductor device described above, this embodiment further provides a method for forming a semiconductor device.

[0102] Figure 3 FIG. 1 is a flow chart of a method for forming a semiconductor device in one embodiment of the present invention. Figure 4a to Figure 4g1 is a schematic structural diagram of a method for forming a semiconductor device in an embodiment of the present invention during its preparation process. The following describes in detail each step of the method for forming a semiconductor device in this embodiment in conjunction with the accompanying drawings.

[0103] In step S100, refer to Figure 4a As shown, a substrate 100 is provided, and a first isolation trench 110 , a second isolation trench 120 and a third isolation trench 130 with opening sizes increasing in sequence are formed in the substrate 100 .

[0104] Among them, the preparation method of the first isolation trench 110, the second isolation trench 120 and the third isolation trench 130, for example, includes: first, forming a mask layer 400 on the substrate 100, and the mask layer 400 defines the pattern of the first isolation trench 110, the second isolation trench 120 and the third isolation trench 130; then, etching the substrate 100 using the mask layer 400 as a mask to form the first isolation trench 110, the second isolation trench 120 and the third isolation trench 130.

[0105] Furthermore, since the opening size of the first isolation trench 110 is relatively small, and the opening sizes of the second isolation trench 120 and the third isolation trench 130 are relatively large, isolation trenches with different depths can be formed by utilizing the loading effect of the etching process, for example.

[0106] In this embodiment, the depths of the second isolation trench 120 and the third isolation trench 130 are greater than the depth of the first isolation trench 110. Specifically, the second isolation trench 120 and the third isolation trench 130 extend into the substrate 100 at a second depth H2, and the first isolation trench 110 extends into the substrate at a first depth H1, and the second depth H2 is lower than the first depth H1.

[0107] Furthermore, as described above, the opening sizes of the first isolation trench 110 , the second isolation trench 120 , and the third isolation trench 130 are, for example, gradually reduced from top to bottom.

[0108] For the optional options, please refer to Figure 4b As shown, after forming the first isolation trench 110, the second isolation trench 120, and the third isolation trench 130 using the mask layer 400, an ion implantation process may be further performed using the mask layer 400 to form an ion implantation region (not shown) in at least a portion of the substrate 100 exposed to the first isolation trench 110 and the second isolation trench 120. Furthermore, after performing the ion implantation process to form the ion implantation region, the mask layer 400 may be removed.

[0109] The ion implantation process may include an inclined ion implantation process and a vertical ion implantation process, so that the formed ion implantation region covers the sidewalls and bottom walls of the first isolation trench 110 and the second isolation trench 120. Specifically, through the inclined ion implantation process, dopant ions may be implanted into the sidewalls of the first isolation trench 110 and the second isolation trench 120, and through the vertical ion implantation process, dopant ions may be implanted into the bottom walls of the first isolation trench 110 and the second isolation trench 120, thereby covering the peripheries of the first isolation trench 110 and the second isolation trench 120 with the ion implantation region.

[0110] In addition, in this embodiment, the ion implantation region is also formed at the periphery of the third isolation trench 130 .

[0111] As described in the above embodiment, the conductivity type of the dopant ions implanted in the ion implantation process may be the same as the conductivity type of the substrate, for example, both are P-type. Furthermore, the implanted dopant ions may include boron ions.

[0112] In step S200, refer to Figure 4c As shown, a first insulating material 210 is formed in the first isolation trench 110 , the second isolation trench 120 and the third isolation trench 130 .

[0113] like Figure 4c As shown, the first insulating material 210 fills the first isolation trench 110 and covers the inner walls of the second isolation trench 120 and the third isolation trench 130 .

[0114] Specifically, the first insulating material 210 may be deposited simultaneously in the first isolation trench 110 , the second isolation trench 120 , and the third isolation trench 130 by using a deposition process.

[0115] It should be noted that, in this embodiment, Figure 1a The semiconductor device shown in FIG. 1 is used as an example for explanation. At this point, a gap 121 is defined by the first insulating material 210 in the second isolation trench 120. Since the opening of the first isolation trench 110 is relatively small, the deposited first insulating material 210 can directly fill the first isolation trench 110. Furthermore, in the second isolation trench 120, due to its greater depth and steeper trench sidewalls at its bottom, the first insulating material 120 easily forms the gap 121 in the region near the bottom of the second isolation trench 120.

[0116] Of course, in other embodiments, when it is necessary to form, for example Figure 1b and Figure 1cIn the semiconductor device shown, when depositing the first insulating material, the deposition process can be adjusted to form the first insulating material without gaps in the second isolation trench 120 .

[0117] In step S300, refer to Figure 4d to Figure 4e As shown, a second insulating material 220 is formed in the second isolation trench 120 and the third isolation trench 130 , and a third insulating material 230 is formed in the third isolation trench 130 .

[0118] As described above, in this embodiment, the Figure 1a The semiconductor device shown is taken as an example for explanation. Based on this, the bottom of the second insulating material 220 in this embodiment closes the top opening of the gap 121 in the second isolation trench 120 and is located above the gap 121 .

[0119] Specifically, in the second isolation trench 120 formed with the first insulating material 210, the space defined by the first insulating material 210 includes the gap 121 and the filling space above the gap 121. When the second insulating material 220 is deposited, the second insulating material 220 fills the filling space above the gap 121 to the top of the second isolation trench 120.

[0120] In addition, when depositing the second insulating material 220 , the second insulating material 220 is also deposited on the top surface of the substrate 100 and covers the first insulating material 210 in the first isolation trench 110 .

[0121] Continue to refer Figure 4e As shown, in the third isolation trench 130 , the second insulating material 220 conformally covers the inner wall of the third isolation trench 130 , and the third insulating material 230 fills the space defined by the second insulating material 220 .

[0122] Furthermore, after filling the third isolation trench 130 with the third insulating material 230, the method further includes performing a planarization process on the third insulating material 230 to planarize the top surface of the third insulating material 230. In this embodiment, the third insulating material 230 remaining after the planarization process fills the third isolation trench 130 and covers the top surface of the substrate 100.

[0123] At this point, the first isolation trench 110 filled with insulating material forms a first trench isolation structure, the second isolation trench 120 filled with insulating material forms a second trench isolation structure, and the third isolation trench 130 filled with insulating material forms a third trench isolation structure.

[0124] It should be noted that, for a specific semiconductor device, after forming the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure as described above, the third trench isolation structure can be used to define a device cell region and a peripheral region of the semiconductor device, and the first trench isolation structure and the second trench isolation structure can be used to define multiple active regions within the device cell region. Furthermore, after defining the device cell region, subsequent processes can be further performed within the device cell region.

[0125] Specifically, in step S400, refer to Figure 4f and Figure 4g As shown, an electrically conductive layer is formed in the substrate 100 , and the electrically conductive layer is at least partially formed in the second isolation trench 120 .

[0126] For example, if the semiconductor device is a memory device, the third trench isolation structure can define a memory area of ​​the memory, and the first trench isolation structure and the second trench isolation structure can further define multiple active areas within the memory area. Furthermore, the electrically conductive layer can constitute a word line 300 of the memory device, and the portion of the word line 300 formed in the second isolation trench 120 can constitute a first word line portion.

[0127] In this embodiment, the Figure 1a The semiconductor device shown is taken as an example for explanation. Therefore, the first word line portion is located above at least a portion of the second insulating material 220 in the second isolation trench 120 .

[0128] Specifically, the method for forming the electrically conductive layer (eg, the word line 300 of the memory) includes the following steps.

[0129] First step, specific reference Figure 4f As shown, a trench for forming an electrically conductive layer is formed in the substrate 100 . The method for forming the trench for the electrically conductive layer includes: etching the second insulating material 220 and the first insulating material 210 in the second isolation trench 120 .

[0130] In this embodiment, the groove of the electrically conductive layer is a word line groove 300a, the word line groove 300a extends along a predetermined direction and intersects with the corresponding active area, and the word line groove 300a is also partially located in the second trench isolation structure (that is, the word line groove 300a is also partially located in the second isolation trench 120).

[0131] Continue to refer Figure 4fAs shown, the depth value of the word line trench 300a is less than the depth value of the first isolation trench 110, that is, the depth position of the word line trench 300a extending in the substrate 100 is higher than the depth position of the first isolation trench 110 extending in the substrate 100 (that is, higher than the first height position H1).

[0132] In addition, in this embodiment, the Figure 1a Taking the semiconductor device shown in FIG. 1 as an example, the bottom of the word line trench 300 a stops at the second insulating material 220 and is higher than the gap 121 in the second isolation trench 120. That is, the bottom of the word line trench 300 a does not extend to the gap 121, and the gap 121 is still closed by the second insulating material 220.

[0133] It should be appreciated that in other embodiments, when it is desired to form Figure 1b and Figure 1c Taking the semiconductor device shown in FIG. 1 as an example, the bottom of the word line trench 300a also stops at the second insulating material. Alternatively, in other embodiments, when it is necessary to form a Figure 1d In the semiconductor device shown, the top of the gap 121 in the second isolation trench is located higher. At this time, the bottom of the word line trench can extend to the top of the gap, so that the word line trench and the gap are connected.

[0134] The second step, specific reference Figure 4g As shown, the conductive material is filled in the trench of the electrically conductive layer. In this embodiment, the word line material is filled in the word line trench 300 a to form the word line 300 .

[0135] It should be noted that, in other embodiments, when it is necessary to form Figure 1d In the semiconductor device shown, since the word line trench is connected to the gap, the deposited conductive material may enter the gap, so that a trace amount of conductive material is still present in the gap.

[0136] In this embodiment, the top of the word line 300 is lower than the top of the word line trench 300a, so there is still vacant accommodation space in the area of ​​the word line trench 300a above the word line 300. At this time, a capping layer 300b can be further filled in the accommodation space to cover the word line 300.

[0137] In summary, the semiconductor device provided by this embodiment can be provided with isolation trenches of varying opening sizes, and the insulating materials used to fill the isolation trenches can be adjusted accordingly based on the different opening sizes, thereby achieving diversification of the trench isolation structures in the semiconductor device. This allows trench isolation structures of varying structures to be selected for different isolation regions, thereby increasing the application flexibility of the trench isolation structures. Furthermore, the trench isolation structures with different insulating materials in this embodiment can also simplify the preparation of each trench isolation structure, thereby improving the production efficiency of semiconductor devices.

[0138] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0139] It should also be noted that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0140] It should also be understood that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. In addition, the implementation of the methods and / or apparatus in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that: include: a substrate, wherein a second isolation trench is formed in the substrate, and the second isolation trench is filled with a first insulating material and at least a portion of an electrically conductive layer; In the second isolation trench, the first insulating material covers the inner wall of the second isolation trench and defines a gap, and a portion of the electrically conductive layer formed in the second isolation trench is located above the gap.

2. The semiconductor device according to claim 1, wherein The second isolation trench is further filled with a second insulating material, and the electrically conductive layer is formed on at least a portion of the second insulating material.

3. The semiconductor device according to claim 1, wherein The substrate is further provided with a first isolation trench. The opening sizes of the first isolation trench and the second isolation trench increase successively. The first isolation trench is filled with a first insulating material.

4. The semiconductor device according to claim 2, wherein The substrate is further provided with a third isolation trench, and the opening sizes of the second isolation trench and the third isolation trench increase sequentially; The third isolation trench is filled with the first insulating material, and the first insulating material in the third isolation trench has a predetermined thickness in a direction perpendicular to the trench sidewall; Furthermore, in the second isolation trench, the portion of the first insulating material covering the trench sidewall gradually approaches from top to bottom until they are closed to each other, and the height difference between the starting position where the first insulating material is closed to the bottom position of the second isolation trench is greater than or equal to 2 times the predetermined thickness value.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The bottom of the electrically conductive layer closes the top opening of the gap.

6. The semiconductor device according to claim 3, wherein The second isolation trench extends to a depth in the substrate that is lower than the depth in the substrate that the first isolation trench extends to.

7. The semiconductor device according to claim 3, wherein The bottom of the gap is lower than the bottom of the first isolation trench.

8. The semiconductor device according to any one of claims 1 to 4, wherein: The gap also contains the conductive material of the electrically conductive layer.

9. A semiconductor device, characterized in that: include: A substrate, wherein a second isolation trench and a third isolation trench are formed in the substrate, the opening sizes of which increase successively; wherein, The second isolation trench is filled with a first insulating material, a second insulating material and at least a portion of an electrically conductive layer; The third isolation trench is sequentially filled with the first insulating material, the second insulating material and the third insulating material; In a direction perpendicular to the substrate, a bottom of the second insulating material in the second isolation trench is higher than a bottom of the second insulating material in the third isolation trench.

10. The semiconductor device according to claim 9, wherein The substrate is further provided with a first isolation trench filled with the first insulating material; the third isolation trench extends to a depth lower than the first isolation trench extends to the substrate.

11. A semiconductor device, characterized in that: include: A substrate, wherein a second isolation trench and a third isolation trench are formed in the substrate, the opening sizes of which increase successively; wherein, The second isolation trench is filled with a first insulating material, a second insulating material and at least a portion of an electrically conductive layer; and The third isolation trench is sequentially filled with the first insulating material, the second insulating material and the third insulating material; There is a height difference between the bottom position of the second insulating material in the second isolation trench and the bottom position of the second isolation trench, and there is a predetermined thickness value between the bottom position of the second insulating material in the third isolation trench and the bottom position of the third isolation trench, and the height difference is greater than the predetermined thickness value.

12. The semiconductor device according to claim 11, wherein The height difference is greater than or equal to 2 times the predetermined thickness value.

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