Vertical cavity surface emitting laser and preparation method thereof

Abstract

The invention relates to a vertical cavity surface emitting laser and a preparation method thereof. The vertical cavity surface emitting laser comprises a heat dissipation substrate and at least one light emitting unit. The light emitting unit comprises an epitaxial base structure located on the heat dissipation substrate; the bottom layer of the epitaxial base structure is a first current diffusion layer, and the top layer of the epitaxial base structure is a second current diffusion layer; the first electrode is located on the epitaxial base structure and extends into the epitaxial base structure; the second electrode is located on the lower surface of the heat dissipation substrate; or the epitaxial base structure is provided with a mesa, the mesa exposes part of the upper surface of the first current diffusion layer, and the second electrode is located on the upper surface of the first current diffusion layer. In the vertical cavity surface emitting laser, the top surface of the epitaxial base structure is not covered by the cover layer, so that the absorption of short waves is greatly reduced; and the vertical-cavity surface-emitting laser adopts the heat dissipation substrate and has relatively small thermal resistance, so that the performance of the vertical-cavity surface-emitting laser can be ensured.

Description

Technical Field

[0001] The present application relates to the field of laser technology, and in particular to a vertical cavity surface emitting laser and a preparation method thereof. Background Art

[0002] Vertical Cavity Surface Emitting Laser (VCSEL) is a new type of laser that emits light vertically from the surface. Due to its advantages such as small size, circular output spot, low threshold current, high modulation frequency, easy fiber coupling, and ease of forming large-area arrays, it is increasingly used in optical communications, optical interconnection, optical information processing, mobile phones, driverless cars, lidar and other fields.

[0003] However, the existing VCSEL has a light-emitting surface covered by a cap layer (Cap), which has a large absorption capacity for short wavelengths (for example, 808nm or 680nm), resulting in low light extraction efficiency. In addition, the existing VCSEL retains a growth substrate as a support, and the growth substrate generally has a high thermal resistance, which affects the performance of the VCSEL. Summary of the Invention

[0004] Based on this, it is necessary to provide a vertical cavity surface emitting laser and its preparation method to address the problems in the above-mentioned background technology. The vertical cavity surface emitting laser has the advantages of greatly reducing the absorption of short waves, being suitable for the field of short wave technology, and having low thermal resistance, thereby ensuring the performance of the vertical cavity surface emitting laser.

[0005] In order to solve the above technical problems and other problems, in a first aspect, the present application provides a vertical cavity surface emitting laser, the vertical cavity surface emitting laser comprising:

[0006] A heat dissipation substrate and at least one light-emitting unit; the light-emitting unit comprises:

[0007] An epitaxial base structure is located on the heat dissipation substrate; the bottom layer of the epitaxial base structure is a first current diffusion layer, and the top layer of the epitaxial base structure is a second current diffusion layer;

[0008] a first electrode, located on the epitaxial base structure and extending into the epitaxial base structure;

[0009] The second electrode is located on the lower surface of the heat dissipation substrate; or the epitaxial base structure has a table, the table exposes a portion of the upper surface of the first current diffusion layer, and the second electrode is located on the upper surface of the first current diffusion layer.

[0010] In the vertical cavity surface emitting laser of the above embodiment, the top surface of the epitaxial base structure is not covered by a capping layer, which greatly reduces the absorption of short waves and is suitable for the field of short wave technology; and the vertical cavity surface emitting laser adopts a heat dissipation substrate, which has a smaller thermal resistance, thereby ensuring the performance of the vertical cavity surface emitting laser.

[0011] In some embodiments, the epitaxial infrastructure further comprises:

[0012] a first Bragg reflection layer, located on an upper surface of the first current diffusion layer;

[0013] an active layer, located on an upper surface of the first Bragg reflector layer;

[0014] a second Bragg reflection layer, located above the active layer;

[0015] an oxide layer, located between the second Bragg reflective layer and the active layer, or located in the second Bragg reflective layer; the oxide layer has a light-transmitting hole penetrating along the thickness direction;

[0016] The second current diffusion layer is located on an upper surface of the second Bragg reflection layer.

[0017] In some embodiments, the epitaxial base structure further includes a capping layer, which is located on the upper surface of the second current diffusion layer; the capping layer has a through hole penetrating along the thickness direction, and the through hole is arranged correspondingly to the light-transmitting hole above and below.

[0018] In the vertical cavity surface emitting laser of the above embodiment, although the epitaxial base structure has a capping layer, the capping layer has a through hole corresponding to the light-transmitting hole, which can increase the current density corresponding to the light-transmitting hole area and greatly reduce the absorption of short waves, and is suitable for the field of short-wave technology.

[0019] In some embodiments, the vertical cavity surface emitting laser further includes a backside interconnect metal layer located between the heat dissipation substrate and the epitaxial base structure.

[0020] In some embodiments, the vertical cavity surface emitting laser further comprises:

[0021] A trench is located in the epitaxial base structure; a portion of the first electrode extending into the epitaxial base structure is located in the trench;

[0022] a first dielectric layer, located on the upper surface of the epitaxial base structure;

[0023] an interconnect metal layer, located on the upper surface of the epitaxial base structure and within the first dielectric layer;

[0024] a second dielectric layer, located on the upper surface of the first dielectric layer, the upper surface of the interconnect metal layer, and the sides and bottom of the trench;

[0025] The first opening penetrates the second dielectric layer along the thickness direction and exposes the interconnection metal layer; the first electrode is also located in the first opening and contacts the interconnection metal layer.

[0026] In some embodiments, when the epitaxial base structure has a table, the vertical cavity surface emitting laser further includes a third dielectric layer, the third dielectric layer is located on the upper surface of the second dielectric layer and the upper surface of the exposed first current diffusion layer; the first opening also penetrates the third dielectric layer along the thickness direction; the third dielectric layer has a second opening, the second opening exposes a portion of the first current diffusion layer; the second electrode is located in the second opening; and / or

[0027] When the second electrode is located on the lower surface of the heat dissipation substrate, the heat dissipation substrate includes a heat dissipation conductive substrate.

[0028] In some embodiments, when the epitaxial base structure has a mesa, the thickness of the first electrode and the thickness of the second electrode are both greater than or equal to 3 μm.

[0029] In some embodiments, the vertical cavity surface emitting laser includes at least one light-emitting area, and the light-emitting area includes a plurality of the light-emitting units; the plurality of light-emitting units are distributed at intervals along the first direction and the second direction within the light-emitting area, and along the first direction and the second direction, the spacing between adjacent light-emitting units is Gaussian distributed; the first direction is perpendicular to the second direction.

[0030] In some embodiments, there are multiple light-emitting areas, and the multiple light-emitting areas are arranged at intervals along the first direction and the second direction; the vertical cavity surface emitting laser also includes a junction area, and the junction area is located between adjacent light-emitting areas; the junction area has multiple light-emitting units arranged at intervals along the first direction and the second direction; within the junction area, along the first direction and the second direction, the spacing between adjacent light-emitting units is Gaussian distributed; the spacing between the light-emitting units in the junction area and the nearest light-emitting units of the adjacent light-emitting areas is greater than the maximum spacing between adjacent light-emitting units in the light-emitting area.

[0031] In a second aspect, the present application further provides a method for preparing a vertical cavity surface emitting laser, comprising:

[0032] providing a growth substrate;

[0033] forming an epitaxial base structure on the growth substrate; wherein the bottom layer of the epitaxial base structure is a first current diffusion layer, and the top layer of the epitaxial base structure is a second current diffusion layer;

[0034] The growth substrate is removed, and a heat dissipation substrate is bonded to the bottom of the epitaxial base structure to form a first electrode and a second electrode; the first electrode is located on the epitaxial base structure and extends into the epitaxial base structure; the second electrode is located on the lower surface of the heat dissipation substrate; or the epitaxial base structure has a table, the table exposes a portion of the upper surface of the first current diffusion layer, and the second electrode is located on the upper surface of the first current diffusion layer.

[0035] In the method for preparing the vertical cavity surface emitting laser in the above embodiment, the top surface of the epitaxial base structure is not covered by a capping layer, which greatly reduces the absorption of short waves and is suitable for the field of short wave technology; and the vertical cavity surface emitting laser uses a heat dissipation substrate with a small thermal resistance, thereby ensuring the performance of the vertical cavity surface emitting laser.

[0036] In some embodiments, before forming the epitaxial base structure on the growth substrate, the method further includes: forming an etch stop layer on the upper surface of the growth substrate;

[0037] The forming of the epitaxial basic structure on the growth substrate includes: forming the first current diffusion layer on the upper surface of the etch stop layer; forming a first Bragg reflective layer on the upper surface of the first current diffusion layer; forming an active layer on the upper surface of the first Bragg reflective layer; forming a second Bragg reflective layer and a layer to be oxidized on the active layer, wherein the layer to be oxidized is located between the active layer and the second Bragg reflective layer or within the second Bragg reflective layer; forming a second current diffusion layer on the upper surface of the second Bragg reflective layer; and forming a cap layer on the upper surface of the second current diffusion layer.

[0038] In some embodiments, before removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming the first electrode and the second electrode, the method further includes:

[0039] forming an interconnect metal layer on the upper surface of the cap layer;

[0040] etching the cover layer to form a through hole in the cover layer;

[0041] forming a first dielectric layer, wherein the first dielectric layer covers the upper surface of the cover layer and the through hole, and the interconnection metal layer is located in the first dielectric layer;

[0042] Etching the first dielectric layer and the epitaxial base structure to form a trench; the trench penetrates the first dielectric layer, the second current diffusion layer, the second Bragg reflective layer, the layer to be oxidized, and the active layer in a thickness direction, and extends into the first Bragg reflective layer;

[0043] Oxidizing the layer to be oxidized based on the groove to obtain an oxide layer having a light-transmitting hole, wherein the light-transmitting hole is arranged correspondingly to the through hole above and below;

[0044] forming a second dielectric layer, wherein the second dielectric layer covers an upper surface of the first dielectric layer, an upper surface of the interconnect metal layer, and sidewalls and a bottom of the trench;

[0045] A first opening is formed in the second dielectric layer, wherein the first opening exposes the interconnection metal layer.

[0046] In some embodiments, removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming the first electrode and the second electrode include:

[0047] forming a first electrode, wherein the first electrode is located on the upper surface of the second dielectric layer, in the trench and in the first opening, and contacts the interconnect metal layer;

[0048] Providing a bonding substrate, and bonding the bonding substrate to the upper surface of the structure obtained in the previous step via a bonding layer;

[0049] removing the growth substrate and the etch stop layer;

[0050] forming a back-side interconnection metal layer on the lower surface of the first current diffusion layer;

[0051] Providing a heat dissipation substrate having a second electrode formed on the back side, and bonding the heat dissipation substrate to the lower surface of the back side interconnection metal layer;

[0052] The bonding substrate and the bonding layer are removed.

[0053] In some embodiments, removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming the first electrode and the second electrode include:

[0054] providing a bonding substrate, and bonding the bonding substrate to the upper surface of the cover layer via a bonding layer;

[0055] removing the growth substrate and the etch stop layer;

[0056] forming a back-side interconnection metal layer on the lower surface of the first current diffusion layer;

[0057] Providing the heat dissipation substrate and bonding the heat dissipation substrate to the lower surface of the backside interconnect metal layer;

[0058] removing the bonding substrate and the bonding layer;

[0059] forming an interconnect metal layer on the upper surface of the cap layer;

[0060] etching the cover layer to form a through hole in the cover layer;

[0061] forming a first dielectric layer, wherein the first dielectric layer covers the upper surface of the cover layer and the through hole, and the interconnection metal layer is located in the first dielectric layer;

[0062] Etching the first dielectric layer and the epitaxial base structure to form a trench; the trench penetrates the first dielectric layer, the second current diffusion layer, the second Bragg reflective layer, the layer to be oxidized, and the active layer in a thickness direction, and extends into the first Bragg reflective layer;

[0063] Oxidizing the layer to be oxidized based on the groove to obtain an oxide layer having a light-transmitting hole, wherein the light-transmitting hole is arranged correspondingly to the through hole above and below;

[0064] forming a second dielectric layer, wherein the second dielectric layer covers an upper surface of the first dielectric layer, an upper surface of the interconnect metal layer, and sidewalls and a bottom of the trench;

[0065] Etching and removing a portion of the second dielectric layer and the first dielectric layer to expose a portion of the cap layer;

[0066] Etching the cap layer, the second current diffusion layer, the second Bragg reflection layer, the oxide layer, the active layer, and the first Bragg reflection layer to expose a portion of the first current diffusion layer and form a mesa;

[0067] forming a third dielectric layer, wherein the third dielectric layer covers the upper surface of the second dielectric layer, the side of the mesa, and the exposed first current diffusion layer;

[0068] Etching the third dielectric layer located on the mesa, the second dielectric layer located on the mesa, and the third dielectric layer covering the first current diffusion layer to form a first opening and a second opening; the first opening is located on the mesa and penetrates the third dielectric layer and the second dielectric layer along the thickness direction to expose the interconnect metal layer; the second opening penetrates the third dielectric layer covering the first current diffusion layer along the thickness direction to expose the first current diffusion layer;

[0069] A first electrode and a second electrode are formed; the first electrode is located in the groove, in the first opening, and on the upper surface of the third dielectric layer on the mesa; and the second electrode is located in the second opening.

[0070] In some embodiments, before forming the epitaxial base structure on the growth substrate, the method further includes: forming an etch stop layer on the upper surface of the growth substrate;

[0071] The forming of the epitaxial base structure on the growth substrate includes: forming the second current diffusion layer on the upper surface of the etch stop layer; forming a second Bragg reflective layer on the upper surface of the second current diffusion layer; forming an active layer on the upper surface of the second Bragg reflective layer; forming a first Bragg reflective layer and a layer to be oxidized on the active layer, wherein the layer to be oxidized is located between the active layer and the first Bragg reflective layer or within the first Bragg reflective layer; forming a first current diffusion layer on the upper surface of the first Bragg reflective layer; and forming a cap layer on the upper surface of the first current diffusion layer.

[0072] In some embodiments, removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming the first electrode and the second electrode include:

[0073] removing the cover layer;

[0074] forming a back-side interconnection metal layer on the upper surface of the first current diffusion layer;

[0075] Providing a heat dissipation substrate having a second electrode formed on the back side, and bonding the heat dissipation substrate to the upper surface of the back side interconnection metal layer;

[0076] removing the growth substrate and the etch stop layer;

[0077] Turning the obtained structure over so that the heat dissipation substrate with the second electrode formed on the back side is located at the bottom layer;

[0078] forming an interconnect metal layer on the upper surface of the second current diffusion layer;

[0079] forming a first dielectric layer on the upper surface of the second current diffusion layer, wherein the interconnection metal layer is located in the first dielectric layer;

[0080] Etching the first dielectric layer and the epitaxial base structure to form a trench; the trench penetrates the first dielectric layer, the second current diffusion layer, the second Bragg reflective layer, the layer to be oxidized, and the active layer in a thickness direction, and extends into the first Bragg reflective layer;

[0081] Oxidizing the layer to be oxidized based on the groove to obtain an oxide layer having a light-transmitting hole, wherein the light-transmitting hole is arranged correspondingly to the through hole above and below;

[0082] forming a second dielectric layer, wherein the second dielectric layer covers an upper surface of the first dielectric layer, an upper surface of the interconnect metal layer, and sidewalls and a bottom of the trench;

[0083] forming a first opening in the second dielectric layer, wherein the first opening exposes the interconnect metal layer;

[0084] A first electrode is formed, where the first electrode is located on the upper surface of the second dielectric layer, in the trench and in the first opening, and is in contact with the interconnection metal layer.

[0085] In some embodiments, removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming the first electrode and the second electrode include:

[0086] removing the cover layer;

[0087] forming a back-side interconnection metal layer on the upper surface of the first current diffusion layer;

[0088] Providing the heat dissipation substrate, and bonding the heat dissipation substrate to the upper surface of the backside interconnect metal layer;

[0089] removing the growth substrate and the etch stop layer;

[0090] flipping the resulting structure over so that the heat dissipation substrate is located at the bottom layer;

[0091] forming an interconnect metal layer on the upper surface of the second current diffusion layer;

[0092] forming a first dielectric layer on the upper surface of the second current diffusion layer, wherein the interconnection metal layer is located in the first dielectric layer;

[0093] Etching the first dielectric layer and the epitaxial base structure to form a trench; the trench penetrates the first dielectric layer, the second current diffusion layer, the second Bragg reflective layer, the layer to be oxidized, and the active layer in a thickness direction, and extends into the first Bragg reflective layer;

[0094] Oxidizing the layer to be oxidized based on the groove to obtain an oxide layer having a light-transmitting hole, wherein the light-transmitting hole is arranged correspondingly to the through hole above and below;

[0095] forming a second dielectric layer, wherein the second dielectric layer covers an upper surface of the first dielectric layer, an upper surface of the interconnect metal layer, and sidewalls and a bottom of the trench;

[0096] Etching and removing a portion of the second dielectric layer and the first dielectric layer to expose a portion of the second current diffusion layer;

[0097] etching the second current diffusion layer, the second Bragg reflection layer, the oxide layer, the active layer, and the first Bragg reflection layer to expose a portion of the first current diffusion layer and form a mesa;

[0098] forming a third dielectric layer, wherein the third dielectric layer covers the upper surface of the second dielectric layer, the side of the mesa, and the exposed first current diffusion layer;

[0099] Etching the third dielectric layer located on the mesa, the second dielectric layer located on the mesa, and the third dielectric layer covering the first current diffusion layer to form a first opening and a second opening; the first opening is located on the mesa and penetrates the third dielectric layer and the second dielectric layer along the thickness direction to expose the interconnect metal layer; the second opening penetrates the third dielectric layer covering the first current diffusion layer along the thickness direction to expose the first current diffusion layer;

[0100] A first electrode and a second electrode are formed; the first electrode is located in the groove, in the first opening, and on the upper surface of the third dielectric layer on the mesa; and the second electrode is located in the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0101] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0102] Figures 1 to 4 Schematic diagram of the cross-sectional structure of a vertical cavity surface emitting laser provided in different embodiments of the present application;

[0103] Figure 5 A top view of a light-emitting area in the vertical cavity surface emitting laser provided in this application;

[0104] Figure 6 for Figure 5 Gaussian distribution diagram from d1 to d6;

[0105] Figure 7 A top view of multiple light-emitting areas and boundary areas in the vertical cavity surface emitting laser provided by this application;

[0106] Figure 8 for Figure 7Gaussian distribution diagram of d1 to d18; wherein d9 and d10 are the distances between the light-emitting unit in the boundary area and the nearest light-emitting unit in the adjacent light-emitting area;

[0107] Figures 9 to 26 This is a schematic diagram of the cross-sectional structure of the structure obtained in each step of the preparation method of the vertical cavity surface emitting laser provided in this application.

[0108] Description of reference numerals:

[0109] 1. Light-emitting unit; 111. First current diffusion layer; 112. First Bragg emission layer; 113. Active layer; 114. Second Bragg reflection layer; 115. Oxide layer; 1151. Light-transmitting hole; 1152. Layer to be oxidized; 116. Second current diffusion layer; 117. Cap layer; 118. Interconnection metal layer; 119. First electrode; 120. Second electrode; 121. Back-side interconnection metal layer; 122. Groove; 123. First dielectric layer; 124. Second dielectric layer; 125. Third dielectric layer; 2. Heat dissipation substrate; 21. Metal bonding layer; 3. Light-emitting region; 4. Junction region; 5. Growth substrate; 51. Etching stop layer; 6. Bonding substrate; 61. Bonding layer. DETAILED DESCRIPTION

[0110] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0111] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0112] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0113] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0114] In this application, unless otherwise specified or limited, the terms "connected" and "connection" should be understood in a broad sense. For example, they can refer to direct connection or indirect connection through an intermediate medium, internal communication between two elements, or interaction between two elements. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0115] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0116] See also Figures 1 to 8 The present application provides a vertical cavity surface emitting laser, which may include: a heat dissipation substrate 2 and at least one light emitting unit 1; the light emitting unit 1 includes:

[0117] An epitaxial base structure (not shown), the epitaxial base structure is located on the heat dissipation substrate 2; the bottom layer of the epitaxial base structure may be a first current diffusion layer, and the top layer of the epitaxial base structure may be a second current diffusion layer;

[0118] A first electrode 119 is located on the epitaxial base structure and extends into the epitaxial base structure;

[0119] The second electrode 120 is located on the lower surface of the heat dissipation substrate 2; or the epitaxial base structure has a table, the table exposes a portion of the upper surface of the first current diffusion layer 111, and the second electrode 120 is located on the upper surface of the first current diffusion layer 111. Specifically, Figure 1 and Figure 3 As shown, the second electrode 120 is located on the lower surface of the heat dissipation substrate 2; Figure 2 and Figure 4 As shown, the epitaxial base structure has a mesa, which exposes a portion of the upper surface of the first current diffusion layer 111 . At this time, the second electrode 120 is located on the upper surface of the first current diffusion layer 111 .

[0120] In the vertical cavity surface emitting laser of the above embodiment, the top surface of the epitaxial base structure is not covered with a capping layer, which greatly reduces the absorption of short waves and is suitable for the field of short wave technology; and the vertical cavity surface emitting laser adopts a heat dissipation substrate 2, which has a smaller thermal resistance, thereby ensuring the performance of the vertical cavity surface emitting laser.

[0121] As an example, see Figures 1 to 4 , the extension infrastructure may also include:

[0122] a first Bragg reflection layer 112 , the first Bragg reflection layer 112 being located on an upper surface of the first current diffusion layer 111 ;

[0123] an active layer 113 , where the active layer 113 is located on an upper surface of the first Bragg reflector layer 112 ;

[0124] a second Bragg reflective layer 114 , the second Bragg reflective layer 114 being located above the active layer 113 ;

[0125] An oxide layer 115 , the oxide layer 115 is located between the second Bragg reflective layer 114 and the active layer 113 , or is located within the second Bragg reflective layer 114 ; the oxide layer 115 has a light-transmitting hole 115 penetrating along the thickness direction;

[0126] The second current spreading layer 116 is located on the upper surface of the second Bragg reflective layer 115 .

[0127] As an example, the first current spreading layer 111 may include, but is not limited to, a highly doped semiconductor layer. The first Bragg reflector layer 112 may be composed of alternating high-refractive-index layers having a thickness that is an odd multiple of a quarter of the lasing wavelength and low-refractive-index layers having a thickness that is an odd multiple of a quarter of the lasing wavelength. The second Bragg reflector layer 114 may also be composed of alternating high-refractive-index layers having a thickness that is an odd multiple of a quarter of the lasing wavelength and low-refractive-index layers having a thickness that is an odd multiple of a quarter of the lasing wavelength. The materials of the first and second Bragg reflector layers 112 and 114 may be III-V semiconductor materials, such as arsenides, phosphides, nitrides, and the like.

[0128] As an example, the polarities of the first Bragg reflector 112 and the second Bragg reflector 114 may be different; for example, the polarity of the first Bragg reflector 112 may be P-type, and in this case the polarity of the second Bragg emitter 114 is N-type; of course, in other examples, the polarity of the first Bragg reflector 112 may be N-type, and in this case the polarity of the second Bragg emitter 114 is P-type.

[0129] As an example, the polarities of the first Bragg reflector 112 and the second Bragg reflector 114 may be partially the same; for example, a tunnel junction may be associated with the first Bragg reflector 112 or the second Bragg reflector 114 so that the first Bragg reflector 112 is entirely or partially of the same type as the second Bragg reflector 114, or the second Bragg reflector 114 is entirely or partially of the same type as the first Bragg reflector 112.

[0130] As an example, active layer 113 may include active thin layers and tunnel junctions stacked sequentially from bottom to top, with both the bottom layer and the top layer of active layer 113 being active thin layers. By configuring active layer 113 as a stacked structure comprising alternating active thin layers and tunnel junctions, the gain of the vertical cavity surface emitting laser can be increased compared to a single active layer structure. The thickness of active layer 113 may be an integer multiple of half the lasing wavelength.

[0131] As an example, see Figure 1 and Figure 2 The epitaxial base structure further includes a cap layer 117, which is located on the upper surface of the second current diffusion layer 116; the cap layer 117 has a through hole (not shown) running through it along the thickness direction, and the through hole is arranged correspondingly to the light-transmitting hole 1151 above and below.

[0132] In the vertical cavity surface emitting laser of the above embodiment, although the epitaxial base structure has a cap layer 117, the cap layer 117 has a through hole corresponding to the light-transmitting hole, which can increase the current density corresponding to the light-transmitting hole area and greatly reduce the absorption of short waves, and is suitable for the field of short-wave technology.

[0133] As an example, the material of the cap layer 117 may include, but is not limited to, gallium arsenide.

[0134] As an example, the vertical cavity surface emitting laser may further include a back-side interconnection metal layer 121 , which is located between the metal bonding layer 21 and the epitaxial base structure; specifically, the back-side interconnection metal layer 121 may be located between the metal bonding layer 21 and the first current diffusion layer 111 .

[0135] As an example, the material of the backside interconnection metal layer 121 may include, but is not limited to, Ti (titanium) / Au (gold).

[0136] As an example, the vertical cavity surface emitting laser may also include:

[0137] A trench 122 is located in the epitaxial base structure; a portion of the first electrode 119 extending into the epitaxial base structure is located in the trench 122;

[0138] The first dielectric layer 123 is located on the upper surface of the epitaxial base structure; when the top layer of the epitaxial base structure is the cap layer 117, the first dielectric layer 123 covers the upper surface of the cap layer 117, such as Figure 1 and Figure 2 When the topmost layer of the epitaxial base structure is the second current diffusion layer 116, the first dielectric layer 123 covers the second current diffusion layer 116, as shown Figure 3 and Figure 4 As shown;

[0139] An interconnect metal layer 118 , the interconnect metal layer 118 is located on the upper surface of the epitaxial base structure and is located within the first dielectric layer 123 ;

[0140] A second dielectric layer 124 , the second dielectric layer 124 being located on the upper surface of the first dielectric layer 123 , the upper surface of the interconnect metal layer 118 , and the sides and bottom of the trench 122 ;

[0141] A first opening (not shown) penetrates the second dielectric layer 124 along the thickness direction and exposes the interconnection metal layer 118 ; the first electrode 119 is also located in the first opening and contacts the interconnection metal layer 118 .

[0142] Specifically, the material of the first dielectric layer 123 and the material of the second dielectric layer 124 can be set according to actual needs and are not specifically limited here.

[0143] As an example, Figure 2 and Figure 4 As shown, when the epitaxial base structure has a mesa, the VCSEL further includes a third dielectric layer 125, which is located on the upper surface of the second dielectric layer 124 and the upper surface of the exposed first current diffusion layer 111. The first opening also penetrates the third dielectric layer 125 along the thickness direction. The third dielectric layer 125 has a second opening (not shown), which exposes a portion of the first current diffusion layer 111. The second electrode 120 is located within the second opening, and the second electrode 120 is in contact with the first current diffusion layer 111. In this example, the heat dissipation substrate 2 may include, but is not limited to, an aluminum nitride substrate or a quartz substrate. The material of the third dielectric layer 125 can be set according to actual needs and is not specifically limited here.

[0144] As an example, Figure 1 and Figure 3 As shown, when the second electrode 120 is located on the lower surface of the heat dissipation substrate 2, the heat dissipation substrate 2 may include a heat dissipation conductive substrate; the heat dissipation substrate 2 may include but is not limited to a silicon carbide substrate or a copper substrate, etc.

[0145] As an example, the VCSEL may further include a metal bonding layer 21, and the heat dissipation substrate 2 may be bonded to the lower surface of the backside interconnect metal layer 121 via the metal bonding layer 21. The material of the metal bonding layer 21 may include but is not limited to tin gold (AuSn).

[0146] As an example, Figure 2 and Figure 4 As shown, when the epitaxial base structure has a mesa, the thickness of the first electrode 119 and the thickness of the second electrode 120 are both greater than or equal to 3 μm. By setting the thickness of the first electrode 119 and the second electrode 120 to be relatively thick (greater than or equal to 3 μm), heat dissipation can be enhanced. The materials of the first electrode 119 and the second electrode 120 can both include, but are not limited to, gold (Au).

[0147] As an example, combine Figures 1 to 4 See Figure 5 and Figure 6 The vertical cavity surface emitting laser includes at least one light emitting region 3, and the light emitting region 3 includes a plurality of light emitting units 1; the plurality of light emitting units 1 are arranged in the light emitting region 3 along a first direction (such as Figure 5 in the horizontal direction) and the second direction (such as Figure 5 The longitudinal direction in the middle is distributed at intervals, and the spacing between adjacent light emitting units 1 along the first direction and the second direction is Gaussian distribution, such as Figure 6 As shown, the spacings d1 to d6 between adjacent light-emitting units 1 spaced apart along a first direction are Gaussian distributed; the first direction is perpendicular to the second direction. The spacings between adjacent light-emitting units 1 along both the first and second directions are Gaussian distributed, allowing the spacing between adjacent light-emitting units 1 at the center of the light-emitting region 3 to be greater than the spacing between adjacent light-emitting units 1 at the edge of the light-emitting region 3, thereby preventing heat accumulation within the light-emitting region 1.

[0148] As an example, combine Figures 1 to 6 See Figure 7 and Figure 8 , there are multiple light-emitting regions 3, and the multiple light-emitting regions 3 are arranged at intervals along the first direction and the second direction; the vertical cavity surface emitting laser also includes a junction region 4, and the junction region 4 is located between adjacent light-emitting regions 3; the junction region 4 has multiple light-emitting units 1 arranged at intervals along the first direction and the second direction; in the junction region 4, along the first direction and the second direction, the spacing between adjacent light-emitting units 1 is Gaussian distributed, such as Figure 8 As shown; the spacing between the light-emitting unit 1 in the boundary area 4 and the light-emitting unit 1 closest to the adjacent light-emitting area 3 is greater than the maximum spacing between adjacent light-emitting units 1 in the light-emitting area 3, as shown Figure 8 As shown; Figure 8The diagram illustrates the distribution of spacings d1 to d18 between a plurality of adjacent light-emitting units 1 along the first direction. This distribution ensures that the spacing between adjacent light-emitting units 1 at the center of each light-emitting region 3 is greater than the spacing between adjacent light-emitting units 1 at the edge of each light-emitting region 3. Furthermore, the spacing between light-emitting units 1 in the central boundary region 4 and adjacent light-emitting regions 3 is maximized, thereby preventing heat accumulation in the light-emitting regions 1 and the boundary regions 4.

[0149] In another embodiment, see Figure 9 , the present application also provides a method for preparing a vertical cavity surface emitting laser, comprising:

[0150] S10: providing a growth substrate;

[0151] S11: forming an epitaxial base structure on a growth substrate; the bottom layer of the epitaxial base structure is a first current diffusion layer, and the top layer of the epitaxial base structure is a second current diffusion layer;

[0152] S12: Remove the growth substrate, bond the heat dissipation substrate to the bottom of the epitaxial base structure, and form a first electrode and a second electrode; the first electrode is located on the epitaxial base structure and extends into the epitaxial base structure; the second electrode is located on the lower surface of the heat dissipation substrate; or the epitaxial base structure has a table, the table exposes a portion of the upper surface of the first current diffusion layer, and the second electrode is located on the upper surface of the first current diffusion layer.

[0153] In the method for preparing the vertical cavity surface emitting laser in the above embodiment, the top surface of the epitaxial base structure is not covered by a capping layer, which greatly reduces the absorption of short waves and is suitable for the field of short wave technology; and the vertical cavity surface emitting laser uses a heat dissipation substrate with a small thermal resistance, thereby ensuring the performance of the vertical cavity surface emitting laser.

[0154] In step S10, refer to Figure 9 S10 steps in Figure 10 , providing a growth substrate 5.

[0155] As an example, the growth substrate 5 may include but is not limited to a gallium arsenide substrate.

[0156] As an example, before step S11 , that is, before forming the epitaxial basic structure on the growth substrate 5 , the following step is further included: forming an etching stop layer 51 on the upper surface of the growth substrate 5 .

[0157] As an example, the etch stop layer 51 may be formed on the upper surface of the growth substrate 5 by using, but not limited to, a chemical vapor deposition process or a physical vapor deposition process. The epitaxial base structure is formed on the upper surface of the etch stop layer 51 .

[0158] As an example, the etch stop layer 51 may include but is not limited to an aluminum gallium arsenide layer.

[0159] In an example, see Figure 10 In step S11, forming an epitaxial base structure on the growth substrate 5 may include the following steps:

[0160] S111: forming a first current diffusion layer 111 on the upper surface of the etch stop layer 51; the first current diffusion layer 111 may include but is not limited to a highly doped semiconductor layer;

[0161] S112: forming a first Bragg reflective layer 112 on the upper surface of the first current spreading layer 111; the first Bragg reflective layer 112 may be composed of alternating high refractive index layers having a thickness of an odd number multiple of a quarter of the lasing wavelength and low refractive index layers having a thickness of an odd number multiple of a quarter of the lasing wavelength;

[0162] S113: forming an active layer 113 on the upper surface of the first Bragg reflector layer 112; the active layer 113 may include active thin layers and tunnel junctions stacked sequentially from bottom to top, with the bottom layer and the top layer of the active layer 113 both being active thin layers;

[0163] S114: forming a second Bragg reflector layer 114 and a layer to be oxidized 1152 on the active layer 113. The layer to be oxidized 1152 may be located between the active layer 113 and the second Bragg reflector layer 114, or may be located within the second Bragg reflector layer 114. The second Bragg reflector layer 114 may also be composed of alternating high-refractive-index layers having a thickness of an odd-numbered multiple of a quarter of the lasing wavelength and low-refractive-index layers having a thickness of an odd-numbered multiple of a quarter of the lasing wavelength. The materials of the first Bragg reflector layer 112 and the second Bragg reflector layer 114 may be III-V semiconductor materials, such as arsenides, phosphides, nitrides, etc. The layer to be oxidized 1152 may include, but is not limited to, a layer of material with a high aluminum content.

[0164] S115 : forming a second current diffusion layer 116 on the upper surface of the second Bragg reflective layer 114 ;

[0165] S116 : forming a cap layer 117 on the upper surface of the second current diffusion layer 116 ; the cap layer 117 may include but is not limited to a gallium arsenide layer.

[0166] As an example, see Figure 11 Before step S12, that is, before removing the growth substrate 5, bonding the heat dissipation substrate 2 to the bottom of the epitaxial base structure, and forming the first electrode 119 and the second electrode 120, the following steps may also be included:

[0167] forming an interconnect metal layer 118 on the upper surface of the cover layer 117;

[0168] Etching the cap layer 117 to form a through hole (not shown) in the cap layer 117; specifically, the cap layer 117 may be etched using a photolithography process;

[0169] A first dielectric layer 123 is formed, the first dielectric layer 123 covers the upper surface of the cap layer 117 and the through hole, and the interconnection metal layer 118 is located in the first dielectric layer 123; the material of the first dielectric layer 123 can be set according to actual needs and is not specifically limited here;

[0170] The first dielectric layer 123 and the epitaxial base structure are etched to form a trench 122; the trench 122 penetrates the first dielectric layer 123, the cap layer 117, the second current diffusion layer 116, the second Bragg reflector layer 114, the layer to be oxidized 1152, and the active layer 113 in the thickness direction, and extends into the first Bragg reflector layer 112; specifically, the first dielectric layer 123 and the epitaxial base structure can be etched using, but not limited to, photolithography and dry etching processes to form the trench 122;

[0171] The layer to be oxidized 1152 is oxidized based on the groove 122 to obtain an oxide layer 115 having a light-transmitting hole 1151 , and the light-transmitting hole 1151 is arranged above and below the through hole;

[0172] A second dielectric layer 124 is formed, and the second dielectric layer 124 covers the upper surface of the first dielectric layer 123, the upper surface of the interconnect metal layer 118, and the sidewalls and bottom of the trench 122. The material of the second dielectric layer 124 can be set according to actual needs and is not specifically limited here.

[0173] A first opening (not shown) is formed in the second dielectric layer 124 , exposing the interconnection metal layer 118 .

[0174] In one example, in step S12, removing the growth substrate 5, bonding the heat dissipation substrate 2 to the bottom of the epitaxial base structure, and forming the first electrode 119 and the second electrode 120 may include:

[0175] S121: forming a first electrode 119, the first electrode 119 is located on the upper surface of the second dielectric layer 124, in the groove 122 and in the first opening, and is in contact with the interconnection metal layer 118, as shown in FIG. Figure 11 As shown;

[0176] S122: providing a bonding substrate 6, and bonding the bonding substrate 6 to the upper surface of the structure bonded in the previous step via a bonding layer 61; specifically, bonding the bonding substrate 6 to the upper surface of the second dielectric layer 124 via the bonding layer 61, and the bonding layer 61 covers the first electrode 119 located on the upper surface of the second dielectric layer 124, as shown in FIG. Figure 12As shown; the bonding substrate 6 may include but is not limited to a sapphire substrate; the bonding layer 61 may include but is not limited to a benzocyclobutene (BCB) layer;

[0177] S123: removing the growth substrate 5 and the etching stop layer 51, as shown in FIG. Figure 13 Specifically, any stripping process can be used to strip off the growth substrate 5 and the etch stop layer 51;

[0178] S124: forming a back-side interconnection metal layer 121 on the lower surface of the first current diffusion layer 111, such as Figure 13 As shown; the material of the backside interconnect metal layer 121 may include but is not limited to Ti (titanium) / Au (gold);

[0179] S125: providing a heat dissipation substrate 2 with a second electrode 120 formed on the back side, and bonding the heat dissipation substrate 2 to the lower surface of the back side interconnection metal layer 122, as shown in FIG. Figure 14 and Figure 15 As shown; the heat dissipation substrate 2 can be bonded to the lower surface of the back-side interconnect metal layer 121 through the metal bonding layer 21; the material of the metal bonding layer 21 can include but is not limited to tin gold (AuSn); the heat dissipation substrate 2 can include a heat dissipation conductive substrate; the heat dissipation substrate 2 can include but is not limited to a silicon carbide substrate or a copper substrate, etc.;

[0180] S126: removing the bonding substrate 6 and the bonding layer 61. The cross-sectional structure diagram of the structure obtained after step S126 is as follows: Figure 15 shown.

[0181] As an example, the thickness of the first electrode 119 is greater than or equal to 3 μm. By setting the thickness of the first electrode 119 to be thicker (greater than or equal to 3 μm), heat dissipation can be enhanced.

[0182] As an example, the material of the first electrode 119 may include but is not limited to gold (Au); the material of the second electrode 120 may include but is not limited to tin gold (AuSn).

[0183] In another example, in step S12, the growth substrate 5 is removed, the heat dissipation substrate 2 is bonded to the bottom of the epitaxial base structure, and the first electrode 119 and the second electrode 120 are formed, which may include the following steps:

[0184] S121: Provide a bonding substrate 6, and bond the bonding substrate 6 to the upper surface of the cap layer 117 via the bonding layer 61, as shown in FIG. Figure 16 As shown;

[0185] S122: removing the growth substrate 5 and the etching stop layer 51, such as Figure 16 Specifically, any stripping process can be used to remove the growth substrate 5 and the etching stop layer 51;

[0186] S123: forming a back-side interconnection metal layer 121 on the lower surface of the first current diffusion layer 111, such as Figure 16 As shown; the material of the backside interconnect metal layer 121 may include but is not limited to Ti (titanium) / Au (gold);

[0187] S124: Provide a heat dissipation substrate 2 and bond the heat dissipation substrate 2 to the lower surface of the backside interconnection metal layer 121, as shown in FIG. Figure 16 As shown; specifically, the heat dissipation substrate 2 is bonded to the upper surface of the back-side interconnection metal layer 121 via the metal bonding layer 21; the heat dissipation substrate 2 may include but is not limited to an aluminum nitride substrate or a quartz substrate, etc.; the material of the metal bonding layer 21 may include but is not limited to tin gold (AuSn);

[0188] S125: Remove the bonding substrate 6 and the bonding layer 61, as shown in FIG. Figure 17 As shown;

[0189] S126: forming an interconnection metal layer 118 on the upper surface of the cap layer 117, such as Figure 18 As shown;

[0190] S127: Etching the cap layer 117 to form a through hole in the cap layer 117, such as Figure 18 As shown;

[0191] S128: forming a first dielectric layer 123, the first dielectric layer 123 covers the upper surface of the cap layer 117 and the through hole, and the interconnection metal layer 118 is located in the first dielectric layer 123, as shown in FIG. Figure 18 As shown;

[0192] S129: Etching the first dielectric layer and the epitaxial base structure 123 to form a trench 122; the trench 122 penetrates the first dielectric layer 123, the cap layer 117, the second current diffusion layer 116, the second Bragg reflective layer 114, the layer to be oxidized 1152 and the active layer 113 along the thickness direction, and extends into the first Bragg reflective layer 112, as shown in FIG. Figure 18 Specifically, the first dielectric layer and the epitaxial base structure 123 may be etched by, but not limited to, photolithography and dry etching processes to form the trench 122;

[0193] S130: Oxidizing the layer to be oxidized 1152 based on the groove 122 to obtain an oxide layer 115 having a light-transmitting hole 1151. The light-transmitting hole 1151 is arranged correspondingly above and below the through hole, such as Figure 18 As shown;

[0194] S131: forming a second dielectric layer 124, the second dielectric layer 124 covers the upper surface of the first dielectric layer 123, the upper surface of the interconnect metal layer 118, the sidewalls and the bottom of the trench 122, as shown in FIG. Figure 18 As shown;

[0195] S132: etching and removing a portion of the second dielectric layer 124 and the first dielectric layer 123 to expose a portion of the cap layer 117, as shown in FIG. Figure 18 As shown;

[0196] S133: etching the cap layer 117, the second current diffusion layer 116, the second Bragg reflection layer 114, the oxide layer 115, the active layer 113 and the first Bragg reflection layer 112 to expose a portion of the first current diffusion layer 111 and form a mesa, such as Figure 19 As shown;

[0197] S134: forming a third dielectric layer 125, the third dielectric layer 125 covers the upper surface of the second dielectric layer 124, the side of the mesa and the exposed first current diffusion layer 111, as shown in FIG. Figure 19 As shown; the material of the third dielectric layer 125 can be set according to actual needs and is not specifically limited here;

[0198] S135: Etching the third dielectric layer 125 located on the mesa, the second dielectric layer 124 located on the mesa, and the third dielectric layer 125 covering the first current diffusion layer 111 to form a first opening (not labeled) and a second opening (not labeled); the first opening is located on the mesa and penetrates the third dielectric layer 125 and the second dielectric layer 124 along the thickness direction to expose the interconnect metal layer 118; the second opening penetrates the third dielectric layer 125 covering the first current diffusion layer 111 along the thickness direction to expose the first current diffusion layer 111;

[0199] S136: forming a first electrode 119 and a second electrode 120; the first electrode 119 is located in the groove 122, in the first opening and on the upper surface of the third dielectric layer 125 on the mesa; the second electrode 120 is located in the second opening, as shown in FIG. Figure 19 .

[0200] In the above example, the thickness of the first electrode 119 and the thickness of the second electrode 120 are both greater than or equal to 3 μm. By setting the thickness of the first electrode 119 and the second electrode 120 to be relatively thick (greater than or equal to 3 μm), heat dissipation can be enhanced. The materials of the first electrode 119 and the second electrode 120 can include, but are not limited to, gold (Au).

[0201] In another example, in step S11, forming the epitaxial base structure on the growth substrate 5 may include the following steps:

[0202] S111: forming a second current diffusion layer 116 on the upper surface of the etch stop layer 51;

[0203] S112: forming a second Bragg reflective layer 114 on the upper surface of the second current spreading layer 116; the second Bragg reflective layer 114 may be composed of alternating high refractive index layers having a thickness of an odd number multiple of a quarter of the lasing wavelength and low refractive index layers having a thickness of an odd number multiple of a quarter of the lasing wavelength;

[0204] S113: forming an active layer 113 on the upper surface of the second Bragg reflector layer 114; the active layer 113 may include active thin layers and tunnel junctions stacked sequentially from bottom to top, and the bottom layer and the top layer of the active layer 113 are both active thin layers;

[0205] S114: forming a first Bragg reflector layer 112 and a layer to be oxidized 1152 on the active layer 113. The layer to be oxidized 1152 may be located between the active layer 113 and the first Bragg reflector layer 112, or may be located within the first Bragg reflector layer 112. The first Bragg reflector layer 112 may be composed of alternating high-refractive-index layers having a thickness of an odd-numbered multiple of a quarter of the lasing wavelength and low-refractive-index layers having a thickness of an odd-numbered multiple of a quarter of the lasing wavelength. The materials of the first Bragg reflector layer 112 and the second Bragg reflector layer 114 may be III-V semiconductor materials, such as arsenides, phosphides, nitrides, etc. The layer to be oxidized 1152 may include, but is not limited to, a layer of material with a high aluminum content.

[0206] S115: forming a first current diffusion layer 111 on the upper surface of the first Bragg reflective layer 112; the first current diffusion layer 111 may include but is not limited to a highly doped semiconductor layer;

[0207] S116: forming a cap layer 117 on the upper surface of the first current diffusion layer 111; the cap layer 117 may include but is not limited to a gallium arsenide layer. The cross-sectional structure diagram of the structure obtained after step S116 is shown in FIG. Figure 20 shown.

[0208] In another example, in step S12, the growth substrate 5 is removed, the heat dissipation substrate 2 is bonded to the bottom of the epitaxial base structure, and the first electrode 119 and the second electrode 120 are formed, which may include the following steps:

[0209] S121: removing the cap layer 117; specifically, the cap layer 117 may be removed by, but is not limited to, an etching process;

[0210] S122: forming a back-side interconnection metal layer 121 on the upper surface of the first current diffusion layer 111; the material of the back-side interconnection metal layer 121 may include but is not limited to Ti (titanium) / Au (gold);

[0211] S123: providing a heat dissipation substrate 2 having a second electrode 120 formed on the back side, and bonding the heat dissipation substrate 2 to the upper surface of the back side interconnection metal layer 121; specifically, the heat dissipation substrate 2 is bonded to the upper surface of the back side interconnection metal layer 121 via the metal bonding layer 21, as shown in FIG. Figure 21 As shown; the material of the metal bonding layer 21 may include but is not limited to tin gold (AuSn); the heat dissipation substrate 2 may include a heat dissipation conductive substrate; the heat dissipation substrate 2 may include but is not limited to a silicon carbide substrate or a copper substrate, etc.;

[0212] S124: removing the growth substrate 5 and the etching stop layer 51, as shown in FIG. Figure 22 As shown;

[0213] S125: The obtained structure is turned over so that the heat dissipation substrate 2 with the second electrode 120 formed on the back is located at the bottom layer, as shown in FIG. Figure 23 As shown; at this time, the top layer is the second current diffusion layer 116;

[0214] S126: forming an interconnect metal layer 118 on the upper surface of the second current diffusion layer 116;

[0215] S127: forming a first dielectric layer 123 on the upper surface of the second current diffusion layer 116 , wherein the interconnection metal layer 118 is located in the first dielectric layer 123 ;

[0216] S128: Etching the first dielectric layer 123 and the epitaxial base structure to form a trench 122; the trench 122 penetrates the first dielectric layer 123, the second current diffusion layer 116, the second Bragg reflector 114, the layer to be oxidized 1152 and the active layer 113 along the thickness direction, and extends into the first Bragg reflector 112;

[0217] S129: Oxidizing the to-be-oxidized layer 1152 based on the groove 122 to obtain the oxide layer 115 having the light-transmitting hole 1151 , where the light-transmitting hole 1151 is arranged correspondingly to the through hole above and below;

[0218] S130: forming a second dielectric layer 124, where the second dielectric layer 124 covers the upper surface of the first dielectric layer 123, the upper surface of the interconnect metal layer 118, and the sidewalls and bottom of the trench 122;

[0219] S131 : forming a first opening (not shown) in the second dielectric layer 124 , wherein the first opening exposes the interconnect metal layer 118 ;

[0220] S132: forming a first electrode 119, the first electrode 119 is located on the upper surface of the second dielectric layer 124, in the groove 122 and in the first opening, and is in contact with the interconnection metal layer 118, as shown in FIG. Figure 23 shown.

[0221] As an example, the thickness of the first electrode 119 is greater than or equal to 3 μm. By setting the thickness of the first electrode 119 to be thicker (greater than or equal to 3 μm), heat dissipation can be enhanced.

[0222] As an example, the material of the first electrode 119 may include but is not limited to gold (Au); the material of the second electrode 120 may include but is not limited to tin gold (AuSn).

[0223] In another example, in step S12, removing the growth substrate 5, bonding the heat dissipation substrate 2 to the bottom of the epitaxial base structure, and forming the first electrode 119 and the second electrode 120 may include the following steps:

[0224] S121: removing the cover layer 117;

[0225] S122: forming a back-side interconnection metal layer 121 on the upper surface of the first current diffusion layer 111; the material of the back-side interconnection metal layer 121 may include but is not limited to Ti (titanium) / Au (gold);

[0226] S123: Provide a heat dissipation substrate 2, and bond the heat dissipation substrate 2 to the upper surface of the back-side interconnection metal layer 121; specifically, the heat dissipation substrate 2 is bonded to the upper surface of the back-side interconnection metal layer 121 via the metal bonding layer 21, as shown in FIG. Figure 24 As shown; the heat dissipation substrate 2 may include but is not limited to an aluminum nitride substrate or a quartz substrate, etc.; the material of the metal bonding layer 21 may include but is not limited to tin gold (AuSn);

[0227] S124: removing the growth substrate 5 and the etching stop layer 51, as shown in FIG. Figure 25 As shown;

[0228] S125: Flip the obtained structure so that the heat dissipation substrate 2 is located at the bottom layer; at this time, the top layer is the second current diffusion layer 116;

[0229] S126: forming an interconnect metal layer 118 on the upper surface of the second current diffusion layer 116;

[0230] S127: forming a first dielectric layer 123 on the upper surface of the second current diffusion layer 116, with the interconnection metal layer 118 located within the first dielectric layer 123; the material of the first dielectric layer 123 can be set according to actual needs and is not specifically limited here;

[0231] S128: Etching the first dielectric layer 123 and the epitaxial base structure to form a trench 122; the trench 122 penetrates the first dielectric layer 123, the second current diffusion layer 116, the second Bragg reflector layer 114, the layer to be oxidized 1152, and the active layer 113 along the thickness direction, and extends into the first Bragg reflector layer 112; specifically, the first dielectric layer and the epitaxial base structure 123 can be etched using, but not limited to, photolithography and dry etching processes to form the trench 122;

[0232] S129: Oxidizing the to-be-oxidized layer 1152 based on the groove 122 to obtain the oxide layer 115 having the light-transmitting hole 1151 , where the light-transmitting hole 1151 is arranged correspondingly to the through hole above and below;

[0233] S130: forming a second dielectric layer 124, where the second dielectric layer 124 covers the upper surface of the first dielectric layer 123, the upper surface of the interconnect metal layer 118, and the sidewalls and bottom of the trench 122; the material of the second dielectric layer 124 can be set according to actual needs and is not specifically limited here;

[0234] S131: etching and removing a portion of the second dielectric layer 124 and the first dielectric layer 123 to expose a portion of the second current diffusion layer 116;

[0235] S132: etching the second current diffusion layer 116, the second Bragg reflection layer 114, the oxide layer 115, the active layer 113 and the first Bragg reflection layer 112 to expose a portion of the first current diffusion layer 111 and form a mesa;

[0236] S133: forming a third dielectric layer 125, the third dielectric layer 125 covering the upper surface of the second dielectric layer 124, the side edges of the mesas, and the exposed first current diffusion layer 111; the material of the third dielectric layer 125 can be set according to actual needs and is not specifically limited here;

[0237] S134: Etching the third dielectric layer 125 located on the mesa, the second dielectric layer 124 located on the mesa, and the third dielectric layer 125 covering the first current diffusion layer 111 to form a first opening (not shown) and a second opening (not shown); the first opening is located on the mesa and penetrates the third dielectric layer 125 and the second dielectric layer 124 along the thickness direction to expose the interconnect metal layer 118; the second opening penetrates the third dielectric layer 125 covering the first current diffusion layer 111 along the thickness direction to expose the first current diffusion layer 111;

[0238] S135: forming a first electrode 119 and a second electrode 120; the first electrode 119 is located in the groove 122, in the first opening and on the upper surface of the third dielectric layer 125 on the mesa; the second electrode 120 is located in the second opening, as shown in FIG. Figure 26 shown.

[0239] In the above example, the thickness of the first electrode 119 and the thickness of the second electrode 120 are both greater than or equal to 3 μm. By setting the thickness of the first electrode 119 and the second electrode 120 to be relatively thick (greater than or equal to 3 μm), heat dissipation can be enhanced. The materials of the first electrode 119 and the second electrode 120 can include, but are not limited to, gold (Au).

[0240] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0241] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0242] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0243] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A vertical cavity surface emitting laser, characterized in that: a heat dissipation substrate and at least one light emitting unit; The light emitting unit includes: An epitaxial base structure is located on the heat dissipation substrate; the bottom layer of the epitaxial base structure is a first current diffusion layer, and the top layer of the epitaxial base structure is a second current diffusion layer; a first electrode, located on the epitaxial base structure and extending into the epitaxial base structure; The second electrode is located on the lower surface of the heat dissipation substrate; or the epitaxial base structure has a table, the table exposes a portion of the upper surface of the first current diffusion layer, and the second electrode is located on the upper surface of the first current diffusion layer.

2. The vertical cavity surface emitting laser according to claim 1, wherein: The epitaxial infrastructure further comprises: a first Bragg reflection layer, located on an upper surface of the first current diffusion layer; an active layer, located on an upper surface of the first Bragg reflector layer; a second Bragg reflection layer, located above the active layer; an oxide layer, located between the second Bragg reflective layer and the active layer, or located in the second Bragg reflective layer; the oxide layer has a light-transmitting hole penetrating along the thickness direction; The second current diffusion layer is located on an upper surface of the second Bragg reflection layer.

3. The vertical cavity surface emitting laser according to claim 2, characterized in that: The epitaxial basic structure further includes a capping layer, which is located on the upper surface of the second current diffusion layer. The capping layer has a through hole penetrating along the thickness direction, and the through hole is arranged correspondingly to the light-transmitting hole above and below.

4. The vertical cavity surface emitting laser according to claim 1, wherein: The vertical cavity surface emitting laser further includes a backside interconnection metal layer located between the heat dissipation substrate and the epitaxial base structure.

5. The vertical cavity surface emitting laser according to claim 1, wherein: The vertical cavity surface emitting laser further comprises: A trench is located in the epitaxial base structure; a portion of the first electrode extending into the epitaxial base structure is located in the trench; a first dielectric layer, located on the upper surface of the epitaxial base structure; an interconnect metal layer, located on the upper surface of the epitaxial base structure and within the first dielectric layer; a second dielectric layer, located on the upper surface of the first dielectric layer, the upper surface of the interconnect metal layer, and the sides and bottom of the trench; The first opening penetrates the second dielectric layer along the thickness direction and exposes the interconnection metal layer; the first electrode is also located in the first opening and contacts the interconnection metal layer.

6. The vertical cavity surface emitting laser according to claim 5, characterized in that: When the epitaxial base structure has a mesa, the vertical cavity surface emitting laser further includes a third dielectric layer, the third dielectric layer being located on the upper surface of the second dielectric layer and the upper surface of the exposed first current diffusion layer; the first opening also penetrates the third dielectric layer along the thickness direction; The third dielectric layer has a second opening therein, and the second opening exposes a portion of the first current diffusion layer; The second electrode is located in the second opening; and / or When the second electrode is located on the lower surface of the heat dissipation substrate, the heat dissipation substrate includes a heat dissipation conductive substrate.

7. The vertical cavity surface emitting laser according to claim 1, wherein: When the epitaxial base structure has a mesa, the thickness of the first electrode and the thickness of the second electrode are both greater than or equal to 3 μm.

8. The vertical cavity surface emitting laser according to any one of claims 1 to 7, characterized in that: The vertical cavity surface emitting laser includes at least one light-emitting area, and the light-emitting area includes a plurality of light-emitting units; the plurality of light-emitting units are distributed at intervals along a first direction and a second direction within the light-emitting area, and along the first direction and the second direction, the spacing between adjacent light-emitting units is Gaussian distributed; the first direction is perpendicular to the second direction.

9. The vertical cavity surface emitting laser according to claim 8, characterized in that: There are multiple light-emitting areas, and the multiple light-emitting areas are arranged at intervals along the first direction and the second direction; the vertical cavity surface emitting laser also includes a junction area, and the junction area is located between adjacent light-emitting areas; the junction area has multiple light-emitting units that are arranged at intervals along the first direction and the second direction; within the junction area, the spacing between adjacent light-emitting units along the first direction and the second direction is Gaussian distributed; the spacing between the light-emitting units in the junction area and the light-emitting units closest to the adjacent light-emitting areas is greater than the maximum spacing between adjacent light-emitting units in the light-emitting areas.

10. A method for preparing a vertical cavity surface emitting laser, characterized in that: include: providing a growth substrate; forming an epitaxial base structure on the growth substrate; The bottom layer of the epitaxial base structure is a first current diffusion layer, and the top layer of the epitaxial base structure is a second current diffusion layer; removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming a first electrode and a second electrode; the first electrode is located on the epitaxial base structure and extends into the epitaxial base structure; The second electrode is located on the lower surface of the heat dissipation substrate; or the epitaxial base structure has a table, the table exposes a portion of the upper surface of the first current diffusion layer, and the second electrode is located on the upper surface of the first current diffusion layer.

11. The method for preparing a vertical cavity surface emitting laser according to claim 10, wherein: Before forming the epitaxial base structure on the growth substrate, the method further includes: forming an etching stop layer on the upper surface of the growth substrate; The forming of the epitaxial basic structure on the growth substrate includes: forming the first current diffusion layer on the upper surface of the etch stop layer; forming a first Bragg reflective layer on the upper surface of the first current diffusion layer; forming an active layer on the upper surface of the first Bragg reflective layer; forming a second Bragg reflective layer and a layer to be oxidized on the active layer, wherein the layer to be oxidized is located between the active layer and the second Bragg reflective layer or within the second Bragg reflective layer; forming a second current diffusion layer on the upper surface of the second Bragg reflective layer; and forming a cap layer on the upper surface of the second current diffusion layer.

12. The method for preparing a vertical cavity surface emitting laser according to claim 11, wherein: Before removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming the first electrode and the second electrode, the method further includes: forming an interconnect metal layer on the upper surface of the cap layer; etching the cover layer to form a through hole in the cover layer; forming a first dielectric layer, wherein the first dielectric layer covers the upper surface of the cover layer and the through hole, and the interconnection metal layer is located in the first dielectric layer; Etching the first dielectric layer and the epitaxial base structure to form a trench; the trench penetrates the first dielectric layer, the second current diffusion layer, the second Bragg reflective layer, the layer to be oxidized, and the active layer in a thickness direction, and extends into the first Bragg reflective layer; Oxidizing the layer to be oxidized based on the groove to obtain an oxide layer having a light-transmitting hole, wherein the light-transmitting hole is arranged correspondingly to the through hole above and below; forming a second dielectric layer, wherein the second dielectric layer covers an upper surface of the first dielectric layer, an upper surface of the interconnect metal layer, and sidewalls and a bottom of the trench; A first opening is formed in the second dielectric layer, wherein the first opening exposes the interconnection metal layer.

13. The method for preparing a vertical cavity surface emitting laser according to claim 12, wherein: The step of removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming a first electrode and a second electrode comprises: forming a first electrode, wherein the first electrode is located on the upper surface of the second dielectric layer, in the trench and in the first opening, and contacts the interconnect metal layer; Providing a bonding substrate, and bonding the bonding substrate to the upper surface of the structure obtained in the previous step via a bonding layer; removing the growth substrate and the etch stop layer; forming a back-side interconnection metal layer on the lower surface of the first current diffusion layer; Providing a heat dissipation substrate having a second electrode formed on the back side, and bonding the heat dissipation substrate to the lower surface of the back side interconnection metal layer; The bonding substrate and the bonding layer are removed.

14. The method for preparing a vertical cavity surface emitting laser according to claim 11, wherein: The step of removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming a first electrode and a second electrode comprises: providing a bonding substrate, and bonding the bonding substrate to the upper surface of the cover layer via a bonding layer; removing the growth substrate and the etch stop layer; forming a back-side interconnection metal layer on the lower surface of the first current diffusion layer; Providing the heat dissipation substrate and bonding the heat dissipation substrate to the lower surface of the backside interconnect metal layer; removing the bonding substrate and the bonding layer; forming an interconnect metal layer on the upper surface of the cap layer; etching the cover layer to form a through hole in the cover layer; forming a first dielectric layer, wherein the first dielectric layer covers the upper surface of the cover layer and the through hole, and the interconnection metal layer is located in the first dielectric layer; Etching the first dielectric layer and the epitaxial base structure to form a trench; the trench penetrates the first dielectric layer, the second current diffusion layer, the second Bragg reflective layer, the layer to be oxidized, and the active layer in a thickness direction, and extends into the first Bragg reflective layer; Oxidizing the layer to be oxidized based on the groove to obtain an oxide layer having a light-transmitting hole, wherein the light-transmitting hole is arranged correspondingly to the through hole above and below; forming a second dielectric layer, wherein the second dielectric layer covers an upper surface of the first dielectric layer, an upper surface of the interconnect metal layer, and sidewalls and a bottom of the trench; Etching and removing a portion of the second dielectric layer and the first dielectric layer to expose a portion of the cap layer; Etching the cap layer, the second current diffusion layer, the second Bragg reflection layer, the oxide layer, the active layer, and the first Bragg reflection layer to expose a portion of the first current diffusion layer and form a mesa; forming a third dielectric layer, wherein the third dielectric layer covers the upper surface of the second dielectric layer, the side of the mesa, and the exposed first current diffusion layer; Etching the third dielectric layer located on the mesa, the second dielectric layer located on the mesa, and the third dielectric layer covering the first current diffusion layer to form a first opening and a second opening; the first opening is located on the mesa and penetrates the third dielectric layer and the second dielectric layer along the thickness direction to expose the interconnect metal layer; the second opening penetrates the third dielectric layer covering the first current diffusion layer along the thickness direction to expose the first current diffusion layer; A first electrode and a second electrode are formed; the first electrode is located in the groove, in the first opening, and on the upper surface of the third dielectric layer on the mesa; and the second electrode is located in the second opening.

15. The method for preparing a vertical cavity surface emitting laser according to claim 10, wherein: Before forming the epitaxial base structure on the growth substrate, the method further includes: forming an etching stop layer on the upper surface of the growth substrate; Forming an epitaxial base structure on the growth substrate includes: forming the second current diffusion layer on the upper surface of the etch stop layer; forming a second Bragg reflective layer on the upper surface of the second current diffusion layer; forming an active layer on the upper surface of the second Bragg reflective layer; forming a first Bragg reflective layer and a layer to be oxidized on the active layer, wherein the layer to be oxidized is located between the active layer and the first Bragg reflective layer, or located within the first Bragg reflective layer; forming a first current diffusion layer on the upper surface of the first Bragg reflective layer; and forming a cap layer on the upper surface of the first current diffusion layer.

16. The method for preparing a vertical cavity surface emitting laser according to claim 15, wherein: The step of removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming a first electrode and a second electrode comprises: removing the cover layer; forming a back-side interconnection metal layer on the upper surface of the first current diffusion layer; Providing a heat dissipation substrate having a second electrode formed on the back side, and bonding the heat dissipation substrate to the upper surface of the back side interconnection metal layer; removing the growth substrate and the etch stop layer; Turning the obtained structure over so that the heat dissipation substrate with the second electrode formed on the back side is located at the bottom layer; forming an interconnect metal layer on the upper surface of the second current diffusion layer; forming a first dielectric layer on the upper surface of the second current diffusion layer, wherein the interconnection metal layer is located in the first dielectric layer; Etching the first dielectric layer and the epitaxial base structure to form a trench; the trench penetrates the first dielectric layer, the second current diffusion layer, the second Bragg reflective layer, the layer to be oxidized, and the active layer in a thickness direction, and extends into the first Bragg reflective layer; Oxidizing the layer to be oxidized based on the groove to obtain an oxide layer having a light-transmitting hole, wherein the light-transmitting hole is arranged correspondingly to the through hole above and below; forming a second dielectric layer, wherein the second dielectric layer covers an upper surface of the first dielectric layer, an upper surface of the interconnect metal layer, and sidewalls and a bottom of the trench; forming a first opening in the second dielectric layer, wherein the first opening exposes the interconnect metal layer; A first electrode is formed, where the first electrode is located on the upper surface of the second dielectric layer, in the trench and in the first opening, and is in contact with the interconnection metal layer.

17. The method for preparing a vertical cavity surface emitting laser according to claim 15, wherein: The step of removing the growth substrate, bonding a heat dissipation substrate to the bottom of the epitaxial base structure, and forming a first electrode and a second electrode comprises: removing the cover layer; forming a back-side interconnection metal layer on the upper surface of the first current diffusion layer; Providing the heat dissipation substrate, and bonding the heat dissipation substrate to the upper surface of the backside interconnect metal layer; removing the growth substrate and the etch stop layer; flipping the resulting structure over so that the heat dissipation substrate is located at the bottom layer; forming an interconnect metal layer on the upper surface of the second current diffusion layer; forming a first dielectric layer on the upper surface of the second current diffusion layer, wherein the interconnection metal layer is located in the first dielectric layer; Etching the first dielectric layer and the epitaxial base structure to form a trench; the trench penetrates the first dielectric layer, the second current diffusion layer, the second Bragg reflective layer, the layer to be oxidized, and the active layer in a thickness direction, and extends into the first Bragg reflective layer; Oxidizing the layer to be oxidized based on the groove to obtain an oxide layer having a light-transmitting hole, wherein the light-transmitting hole is arranged correspondingly to the through hole above and below; forming a second dielectric layer, wherein the second dielectric layer covers an upper surface of the first dielectric layer, an upper surface of the interconnect metal layer, and sidewalls and a bottom of the trench; Etching and removing a portion of the second dielectric layer and the first dielectric layer to expose a portion of the second current diffusion layer; etching the second current diffusion layer, the second Bragg reflection layer, the oxide layer, the active layer, and the first Bragg reflection layer to expose a portion of the first current diffusion layer and form a mesa; forming a third dielectric layer, wherein the third dielectric layer covers the upper surface of the second dielectric layer, the side of the mesa, and the exposed first current diffusion layer; Etching the third dielectric layer located on the mesa, the second dielectric layer located on the mesa, and the third dielectric layer covering the first current diffusion layer to form a first opening and a second opening; the first opening is located on the mesa and penetrates the third dielectric layer and the second dielectric layer along the thickness direction to expose the interconnect metal layer; the second opening penetrates the third dielectric layer covering the first current diffusion layer along the thickness direction to expose the first current diffusion layer; A first electrode and a second electrode are formed; the first electrode is located in the groove, in the first opening, and on the upper surface of the third dielectric layer on the mesa; and the second electrode is located in the second opening.

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