Power device protection device and method and power conversion system

Abstract

The invention provides a protection device for a power device. The protection device comprises a detection circuit, a fault signal latch circuit and a control unit. The detection circuit is configured to detect whether the power device is in a fault state. The fault signal latch circuit is configured to output a drive prohibition signal for prohibiting the power device from being activated during a fault state based on the power device being in the fault state, and latch the drive prohibition signal during the fault state. And the control unit is configured to send a release signal to the fault signal latch circuit after judging that the fault state of the power device disappears, so that the driving prohibition signal is eliminated, and the power device can be started. The power device fault can be quickly responded, the power device is protected in time, the power device is prevented from being restarted by mistake, and repeated occurrence of the fault is avoided.

Description

Technical Field

[0001] The present application relates to a protection device and a protection method, and in particular to a protection device and a protection method for a power device. Background Art

[0002] In the field of power electronics, such as air conditioning, circuits typically incorporate one or more power devices, or power semiconductors. For example, power semiconductor switching devices like MOSFETs and IGBTs are widely used in various power conversion applications, including compact, high-efficiency rectification and variable-frequency inverters, due to their ease of driving, high current capacity, low on-resistance, and high voltage resistance. Summary of the Invention

[0003] The inventors have discovered that during device operation, abnormal power supply, improper operation, or mechanical failures often cause the device to malfunction, leading to power device failure and damage, resulting in the device being unable to start or operate. Because power devices are easily damaged in a short period of time after a failure, timely and effective fault protection must be implemented to prevent recurrence of the failure.

[0004] In existing technologies, one type of fault protection relies on an MCU to block the drive signal to power devices. This approach requires the MCU to respond quickly to power device faults, necessitating the use of the MCU's scarce interrupt resources and shutting off the PWM output to the power device within the device's safe operating range. Short-circuit faults typically occur within, for example, 10µs, requiring an MCU with superior performance and speed. This not only increases costs and places more stringent demands on the control algorithm, but also significantly increases the risk of power device failures not being promptly protected. For example, an inaccurate control algorithm increases the risk of power device failures not being promptly protected, leading to unreliable fault protection.

[0005] Another type of fault protection circuit uses a comparator flipping method. While this meets the protection rate requirements, the hardware characteristics of the comparator circuit are that it flips in real time based on the current state of the power device. This can cause the output to be cut off and then turned back on when a power device fails, preventing the protection from locking and causing repeated faults. The comparator flipping frequency combined with the switching frequency of the power device further increases the risk of power device damage. For example, when a power device fails, the comparator outputs a shutdown signal, reducing the current flowing through the power device. In this case, flipping the comparator based on the power device's reduced current to restart the power device is inappropriate because the power device fault may not have been eliminated.

[0006] To address the above-mentioned issues, the present application provides a power device protection device and protection method. The protection device includes a fault signal latch circuit and a control unit (e.g., including an MCU). Once a power device fault occurs, the fault signal latch circuit latches a drive disable signal to prohibit the power device from being started. The control unit detects that the fault has been resolved, at which point it controls the fault signal latch circuit to unlatch and allow the power device to be started.

[0007] Specifically, according to a first aspect of the present application, a protection device for a power device is provided, comprising a detection circuit, a fault signal latch circuit, and a control unit. The detection circuit is configured to detect whether the power device is in a fault state. The fault signal latch circuit is configured to output a drive disable signal based on the power device being in a fault state, and to latch the drive disable signal during the fault state, wherein the drive disable signal is used to disable the power device from being activated. The control unit is configured to, upon determining that the fault state of the power device has disappeared, send a release signal to the fault signal latch circuit, thereby eliminating the drive disable signal and enabling the power device to be activated.

[0008] According to the first aspect of the present application, the release signal is a pulse signal.

[0009] According to a first aspect of the present application, the fault signal latch circuit includes a latch configured to latch the drive disable signal and release the latch to eliminate the drive disable signal.

[0010] According to a first aspect of the present application, the fault signal latch circuit includes a digital logic circuit and a level conversion circuit. The digital logic circuit includes the latch. The digital logic circuit is configured to output an intermediate drive inhibit signal or an intermediate drive enable signal based on a signal from the detection circuit indicating whether the power device is in a fault state and whether a release signal from the control unit has been received. The level conversion circuit is configured to convert the intermediate drive inhibit signal and the intermediate drive enable signal of a first level into the drive inhibit signal and the drive enable signal of a second level, respectively, wherein the voltage corresponding to the first level is lower than the voltage corresponding to the second level. The drive enable signal is used to allow the power device to be started.

[0011] According to the first aspect of the present application, the level conversion circuit is a transistor drive circuit.

[0012] According to the first aspect of the present application, the fault signal latch circuit outputs the drive disable signal to the drive unit to prohibit the drive unit from outputting the drive control signal to the power device, or outputs the drive disable signal to the power device to prohibit the power device from being started.

[0013] According to the first aspect of the present application, the control unit is configured to receive a signal regarding the fault state from the detection circuit or the fault signal latch circuit.

[0014] According to a first aspect of the present application, the control unit is configured to generate fault status information based on the signal about the fault status, and the fault status information is used for troubleshooting the power device.

[0015] According to the first aspect of the present application, the control unit determines that the fault state of the power device disappears based on the feedback signal from the outside after the fault troubleshooting indicating that the power device is not in a fault state and the failure to receive the signal about the fault state.

[0016] According to the first aspect of the present application, the control unit stops outputting the control signal to the drive unit based on receiving the signal about the fault state, so that the drive unit stops outputting the drive control signal to the power device to stop the power device from operating.

[0017] According to the first aspect of the present application, when the protection device is initially started, the fault signal latch circuit outputs the drive disable signal, and during the initial inspection, the fault signal latch circuit latches the drive disable signal; and after the control unit determines that the power device is not in a fault state after the initial inspection, it outputs the release signal to the fault signal latch circuit, so that the drive disable signal is eliminated, thereby enabling the power device to be started.

[0018] According to a first aspect of the present application, the detection circuit generates the fault state based on at least one type of fault of the power device.

[0019] According to a second aspect of the present application, the present application provides a power conversion system comprising at least one power device, the aforementioned protection device, and a drive unit, wherein the drive unit is configured to generate a drive control signal based on a control signal from a control unit to drive the at least one power device to operate.

[0020] According to the third aspect of the present application, the present application provides a protection method for a power device, which includes: a detection circuit detecting whether the power device is in a fault state; a fault signal latch circuit outputting a drive disable signal based on the power device being in a fault state, and latching the drive disable signal during the fault state, wherein the drive disable signal is used to prohibit the power device from being started; and a control unit outputting a release signal to the fault signal latch circuit after determining that the fault state of the power device disappears, so that the drive disable signal is eliminated, thereby enabling the power device to be started.

[0021] According to a third aspect of the present application, the protection method further includes: the control unit outputting fault status information for troubleshooting based on the received signal regarding the fault status; and the control unit determining whether the fault status of the power device has disappeared after the troubleshooting. The control unit determines that the fault status of the power device has disappeared based on an external feedback signal indicating that the power device is not in a fault state and the absence of the signal regarding the fault status.

[0022] According to the third aspect of the present application, the above-mentioned protection method also includes: at the time of initial startup, the fault signal latch circuit outputs the drive disable signal and latches the drive disable signal during the initial inspection; and after the fault signal latch circuit determines that the power device is not in a fault state after the initial inspection, the fault signal latch circuit outputs the release signal to the fault signal latch circuit, so that the drive disable signal is eliminated, thereby enabling the power device to be started. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings are not drawn to scale. In the drawings, each identical or nearly identical component that is represented in different figures is represented by a like reference numeral. For clarity, not every component may be labeled in every figure. In the drawings:

[0024] Figure 1A shows a structural block diagram of a power conversion system according to a first embodiment of the present application;

[0025] Figure 1B shows a structural block diagram of a power conversion system according to a second embodiment of the present application;

[0026] Figure 1C shows a structural block diagram of a power conversion system according to a third embodiment of the present application;

[0027] Figure 2 Shown Figure 1A A truth table of a fault signal latch circuit according to an embodiment of the present invention is shown;

[0028] Figure 3 Shown Figure 1A A schematic structural diagram of a fault signal latch circuit according to an embodiment of the present invention is shown;

[0029] Figure 4 Shown Figure 3 The logic timing block diagram of the fault signal latch circuit shown;

[0030] Figure 5 A flow chart of a method for protecting a power device according to an embodiment of the present application is shown;

[0031] Figure 6 A structural block diagram showing a protection device according to the present application applied to a PWM rectifier power device circuit; and

[0032] Figure 7 A structural block diagram of a protection device according to the present application applied to a PFC power device circuit is shown. DETAILED DESCRIPTION

[0033] Various embodiments of the present application will be described below with reference to the accompanying drawings which constitute a part of this specification. It should be understood that, where possible, the same or similar reference numerals used in this application refer to the same components.

[0034] Figure 1A FIG. 1 shows a structural block diagram of a power conversion system according to a first embodiment of the present application. Figure 1B FIG. 4 shows a structural block diagram of a power conversion system according to a second embodiment of the present application. Figure 1C A structural block diagram of a power conversion system according to a third embodiment of the present application is shown.

[0035] like Figure 1A As shown, the power conversion system includes a control unit 101, a drive unit 102, a power device circuit 103, a detection circuit 104 and a fault signal latch circuit 105. The power device circuit 103 includes at least one power device 120. For example, the power device 120 is a MOSFET or an IGBT. The control unit 101 outputs a control signal to the drive unit 102, so that the drive unit 102 outputs a drive control signal to the power device 120, thereby controlling the connection and disconnection of the power device 120 (power switching device), and then controlling the power output from the power supply (not shown) to the load 108 via the power device circuit 103 to control the operation of the load 108. For example, the control unit 101 includes an MCU. This embodiment shows an application of a power conversion system to control a load. In other embodiments, the power conversion system is suitable for other suitable applications.

[0036] The protection device in the power conversion system is used to protect the operation of the power device 120. When a fault occurs in the power device 120, the power device 120 is prohibited from being activated until the fault is resolved, thereby protecting the power device from damage. The protection device includes a detection circuit 104, a fault signal latch circuit 105, and a control unit 101. The fault signal latch circuit 105 is a hardware circuit. When the power device 120 is in a fault state, the fault signal latch circuit 105 can quickly respond to output a drive disable signal to prohibit the power device from being activated, thereby promptly protecting the power device 120. Furthermore, the fault signal latch circuit 105 has a latching function that latches the drive disable signal during the fault state of the power device 120 and releases the latch until the fault state is resolved. This prevents the power device from being restarted inadvertently and avoids recurrence of the fault. Furthermore, the reliable latching function of the fault signal latch circuit 105 (hardware) significantly reduces the reliance of the fault protection on the MCU, as the MCU does not require a fast-response interrupt function, thereby reducing the cost of the selected MCU.

[0037] The detection circuit 104 is configured to detect whether the power device 120 is in a fault state. The fault signal latch circuit 105 is configured to output a drive disable signal based on the power device 120 being in a fault state, and latch the drive disable signal during the fault state of the power device 120. The drive disable signal is used to prohibit the power device 120 from being started. The control unit 101 is configured to send a release signal to the fault signal latch circuit 105 after determining that the fault state of the power device 120 disappears, so that the drive disable signal is eliminated, and the fault signal latch circuit 105 outputs a drive enable signal, thereby enabling the power device 120 to be started. The fault signal latch circuit 105 includes a latch 305 (see Figure 3 ), the latch is configured to latch the drive disable signal and release the latch to eliminate the drive disable signal. During a fault state, the latch latches the drive disable signal. Upon receiving a release signal from the control unit 101, the latch releases the latch to eliminate the drive disable signal. In other embodiments, the fault signal latch circuit 105 includes other suitable circuits to implement the above functions.

[0038] like Figure 1A As shown, the detection circuit 104 is connected to the power device circuit 103 via a connection line 121 to detect whether the power device 120 in the power device circuit 103 is in a fault state and output a fault monitoring signal to the fault signal latch circuit 105. The fault monitoring signal indicates whether the power device 120 is in a fault state or not.

[0039] The fault signal latch circuit 105 is connected to the detection circuit 104 via a connection line 122 to receive a fault monitoring signal. When the fault monitoring signal indicates that the power device 120 is in a fault state, the fault signal latch circuit 105 outputs a drive disable signal, for example, the signal FLT-RST is at a first level. During the fault state, the fault signal latch circuit 105 latches the drive disable signal. In one embodiment, the fault signal latch circuit 105 is connected to the drive unit 102 via a connection line 123 to output the drive disable signal to the drive unit 102, thereby prohibiting the drive unit 102 from outputting the drive control signal (PWM) to the power device 120, thereby prohibiting the power device 120 from being activated. At this time, if the control unit 101 outputs a control signal to the drive unit 102, the drive unit 102 is still prohibited from outputting the drive control signal until the drive disable signal is removed. In another embodiment, the fault signal latch circuit 105 is connected to the power device circuit 103 via a connection line 124 (see dashed line) to output the drive disable signal to the power device 120, thereby prohibiting the power device 120 from being activated. At this time, if the control unit 101 outputs a control signal to the driving unit 102 and the driving unit 102 outputs a driving control signal to the power device 120 , the power device 120 is still prohibited from outputting the driving control signal until the driving prohibition signal is eliminated.

[0040] The control unit 101 is configured to stop outputting the control signal to the drive unit 102 based on the signal about the fault state (the power device 120 is in), so that the drive unit 102 stops outputting the drive control signal PWM to the power device 120, so that the power device 120 stops running. In addition, the control unit 101 is also configured to generate fault state information based on the signal about the fault state, and the fault state information is used for troubleshooting of the power device. The fault state information includes the fault type, fault parameter value and / or fault indication signal, etc. In one embodiment, the control unit 101 receives a fault indication signal (a signal about the fault state) from the fault signal latch circuit 105, for example, the signal FLT is a first level. The control unit 101 is connected to the fault signal latch circuit 105 via the connecting line 125 to receive the fault / no fault indication signal FLT. In other embodiments, the control unit 101 receives a signal about the fault state from the detection circuit 104, see for details. Figures 1B-1C .

[0041] The protection system of the present application also includes a status indication module 109 and an external main control module 110. The status indication module 109 is connected to the control unit 101 via a connection line 127 to receive a fault indication signal (the indication signal indicates that the power device 120 is in a fault state), and is configured to send an alarm signal based on the fault indication signal to prompt the operator. The external main control module 110 is connected to the control unit 101 via a connection line 128 to receive a fault type and / or a fault parameter value. For example, the external main control module 110 is configured to display information about the fault type and / or the fault parameter value for the operator to perform troubleshooting. The operator troubleshoots the fault of the power device 120 based on the received alarm signal and / or the information about the fault type and / or the fault parameter value.

[0042] The control unit 101 determines that the fault state of the power device 120 has disappeared based on the external feedback signal indicating that the power device 120 is not in a fault state after troubleshooting, and the lack of a fault signal (from the fault signal latch circuit 105 and the detection circuit 104). For example, after troubleshooting, if the fault has been eliminated, the operator inputs a control signal to the external main control module 110, causing the external main control module 110 to send a fault elimination signal (a signal indicating that the power device 120 is not in a fault state) to the control unit 101. During the troubleshooting period, the detection circuit 104 continuously detects whether the power device 120 is in a fault state. When the detection circuit 104 detects that the power device 120 is not in a fault state, the control unit 101 does not receive a fault signal from the detection circuit 104 and the fault signal latch circuit 105. The control unit 101 determines that the fault state of the power device 120 has disappeared based on the lack of a fault signal and the receipt of a fault elimination signal from the external main control module 110. Furthermore, upon the disappearance of the fault state, the control unit 101 issues a release signal to the fault signal latch circuit 105, for example, signal CLR-FLT at the first level, causing the fault signal latch circuit 105 to release the latch on the drive disable signal, thereby eliminating the drive disable signal. The control unit 101 is connected to the fault signal latch circuit 105 via a connection line 126 to output the release signal to the fault signal latch circuit 105. At this point, the fault signal latch circuit 105 outputs a drive enable signal, for example, signal FLT-RST at the second level, to the drive unit 102, allowing the drive unit 102 to output the drive control signal PWM to the power device 120, thereby enabling the power device 120 to start. Furthermore, based on the signal indicating that the power device 120 is no longer in the fault state, the control unit 101 outputs a control signal to the drive unit 102, causing the drive unit 102 to output the drive control signal to the power device 120, thereby enabling the power device 120 to start operation. In one embodiment, the control unit 101 receives a fault-free indication signal (a signal indicating that the power device 120 is not in a fault state) from the fault signal latch circuit 105 via the connection line 125, for example, the signal FLT is at the second level. In other embodiments, the control unit 101 receives a signal indicating that the power device 120 is not in a fault state from the detection circuit 104, see Figures 1B-1C .

[0043] In one embodiment, the detection circuit 104 includes a sampling detection circuit 106 and a fault detection circuit 107. The sampling detection circuit 106 includes a current sampling circuit 111, a temperature sampling circuit 112, a short-circuit sampling circuit 113, and a voltage sampling circuit 114. The current sampling circuit 111 is configured to sample the current flowing through the power device 120 and output the sampled current value. The temperature sampling circuit 112 is configured to sample the temperature of the power device 120 and output the sampled temperature value. The short-circuit sampling circuit 113 is configured to sample the short-circuit parameter of the power device 120 and output the sampled short-circuit parameter value. The voltage sampling circuit 114 is configured to sample the voltage of the power device 120 and output the sampled voltage value. The fault detection circuit 107 includes an overcurrent detection circuit 115, an overtemperature detection circuit 116, a short-circuit detection circuit 117, and an overvoltage detection circuit 118. Overcurrent detection circuit 115 is configured to determine whether power device 120 is in an overcurrent fault state based on a sampled current value and output an overcurrent monitoring signal to fault signal latch circuit 105. Overtemperature detection circuit 116 is configured to determine whether power device 120 is in an overtemperature fault state based on a sampled temperature value and output an overtemperature monitoring signal to fault signal latch circuit 105. Short-circuit detection circuit 117 is configured to determine whether power device 120 is in a short-circuit fault state based on a short-circuit parameter value and output a short-circuit monitoring signal to fault signal latch circuit 105. Overvoltage detection circuit 118 is configured to determine whether power device 120 is in an overvoltage fault state based on a sampled voltage value and output an overvoltage monitoring signal to fault signal latch circuit 105. The fact that power device 120 is in at least one of an overcurrent fault state, an overtemperature fault state, a short-circuit fault state, and an overvoltage fault state indicates that power device 120 is in a fault state. Detection circuit 104 generates a fault state based on at least one type of fault in the power device. In other embodiments, the detection circuit 104 includes other suitable sampling detection circuits and fault detection circuits to implement the fault monitoring function.

[0044] Control unit 101 is connected to sampling detection circuit 106 of detection circuit 104 via connection line 129 to obtain a sampled operating parameter value of power device 120. As previously described, control unit 101 is configured to generate fault status information based on the signal regarding the fault status. In one embodiment, control unit 101 processes the sampled operating parameter value based on the signal regarding the fault status to generate the fault status information.

[0045] In one embodiment, the first level represents a low level, and the second level represents a high level. In another embodiment, the first level represents a high level, and the second level represents a low level.

[0046] Figure 1B The protection system shown is Figure 1A The protection system shown is basically the same. Figure 1B In the embodiment, the control unit 101 receives a signal regarding a fault state or a non-fault state from the sampling detection circuit 106 of the detection circuit 104. For example, the control unit 101 receives sampled current values, short-circuit parameter values, temperature values, and voltage values ​​from the sampling detection circuit 106 of the detection circuit 104, and determines the fault state based on these parameter values.

[0047] Figure 1C The protection system shown is Figure 1B The protection system shown is basically the same. Figure 1C In the embodiment, the control unit 101 receives a signal regarding a fault state or a non-fault state from the fault detection circuit 107 of the detection circuit 104. As previously described, the fault detection circuit 107 includes an overcurrent detection circuit 115, an overtemperature detection circuit 116, a short-circuit detection circuit 117, and an overvoltage detection circuit 118 to respectively obtain an overcurrent monitoring signal, an overtemperature monitoring signal, a short-circuit monitoring signal, and an overvoltage monitoring signal. In one embodiment, a digital logic circuit (not shown) may be provided in the fault detection circuit 107. The digital logic circuit is connected to the overcurrent detection circuit 115, the overtemperature detection circuit 116, the short-circuit detection circuit 117, and the overvoltage detection circuit 118 and configured to output a fault state signal based on at least one of the overcurrent monitoring signal, the overtemperature monitoring signal, the short-circuit monitoring signal, and the overvoltage monitoring signal indicating a corresponding fault state, thereby indicating that the power device 120 is in a fault state. The provision of the digital logic circuit enables the control unit 101 to receive a signal regarding a fault state or a non-fault state from the fault detection circuit 107 using a single signal port. The control unit 101 is connected to the fault detection circuit 107 via a connection line 130 to receive a signal regarding a fault state or a non-fault state.

[0048] Figure 2 Shown Figure 1A The truth table of the fault signal latch circuit of one embodiment is shown in FIG. Figure 1A As shown, the fault signal latch circuit 105 receives the overcurrent monitoring signal OC, the overtemperature monitoring signal OT, the short circuit monitoring signal SC and the overvoltage monitoring signal OV from the fault detection circuit 107 and the release / no release signal CLR-FLT from the control unit 101, and outputs the drive prohibition / enablement signal FLT-RST and outputs the fault / no fault indication signal FLT to the control unit 101.

[0049] like Figure 2As shown, in the truth table, "0" represents the first level and "1" represents the second level. For example, the first level represents a low level, and the second level represents a high level. For the overcurrent monitoring signal OC, overtemperature monitoring signal OT, short-circuit monitoring signal SC, and overvoltage monitoring signal OV, "0" indicates that the power device 120 is in the corresponding fault state, and "1" indicates that the power device 120 is not in the corresponding fault state. When the signals OC, OT, SC, and OV are not all "1," it indicates that the power device 120 is in a fault state. When the signals OC, OT, SC, and OV are all "1," it indicates that the power device 120 is not in a fault state. For the release / no release signal CLR-FLT, "0" indicates the release signal, and "1" indicates the absence of the release signal (which has no practical meaning). For the drive disable / enable signal FLT-RST, "0" indicates the drive disable signal, and "1" indicates the drive enable signal. For the fault / no fault indication signal FLT, "0" indicates the fault indication signal indicating that the power device is in a fault state, and "1" indicates the no fault indication signal indicating that the power device is not in a fault state. "-" means the state of the signal is not considered, and "X" means the signal does not exist. n Signal indicating the previous state, FLT n+1 Signal indicating the current status. FLT-RST n Signal indicating the previous state, FLT-RST n+1 A signal indicating the current state. The release signal (CLR-FLT is "0") is a pulse signal. In the default state, the signal CLR-FLT is "1." When the control unit 101 outputs the release signal, the signal CLR-FLT is "0" and returns to "1" after the pulse width has elapsed.

[0050] When the input signals OC, OT, SC, and OV are not all "1" (power device in fault state), the input signal CLR-FLT is not "0" (release signal). This is a constraint condition. In other words, the control unit 101 does not output a release signal based on the power device being in a fault state.

[0051] When the input signals OC, OT, SC and OV are not all "1" (the power device is in a fault state), the input signal CLR-FLT is "1" (no release signal), then the output signal FLT-RST n+1 =0 (drive disable signal, used to disable the power device from being started), and output signal FLT n+1 =0 (fault indication signal). At this time, the fault signal latch circuit 105 is in the "protection lock" state to prohibit the power device from being started and lock the prohibition operation. When the power device is prohibited from starting, the input signals OC, OT, SC and OV are all "1" (the power device is not in a fault state), then the output signal FLT-RSTn+1 and FLT n+1 The signal of the previous state is maintained, ie, the fault signal latch circuit 105 remains in the "protection lock" state.

[0052] After a period of time, if the input signal CLR-FLT from the control unit 101 is "0" (release signal, indicating that the fault state is eliminated), the output signal FLT-RST n+1 is "1" (driving enable signal, used to allow the power device to be started), and output signal FLT n+1 =1 (no fault indication signal). At this time, the fault signal latch circuit 105 is in the "protection reset" state to allow the power device to be started, and the control unit 101 and the drive unit 102 control the power device to start and operate normally. After the release signal has passed the pulse width, it returns to "1" (no release signal), and the output signal FLT-RST n+1 and FLT n+1 The signal of the previous state is maintained, ie, the fault signal latch circuit 105 is kept in the "protection reset" state.

[0053] According to the above truth table, the characteristic equation of the logic function is derived as follows:

[0054] FLT n+1 =SD+(CLR_FLT)FLT n Equation 1

[0055] SD + CLR_FLT = 1 Equation 2

[0056] SD=(OC)(OT)(SC)(OV) Equation 3

[0057] Among them, SD is the output signal obtained by performing a logical AND operation on the overcurrent monitoring signal OC, the over-temperature monitoring signal OT, the short-circuit monitoring signal SC and the overvoltage monitoring signal OV, and SD+CLR_FLT=1 is a constraint condition, that is, SD and CLR_FLT are not allowed to be "0" at the same time when the circuit is working.

[0058] The control unit 101 and the detection circuit 104 work together to enable the fault signal latch circuit 105 to operate in the following two states: when the power device is in a fault state, it is in a "protection lock" state to output and latch a drive disable signal, thereby prohibiting the power device from being activated; when the fault state is eliminated or no fault has occurred, it is in a "protection reset" state to output a drive enable signal, thereby allowing the power device to be activated. In other embodiments, the above-mentioned functions of the fault signal latch circuit 105 are implemented using other appropriate truth tables.

[0059] Figure 3 Shown Figure 1A FIG. 1 is a structural diagram of a fault signal latch circuit according to an embodiment of the present invention. Figure 3 The structure of the fault signal latch circuit is based on Figure 2 The truth table in is designed.

[0060] like Figure 3 As shown, the fault signal latch circuit 105 includes a digital logic circuit 301 and a level conversion circuit 302. As previously described, the fault signal latch circuit 105 receives the fault monitoring signals (OC, SC, OT, OV) from the detection circuit 104 and the release / no release signal CLR-FLT from the control unit 101, and outputs the fault / no fault indication signal FLT to the control unit 101 and the drive prohibition / enablement signal to the drive unit 102 or the power device 120. The control unit 101 is adapted to input and output signals of a first level, such as a voltage signal of approximately 3V. The release / no release signal CLR-FLT and the fault / no fault indication signal FLT are signals of a first level. The fault monitoring signal output by the detection circuit 104 is also a signal of a first level. The drive unit 102 is adapted to receive signals of a second level, such as a voltage signal of approximately 5V, and the power device 120 is adapted to receive signals of a third level, such as a voltage signal of approximately 15V. Therefore, the fault signal latch circuit 105 sets a digital logic circuit 301 to generate a signal related to the drive prohibition / enable signal, and sets a level conversion circuit 302 to level-convert the signal related to the drive prohibition / enable signal to generate a drive prohibition / enable signal suitable for output to the drive unit 102 or the power device 120.

[0061] The digital logic circuit 301 is configured to output an intermediate drive inhibit signal or an intermediate drive enable signal (a signal related to the drive inhibit / enable signal) of a first level based on the fault monitoring signal from the detection circuit 104 and whether a release signal is received from the control unit 101. The level conversion circuit 302 is configured to convert the intermediate drive inhibit signal and the intermediate drive enable signal of the first level into a drive inhibit signal and a drive enable signal of a second level, respectively, for output to the drive unit 102, or into a drive inhibit signal and a drive enable signal of a third level, respectively, for output to the power device 120. For example, the voltage corresponding to the first level is lower than the voltage corresponding to the second level, and the voltage corresponding to the second level is lower than the voltage corresponding to the third level.

[0062] In digital logic circuit 301, the two input terminals of AND gate circuit 306 receive fault monitoring signals OC and SC, respectively, and the two input terminals of AND gate circuit 307 receive fault monitoring signals OT and OV, respectively. The two input terminals of AND gate circuit 308 are connected to the output terminals of AND gate circuits 306 and 307, respectively, to receive the signals output by AND gate circuits 306 and 307, respectively. The output terminal of AND gate circuit 308 is connected to the connection point between the first resistor R1 and the third resistor R3 connected in series (one end of each resistor is connected to each other), and outputs signal SD. The other end of first resistor R1 is connected to power supply VDD, and the other end of third resistor R3 is connected to one end of first capacitor C1. The other end of first capacitor C1 is grounded. VDD is the power supply for control unit 101, for example, 3.3V. Digital logic circuit 301 includes latch 305, which includes NAND gate circuits 309 and 310. The first input terminal I1 of the NAND circuit 309 is connected to one end of the capacitor C. The second input terminal I2 of the NAND circuit 309 is connected to the output terminal Q2 of the NAND circuit 310. The output terminal Q1 of the NAND circuit 309 is connected to the first input terminal I3 of the NAND circuit 310. A second resistor R2 and a fourth resistor R4 (one end of each of which is connected to each other) are connected in series and receive the release / no release signal CLR-FLT from the control unit 101 at their connection point. The other end of the second resistor R2 is connected to the power supply VDD. The other end of the fourth resistor R4 is connected to the second input terminal I4 of the NAND circuit 310 and the second input terminal I6 of the NAND circuit 311. The output terminal Q2 of the NAND circuit 310 is also connected to the first input terminal I5 of the NAND circuit 311 and one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to one end of the second capacitor C2 and outputs the fault / no fault indication signal FLT to the control unit 101. The other end of the second capacitor C2 is grounded. The output terminal Q3 of the NAND gate circuit 311 is the output terminal 303 of the digital logic circuit 301. The output terminal 303 of the digital logic circuit 301 is connected to the input terminal 304 of the level conversion circuit 302. In other embodiments, other suitable digital logic circuits can be designed to achieve the above functions.

[0063] The level conversion circuit 302 is a transistor drive circuit. In the level conversion circuit 302, the input end of the diode D is the input end 304 of the level conversion circuit 302. The output end of the diode D is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to one end of the seventh resistor R7 and the base of the transistor T. The other end of the seventh resistor R7 is grounded. The emitter of the transistor T is grounded, and the collector of the transistor T is connected to one end of the eighth resistor R8. The transistor T outputs a fault / no fault indication signal FLT-RST to the drive unit 102. The transistor T is an NPN transistor. The other end of the eighth resistor R8 is connected to the power supply VCC. VCC is the power supply of the drive unit 102, for example, 5V. In other embodiments, other suitable level conversion circuits can be designed to convert the signal level output by the digital logic circuit 301 to a level suitable for output to the power device 120.

[0064] Figure 4 Shown Figure 3 The logic timing diagram of the fault signal latch circuit is shown in FIG. Figure 4 As shown, the input signal SD represents the signal obtained after the fault monitoring signals OC, SC, OT, and OV pass through the AND gate circuits 306, 307, and 308. In the logic timing diagram, the first level is a low level and the second level is a high level.

[0065] At time T0, the input signal SD from the detection circuit 104 is at the second level (indicating that the power device is not in a fault state), the input signal CLR-FLT from the control unit 101 is at the second level (indicating that the release signal has been removed), and the output signal FLT to the control unit 101 and the output signal FLT-RST remain at their previous states. Then, at time T1, the input signal CLR-FLT from the control unit 101 transitions to the first level (indicating that the control unit 101 outputs the release signal). The output signal FLT to the control unit 101 transitions to the second level, allowing the control unit 101 to output the control signal, and the output signal FLT-RST transitions to the second level, allowing the power device to start. Thus, the power device is activated by the control unit 101 and the drive unit 102 for normal operation. Then, at time T2, the input signal CLR-FLT from the control unit 101 transitions to the second level (indicating that the release signal has been removed) after a pulse width has elapsed. At this point, the output signals FLT and FLT-RST remain at their previous states, allowing the power device to continue normal operation. Next, at time T3, the detection circuit 104 detects that the power device is in a fault state. The input signal SD from the detection circuit 104 changes to the first level. The signal FLT output to the control unit 101 then changes to the first level, causing the control unit 101 to disable output of control signals and generate fault status information to instruct the operator to troubleshoot the fault. The output signal FLT-RST also changes to the first level, prohibiting the power device from starting. The first-level signal FLT-RST is latched until it receives a release signal from the control unit 101. Next, at time T4, after the power device has stopped operating, the detection circuit 104 detects that the power device is no longer in a fault state. The input signal SD from the detection circuit 104 changes to the second level. At this point, the output signals FLT and FLT-RST maintain their previous states, preventing the power device from starting.

[0066] Then, at time T5, after troubleshooting, the control unit 101 determines that the fault state has been eliminated and outputs a release signal to the fault signal latch circuit 105. That is, the input signal CLR-FLT from the control unit 101 changes to the first level (i.e., the release signal), and the signal FLT output to the control unit 101 changes to the second level, allowing the control unit 101 to output the control signal, and the output signal FLT-RST changes to the second level, allowing the power device to start. Therefore, the power device is started by the control unit 101 and the drive unit 102 to operate normally. Then, at time T6, the input signal CLR-FLT from the control unit 101 changes to the second level after the pulse width (indicating that the release signal has been eliminated). At this time, the output signals FLT and FLT-RST maintain their previous states, allowing the power device to continue normal operation. Then, at time T7, the detection circuit 104 detects that the power device is in a fault state. The input signal SD from the detection circuit 104 changes to the first level. The signal FLT output to the control unit 101 changes to the first level, causing the control unit 101 to prohibit outputting control signals and generate fault status information to instruct the operator to troubleshoot the fault. The output signal FLT-RST also changes to the first level, prohibiting the power device from starting. Then, at time T8, the detection circuit 104 detects that the power device is not in a fault state after the power device stops operating. The input signal SD from the detection circuit 104 changes to the second level. At this time, the output signals FLT and FLT-RST maintain their previous states, so that the power device continues to be prohibited from starting.

[0067] Figure 5 A flow chart of a power device protection method according to an embodiment of the present application is shown.

[0068] like Figure 5 As shown, at step 502 , the power device protection method 500 is started. Then, the process proceeds from step 502 to step 504 .

[0069] At step 504, during initial startup of the power conversion system, fault signal latch circuit 105 outputs a drive disable signal (e.g., FLT_RST is at the first level) and latches this drive disable signal during the initial check. The drive disable signal is used to disable startup of power device 120. The process then proceeds from step 504 to step 506.

[0070] At step 506, after the initial check period, the control unit 101 determines that the power device 120 is not in a fault state and outputs a release signal (e.g., CLR_FLT is at the first level) to the fault signal latch circuit 105. Then, the process proceeds from step 506 to step 508. The release signal is a pulse signal. After the pulse width has elapsed, the control unit 101 removes the release signal (e.g., CLR_FLT transitions to the second level).

[0071] At step 508, based on the release signal from the control unit 101, the drive disable signal is eliminated, and the fault signal latch circuit 105 outputs a drive enable signal (e.g., FLT_RST transitions to the second level) to enable the power device 120 to be started. Then, the process proceeds from step 508 to step 510. In one embodiment, the fault signal latch circuit 105 also outputs a no-fault indication signal (e.g., FLT is at the second level) to the control unit 101.

[0072] At step 510, control unit 101 outputs a control signal to drive unit 102 based on the signal indicating that the power device is not in a fault state, causing drive unit 102 to output a drive control signal to power device 120, thereby enabling power device 120 to operate normally. The process then proceeds from step 510 to step 512. In one embodiment, control unit 101 outputs a control signal to drive unit 102 based on a fault-free indication signal from fault signal latch circuit 105.

[0073] At step 512, the detection circuit 104 detects whether the power device 120 is in a fault state. If the power device 120 is not in a fault state, the power device 120 continues to operate normally, and the process proceeds from step 512 to step 508. If the power device 120 is in a fault state, the process proceeds from step 512 to step 514.

[0074] At step 514, the fault signal latch circuit 105 outputs a drive disable signal (e.g., FLT_RST is at the first level) based on detection that the power device 120 is in a fault state, and latches the drive disable signal during the fault state, thereby prohibiting the power device 120 from being activated. Then, the process proceeds from step 514 to step 516. In one embodiment, the fault signal latch circuit 105 also outputs a fault indication signal (e.g., FLT is at the first level) to the control unit 101.

[0075] At step 516, the control unit 101 receives the signal regarding the fault status, generates fault status information for use in troubleshooting the power device 120, and stops outputting control signals to the drive unit 102. The process then proceeds from step 516 to step 518. In one embodiment, the control unit 101 processes the sampled operating parameter values ​​of the power device obtained from the sampling detection circuit 106 of the detection circuit 104 based on the fault indication signal from the fault signal latch circuit 105 to generate fault status information. The control unit 101 then outputs a signal related to the fault status information to an operator via the status indication module 109 and the external main control module 110, instructing the operator to perform fault troubleshooting.

[0076] At step 518, after the control unit 101 determines that the fault state of the power device has disappeared, it sends a release signal to the fault signal latch circuit 105, thereby enabling the power device 120 to be activated. The process then proceeds from step 518 to step 520. In one embodiment, the control unit 101 determines that the fault state of the power device has disappeared based on an external feedback signal indicating that the power device is not in a fault state after troubleshooting and the fact that no signal regarding the fault state has been received (e.g., no signal regarding the fault state has been received from the detection circuit 104 and the fault signal latch circuit 105).

[0077] At step 520, it is determined whether the device needs to be shut down. If the device does not need to be shut down, the process proceeds from step 520 to step 508, where the fault signal latch circuit 105 outputs a drive enable signal to enable the power device 120. If the device needs to be shut down, the process proceeds from step 520 to step 522 to stop the device.

[0078] Those skilled in the art will appreciate that the steps in the above control method are merely examples and do not necessarily imply that the control method must be divided into the above steps, nor do they necessarily imply that the steps must be performed in the order shown. For example, steps 514 and 516 may be performed simultaneously, as long as the designed steps can achieve protection operations for the power device.

[0079] Figure 6 The following is a structural block diagram showing a protection device according to the present application applied to a PWM rectifier power device circuit. Figure 7 A structural block diagram of a protection device according to the present application applied to a PFC power device circuit is shown. Figure 6 and Figure 7 The protective device in Figures 1A-1C The protective device is the same as in.

[0080] like Figure 6As shown, the detection circuit in the protection device is connected to the PWM rectifier power device circuit 601 to detect whether the power device 120 in the PWM rectifier power device circuit 601 is in a fault state. The fault signal latch circuit 105 in the protection device outputs a drive prohibition signal or a drive permission signal (FLT-RST signal) to the drive unit 102 or the PWM rectifier power device circuit 601, thereby prohibiting or allowing the power device 120 to be started.

[0081] like Figure 7 As shown, the detection circuit in the protection device is connected to the PFC power device circuit 701 to detect whether the power device 120 in the PFC power device circuit 701 is in a fault state. The fault signal latch circuit 105 in the protection device outputs a drive disable signal or a drive enable signal (FLT-RST signal) to the drive unit 102 or the PFC power device circuit 701, thereby disabling or enabling the activation of the power device 120. The sampling detection circuit 106 in the detection circuit 104 includes a current sampling circuit and a temperature sampling circuit, and the fault detection circuit 107 in the detection circuit 104 includes an overcurrent detection circuit and an overtemperature detection circuit.

[0082] This application can solve the problems of existing power device fault protection, such as the lack of rapid response, false protection, unreliable protection, and repeated faults. Furthermore, the reliable latching function of the fault signal latch circuit (hardware) greatly reduces the reliance of fault protection on the MCU, as the MCU does not require a fast-response interrupt function, thereby reducing the cost of the selected MCU.

[0083] Although the present application has been described in conjunction with the examples of the embodiments outlined above, it is likely that various alternatives, modifications, variations, improvements and / or substantial equivalents, whether known or currently or soon foreseeable, will be apparent to those skilled in the art. In addition, the technical effects and / or technical problems described in this specification are exemplary and not restrictive; so the disclosures in this specification may be used to solve other technical problems and have other technical effects and / or may solve other technical problems. Therefore, the examples of the embodiments of the present application as stated above are intended to be illustrative and not restrictive. Various changes may be made without departing from the spirit or scope of the present application. Therefore, the present application is intended to include all known or earlier developed alternatives, modifications, variations, improvements and / or substantial equivalents.

Claims

1. A protection device for power devices, characterized in that include: a detection circuit (104), the detection circuit (104) being configured to detect whether the power device is in a fault state; a fault signal latch circuit (105), the fault signal latch circuit (105) being configured to output a drive disable signal based on the power device being in a fault state, and latch the drive disable signal during the fault state, the drive disable signal being used to disable the power device from being started; and A control unit (101) is configured to: when it is determined that the fault state of the power device disappears, send a release signal to the fault signal latch circuit (105), so that the drive prohibition signal is eliminated, thereby enabling the power device to be started.

2. The protection device for power devices according to claim 1, characterized in that: The release signal is a pulse signal.

3. The protection device for power devices according to claim 1, characterized in that: The fault signal latch circuit (105) includes a latch (305) configured to latch the drive disable signal and release the latch to eliminate the drive disable signal.

4. The protection device for power devices according to claim 3, characterized in that: The fault signal latch circuit (105) comprises: a digital logic circuit (301), the digital logic circuit (301) including the latch (305), the digital logic circuit (301) being configured to output an intermediate drive prohibition signal or an intermediate drive permission signal based on a signal indicating whether the power device is in a fault state from the detection circuit (104) and whether a release signal from the control unit (101) is received; and A level conversion circuit (302) is configured to convert the intermediate drive prohibition signal and the intermediate drive enable signal of a first level into the drive prohibition signal and the drive enable signal of a second level, respectively, wherein a voltage corresponding to the first level is lower than a voltage corresponding to the second level, and the drive enable signal is used to allow the power device to be started.

5. The protection device for power devices according to claim 4, characterized in that: The level conversion circuit (302) is a transistor drive circuit.

6. The protection device for power devices according to claim 1, characterized in that: The fault signal latch circuit (105) outputs the drive prohibition signal to the drive unit (102) to prohibit the drive unit (102) from outputting the drive control signal to the power device, or outputs the drive prohibition signal to the power device to prohibit the power device from being started.

7. The protection device for power devices according to claim 6, characterized in that: The control unit (101) is configured to receive a signal regarding the fault state from the detection circuit (104) or the fault signal latch circuit (105).

8. The protection device for power devices according to claim 7, characterized in that: The control unit (101) is configured to generate fault status information based on the signal about the fault status, and the fault status information is used for troubleshooting the power device.

9. The protection device for power devices according to claim 8, characterized in that: The control unit (101) determines that the fault state of the power device disappears based on the feedback signal from the outside after the fault troubleshooting indicating that the power device is not in a fault state and the failure to receive the signal regarding the fault state.

10. The protection device for power devices according to claim 7, characterized in that: The control unit (101) stops outputting the control signal to the drive unit (102) based on receiving the signal about the fault state, so that the drive unit (102) stops outputting the drive control signal to the power device, so that the power device stops operating.

11. The protection device for power devices according to claim 1, characterized in that: When the protection device is initially started, the fault signal latch circuit (105) outputs the drive prohibition signal, and during the initial inspection period, the fault signal latch circuit (105) latches the drive prohibition signal; as well as After the control unit (101) determines that the power device is not in a fault state after the initial inspection, it outputs the release signal to the fault signal latch circuit (105) so that the drive prohibition signal is eliminated, thereby enabling the power device to be started.

12. The protection device for power devices according to claim 1, characterized in that: The detection circuit (104) generates the fault status based on at least one type of fault of the power device.

13. A power conversion system, characterized in that: The power conversion system comprises: at least one power device (120); The protection device according to any one of claims 1 to 12; and A driving unit (102) is configured to generate a driving control signal (PWM) based on a control signal from a control unit (101) to drive the at least one power device (120) to operate.

14. A protection method (500) for a power device, characterized in that include: The detection circuit detects whether the power device is in a fault state; A fault signal latch circuit outputs a drive disable signal based on the power device being in a fault state, and latches the drive disable signal during the fault state, wherein the drive disable signal is used to prohibit the power device from being started; as well as After determining that the fault state of the power device disappears, the control unit outputs a release signal to the fault signal latch circuit, so that the drive prohibition signal is eliminated, thereby enabling the power device to be started.

15. The protection method (500) for a power device according to claim 14, characterized in that Also includes: Outputting fault status information by the control unit based on the received signal about the fault status for use in troubleshooting; and The control unit determines whether the fault state of the power device disappears after the fault is checked, wherein the control unit determines that the fault state of the power device disappears based on a feedback signal from the outside indicating that the power device is not in a fault state and that the signal about the fault state is not received.

16. The protection method (500) for a power device according to claim 14, characterized in that Also includes: At initial startup, the fault signal latch circuit outputs the drive disable signal and latches the drive disable signal during an initial check period; and After the fault signal latch circuit determines that the power device is not in a fault state after the initial check, the release signal is output to the fault signal latch circuit to eliminate the drive prohibition signal, thereby enabling the power device to be started.

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