Improved ring oscillator capable of adjusting output oscillation frequency

Abstract

An improved ring oscillator capable of adjusting output oscillation frequency comprises a capacitor, a resistor, a NOR gate, an NAND gate, a first buffer, a second buffer, a first phase inverter, a second phase inverter, a third phase inverter and a Schmitt trigger. The input end of the NOR gate is connected with an enable signal, the output is connected with the input end A of the NAND gate, the input end B of the NAND gate is connected with one end of the capacitor, the output end of the NAND gate is connected with the input end of the first buffer, the output end of the first buffer is connected with the resistor, and the other end of the resistor is connected with the Schmitt trigger and the Schmitt trigger. The output end of the Schmitt trigger is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the second buffer. The oscillator circuit further comprises a third phase inverter connected between the second phase inverter and the input end of the NAND gate B. On the basis of a traditional oscillator circuit, an improved structure is used, the output frequency of the oscillator can be finely adjusted, low frequency can be achieved under the condition that many inverters are not used, and meanwhile the oscillator circuit can be simply and conveniently controlled to be switched on and off.

Description

Technical Field

[0001] The invention belongs to the technical field of analog circuits, relates to an oscillator circuit, and particularly relates to an improved oscillator circuit. Background Art

[0002] An oscillator circuit is an electronic circuit that automatically generates periodic electrical signals (such as sine waves and square waves). It is widely used in communications, electronic equipment, and measuring instruments. Oscillators primarily include crystal oscillators, LC oscillators, ring oscillators, and RC relaxation oscillators. Ring oscillators are widely used because of their simple structure, ease of implementation in integrated circuits, and small chip footprint.

[0003] Figure 1 The figure shows a basic ring oscillator. It consists of an odd number of logic inverters (NOT gates) connected in series, with the output of the last inverter connected back to the input of the first inverter, forming a closed loop. Its operating principle relies on the inherent propagation delay of the inverters. When the circuit is powered on, the first inverter inverts the initial state of the loop. This inverted signal, after a propagation delay, is transmitted to the next inverter, where it is inverted again. This signal continues through all odd-numbered inverters in this manner. Because the number of inverters is odd, when the signal returns to its starting point after a full circuit, its state is necessarily the opposite of its initial state. This inverted signal triggers a new inversion process, and this cycle repeats, generating continuous oscillations within the loop.

[0004] The oscillation frequency is mainly determined by the number of inverter stages and the average transmission delay of each inverter stage. The approximate calculation formula is

[0005] f≈1 / (2*N*Tpd)

[0006] Where N is the number of inverter stages (odd number), T pd The 2 in the formula is because the signal needs to propagate through the loop for two complete cycles (one high and one low level change) to form a complete oscillation cycle.

[0007] The oscillation frequency of a ring oscillator is discretely adjustable. Each time two inverter stages are added or removed, the frequency changes significantly, making fine tuning impossible. Furthermore, achieving lower frequencies requires adding a large number of inverters, significantly increasing the chip area. Ring oscillators are also very sensitive to process variations, power supply voltage fluctuations, and operating temperature changes, resulting in poor frequency stability and typically high output signal phase noise and jitter. Summary of the Invention

[0008] In response to the above-mentioned defects in the prior art, the present invention discloses an improved ring oscillator with adjustable output oscillation frequency, comprising a capacitor, a resistor, a NOR gate, a NAND gate, a first buffer, a second buffer, a first inverter, a second inverter, a third inverter, and a Schmitt trigger. The NOR gate has an input connected to an enable signal, an output connected to the A input of the NAND gate, a B input of the NAND gate connected to one end of the capacitor, an output of the NAND gate connected to the input of the first buffer, an output of the first buffer connected to a resistor, the other end of the resistor connected to the input of the Schmitt trigger, an output of the Schmitt trigger connected to the input of the second inverter, an output of the second inverter connected to the input of the third inverter, and an output of the third inverter connected to the second buffer. The oscillator circuit further comprises a first inverter connected between the second inverter and the B input of the NAND gate.

[0009] The present invention uses an improved structure based on the traditional oscillator circuit, which can finely and continuously adjust the oscillator output frequency, achieve a lower frequency without using more inverters, and can easily control the oscillator circuit switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG2 is a schematic diagram of a specific embodiment of a conventional ring oscillator circuit;

[0011] Figure 2 FIG2 is a schematic diagram showing a specific implementation of the improved oscillator circuit of the present invention;

[0012] Figure 3 The figure shows the output oscillation waveform of the oscillator of the present invention when the resistance is 0.5MΩ and the capacitance is 0.3pf;

[0013] Figure 4 The figure shows the output oscillation waveform of the oscillator of the present invention when the resistance is 0.5MΩ and the capacitance is 30pf;

[0014] Figure 5 The figure shows how the frequency of a traditional ring oscillator changes with the number of cascaded inverters.

[0015] Figure 6 The figure shows the change of the frequency of the ring oscillator with the improved structure with the capacitance value;

[0016] Figure 7 The diagram shows how the frequency of the ring oscillator with the improved structure changes with the resistance value of the resistor; DETAILED DESCRIPTION

[0017] In order to more intuitively and clearly describe the specific details of the technical solution of the present invention, a detailed description will be given below in conjunction with specific embodiments and example drawings.

[0018] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely explained below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0019] like Figure 2 As shown, the improved ring oscillator circuit with adjustable output oscillation frequency described in the present invention includes a capacitor, a resistor, a NOR gate, a NAND gate, a first buffer, a second buffer, a first inverter, a second inverter, a third inverter, and a Schmitt trigger. The NOR gate has an input connected to an enable signal, an output connected to the A input of the NAND gate, a NAND gate B input connected to one end of the capacitor, an NAND gate output connected to the first buffer input, the first buffer output connected to a resistor, the other end of the resistor connected to the Schmitt trigger input, the Schmitt trigger output connected to the second inverter input, the second inverter output connected to the third inverter input, and the third inverter output connected to the second buffer. The oscillator circuit also includes a first inverter connected between the second inverter and the NAND gate B input.

[0020] The oscillator circuit can control whether the oscillator circuit works by controlling an enable signal. When the enable signal is at a high level, the circuit will stop working and no longer output the oscillation frequency.

[0021] The capacitor and resistor in the circuit together form an RC delay. During normal oscillator operation, the enable signal is low. In the first state, the voltage at point Y jumps from low to high, while the voltages at points A and B jump from high to low. Consequently, the NAND gate output jumps from low to high. Because the voltage on capacitor C cannot change in a sudden manner, this inevitably triggers an RC circuit transient. The voltage at point X inevitably follows the voltage at point B, which drops. This negative transition keeps Y high. Since the NAND gate output is high and the voltages at points A and B are low, current flows through resistor R, charging capacitor C and gradually increasing the voltage at point X until it reaches the gate threshold voltage, causing Y to drop from high to low. This causes B to jump from low to high, and the NAND gate output to drop from high to low. During the first state, the oscillator circuit output signal is high. In the second state, similar to the first, after the gate states flip, X inevitably follows B and rises because the capacitor voltage cannot change in a sudden manner. This positive transition keeps Y low. Next, because the NAND gate output is low and B is high, capacitor C begins to discharge through the resistor and inverter, causing the voltage at point X to gradually decrease. When the voltage drops to the threshold voltage, Y jumps from a low level to a high level, repeating the first state. During the second state, the oscillator circuit output signal is low. This cycle repeats, generating an oscillating signal.

[0022] According to the charge conservation formula

[0023] i×dt=C×dV

[0024] There are

[0025] V≈iR

[0026] The charge and discharge time of the capacitor is thus obtained as

[0027] t≈RC

[0028] Finally, the oscillator output frequency formula can be obtained as

[0029] f≈1 / 2(RC+T pdall )

[0030] In the formula, T pd all Transmission delay refers to the delay in the signal passing through the inverter, Schmitt trigger, and buffer. During circuit operation, the charge and discharge time of a capacitor is much longer than the propagation delay of a logic gate. By changing the capacitance or resistance of a capacitor, and thereby the charge and discharge time, the oscillator's output frequency can be adjusted simply and continuously.

[0031] exist Figure 3 In the specific embodiment, the resistance is 0.5MΩ, the capacitance is 0.3pf, and the output oscillation frequency is 3.012MHz. Figure 4 In the specific embodiment, the resistor is 0.5MΩ and the capacitor is 30pf, and the output oscillation frequency is 32.98kHz. Due to the influence of transmission delay, the output oscillation frequency is not completely inversely proportional to the capacitance value, but the deviation is very small, and when the oscillation frequency is low, the transmission delay can be ignored.

[0032] Figure 5 In the figure, N is the number of cascaded inverters. As can be seen from the figure, the frequency that can be achieved by adjusting the number of cascaded inverters in the traditional ring oscillator is discontinuous and the frequency range is small. Figure 6 In the specific embodiment of the invention, the frequency range of the ring oscillator with the improved structure varies with the capacitance value, which is 0.5MHz to 62.5MHz. The range is large and can reach a lower frequency. Similarly, the output oscillation frequency can be changed by adjusting the resistance value. Figure 7 In a specific embodiment of the present invention, the frequency range of the ring oscillator with the improved structure varies with the resistance value of the resistor, which has a larger range and can reach a lower frequency.

[0033] The foregoing are the preferred embodiments of the present invention. Unless the preferred implementation modes in each preferred embodiment are obviously self-contradictory or based on a certain preferred implementation mode, each preferred implementation mode can be arbitrarily superimposed and used in combination. The embodiments and the specific parameters in the embodiments are only for the purpose of clearly describing the inventor's invention verification process, and are not intended to limit the patent protection scope of the present invention. The patent protection scope of the present invention shall still be based on its claims. Any equivalent structural changes made using the contents of the description and drawings of the present invention should also be included in the protection scope of the present invention.

Claims

1. An improved ring oscillator circuit with adjustable output oscillation frequency, comprising a capacitor, a resistor, a NOR gate, a NAND gate, a first buffer, a second buffer, a first inverter, a second inverter, a third inverter, and a Schmitt trigger; wherein one input of the NOR gate is connected to an enable signal, the output is connected to the A input of the NAND gate, the B input of the NAND gate is connected to one end of the capacitor, the output of the NAND gate is connected to the input of the first buffer, the output of the first buffer is connected to a resistor, the other end of the resistor is connected to the Schmitt trigger input, the output of the Schmitt trigger is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the second buffer. The oscillator circuit further comprises a third inverter connected between the second inverter and the B input of the NAND gate.

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