Semiconductor device and operating method thereof

Abstract

A semiconductor device and an operating method thereof are provided. The semiconductor device includes a first transistor, a second transistor, a first inductor, and a second inductor. The control end of the first transistor is used for receiving an input signal. The second transistor is connected in series with the first transistor. A first end of the second transistor is used for receiving an input signal at a first node. The first inductor is connected in series between the first transistor and the first node. The second inductor is connected to the control end of the second transistor. The first inductor and the second inductor are coupled to each other through a transformer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an operating method thereof. Background Art

[0002] In radio frequency (RF) circuit design, the front-end circuitry of radio frequency (RF) receivers, known as low-noise amplifiers (LNAs), plays a crucial role. In current applications, LNAs typically require differential signals to provide better noise immunity and a larger output swing. To convert the signal to differential form, a balun (balun) transformer is required to achieve the one-to-two conversion. However, the use of a balun has the disadvantage of inherent losses, which increases the overall noise figure and degrades performance. Summary of the Invention

[0003] One embodiment of the present disclosure provides a semiconductor device comprising a first transistor, a second transistor, a first inductor, and a second inductor. The control terminal of the first transistor is configured to receive an input signal. The second transistor is connected in series with the first transistor. The first terminal of the second transistor is configured to receive an input signal at a first node. The first inductor is connected in series between the first transistor and the first node. The second inductor is connected to the control terminal of the second transistor. The first and second inductors are coupled to each other via a transformer.

[0004] An embodiment of the present disclosure provides an operating method for a semiconductor device, comprising the following steps: receiving an input signal from each of a control terminal of a first transistor and a first terminal of a second transistor; in response to the input signal, sensing a current signal flowing through a first inductor, the first inductor being connected to the control terminal of the second transistor; and generating a first output signal at a second terminal of the second transistor.

[0005] One embodiment of the present disclosure provides a semiconductor device comprising a first transistor, a first inductor, a second transistor, and a second inductor. A first terminal of the first inductor is coupled to a first terminal of the first transistor. A first terminal of the second transistor is connected in series to a second terminal of the first inductor. The second inductor is connected to a control terminal of the second transistor. The first and second inductors are coupled to each other via a transformer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0008] Figure 2 According to some embodiments of the present disclosure Figure 1 A schematic diagram of a semiconductor device corresponding to the semiconductor device shown;

[0009] Figure 3A According to some embodiments of the present disclosure Figure 2 A schematic diagram of a semiconductor device corresponding to the semiconductor device shown;

[0010] Figure 3B corresponding to a transformer coupling common source (TC-CS) path CSP according to some embodiments of the present disclosure. Figure 3A A schematic diagram of a portion of a semiconductor device is shown;

[0011] Figure 3C corresponds to a transformer coupling common gate (TC-CG) path CGP according to some embodiments of the present disclosure. Figure 3A A schematic diagram of a portion of a semiconductor device is shown;

[0012] Figure 4 According to some embodiments of the present disclosure Figure 3A The layout diagram of the input transformer corresponding to the inductor shown;

[0013] Figure 5 According to some embodiments of the present disclosure Figure 3A The layout diagram of the output transformer corresponding to the inductor shown;

[0014] Figure 6 According to some embodiments of the present disclosure Figures 1 to 3A A flowchart of a method corresponding to the semiconductor device shown;

[0015] Figure 7 For designing and / or manufacturing according to some embodiments of the present disclosure Figures 1 to 3A A schematic diagram of a system of at least one semiconductor device is shown;

[0016] Figure 8 FIG. 1 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system and an associated IC manufacturing process according to some embodiments of the present disclosure.

[0017]

Explanation of symbols

[0018] 100, 200, 300: semiconductor devices

[0019] 400: Input transformer

[0020] 500: output transformer

[0021] 600:Method

[0022] 700, 800: system

[0023] 702: Processor

[0024] 704: Storage Media

[0025] 706: Computer program code

[0026] 707: Bus

[0027] 710:I / O interface

[0028] 712: Network interface

[0029] 714: Network

[0030] 716:Layout Design

[0031] 718: User Interface

[0032] 720: Manufacturing Unit

[0033] 722: Manufacturing Tools

[0034] 820: Design Studio

[0035] 822:IC Design Layout

[0036] 830: Shielded Room

[0037] 832: Shielding Data Preparation

[0038] 834:Shielding Manufacturing

[0039] 840:IC wafer fab

[0040] 842:Semiconductor wafer

[0041] 860:IC device

[0042] CGP:TC-CG path

[0043] CLG1, CP1, CP2: capacitors

[0044] CSP:TC-CS path

[0045] LDN, LDP: load

[0046] LG, LS: Inductors

[0047] LG41 to LG49, LN51 to LN53, LS41 to LS49, LP51 to LP57: Inductors LN, LP, LS1, LS2: Inductors

[0048] MN1, MN2, MP1, MP2: transistors

[0049] N11~N16, N21~N24, N33: nodes

[0050] OP61~OP63: Operation

[0051] R1: Resistor

[0052] VBSCN, VBSCP, VBSN, VBSP: bias voltage signals

[0053] VDD, VSS: reference voltage signal

[0054] VIN: input signal

[0055] VON, VOP: output signal DETAILED DESCRIPTION

[0056] The following disclosure provides different embodiments or examples of features for achieving the provided objectives. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. can be expected. For example, in the description below, forming a first feature above or on a second feature may include an embodiment in which the first and second features are directly contacted, and may also include an embodiment in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, the disclosure may repeat component symbols and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not, in itself, specify the relationship between the various embodiments or configurations discussed.

[0057] In addition, for ease of description, spatially relative terms such as "below," "beneath," "below," "above," and "above" may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. As used herein, "about," "approximately," or "substantially" may generally mean within 20%, or within 10%, or within 5% of a given value or range. The values ​​given herein are approximate, meaning that if not explicitly stated, the terms "about," "about," "approximately," or "substantially" can be inferred. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and may decrease as integrated circuits shrink.

[0058] The terms used in the following description and patent claims generally have their ordinary meanings as they are used in the art or in the specific context in which each term is used. A person skilled in the art will appreciate that a component or process may be referred to by different names. The numerous different embodiments detailed in this specification are for illustrative purposes only and are not intended to limit the scope or spirit of the disclosure or any exemplary term.

[0059] It should be noted that the terms "first" and "second" are used herein to describe various components or processes to distinguish between the components or processes. However, the components, processes, and their order are not limited by these terms. For example, a first component can be referred to as a second component, and a second component can be similarly referred to as a first component without departing from the scope of this disclosure.

[0060] In the following discussion and in the scope of the invention claims, the terms "comprising," "including," "containing," "having," "involving," etc. should be understood as open-ended, that is, to include but not limited to. As used herein, the term "and / or" is not mutually exclusive and includes any relevant listed items and all combinations of one or more relevant listed items.

[0061] Figure 1 FIG1 is a schematic diagram of a semiconductor device 100 according to some embodiments of the present disclosure. Semiconductor device 100 is configured to generate output signals VON and VOP based on an input signal VIN. In some embodiments, input signal VIN is referred to as a single input signal, and output signals VON and VOP are referred to as differential output signals. Semiconductor device 100 utilizes a single differential architecture to suppress common-mode noise and reduce even-order distortion, resulting in lower noise performance. Therefore, semiconductor device 100 is referred to as a single differential low-noise amplifier.

[0062] like Figure 1 Illustratively, semiconductor device 100 includes inductors LS and LG, capacitors CP1 and CP2, loads LDN and LDP, a resistor R1, and transistors MN1 and MP1. In some embodiments, transistors MN1 and MP1 have different conductivity types. For example, transistors MN1 and MP1 are implemented as an N-type metal-oxide-semiconductor (MOS) transistor and a P-type MOS transistor, respectively.

[0063] like Figure 1 For illustrative purposes, one terminal of load LDN is configured to receive reference voltage signal VDD, and the other terminal of load LDN is connected to transistor MN1 at node N11. One terminal of transistor MN1 is connected to load LDN at node N11, the other terminal of transistor MN1 is connected to inductor LS at node N12, and the control terminal of transistor MN1 is connected to capacitor CP1 at node N21. One terminal of capacitor CP1 is connected to node N21, and the other terminal of capacitor CP1 is configured to receive input signal VIN. One terminal of load LDP is configured to receive reference voltage signal VSS, and the other terminal of load LDN is connected to transistor MP1 at node N14. One terminal of transistor MP1 is connected to load LDP at node N14, the other terminal of transistor MP1 is connected to inductor LS at node N13, and the control terminal of transistor MP1 is connected to inductor LG at node N15. One terminal of inductor LG is connected to node N15, and the other terminal of inductor LG is configured to receive bias voltage signal VBSP at node N16. One end of the capacitor CP2 is connected to the node N13, and the other end of the capacitor CP1 is used to receive the input signal VIN. One end of the resistor R1 is connected to the node N21, and the other end of the resistor R1 is used to receive the bias voltage signal VBSN.

[0064] In some embodiments, the reference voltage signal VDD has a power supply voltage level, and the reference voltage signal VSS has a ground voltage level. In some embodiments, the voltage level of the reference voltage signal VDD is greater than the voltage level of the reference voltage signal VSS.

[0065] In some embodiments, the voltage level of bias voltage signal VBSN is lower than the voltage level of reference voltage signal VDD but higher than the voltage level of bias voltage signal VBSP. Furthermore, the voltage level of bias voltage signal VBSP is higher than the voltage level of reference voltage signal VSS. In some embodiments, bias voltage signals VBSN and VBSP are generated by a bias circuit. Note that the bias circuit is not shown in the figures.

[0066] In some embodiments, inductors LG and LS are coupled to each other via a transformer. Alternatively, a current signal flowing through inductor LS induces a current signal flowing through inductor LG. During operation, semiconductor device 100 generates a current signal based on input signal VIN via inductor LS and transistors MN1 and MP1. In some embodiments, transformer coupling of inductors LG and LS is referred to as input transformer coupling. The transformer corresponding to inductors LG and LS is referred to as a center-tapped transformer.

[0067] In some embodiments, regarding the polarity of inductors LG and LS, nodes N13 and N16 have the same polarity, and nodes N12 and N15 have the same polarity, which is opposite to the polarity of nodes N13 and N16. For example, when node N13 has a positive polarity in response to input signal VIN, node N16 also has a positive polarity, while node N15 has a negative polarity. Conversely, when node N13 has a negative polarity in response to input signal VIN, node N16 also has a negative polarity, while node N15 has a positive polarity. Therefore, inductors LG and LS are used to increase the voltage difference between the gate and source terminals of transistor MP1 (i.e., nodes N15 and N13), thereby enhancing the transconductance of semiconductor device 100.

[0068] In some embodiments, the inductors LG and LS and the transistors MN1 and MP1 correspond to a common source (CS) amplifier and a common gate (CG) amplifier. The CS amplifier and the CG amplifier are stacked to share the DC current flowing through the inductor LS, thereby improving the current efficiency. Therefore, the semiconductor device 100 is called a current reuse amplifier. Figure 3B and Figure 3C The related embodiments describe more details of the CS amplifier and the CG amplifier.

[0069] In some methods, the amplifier has a single-ended input and single-ended output structure and does not include an inductor. In these methods, common-mode noise cannot be eliminated and transconductance is not enhanced.

[0070] Compared to the above methods, in some embodiments of the present disclosure, the semiconductor device 100 has a single-ended input-differential output structure for noise reduction and includes inductors LS and LG for transconductance enhancement. In addition, the current reuse structure improves current efficiency.

[0071] Figure 2 According to some embodiments of the present disclosure Figure 1 The semiconductor device 100 shown is a schematic diagram of a semiconductor device 200 corresponding to the semiconductor device 100. Figure 2 and Figure 1 , the semiconductor device 200 is an alternative embodiment of the semiconductor device 100 . Figure 2 Follow and Figure 1 Similar markup conventions. For the sake of brevity, the discussion will focus more on Figure 2 and Figure 1 Compared to the semiconductor device 100 , the semiconductor device 200 includes inductors LN and LP instead of loads LDN and LDP.

[0072] like Figure 2 For illustrative purposes, one end of inductor LN is connected to node N11, and the other end of inductor LN is configured to receive reference voltage signal VDD at node N23. One end of inductor LP is connected to node N14, and the other end of inductor LP is configured to receive reference voltage signal VSS at node N24. One end of capacitor CP1 is connected to the control terminal of transistor MN1 at node N21, and the other end of capacitor CP1 is configured to receive input signal VIN. One end of capacitor CP2 is connected to node N13, and the other end of capacitor CP2 is configured to receive input signal VIN. One end of capacitor CLG1 is connected to inductor LS at node N22, and the other end of capacitor CLG1 is configured to receive reference voltage signal VSS.

[0073] In some embodiments, resistor R1 is used to provide a bias voltage signal VBSN to node N21. Resistor R2 is used to provide a bias voltage signal VBSP to node N16. Each of capacitors CP1, CP2, and CLG1 is used to filter a DC portion of a signal.

[0074] In some embodiments, the inductors LN and LP are coupled to each other via a transformer. Alternatively, a current signal flowing through one of the inductors LN and LP induces a current signal flowing through the other inductor LN and LP.

[0075] In some embodiments, with respect to the polarity of inductors LN and LP, nodes N11 and N24 have the same polarity, and nodes N14 and N23 have the same polarity, which is opposite to the polarity of nodes N11 and N24. For example, when node N11 has a positive polarity in response to output signal VON, node N24 also has a positive polarity, while nodes N14 and N23 have a negative polarity. Conversely, when node N11 has a negative polarity in response to output signal VON, node N24 also has a negative polarity, while nodes N14 and N23 have a positive polarity.

[0076] During operation, inductors LN and LP are coupled to each other to enhance the voltage gain of semiconductor device 200 and improve the balance of differential output signals VON and VOP. In some embodiments, the transformer coupling of inductors LN and LP is referred to as output transformer coupling.

[0077] In some approaches, there is no transformer-type inductor at the amplifier output. In these approaches, the differential output is poorly balanced, resulting in a large gain difference (Δ gain) and a phase difference (Δ phase) far from 180 degrees.

[0078] Compared to the above-described method, in some embodiments of the present disclosure, semiconductor device 200 includes inductors LN and LP to improve the balance of the differential outputs. Consequently, the gain difference of semiconductor device 200 is minimal, and the phase difference is close to 180 degrees. Furthermore, the gain of the semiconductor device is increased.

[0079] In some embodiments, the inductor ratio of inductors LS and LG is 2:1. The inductor ratio of inductors LP and LN is 1:1. However, the embodiments of the present disclosure are not limited thereto. In various embodiments, various ratios between the inductors are contemplated to be within the scope of the present disclosure.

[0080] Figure 3A According to some embodiments of the present disclosure Figure 2 The semiconductor device 200 shown in FIG. 3 is a schematic diagram of a semiconductor device 300 corresponding to the semiconductor device 200. Figure 2 and Figure 3A , the semiconductor device 300 is an alternative embodiment of the semiconductor device 300 . Figure 3A Follow and Figure 2 Similar markup conventions. For the sake of brevity, the discussion will focus more on Figure 2 and Figure 3A Compared with the semiconductor device 200 , the semiconductor device 300 further includes transistors MP2 and MN2 .

[0081] like Figure 3A For illustrative purposes, one terminal of transistor MN2 is connected in series to inductor LN at node N11, the other terminal of transistor MN2 is connected in series to transistor MN1 at node N31, and the control terminal of transistor MN2 is configured to receive bias voltage signal VBSCN. One terminal of transistor MP2 is connected in series to inductor LP at node N14, the other terminal of transistor MP2 is connected in series to transistor MP1 at node N32, and the control terminal of transistor MP2 is configured to receive bias voltage signal VBSCP.

[0082] In some embodiments, the voltage level of bias voltage signal VBSCN is greater than the voltage level of bias voltage signal VBSN and less than the voltage level of reference voltage signal VDD. The voltage level of bias voltage signal VBSCP is less than the voltage level of bias voltage signal VBSP and greater than the voltage level of reference voltage signal VSS. In some embodiments, bias voltage signals VBSCN and VBSCP are generated by a bias circuit. Note that the bias circuit is not shown in the figures.

[0083] In some embodiments, transistors MN1 and MN2 have the same conductivity type, and transistors MP1 and MP2 have the same conductivity type. For example, transistors MN1 and MN2 are implemented by N-type MOS transistors, and transistors MP1 and MP2 are implemented by P-type MOS transistors.

[0084] In some embodiments, transistors MN2 and MP2 serve as a cascade (cascaded to the cathode) stage for output signals VON and VOP. Specifically, transistor MN2 isolates transistor MN1 from node N11, and transistor MP2 isolates transistor MP1 from node N14. Consequently, semiconductor device 300 has better isolation and higher output impedance.

[0085] like Figure 3A For illustrative purposes, in some embodiments, the inductor LS includes an inductor LS2 and an inductor LS1. One end of the inductor LS2 is connected in series to the node N12, and the other end of the inductor LS2 is connected in series to the node N22. One end of the inductor LS1 is connected in series to the node N13, and the other end of the inductor LS2 is connected in series to the node N22.

[0086] Figure 3B According to some embodiments of the present disclosure Figure 3A A schematic diagram of a transformer coupling common source (TC-CS) path CSP corresponding to a portion of a semiconductor device 300 is shown.

[0087] like Figure 3B and Figure 3A Illustratively, inductor LS1 is configured to receive reference voltage signal VSS at node N33 and is connected to node N21 via capacitors CP1 and CP2. Inductor LS2 is configured to receive reference voltage signal VSS at node N34. In some embodiments, inductors LS2 and LS1 are coupled to each other via a transformer.

[0088] In some embodiments, with respect to the polarity of inductors LS2 and LS1, nodes N21 and N34 have the same polarity, and nodes N12 and N33 have the same polarity, which is opposite to the polarity of nodes N21 and N34. For example, when node N21 has a positive polarity in response to input signal VIN, node N34 also has a positive polarity, while nodes N12 and N33 have a negative polarity. Conversely, when node N21 has a negative polarity in response to input signal VIN, node N34 also has a negative polarity, while nodes N12 and N33 have a positive polarity.

[0089] During operation, when the input signal VIN is transmitted along the TC-CS path CSP, the input signal VIN generates a current signal flowing through inductor LS2. At this time, the reverse current signal flowing through inductor LS1 is induced by the current signal flowing through inductor LS2, thereby achieving a transconductance enhancement effect.

[0090] Figure 3C According to some embodiments of the present disclosure Figure 3A A portion of the semiconductor device 300 is shown as a schematic diagram of a device corresponding to a transformer coupling common gate (TC-CG) path CGP.

[0091] like Figure 3C Illustratively, inductor LS1 is configured to receive a reference voltage signal VDD at node N33 and an input signal VIN at node N13. Inductor LG is configured to receive a bias voltage signal VBSCP at node N16. In some embodiments, inductors LS2 and LS1 are coupled to each other via a transformer.

[0092] In some embodiments, with respect to the polarity of inductors LG and LS1, nodes N13 and N16 have the same polarity, and nodes N15 and N33 have the same polarity, which is opposite to the polarity of nodes N13 and N16. For example, when node N13 has a positive polarity in response to input signal VIN, node N16 also has a positive polarity, while nodes N15 and N33 have a negative polarity. Conversely, when node N13 has a negative polarity in response to input signal VIN, node N16 also has a negative polarity, while nodes N15 and N33 have a positive polarity.

[0093] During operation, when the input signal VIN is transmitted along the TC-CG path CGP, the input signal VIN generates a current signal flowing through the inductor LS1. At this time, the reverse current signal flowing through the inductor LG is induced by the current signal flowing through the inductor LS1. Therefore, a transconductance enhancement effect is achieved. Figures 3A to 3C In some embodiments, by Figure 3B and Figure 3C The illustrated devices are combined to form a semiconductor device 300 .

[0094] Figure 4 According to some embodiments of the present disclosure Figure 3A The layout diagram of the input transformer 400 corresponding to the inductors LS1, LS2 and LG is shown. Figure 4 Illustratively, input transformer 400 includes inductor sections LS41 - LS49 and LG41 - LG49 .

[0095] In some embodiments, inductor sections LP54, LG42, and LS46 are arranged in the same layer. Inductor sections LS48, LG44, and LS44 are arranged in the same layer, which is located above the layer of inductor sections LS42, LG42, and LS46. Inductor sections LS41, LS43, LS45, LS47, LS49, LG41, LG43, and LS45 are arranged in the same layer, which is located above the layer of inductor sections LS42, LG42, and LS46.

[0096] like Figure 4 For illustrative purposes, inductor section LS44 intersects inductor section LS46. Inductor section LG44 intersects inductor section LG42. Inductor section LS48 intersects inductor section LS42. Inductor section LS45 intersects inductor sections LS48 and LG44. Input transformer 400 has a roughly circular shape. On one side of the circle, inductor sections LS47, LG41, and LS45 are sequentially arranged between inductor sections LS41 and LG43. On the other side of the circle, inductor sections LS43, LG45, and LS45 are sequentially arranged between inductor sections LS49 and LG43.

[0097] In some embodiments, inductor sections LS41 and LS43 are coupled to both ends of inductor section LS42. Inductor sections LS43 and LS45 are connected to both ends of inductor section LS44. Inductor sections LS45 and LS47 are connected to both ends of inductor section LS46. Inductor sections LS47 and LS49 are connected to both ends of inductor section LS48. Inductor sections LG41 and LG43 are connected to both ends of inductor section LG42. Inductor sections LG43 and LG45 are connected to both ends of inductor section LG44.

[0098] See also Figure 4 and Figure 3A In some embodiments, inductors LS1, LS2, and LG are implemented by input transformer 400. Inductor LS1 is implemented by inductor sections LS41-LS44 and a portion of inductor section LS45. Inductor LSS is implemented by inductor sections LS46-LS49 and another portion of inductor section LS45. Inductor LG is implemented by inductor sections LG41-LS45.

[0099] In some embodiments, inductor portion LS41 corresponds to a port of inductor LS and is connected to node N13. Inductor portion LS49 corresponds to a port of inductor LS and is connected to node N12. Inductor portion LS45 corresponds to the center tap port of inductor LS and is connected to node N22. Inductor portion LG41 corresponds to a port of inductor LG and is connected to node N16. Inductor portion LG45 corresponds to a port of inductor LG and is connected to node N15.

[0100] It should be noted that the implementation of inductors LS1, LS2 and LG is not limited to Figure 4 In various embodiments, inductors LS1, LS2, and LG are implemented in various configurations.

[0101] Figure 5 According to some embodiments of the present disclosure Figure 3A The layout diagram of the output transformer 500 corresponding to the inductors LP and LN is shown in FIG. Figure 5 Illustratively, output transformer 500 includes inductor sections LP51 - LP57 and LN51 - LN53 .

[0102] In some embodiments, inductor portions LP54, LP56, and LP52 are disposed in the same layer above inductor portion LN52. Inductor portions LP51, LP53, LP55, LP57, LN51, and LN53 are disposed in the same layer above inductor portions LP54, LP56, and LP52.

[0103] like Figure 5 For illustrative purposes, inductor section LP54 intersects inductor section LN52. Inductor section LN51 intersects inductor section LP52. Inductor section LN53 intersects inductor section LP56. Inductor sections LN53 and LP57 each intersect inductor section LP54. Output transformer 500 has a roughly circular shape. On one side of the circle, inductor sections LN51 and LP55 are sequentially arranged between inductor sections LP51 and LN53. On the other side of the circle, inductor sections LN53 and LP53 are sequentially arranged between inductor section LP57 and LN51.

[0104] In some embodiments, inductor sections LP51 and LP53 are connected to both ends of inductor section LP52. Inductor sections LP53 and LP55 are connected to both ends of inductor section LP54. Inductor sections LP55 and LP57 are connected to both ends of inductor section LP56. Inductor sections LN51 and LN53 are connected to both ends of inductor section LN52.

[0105] See also Figure 5 and Figure 3A In some embodiments, inductors LP and LN are implemented by input transformer 500. Inductor LP is implemented by inductor sections LP51-LP57. Inductor LN is implemented by inductor sections LN51-LN53.

[0106] In some embodiments, inductor portion LP51 corresponds to a port of inductor LP and is connected to node N11. Inductor portion LP57 corresponds to a port of inductor LP and is connected to node N23. Inductor portion LN51 corresponds to a port of inductor LN and is connected to node N24. Inductor portion LN53 corresponds to a port of inductor LN and is connected to node N14.

[0107] It should be noted that the implementation of inductors LP and LN is not limited to Figure 5 In various embodiments, inductors LP and LN are implemented in various configurations.

[0108] Figure 6 According to some embodiments of the present disclosure Figures 1 to 3A The flowchart of the method 600 corresponding to the semiconductor devices 100, 200 and 300 is shown. Figure 6 Illustratively, method 600 includes operations OP61 - OP63 .

[0109] During operation OP61 , each of the control terminal of the transistor MN1 and the first terminal of the transistor MP1 receives the input signal VIN.

[0110] During operation OP62 , a current signal flowing through the inductor LG is sensed in response to an input signal VIN generating a current signal flowing through the inductor LS, wherein the inductor LG is connected to the control terminal of the transistor MP1 .

[0111] During operation OP63 , the output signal VOP is generated at the second terminal of transistor MP1 .

[0112] Figure 7 For designing and / or manufacturing according to some embodiments of the present disclosure Figures 1 to 3AA schematic diagram of a system 700 for at least one of semiconductor devices 100, 200, and 300 is shown. As described herein, system 700 generates or places one or more IC layout designs corresponding to at least one of semiconductor devices 100, 200, and 300. In some embodiments, system 700 manufactures one or more semiconductor devices based on the one or more IC layout designs, as described herein. System 700 includes a hardware processor 702 and a non-transitory computer-readable storage medium 704 encoded with (e.g., storing) computer program code 706 (i.e., a set of executable instructions). Computer-readable storage medium 704 is configured to interface with a fabrication machine for producing semiconductor devices. Processor 702 is electrically coupled to computer-readable storage medium 704 via bus 707. Processor 702 is also electrically coupled to I / O interface 710 via bus 707. Network interface 712 is also electrically connected to processor 702 via bus 707. The network interface 712 is connected to a network 714, enabling the processor 702 and the computer-readable storage medium 704 to connect to external components via the network 714. The processor 702 is configured to execute computer program code 706 encoded in the computer-readable storage medium 704 to enable the system 700 to design and / or manufacture at least one of the semiconductor devices 100, 200, and 300.

[0113] In some embodiments, the processor 702 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0114] In some embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, a removable computer disk, random access memory (RAM), read-only memory (ROM), a rigid disk, and / or an optical disk. In some embodiments using optical disks, the computer-readable storage medium 704 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0115] In some embodiments, the storage medium 704 also stores information required to design and / or manufacture at least one of the semiconductor devices 100 , 200 , and 300 , such as a layout design 716 , a user interface 718 , a fabrication unit 720 , and / or a set of executable instructions for designing and / or manufacturing at least one of the semiconductor devices 100 , 200 , and 300 .

[0116] In some embodiments, storage medium 704 stores instructions (eg, computer program code 706 ) for interfacing with a fabrication machine. The instructions (eg, computer program code 706 ) enable processor 702 to generate fabrication instructions readable by the fabrication machine to effectively implement semiconductor devices 100 , 200 , and 300 .

[0117] System 700 includes an I / O interface 710. I / O interface 710 is coupled to external circuitry. In some embodiments, I / O interface 710 includes a keyboard, keypad, mouse, trackball, touchpad, and / or cursor arrow keys for communicating information and commands to processor 702.

[0118] System 700 also includes a network interface 712 coupled to processor 702. Network interface 712 allows system 700 to communicate with a network 714 to which one or more other computer systems are connected. Network interface 712 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or a wired network interface such as ETHERNET, USB, or IEEE-13154. In some embodiments, the design and / or fabrication of at least one of semiconductor devices 100, 200, and 300 is implemented in two or more systems 700, and information such as layout design 716, user interface 718, and fabrication unit 720 is exchanged between the different systems 700 via network 714.

[0119] System 700 is configured to receive information related to a layout design 716 via I / O interface 710 or network interface 712. This information is transmitted to processor 702 via bus 707 to determine a layout design for generating an IC. The layout design is then stored in computer-readable medium 704 as layout design 716. System 700 is configured to receive information related to a user interface via I / O interface 710 or network interface 712. This information is stored in computer-readable medium 704 as user interface 718. System 700 is configured to receive information related to a manufacturing unit via I / O interface 710 or network interface 712. This information is stored in computer-readable medium 704 as manufacturing unit 720. In some embodiments, manufacturing unit 720 includes manufacturing information utilized by system 700.

[0120] In some embodiments, the design and / or manufacture of at least one of the semiconductor devices 100, 200, and 300 is implemented as a standalone software application executed by a processor. In some embodiments, the design and / or manufacture of at least one of the semiconductor devices 100, 200, and 300 is implemented as a software application that is part of an additional software application. In some embodiments, the design and / or manufacture of at least one of the semiconductor devices 100, 200, and 300 is implemented as a plug-in to a software application. In some embodiments, the design and / or manufacture of at least one of the semiconductor devices 100, 200, and 300 is implemented as a software application that is part of an EDA tool. In some embodiments, the design and / or manufacture of at least one of the semiconductor devices 100, 200, and 300 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design for an integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer-readable medium. In some embodiments, the layout design is stored on a non-transitory computer-readable medium using a computer programmable logic controller (CDMA) provided by Cadence Electronics Co., Ltd. The system 700 may be used to generate a layout design using a fabrication tool or other suitable layout generation tool. In some embodiments, the layout design is generated based on a netlist created from a contemplated design. In some embodiments, fabrication of at least one of the semiconductor devices 100, 200, and 300 is accomplished by fabricating an integrated circuit using a set of masks fabricated based on one or more layout designs generated by the system 700. In some embodiments, the system 700 includes a fabrication tool (e.g., fabrication tool 722) to fabricate an integrated circuit using a set of masks fabricated based on one or more layout designs of the present disclosure.

[0121] Figure 8 FIG. 8 is a block diagram of an integrated circuit (IC) / semiconductor device manufacturing system 800 and an associated IC manufacturing process according to some embodiments of the present disclosure.

[0122] exist Figure 8In the present invention, IC manufacturing system 800 includes entities that interact with each other during the design, development, and manufacturing cycles and / or services related to manufacturing an IC device (semiconductor device) 860, including at least one of semiconductor devices 100, 200, and 300, such as a design office 820, a shielded room 830, and an IC manufacturer / fabricator ("fab") 840. The entities in system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design office 820, shielded room 830, and IC fab 840 are owned by a single company. In some embodiments, two or more of design office 820, shielded room 830, and IC fab 840 coexist in a common facility and use common resources.

[0123] The design office (or design team) 820 generates an IC design layout 822. The IC design layout 822 includes various geometric patterns designed for the IC device 860. The geometric patterns correspond to the patterns of the metal, oxide, or semiconductor layers that make up the various components of the IC device 860 to be manufactured. The various layers combine to form various IC features. For example, a portion of the IC design layout 822 includes various IC features, such as active regions, gate structures, source / drain structures, interlayer interconnect structures, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 820 implements an appropriate design program to form the IC design layout 822. The design program includes one or more of a logical design, a physical design, or placement and routing. The IC design layout 822 is presented in one or more data files having geometric pattern information. For example, the IC design layout 822 can be expressed in a GDSII file format or a DFII file format.

[0124] The shield chamber 830 includes shield data preparation 832 and shield fabrication 834. The shield chamber 830 uses the IC design layout 822 to fabricate one or more shields for fabricating various layers of the IC device 860 based on the IC design layout 822. The shield chamber 830 performs shield data preparation 832, wherein the IC design layout 822 is converted into a representative data file ("representative datafile, RDF"). The shield data preparation 832 provides the RDF to the shield fabrication 834. The shield fabrication 834 includes a shield writer. The shield writer converts the RDF into an image on a substrate, such as a shield (photoshield) or a semiconductor wafer, or a metal layer that is formed and then selectively etched to form a redistribution layer in the back-end process of the wafer fab. The design layout is manipulated by the shield data preparation 832 to conform to the specific characteristics of the shield writer and / or the requirements of the IC wafer fab 840. In Figure 8 , shield data preparation 832 and shield manufacturing 834 are illustrated as separate components. In some embodiments, shield data preparation 832 and shield manufacturing 834 may be collectively referred to as shield data preparation.

[0125] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for imaging errors, such as those that may be caused by diffraction, interference, or other processing effects. OPC adjusts IC design layout 822. In some embodiments, mask data preparation 832 includes other resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution assist features, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0126] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks the IC design layout, which has been processed in OPC, using a set of mask establishment rules. The mask establishment rules contain certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for the constraints during mask fabrication 834, which may cancel a portion of the modifications performed by OPC to satisfy the mask establishment rules.

[0127] In some embodiments, mask data preparation 832 includes lithography process checking (LPC), which simulates the process to be performed by the IC fab 840 to manufacture the IC device 860. LPC simulates the process based on the IC design layout 822 to create a simulated manufacturing device, such as the IC device 860. The process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc. or a combination thereof. In some embodiments, after the simulated manufacturing device is created by LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 822.

[0128] It should be understood that the above description of mask data preparation 832 has been simplified for clarity. In some embodiments, mask data preparation 832 includes additional features, such as logic operations (LOPs), to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to IC design layout 822 during mask data preparation 832 can be performed in a variety of different orders.

[0129] After mask data preparation 832 and during mask fabrication 834, a mask or set of masks is fabricated based on the modified IC design layout. In some embodiments, an electron beam or multiple electron beams are used to form a pattern on a mask (photomask or light shield) based on the modified IC design layout. The mask can be formed using various techniques. In some embodiments, the mask is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (such as an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, the binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque areas of the mask. In another example, the mask is formed using a phase shift technique. In a phase shift mask (PSM), various features in the pattern formed on the mask are designed to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask fabrication 834 is used in various processes. For example, the mask may be used in an ion implantation process to form various doped regions in a semiconductor wafer, may be used in an etching process to form various etched regions in a semiconductor wafer, and / or may be used in other suitable processes.

[0130] IC fab 840 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 840 is a semiconductor foundry. For example, a first manufacturing facility may be used for front-end manufacturing of multiple IC products (e.g., source / drain structures, gate structures), a second manufacturing facility may provide mid-end manufacturing of interconnects for IC products (e.g., MD, VD, VG), a third manufacturing facility may provide back-end manufacturing for interconnects and packaging of IC products (e.g., M0 tracks, M1 tracks, BM0 tracks, BM1 tracks), and a fourth manufacturing facility may provide other services to the foundry entity.

[0131] IC fab 840 uses one or more shields fabricated by shield chamber 830 to fabricate IC devices 860. Thus, IC fab 840 at least indirectly uses IC design layout 822 to fabricate IC devices 860. In some embodiments, semiconductor wafers are fabricated by IC fab 840 using one or more shields to form IC devices 860. Semiconductor wafer 842 includes a silicon substrate or other suitable substrate on which material layers are formed. The semiconductor wafer also includes one or more various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent fabrication steps).

[0132] A semiconductor device is also disclosed. The semiconductor device includes a first transistor, a second transistor, a first inductor, and a second inductor. The control terminal of the first transistor is configured to receive an input signal. The second transistor is connected in series with the first transistor, and the first terminal of the second transistor is configured to receive an input signal at a first node. The first inductor is connected between the first transistor and the first node. The second inductor is connected to the control terminal of the second transistor. The first and second inductors are coupled to each other via a transformer.

[0133] In some embodiments, the semiconductor device further includes a third inductor and a fourth inductor connected in series with the first transistor and the second transistor, wherein the first transistor and the second transistor are connected between the third inductor and the fourth inductor.

[0134] In some embodiments, the third inductor and the fourth inductor are coupled to each other via a transformer.

[0135] In some embodiments, the semiconductor device further includes a third inductor configured to receive a reference voltage signal, a second inductor configured to receive a first bias voltage signal, and a second transistor connected in series between the first inductor and the third inductor.

[0136] In some embodiments, the semiconductor device further includes a third transistor connected in series between the third inductor and the second transistor, and a control terminal of the third transistor is configured to receive a second bias voltage signal.

[0137] In some embodiments, the first inductor includes a third inductor and a fourth inductor. The third inductor is connected to the first transistor and is used to receive a reference voltage signal at the second node. The fourth inductor is connected to the second transistor and is used to receive the reference voltage signal at the second node.

[0138] In some embodiments, the semiconductor device further includes a third inductor and a third transistor. The third inductor is configured to receive a reference voltage signal. The third transistor is coupled in series between the third inductor and the first transistor. A control terminal of the third transistor is configured to receive a first bias voltage signal.

[0139] A method for operating a semiconductor device is also disclosed. The method includes the following steps: receiving an input signal at each of a control terminal of a first transistor and a first terminal of a second transistor; in response to the input signal, sensing a current signal flowing through a first inductor connected to the control terminal of the second transistor; and generating a first output signal at a second terminal of the second transistor.

[0140] In some embodiments, the induced current signal includes a induced current signal by a second inductor connected between the first transistor and the second transistor.

[0141] In some embodiments, the operating method further includes receiving a bias voltage signal and a reference voltage signal from the first inductor and the second inductor, respectively.

[0142] In some embodiments, the operating method further includes receiving a first bias voltage signal and a first reference voltage signal from a control terminal of the third transistor and a second inductor, respectively. The second transistor, the second inductor, and the third transistor are connected in series.

[0143] In some embodiments, the operating method further includes receiving a second bias voltage signal and a second reference voltage signal through a control terminal of the fourth transistor and the third inductor. The first transistor, the third inductor, and the fourth transistor are connected in series, and the second reference voltage signal is different from the first reference voltage signal.

[0144] In some embodiments, the second inductor and the third inductor are coupled to each other via a transformer.

[0145] A semiconductor device is also disclosed. The semiconductor device includes a first transistor, a second transistor, a first inductor, and a second inductor. A first terminal of the first inductor is coupled to a first terminal of the first transistor. A first terminal of the second transistor is coupled to a second terminal of the first inductor. The second inductor is connected to a control terminal of the second transistor. The first and second inductors are coupled to each other via a transformer.

[0146] In some embodiments, the first inductor includes a third inductor and a fourth inductor. The third inductor is connected to the first transistor and is used to receive the first reference voltage signal at the first node. The fourth inductor is connected in series to the second transistor and is used to receive the first reference voltage signal at the first node.

[0147] In some embodiments, the second inductor is configured to receive a first bias voltage signal.

[0148] In some embodiments, the semiconductor device further includes a fifth inductor connected in series with the second transistor and configured to receive the first reference voltage signal.

[0149] In some embodiments, the semiconductor device further includes a sixth inductor. The sixth inductor is connected in series with the first transistor and coupled to the fifth inductor via transformer coupling. The first transistor and the second transistor are coupled between the fifth inductor and the sixth inductor.

[0150] In some embodiments, the semiconductor device further includes a third transistor connected between the sixth inductor and the first transistor. A control terminal of the third transistor is configured to receive a first bias voltage signal, and the sixth inductor is configured to receive a second reference voltage signal different from the first reference voltage signal.

[0151] In some embodiments, the semiconductor device further includes a fourth transistor connected between the fifth inductor and the second transistor, and a control terminal of the fourth transistor for receiving a second bias voltage signal.

[0152] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made to these equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a first transistor, wherein a control terminal of the first transistor is used to receive an input signal; a second transistor connected in series with the first transistor, wherein a first terminal of the second transistor is configured to receive the input signal at a first node; a first inductor connected in series between the first transistor and the first node; and a second inductor connected to a control terminal of the second transistor, The first inductor and the second inductor are coupled to each other through a transformer.

2. The semiconductor device according to claim 1, wherein Also includes: a third inductor and a fourth inductor connected in series with the first transistor and the second transistor, The first transistor and the second transistor are connected in series between the third inductor and the fourth inductor.

3. The semiconductor device according to claim 2, wherein The third inductor and the fourth inductor are coupled to each other through a transformer.

4. The semiconductor device according to claim 1, wherein Also includes: a third inductor, for receiving a reference voltage signal, The second inductor is used to receive a first bias voltage signal, and The second transistor is connected in series between the first inductor and the third inductor.

5. The semiconductor device according to claim 4, wherein Also includes: A third transistor is connected in series between the third inductor and the second transistor. A control terminal of the third transistor is used for receiving a second bias voltage signal.

6. The semiconductor device according to claim 4, wherein The first inductor comprises: a fourth inductor connected to the first transistor and configured to receive the reference voltage signal at a second node; and A fifth inductor is connected to the second transistor and is used for receiving the reference voltage signal at the second node.

7. The semiconductor device according to claim 1, wherein Also includes: a third inductor, configured to receive a reference voltage signal; and A third transistor is connected in series between the third inductor and the first transistor. A control terminal of the third transistor is used for receiving a first bias voltage signal.

8. A method for operating a semiconductor device, characterized in that: Include: receiving an input signal from each of a control terminal of a first transistor and a first terminal of a second transistor; In response to the input signal, sensing a current signal flowing through a first inductor, the first inductor being connected to a control terminal of the second transistor; and A first output signal is generated at a second terminal of the second transistor.

9. The operating method according to claim 8, characterized in that: The induced current signal includes: The current signal is induced by a second inductor connected in series between the first transistor and the second transistor.

10. A semiconductor device, characterized in that: Include: a first transistor; a first inductor, wherein a first terminal of the first inductor is connected in series to a first terminal of the first transistor; a second transistor, a first terminal of the second transistor being connected in series to a second terminal of the first inductor; and a second inductor connected in series to a control terminal of the second transistor, The first inductor and the second inductor are coupled to each other through a transformer.

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