Frequency source synthesis system
By combining the control module, phase-locked loop and direct digital frequency synthesis module, combined with a low-voltage difference linear regulated power supply, the problem that the direct phase-locked loop is difficult to meet the low phase noise requirement is solved, low-cost low-phase noise frequency synthesis is achieved, and the reliability and flexibility of the frequency source synthesis system are improved.
Patent Information
- Application Number
- CN202510753425.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-06
- Publication Date
- 2025-09-16
AI Technical Summary
In the existing technology, the direct phase-locked loop cannot meet the low phase noise requirements of the launch vehicle measurement and control system, resulting in high cost and insufficient performance of the frequency source synthesis system.
A control module, a first phase-locked loop module, a direct digital frequency synthesis module and a second phase-locked loop module are combined, a phase-locked loop is used for frequency multiplication and division, a low-voltage difference linear regulated power supply is used for independent power supply, and chips with different phase noise performance are selected to reduce costs.
The target frequency synthesis with low phase noise is achieved, the system cost is reduced, and the reliability and flexibility of the frequency source synthesis system are improved.
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Figure CN120658257A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of frequency source synthesis, and in particular relates to a frequency source synthesis system. Background Art
[0002] Currently, launch vehicles primarily utilize telemetry tracking from ground-based tracking stations combined with space-based tracking and control. With the continuous advancement of tracking and control communication technology, the frequency bands and bandwidths of tracking and control are becoming increasingly higher, leading to increasingly stringent requirements for the frequency sources used by tracking and control systems.
[0003] In related technologies, a direct phase-locked loop is usually used for frequency synthesis, but this technology is difficult to meet the demand for low phase noise in current practical applications. Summary of the Invention
[0004] The embodiments of the present application provide a frequency source synthesis system, thereby being able to obtain a target frequency with low phase noise at least to a certain extent.
[0005] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by practice of the present application.
[0006] According to a first aspect of an embodiment of the present application, a frequency source synthesis system is provided, comprising: a control module, a first phase-locked loop (PLL) module, a direct digital frequency synthesis (DDS) module, and a second phase-locked loop (PLL) module, wherein the control module is connected to a controlled end of the first phase-locked loop (PLL) module, a controlled end of the DDS module, and a controlled end of the second phase-locked loop (PLL) module, respectively. The control module is configured to determine, based on a target frequency and a preliminary frequency output by a reference frequency source, a first frequency multiplication number output to the first phase-locked loop (PLL) module, a frequency division number output to the DDS module, and a second frequency multiplication number output to the second phase-locked loop (PLL) module. The first phase-locked loop (PLL) module has an input end configured to be connected to the reference frequency source, and an output end configured to be connected to the DDS module. The first phase-locked loop (PLL) module is configured to multiply the initial frequency by the first frequency multiplication number using a phase-locked loop (PLL) to obtain a first frequency. The output end of the DDS module is connected to the input end of the second phase-locked loop (PLL) module. The DDS module is configured to divide the first frequency by the frequency division number using a DDS to obtain a second frequency. The second phase-locked loop (PLL) module is configured to multiply the second frequency by the second frequency multiplication number using a phase-locked loop (PLL) to obtain a target frequency.
[0007] In some embodiments, the first phase-locked loop module includes: a first phase-locked loop and a first filter, wherein the input end of the first phase-locked loop is the input end of the first phase-locked loop module, and the output end is connected to the input end of the first filter; the output end of the first filter is the output end of the first phase-locked loop module.
[0008] In some embodiments, the direct digital frequency synthesis module includes: a direct digital frequency synthesizer and a second filter, wherein the input end of the direct digital frequency synthesizer is the input end of the direct digital frequency synthesis module, and the output end is connected to the input end of the second filter; the output end of the second filter is the output end of the direct digital frequency synthesis module.
[0009] In some embodiments, the second filter is a bandpass filter, and a frequency range of the bandpass filter is determined according to the target frequency.
[0010] In some embodiments, the second phase-locked loop module includes: a second phase-locked loop and a third filter, wherein the input end of the second phase-locked loop is the input end of the second phase-locked loop module, and the output end is connected to the input end of the third filter; the output end of the third filter is the output end of the second phase-locked loop module.
[0011] In some embodiments, the second phase-locked loop uses a chip with a phase noise higher than the phase noise of the first phase-locked loop.
[0012] In some embodiments, the second phase-locked loop module further includes: a frequency multiplier, and the output end of the second phase-locked loop is connected to the input end of the third filter via the frequency multiplier.
[0013] In some embodiments, the frequency source synthesis system further includes a low voltage difference linear regulated power supply, which is respectively connected to the power supply end of the first phase-locked loop module, the power supply end of the direct digital frequency synthesis module, and the power supply end of the second phase-locked loop module.
[0014] In some embodiments, the low-voltage difference linear regulated power supply includes a low-voltage difference linear regulator, a first filter capacitor and a second filter capacitor, wherein the input end of the low-voltage difference linear regulator is connected to the first filter capacitor, and the output end is connected to the power supply end of the first phase-locked loop module, the power supply end of the direct digital frequency synthesis module and the power supply end of the second phase-locked loop module through the second filter capacitor.
[0015] In some embodiments, the maximum output current of the low dropout linear regulator is greater than 1.25 times the total maximum current of the first phase-locked loop module, the direct digital frequency synthesis module, and the second phase-locked loop module.
[0016] In the present application, a control module, a first phase-locked loop module, a direct digital frequency synthesis module and a second phase-locked loop module are designed, wherein the control module is connected to the controlled end of the first phase-locked loop module, the controlled end of the direct digital frequency synthesis module and the controlled end of the second phase-locked loop module respectively, and the control module is used to determine the first frequency multiplication number output to the first phase-locked loop module, the frequency division number output to the direct digital frequency synthesis module and the second frequency multiplication number output to the second phase-locked loop module according to the target frequency and the preliminary frequency output by the reference frequency source; the input end of the first phase-locked loop module is used to be connected to the reference frequency source, and the output end is connected to the direct digital frequency synthesis module; the first phase-locked loop module is used to use the phase-locked loop to multiply the initial frequency by the first frequency multiplication number to obtain the first frequency; the output end of the direct digital frequency synthesis module is connected to the input end of the second phase-locked loop module, and the direct digital frequency synthesis module is used to use a direct digital frequency synthesizer to divide the first frequency by the frequency division number to obtain the second frequency; the second phase-locked loop module is used to use the phase-locked loop to multiply the second frequency by the second frequency multiplication number to obtain the target frequency. By performing frequency synthesis using the first phase-locked loop module, the direct digital frequency synthesis module and the second phase-locked loop module, a target frequency with low phase noise can be obtained.
[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, explaining the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:
[0019] Figure 1 A schematic diagram of functional modules of a frequency source synthesis system according to some embodiments of the present application is shown;
[0020] Figure 2 A schematic structural diagram of a frequency source synthesis system according to some embodiments of the present application is shown;
[0021] Figure 3 A structural schematic diagram of a frequency source synthesis system according to some other embodiments of the present application is shown.
[0022] Description of the accompanying drawings: 10-control module, 20-first phase-locked loop module, 30-direct digital frequency synthesis module, 40-second phase-locked loop module, 50-reference frequency source, 60-low voltage difference linear regulated power supply, PLL1-first phase-locked loop, 201-first filter, 301-second filter, PLL2-second phase-locked loop, 401-third filter, 402-frequency multiplier. DETAILED DESCRIPTION
[0023] The following describes the specific implementation of the embodiment of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiment of the present invention and is not used to limit the embodiment of the present invention.
[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0025] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.
[0026] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0027] In order to enable those skilled in the art to better understand the present application, the technical background involved in the present application is first briefly described.
[0028] In related technologies, a phase-locked loop (PLL) is typically used to multiply the frequency output by a reference frequency source to a target frequency. This approach places extremely high demands on the phase noise performance of the reference frequency source, resulting in a very high cost for the entire frequency source synthesis system. However, the present application utilizes a first PLL module, a direct digital frequency synthesis module, and a second PLL module for frequency synthesis. This allows the use of a reference frequency source with standard phase noise performance to generate a low-phase-noise target frequency, achieving low-phase-noise and high-reliability frequency synthesis at a low cost.
[0029] Figure 1 FIG. 1 shows a functional module diagram of a frequency source synthesis system according to some embodiments of the present application. Figure 1 As shown, the frequency source synthesis system may include: a control module 10, a first phase-locked loop module 20, a direct digital frequency synthesis module 30, and a second phase-locked loop module 40, wherein the control module 10 is connected to the controlled end of the first phase-locked loop module 20, the controlled end of the direct digital frequency synthesis module 30, and the controlled end of the second phase-locked loop module 40, respectively. The control module 10 is used to determine the first multiplication number output to the first phase-locked loop module 20, the frequency division number output to the direct digital frequency synthesis module 30, and the second multiplication number output to the second phase-locked loop module 40 according to the target frequency and the preliminary frequency output by the reference frequency source 50. ; The input end of the first phase-locked loop module 20 is used to be connected to the reference frequency source 50, and the output end is connected to the direct digital frequency synthesis module 30. The first phase-locked loop module 20 is used to use the phase-locked loop to multiply the initial frequency by a first multiplication number to obtain a first frequency; the output end of the direct digital frequency synthesis module 30 is connected to the input end of the second phase-locked loop module 40. The direct digital frequency synthesis module 30 is used to use a direct digital frequency synthesizer to divide the first frequency by a division number to obtain a second frequency; the second phase-locked loop module 40 is used to use the phase-locked loop to multiply the second frequency by a second multiplication number to obtain a target frequency.
[0030] Among them, the reference frequency source 50 can use an oven-controlled crystal oscillator (OCXO) with low phase noise. The phase noise performance of the oven-controlled crystal oscillator can reach ≤-150dBc / Hz@100Hz, ≤-155dBc / Hz@1kHz, ≤-163dBc / Hz@10kHz, and ≤-165dBc / Hz@100kHz. The crystal oscillator with better phase noise performance determines the peak of the phase noise performance of the initial frequency ultimately output by the reference frequency source 50. During the implementation process, the frequency source synthesis system may also include a reference frequency source 50. Selecting an oven-controlled crystal oscillator as the reference frequency source 50 is beneficial to improving the performance of the entire frequency source synthesis system.
[0031] It is understandable that the first PLL module 20 and the second PLL module 40 both include phase-locked loops, the direct digital frequency synthesis module 30 includes a direct digital synthesizer (DDS), and the control module 10 may be a microcontroller unit (MCU).
[0032] The main function of the phase-locked loop in the first phase-locked loop module 20 is to provide a first frequency with a higher frequency to the direct digital frequency synthesis module 30 through frequency multiplication, so as to reduce in-band spurious signals of the second frequency output by the direct digital frequency synthesis module 30 .
[0033] To meet the design requirements for frequency conversion, a direct digital frequency synthesis module 30 is used as the frequency conversion center of the entire frequency source synthesis system, dividing the first frequency to obtain a controllable second frequency. The frequency division process reduces phase noise and has minimal impact on the phase noise of the entire frequency source synthesis system.
[0034] The second frequency is used as the excitation of the second phase-locked loop module 40, and the second phase-locked loop module 40 can multiply the second frequency to obtain the target frequency. The second phase-locked loop module 40 can use the phase-locked loop to multiply the second frequency by the second multiplication factor to directly obtain the target frequency, or can use the phase-locked loop to multiply the second frequency by the second multiplication factor and then multiply the second frequency to obtain the target frequency.
[0035] In some embodiments, when control module 10 is an MCU, the MCU writes the first multiplication factor into the register of the phase-locked loop (PLL) in first PLL module 20, writes the frequency division factor into the register of the direct digital frequency synthesizer (DDS) in DDS module 30, and writes the second multiplication factor into the register of the PLL in second PLL module 40. The PLL and DDS can then operate according to the configured parameters. Taking the microwave broadband synthesizer chip ADF4372 as an example, when the frequency division factor is 50, the MCU can write the data in register address 0x25 to 0x32, where register address 0x25 is used to configure the frequency division factor.
[0036] For example, if the target frequency is 12.5 GHz and the initial frequency is 250 MHz, various combinations of the first multiplication factor, the division factor, and the second multiplication factor are possible, as long as the initial frequency of 250 MHz can reach the target frequency of 12.5 GHz after multiplication, division, and multiplication. To minimize phase noise degradation, the first multiplication factor should be as small as possible. Therefore, the MCU can select the parameter with the smallest first multiplication factor from the various combinations and write it into the register.
[0037] In the embodiment of the present application, the control module 10 inputs a first multiplication factor to the first phase-locked loop module 20, a frequency division factor to the direct digital frequency synthesis module 30, and a second multiplication factor to the second phase-locked loop module 40 based on the target frequency and the initial frequency output by the reference frequency source 50. The first phase-locked loop module 20 uses a phase-locked loop to multiply the initial frequency by the first multiplication factor to obtain a first frequency. The direct digital frequency synthesis module 30 uses a direct digital frequency synthesizer to divide the first frequency by the frequency division factor to obtain a second frequency. The second phase-locked loop module 40 uses a phase-locked loop to multiply the second frequency by the second multiplication factor to obtain the target frequency. By performing frequency synthesis using the first phase-locked loop module 20, the direct digital frequency synthesis module 30, and the second phase-locked loop module 40, a target frequency with low phase noise can be obtained.
[0038] Figure 2 FIG. 1 shows a schematic diagram of a frequency source synthesis system according to some embodiments of the present application. Figure 2 As shown, in some embodiments, the first phase-locked loop module 20 includes: a first phase-locked loop PLL1 and a first filter 201, wherein the input end of the first phase-locked loop PLL1 is the input end of the first phase-locked loop module 20, and the output end is connected to the input end of the first filter 201; the output end of the first filter 201 is the output end of the first phase-locked loop module 20.
[0039] The first phase-locked loop (PLL1) can use an ultra-low phase noise chip to minimize phase noise degradation. Taking the HMC829 ultra-low phase noise chip as an example, the normalized in-band phase noise is -227dBc / Hz, and the flicker noise at a 10kHz frequency offset is -226dBc / Hz. The calculated phase noise of the HMC829 is -113.17dBc / Hz at 10kHz.
[0040] The first filter 201 can be a bandpass filter. Since the in-band spurious signals cannot be filtered out by the filter, they will deteriorate in the form of 20LgN after being multiplied by the first phase-locked loop PLL1, thereby introducing more spurious signals. In order to avoid affecting the purity of the target frequency, a frequency in a frequency band with high purity can be selected as the input frequency of the direct digital frequency synthesis module 30.
[0041] In some embodiments, the direct digital frequency synthesis module 30 includes: a direct digital frequency synthesizer and a second filter 301, wherein the input end of the direct digital frequency synthesizer is the input end of the direct digital frequency synthesis module 30, and the output end is connected to the input end of the second filter 301; the output end of the second filter 301 is the output end of the direct digital frequency synthesis module 30.
[0042] It should be noted that although the frequency division of the direct digital frequency synthesizer will reduce the phase noise and cause less deterioration of the phase noise of the entire frequency source, the frequency division will introduce new spurious signals. Therefore, it is necessary to select a filter with a suitable frequency range to filter out the spurious signals to ensure that the second frequency provided by the direct digital frequency synthesis module 30 to the second phase-locked loop module 40 is a frequency with less phase noise deterioration and higher purity.
[0043] In some embodiments, the second filter 301 is a bandpass filter, and the frequency range of the bandpass filter is determined according to the target frequency.
[0044] Taking the frequency range of the target frequency as 12.5-13.5 GHz as an example, when the second frequency needs to be amplified 50 times to obtain the target frequency, the frequency range of the second filter 301 may be 250-270 MHz.
[0045] In some embodiments, the second phase-locked loop module 40 includes: a second phase-locked loop PLL2 and a third filter 401, wherein the input end of the second phase-locked loop PLL2 is the input end of the second phase-locked loop module 40, and the output end is connected to the input end of the third filter 401; the output end of the third filter 401 is the output end of the second phase-locked loop module 40.
[0046] It should be noted that the second phase-locked loop PLL2 has the greatest impact on the phase noise and spurious signals of the entire frequency source. In order to achieve the target frequency, the second multiplication number of the second phase-locked loop PLL2 is higher than the first multiplication number of the first phase-locked loop PLL1. Therefore, the phase noise deteriorates more seriously. It is necessary to select a chip with superior performance as the chip of the second phase-locked loop PLL2 to reduce the deterioration of the phase noise.
[0047] In some embodiments, the second phase-locked loop PLL2 uses a chip having a phase noise higher than the phase noise of the first phase-locked loop PLL1 .
[0048] It should be noted that the first phase-locked loop PLL1 uses an ultra-low phase noise chip, which is very expensive. Considering that the second multiplication number of the second phase-locked loop PLL2 is higher than the first multiplication number of the first phase-locked loop PLL1, its phase noise is higher than the phase noise of the first phase-locked loop PLL1. Therefore, the second phase-locked loop PLL2 uses a chip with a phase noise higher than the phase noise of the first phase-locked loop PLL1, which can save costs.
[0049] During the implementation process, the power of the output signal of the second phase-locked loop PLL2 is generally around 0 dBm. The power will be increased later based on the actual usage scenario to amplify the frequency.
[0050] Figure 3FIG1 shows a schematic diagram of the structure of a frequency source synthesis system according to some other embodiments of the present application. Figure 2 and Figure 3 In some embodiments, the second phase-locked loop module 40 further includes: a frequency multiplier 402 , and the output end of the second phase-locked loop PLL2 is connected to the input end of the third filter 401 via the frequency multiplier 402 .
[0051] It should be noted that if the second phase-locked loop PLL2 can directly obtain the target frequency through frequency multiplication, then the second phase-locked loop module 40 does not need the frequency multiplier 402. If the frequency obtained by the second phase-locked loop PLL2 through frequency multiplication is still lower than the target frequency, the frequency multiplier 402 can be added.
[0052] For example, if the target frequency is 12.5 GHz and the initial frequency is 250 MHz, then if the second frequency can reach the target frequency of 12.5 GHz after multiplication by the second multiplication factor, then the frequency multiplier 402 is not required. If the second frequency is 6.25 GHz after multiplication by the second multiplication factor, then a double frequency multiplier 402 can be added to multiply the 6.25 GHz frequency to the target frequency of 12.5 GHz. The frequency range of the frequency multiplier 402 is determined by the target frequency. For example, the frequency multiplier 402 with double frequency multiplication can be selected based on half of the target frequency.
[0053] In some embodiments, the frequency source synthesis system further includes a low voltage difference linear regulated power supply 60 connected to the power supply end of the first phase-locked loop module 20, the power supply end of the direct digital frequency synthesis module 30 and the power supply end of the second phase-locked loop module 40 respectively.
[0054] As you can understand, the power supply is a crucial component of the frequency source. First, it determines the proper functioning of the first phase-locked loop module 20, the direct digital frequency synthesis module 30, and the second phase-locked loop module 40. Second, it is crucial to ensure that power supply noise does not interfere with other circuits in the frequency source. Therefore, the power supply must provide voltage stabilization and filtering.
[0055] It should be noted that phase-locked loops and direct digital frequency synthesizers are hybrid digital-analog devices, requiring high circuit purity. Circuit noise can easily interfere with these devices, impacting performance. Therefore, independent power supplies are required. During implementation, a low-dropout linear regulated power supply 60 can be used to power the first phase-locked loop module 20, the direct digital frequency synthesizer module 30, and the second phase-locked loop module 40, respectively.
[0056] In some embodiments, the low-voltage difference linear regulated power supply 60 includes a low-voltage difference linear regulator, a first filter capacitor (not shown) and a second filter capacitor (not shown), wherein the input end of the low-voltage difference linear regulator is connected to the first filter capacitor, and the output end is connected to the power supply end of the first phase-locked loop module 20, the power supply end of the direct digital frequency synthesis module 30 and the power supply end of the second phase-locked loop module 40 respectively through the second filter capacitor.
[0057] The input and output of the low-voltage-dropout linear regulated power supply 60 can be filtered by adding multiple first and second filter capacitors, respectively. The second filter capacitors are located closer to the low-voltage-dropout linear regulated power supply 60 than to the first phase-locked loop module 20, the direct digital frequency synthesizer module 30, and the second phase-locked loop module 40. Generally, the filter capacitors are arranged in three levels: uF, nF, and pF. Because the low-voltage-dropout linear regulated power supply 60 has relatively low noise, the addition of the second filter capacitors can minimize power supply ripple, significantly reducing interference with the phase-locked loop and direct digital frequency synthesizer.
[0058] In some embodiments, the maximum output current of the low dropout linear regulator is greater than 1.25 times the total maximum current of the first phase-locked loop module 20 , the direct digital frequency synthesis module 30 , and the second phase-locked loop module 40 .
[0059] It should be noted that when selecting a low-dropout linear regulator, sufficient current margin is required to prevent complete saturation, and current utilization efficiency generally cannot reach 100%. If the maximum output current of the low-dropout linear regulator is greater than 1.25 times the total maximum current of the first phase-locked loop module 20, the direct digital frequency synthesis module 30, and the second phase-locked loop module 40, the low-dropout linear regulator should have at least 25% margin to ensure sufficient power supply to the first phase-locked loop module 20, the direct digital frequency synthesis module 30, and the second phase-locked loop module 40.
[0060] Through the above scheme, the target frequency output by the frequency source can range up to the Ku band, and the output target frequency has low phase noise. At the same time, the target frequency can be switched, which has high flexibility and can meet the use of various engineering applications.
[0061] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of the claims of the present application.
Claims
1. A frequency source synthesis system, characterized in that: include: control module, a first phase-locked loop module, a direct digital frequency synthesis module and a second phase-locked loop module, wherein: The control module is connected to the controlled end of the first phase-locked loop module, the controlled end of the direct digital frequency synthesis module, and the controlled end of the second phase-locked loop module respectively, and the control module is used to determine a first frequency multiplication number output to the first phase-locked loop module, a frequency division number output to the direct digital frequency synthesis module, and a second frequency multiplication number output to the second phase-locked loop module according to a target frequency and a preliminary frequency output by a reference frequency source; The input end of the first phase-locked loop module is used to be connected to the reference frequency source, and the output end is connected to the direct digital frequency synthesis module. The first phase-locked loop module is used to use a phase-locked loop to multiply the initial frequency by the first multiplication factor to obtain a first frequency; The output end of the direct digital frequency synthesis module is connected to the input end of the second phase-locked loop module, and the direct digital frequency synthesis module is used to divide the first frequency by the frequency division number using a direct digital frequency synthesizer to obtain a second frequency; The second phase-locked loop module is configured to utilize a phase-locked loop to multiply the second frequency by the second multiplication factor to obtain the target frequency.
2. The frequency source synthesis system according to claim 1, characterized in that: The first phase-locked loop module includes: a first phase-locked loop and a first filter, wherein: The input end of the first phase-locked loop is the input end of the first phase-locked loop module, and the output end is connected to the input end of the first filter; The output end of the first filter is the output end of the first phase-locked loop module.
3. The frequency source synthesis system according to claim 2, characterized in that: The direct digital frequency synthesis module includes: a direct digital frequency synthesizer and a second filter, wherein: The input end of the direct digital frequency synthesizer is the input end of the direct digital frequency synthesis module, and the output end is connected to the input end of the second filter; The output end of the second filter is the output end of the direct digital frequency synthesis module.
4. The frequency source synthesis system according to claim 3, characterized in that: The second filter is a bandpass filter, and a frequency range of the bandpass filter is determined according to the target frequency.
5. The frequency source synthesis system according to claim 3, characterized in that: The second phase-locked loop module includes: a second phase-locked loop and a third filter, wherein: The input end of the second phase-locked loop is the input end of the second phase-locked loop module, and the output end is connected to the input end of the third filter; The output end of the third filter is the output end of the second phase-locked loop module.
6. The frequency source synthesis system according to claim 5, characterized in that: The second phase-locked loop uses a chip with a phase noise higher than that of the first phase-locked loop.
7. The frequency source synthesis system according to claim 5, characterized in that: The second phase-locked loop module further includes a frequency multiplier, and the output end of the second phase-locked loop is connected to the input end of the third filter via the frequency multiplier.
8. The frequency source synthesis system according to claim 7, characterized in that: It also includes a low voltage difference linear regulated power supply, which is respectively connected to the power supply end of the first phase-locked loop module, the power supply end of the direct digital frequency synthesis module and the power supply end of the second phase-locked loop module.
9. The frequency source synthesis system according to claim 8, characterized in that: The low voltage difference linear regulated power supply includes a low voltage difference linear regulator, a first filter capacitor and a second filter capacitor, wherein: The input end of the low voltage difference linear regulator is connected to the first filter capacitor, and the output end is connected to the power supply end of the first phase-locked loop module, the power supply end of the direct digital frequency synthesis module and the power supply end of the second phase-locked loop module through the second filter capacitor.
10. The frequency source synthesis system according to claim 9, characterized in that: The maximum output current of the low-dropout linear regulator is greater than 1.25 times the total maximum current of the first phase-locked loop module, the direct digital frequency synthesis module, and the second phase-locked loop module.