An anti-radiation low-jitter injection-locked phase-locked loop based on threshold filtering technology

Abstract

The present application relates to the technical fields of digital-analog hybrid integrated circuit design, and specifically provides an anti-radiation low-jitter injection-locked phase-locked loop based on threshold filtering technology, comprising a pulse calibration circuit, a pulse injection unit and an injection-locked phase-locked loop; the pulse injection unit generates an injection signal and a threshold signal according to a pulse calibration signal output by the pulse calibration circuit and a feedback signal output by the injection-locked phase-locked loop, so as to judge whether the injection signal is output to the injection-locked phase-locked loop according to the threshold signal. The present application is reinforced based on the structure and architecture of the injection-locked phase-locked loop, and proposes the pulse injection unit, which generates the injection signal and the threshold signal at the same time, controls the conduction state of the injection path of the injection signal according to the threshold signal, greatly reduces the probability of error injection, filters most of the injection errors from the source, and thus reduces the phase-locked loop jitter while improving the anti-radiation performance.

Description

Technical Field

[0001] The present application relates to the technical field of digital-analog hybrid integrated circuit design, and in particular to a radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology. Background Art

[0002] As a clock generation circuit, the phase-locked loop circuit is one of the most important modules in integrated circuits. With the development of technology, it has been widely used in electronic communications, measurement, control, signal processing and other fields. It can be used for tasks such as frequency synthesis, clock recovery, modulation and demodulation, and phase control. It has the advantages of high precision, high stability, fast response and good anti-interference performance.

[0003] The traditional radiation-resistant charge pump phase-locked loop has a simple and stable structure. Although it can resist radiation, its anti-jitter performance is poor.

[0004] Injection-locked phase-locked loops (PLLs) can suppress both in-band and out-of-band phase noise by injecting a low-jitter signal into the oscillator, with virtually no additional cost. However, this injection introduces new radiation response issues, necessitating design hardening. Single-event effects in the injection path can alter the position of the injected pulse or generate erroneous injected pulses, leading to the injection of erroneous signals and the loss of PLL lock. Traditional hardening methods employ triple-mode redundant oscillator designs and components using radiation-hardened processes. However, triple-mode redundant oscillator designs can increase chip area and power consumption, as well as common-mode fault delays; using radiation-hardened process components can increase cost, reduce performance, and increase design complexity. Therefore, traditional LPL hardening methods fail to simultaneously improve the LPL's anti-jitter performance and radiation resistance. Summary of the Invention

[0005] To address the above problems, the present application provides a radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology, which performs system-level reinforcement of the injection-locked structure based on threshold filtering technology, thereby reducing the phase-locked loop jitter while improving the radiation resistance performance.

[0006] To achieve the purpose of this application, this application provides the following technical solutions:

[0007] In a first aspect, the present application provides a radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology, comprising a pulse calibration circuit, a pulse injection unit, and an injection-locked phase-locked loop;

[0008] The first input end of the pulse injection unit is connected to the output end of the pulse calibration circuit, the second input end is connected to the first output end of the injection locked phase locked loop, the first output end is connected to the first input end of the pulse calibration circuit, and the second output end is connected to the first input end of the injection locked phase locked loop;

[0009] The second output terminal of the injection locked phase locked loop is connected to the second input terminal of the pulse calibration circuit;

[0010] The pulse injection unit is used to receive a first signal, a second signal and a reference signal, and generate an injection signal and a threshold signal based on the first signal, the second signal and the reference signal, the first signal is the pulse calibration signal output by the pulse calibration circuit, the second signal is the first feedback signal output by the injection-locked phase-locked loop, and the threshold signal is used to determine whether to output the injection signal to the injection-locked phase-locked loop.

[0011] In a possible implementation, the pulse injection unit includes a pulse injection circuit and a digitally controlled threshold circuit;

[0012] The input end of the pulse injection circuit is connected to the output end of the pulse calibration circuit, and is configured to receive the first signal and generate the injection signal based on the first signal;

[0013] The first input end of the digital control threshold circuit is connected to the output end of the pulse injection circuit, the second input end is connected to the first output end of the injection locked phase locked loop, and the output end is connected to the first input end of the injection locked phase locked loop;

[0014] The digitally controlled threshold circuit is used to receive the injection signal, the second signal and the reference signal, generate the threshold signal based on the injection signal, the second signal and the reference signal, and then control the conduction of the injection path of the injection signal based on the threshold signal.

[0015] In a possible implementation, the pulse injection circuit includes a first injection sub-circuit, a second injection sub-circuit, and a third injection sub-circuit;

[0016] The input end of the injection sub-circuit is connected to the output end of the pulse calibration circuit, and is configured to receive the first signal and generate the injection signal based on the first signal;

[0017] Output terminals of the first injection sub-circuit and the second injection sub-circuit are both grounded;

[0018] The output end of the third injection sub-circuit is connected to the first input end of the digitally controlled threshold circuit, and is used to transmit the injection signal to the digitally controlled threshold circuit.

[0019] In a possible implementation, the injection subcircuit includes a first voltage-controlled delay line circuit, a second voltage-controlled delay line circuit, and a two-input AND gate;

[0020] An input end of the first voltage-controlled delay line circuit is connected to an output end of the pulse calibration circuit for receiving the first signal;

[0021] The input end of the second voltage-controlled delay line circuit is connected to the output end of the first voltage-controlled delay line circuit;

[0022] The first input end of the two-input AND gate is connected to the output end of the first voltage-controlled delay line circuit, and the second input end is connected to the output end of the second voltage-controlled delay line circuit;

[0023] The two-input AND gate is used to receive a third signal and a fourth signal, and generate the injection signal based on the third signal and the fourth signal, wherein the third signal and the fourth signal are respectively the signal output by the first voltage-controlled delay line circuit and the signal output by the second voltage-controlled delay line circuit.

[0024] In a possible implementation, the voltage-controlled delay line circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first resistor, a second resistor, and a current source;

[0025] The control signal input end of the voltage-controlled delay line circuit is commonly connected to the gates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor; the positive input end of the voltage-controlled delay line circuit is connected to the gate of the fifth NMOS transistor, and the negative input end is connected to the gate of the sixth NMOS transistor; the positive output end of the voltage-controlled delay line circuit is commonly connected to one end of the first resistor and the drains of the first NMOS transistor and the third NMOS transistor; the negative output end of the voltage-controlled delay line circuit is commonly connected to one end of the second resistor and the drains of the second NMOS transistor and the fourth NMOS transistor; the other ends of the first resistor and the second resistor are both connected to a power supply; the drain of the fifth NMOS transistor is commonly connected to the source of the second NMOS transistor and the third NMOS transistor; the drain of the sixth NMOS transistor is commonly connected to the source of the first NMOS transistor and the fourth NMOS transistor; the input end of the current source is commonly connected to the source of the fifth NMOS transistor and the sixth NMOS transistor, and the output end of the current source is grounded.

[0026] In a possible implementation, the digitally controlled threshold circuit includes three D flip-flops and a transmission gate;

[0027] The first input terminal of the D flip-flop is connected to the output terminal of the pulse injection circuit for receiving the injection signal;

[0028] The second input terminal of the D trigger is connected to the first output terminal of the injection locked phase locked loop, and is used to receive the second signal;

[0029] The third input terminal of the D flip-flop is connected to the reference signal;

[0030] The output terminal of the D flip-flop is connected to both control terminals of the transmission gate, for outputting the threshold signal to the transmission gate;

[0031] The input end of the transmission gate is connected to the output end of the pulse injection circuit for receiving the injection signal, and the output end is connected to the injection-locked phase-locked loop for outputting the injection signal;

[0032] The D flip-flop is configured to generate the threshold signal based on the injection signal, the second signal and the reference signal;

[0033] The transmission gate is used to determine whether to output the injection signal to the injection-locked phase-locked loop based on the threshold signal.

[0034] In a possible implementation, the transmission gate includes a first PMOS transistor and a seventh NMOS transistor;

[0035] The gates of the first PMOS transistor and the seventh NMOS transistor are both connected to the output end of the D flip-flop for receiving the threshold signal;

[0036] The source of the first PMOS transistor, the drain of the seventh NMOS transistor and the output end of the pulse injection circuit are commonly connected to receive the injection signal;

[0037] The drain of the first PMOS transistor is connected to the source of the seventh NMOS transistor and the first input terminal of the injection-locked phase-locked loop.

[0038] In one possible implementation, the pulse calibration circuit includes a comparator and an accumulator;

[0039] The positive input terminal of the comparator is connected to the output terminal of the pulse injection circuit, and the negative input terminal is connected to the second output terminal of the injection locked phase locked loop;

[0040] The comparator is configured to receive the injection signal and a second feedback signal output by the injection-locked phase-locked loop, and generate a phase difference signal based on the injection signal and the second feedback signal;

[0041] The input end of the accumulator is connected to the output end of the comparator, and is configured to receive the phase difference signal and generate the first signal based on the phase difference signal.

[0042] In a possible implementation, the injection-locked phase-locked loop includes an injection-locked oscillator, a phase frequency detector, a charge pump, a low-pass filter, and a frequency divider;

[0043] The first input terminal of the injection-locked oscillator is connected to the output terminal of the digitally controlled threshold circuit, and the second input terminal is connected to the output terminal of the low-pass filter; the injection-locked oscillator is used to receive the injection signal and a fifth signal, and generate the second feedback signal based on the injection signal and the fifth signal, wherein the fifth signal is a DC control voltage signal output by the low-pass filter;

[0044] The input end of the frequency divider is connected to the output end of the injection locked oscillator, and the output end is connected to the second input end of the digitally controlled threshold circuit and the first input end of the phase frequency detector; the frequency divider is used to receive the second feedback signal and generate the second signal based on the second feedback signal;

[0045] The phase frequency detector is used to receive the reference signal and the second signal, and generate an error signal based on the reference signal and the second signal;

[0046] The first input terminal and the second input terminal of the charge pump are connected to the first output terminal and the second output terminal of the phase and frequency detector respectively, and the charge pump is used to receive the error signal and generate a controllable current based on the error signal;

[0047] An input end of the low-pass filter is connected to an output end of the charge pump. The low-pass filter is configured to receive the controllable current and generate the fifth signal based on the controllable current.

[0048] In a possible implementation, the injection-locked oscillator includes an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first differential delay unit, a second differential delay unit, a third differential delay unit, and a buffer;

[0049] The gates of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are all connected to the output end of the digital control threshold circuit for receiving the injection signal; the sources of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are respectively connected to the first input end of the first differential delay unit, the first input end of the second differential delay unit, and the first input end of the third differential delay unit; the drains of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are respectively connected to the second input end of the first differential delay unit, the second input end of the second differential delay unit, and the second input end of the third differential delay unit;

[0050] The first input end of the first differential delay unit is connected to the first output end of the third differential delay unit, the second input end is connected to the second output end of the third differential delay unit, the first output end is connected to the first input end of the second differential delay unit, and the second output end is connected to the second input end of the second differential delay unit;

[0051] The first output end of the second differential delay unit is connected to the first input end of the third differential delay unit, and the second output end is connected to the second input end of the third differential delay unit;

[0052] The first output end of the third differential delay unit is connected to the first input end of the buffer, and the second output end is connected to the second input end of the buffer;

[0053] The third input end of the first differential delay unit, the third input end of the second differential delay unit, and the third input end of the third differential delay unit are all connected to the output end of the low-pass filter and are all used to receive the fifth signal.

[0054] Beneficial effects:

[0055] This application is based on the reinforcement of the injection-locked phase-locked loop structure architecture and proposes a pulse injection unit. It generates an injection signal and a threshold signal at the same time. The conduction state of the injection path of the injection signal is controlled according to the threshold signal, which greatly reduces the probability of error injection and filters out most of the injection errors from the source, thereby reducing the phase-locked loop jitter while improving the radiation resistance performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The accompanying drawings are used to provide a further understanding of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not limit the present application.

[0057] Figure 1 A schematic diagram of the structure of a radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology provided in an embodiment of the present application;

[0058] Figure 2 A schematic diagram of another structure of a radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology provided in an embodiment of the present application;

[0059] Figure 3 A schematic diagram of the structure of an injection circuit provided in an embodiment of the present application;

[0060] Figure 4 A schematic diagram of the structure of a voltage-controlled delay line circuit provided in an embodiment of the present application;

[0061] Figure 5A schematic diagram of the structure of a digital control threshold circuit provided in an embodiment of the present application;

[0062] Figure 6 A schematic diagram of a signal waveform for introducing a single event effect provided in an embodiment of the present application;

[0063] Figure 7 A single event effect diagram outside the injection threshold provided in an embodiment of the present application;

[0064] Figure 8 Schematic diagram of simulation results of injection threshold under different PVT conditions provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0066] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features indicated. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features; and in the description of this application, unless otherwise specified, "plurality" means two or more.

[0067] An embodiment of the present application provides a radiation-resistant low-jitter injection-locked phase-locked loop based on a threshold filtering technology, comprising: a pulse calibration circuit, a pulse injection unit, and an injection-locked phase-locked loop;

[0068] The first input end of the pulse injection unit is connected to the output end of the pulse calibration circuit, the second input end is connected to the first output end of the injection locked phase locked loop, the first output end is connected to the first input end of the pulse calibration circuit, and the second output end is connected to the first input end of the injection locked phase locked loop;

[0069] The second output terminal of the injection locked phase locked loop is connected to the second input terminal of the pulse calibration circuit;

[0070] The pulse injection unit is used to receive a first signal, a second signal and a reference signal, and generate an injection signal and a threshold signal based on the first signal, the second signal and the reference signal, the first signal is the pulse calibration signal output by the pulse calibration circuit, the second signal is the first feedback signal output by the injection-locked phase-locked loop, and the threshold signal is used to determine whether to output the injection signal to the injection-locked phase-locked loop.

[0071] The technical solution of the present invention is described below with reference to the embodiments shown in the accompanying drawings:

[0072] like Figure 1 As shown, a radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology may include:

[0073] Pulse calibration circuit 11, pulse injection unit 12 and injection locked phase locked loop 13;

[0074] The first input end of the pulse injection unit 12 is connected to the output end of the pulse calibration circuit 11, the second input end is connected to the first output end of the injection locked phase locked loop 13, the first output end is connected to the first input end of the pulse calibration circuit 11, and the second output end is connected to the first input end of the injection locked phase locked loop 13;

[0075] The second output end of the injection locked phase locked loop 13 is connected to the second input end of the pulse calibration circuit 11;

[0076] The pulse injection unit 12 is used to receive a first signal, a second signal and a reference signal, and generate an injection signal and a threshold signal based on the first signal, the second signal and the reference signal, the first signal is the pulse calibration signal output by the pulse calibration circuit 11, the second signal is the first feedback signal output by the injection-locked phase-locked loop 13, and the threshold signal is used to determine whether to output the injection signal to the injection-locked phase-locked loop 13.

[0077] It should be noted that the traditional radiation-resistant charge pump phase-locked loop has a simple and stable structure, but poor anti-jitter performance. The injection-locked phase-locked loop only introduces one injection path on the basis of the charge pump phase-locked loop, has a simple structure, and does not introduce too many additional sensitive nodes. For the reinforcement of the injection-locked phase-locked loop, the single-particle effect in the injection path will change the injection pulse position or generate an erroneous injection pulse, resulting in the injection of an erroneous signal, causing the phase-locked loop to lose lock, and the injection will also introduce new radiation response problems. Therefore, if most of the error injections caused by the single-particle effect can be filtered out after the injection signal is generated, it is possible to reduce the jitter of the phase-locked loop while enhancing the anti-radiation capability of the phase-locked loop. Therefore, this embodiment proposes a pulse injection unit to generate an injection signal and filter the error injection.

[0078] In the embodiments of this application, Figure 2 As shown, the pulse injection unit includes a pulse injection circuit and a digitally controlled threshold circuit; the input end of the pulse injection circuit is connected to the output end of the pulse calibration circuit, and is used to receive the first signal and generate the injection signal based on the first signal;

[0079] The first input end of the digital control threshold circuit is connected to the output end of the pulse injection circuit, the second input end is connected to the first output end of the injection locked phase locked loop, and the output end is connected to the first input end of the injection locked phase locked loop;

[0080] The digitally controlled threshold circuit is used to receive the injection signal, the second signal and the reference signal, generate the threshold signal based on the injection signal, the second signal and the reference signal, and then conduct the injection path of the injection signal based on the threshold signal.

[0081] It can be understood that the pulse injection circuit receives the voltage signal output by the pulse calibration circuit, that is, the pulse calibration signal. The pulse injection circuit delays the pulse calibration signal through the delay circuit to generate an injection signal and outputs the injection signal to the digital control threshold circuit.

[0082] In this embodiment, if Figure 2 As shown, the pulse calibration circuit includes a comparator and an accumulator;

[0083] The positive input terminal of the comparator is connected to the output terminal of the pulse injection circuit, and the negative input terminal is connected to the second output terminal of the injection locked phase locked loop;

[0084] The comparator is configured to receive the injection signal and a second feedback signal output by the injection-locked phase-locked loop, and generate a phase difference signal based on the injection signal and the second feedback signal;

[0085] The input end of the accumulator is connected to the output end of the comparator, and is configured to receive the phase difference signal and generate the first signal based on the phase difference signal.

[0086] It can be understood that because the injection signal needs to be adjusted according to the frequency and phase of the output signal of the injection-locked oscillator, the adjusted injection signal can make the oscillator operate at the desired operating frequency, so the comparator will compare the injection signal and the feedback signal output by the injection-locked phase-locked loop, thereby outputting a phase difference signal, and then accumulate the phase difference value through the accumulator to obtain a pulse calibration signal.

[0087] In this embodiment, if Figure 2 As shown, the pulse injection circuit includes a first injection circuit, a second injection circuit and a third injection circuit;

[0088] The input end of each injection circuit is connected to the output end of the pulse calibration circuit and is used to receive the first signal;

[0089] Output terminals of the first injection circuit and the third injection circuit are both grounded;

[0090] The output end of the second injection circuit is connected to the first input end of the digitally controlled threshold circuit, and is used to output the injection signal.

[0091] Each injection circuit generates an injection signal. The output of the second injection circuit is used as the injection circuit output, and the outputs of the other two injection sub-circuits are grounded mainly to optimize phase noise suppression, reduce interference and improve the linearity of the injection system.

[0092] In this embodiment, if Figure 3 As shown, the injection sub-circuit includes a first voltage-controlled delay line circuit, a second voltage-controlled delay line circuit and a two-input AND gate;

[0093] An input end of the first voltage-controlled delay line circuit is connected to an output end of the pulse calibration circuit for receiving the first signal;

[0094] The input end of the second voltage-controlled delay line circuit is connected to the output end of the first voltage-controlled delay line circuit;

[0095] The first input end of the two-input AND gate is connected to the output end of the first voltage-controlled delay line circuit, and the second input end is connected to the output end of the second voltage-controlled delay line circuit;

[0096] The two-input AND gate is used to receive a third signal and a fourth signal, and generate the injection signal based on the third signal and the fourth signal, wherein the third signal and the fourth signal are respectively the signal output by the first voltage-controlled delay line circuit and the signal output by the second voltage-controlled delay line circuit.

[0097] It can be understood that the two-input AND gate can calculate the time difference between the calibration signal passing through the first voltage-controlled delay line and the second voltage-controlled delay line, and this time difference forms the pulse width of the injection signal through the AND gate.

[0098] In this embodiment, if Figure 4 As shown, the voltage-controlled delay line circuit includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a first resistor, a second resistor and a current source;

[0099] The control signal input end of the voltage-controlled delay line circuit is commonly connected to the gates of the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, and the fourth NMOS transistor N4; the positive input end of the voltage-controlled delay line circuit is connected to the gate of the fifth NMOS transistor N5, and the negative input end is connected to the gate of the sixth NMOS transistor N6; the positive output end of the voltage-controlled delay line circuit is commonly connected to one end of the first resistor and the drains of the first NMOS transistor N1 and the third NMOS transistor N3; the negative output end of the voltage-controlled delay line circuit is commonly connected to the second resistor One end of the first resistor and the drain of the second NMOS transistor N2 and the fourth NMOS transistor N4 are commonly connected; the other ends of the first resistor and the second resistor are both connected to a power supply; the drain of the fifth NMOS transistor N5 is commonly connected to the source of the second NMOS transistor N2 and the third NMOS transistor N3; the drain of the sixth NMOS transistor N6 is commonly connected to the source of the first NMOS transistor N1 and the fourth NMOS transistor N4; the input end of the current source is commonly connected to the source of the fifth NMOS transistor N5 and the sixth NMOS transistor N6, and the output end of the current source is grounded.

[0100] It will be appreciated that the control signal input of the voltage-controlled delay circuit receives an external voltage control signal for dynamically adjusting the delay time of the delay line. The positive input and negative input are respectively used to receive the positive and negative phase components of the pulse calibration signal. Each injection signal generated by the second injection circuit passes through a digitally controlled threshold circuit to determine whether the injection signal is an error signal, thereby filtering out any error signals.

[0101] In this embodiment, if Figure 5 As shown, the digital control threshold circuit includes three D flip-flops and a transmission gate;

[0102] The clock input terminal of the D flip-flop, i.e., the CLK terminal, is connected to the output terminal of the pulse injection circuit for receiving the injection signal;

[0103] The data input terminal of the D flip-flop, i.e., the D terminal, is connected to the first output terminal of the injection-locked phase-locked loop for receiving the second signal;

[0104] The reset signal terminal of the D flip-flop, i.e., the Reset terminal, is used to receive the reference signal;

[0105] The output terminal of the D flip-flop, i.e., the Q terminal, is connected to both control terminals of the transmission gate, for outputting the threshold signal to the transmission gate;

[0106] The input end of the transmission gate is connected to the output end of the pulse injection circuit for receiving the injection signal, and the output end is connected to the injection-locked phase-locked loop for outputting the injection signal;

[0107] The D flip-flop is configured to generate the threshold signal based on the injection signal, the second signal and the reference signal;

[0108] The transmission gate is used to determine whether to output the injection signal to the injection-locked phase-locked loop.

[0109] The transmission gate includes a first PMOS transistor and a seventh NMOS transistor;

[0110] The gates of the first PMOS transistor and the seventh NMOS transistor are both connected to the output end of the D flip-flop for receiving the threshold signal;

[0111] The source of the first PMOS transistor, the drain of the seventh NMOS transistor and the output end of the pulse injection circuit are commonly connected to receive the injection signal;

[0112] The drain of the first PMOS transistor is connected to the source of the seventh NMOS transistor and the first input terminal of the injection-locked phase-locked loop.

[0113] It can be understood that after the D flip-flop receives the injection signal, the reference signal, and the feedback signal from the injection-locked phase-locked loop (ILPL), the feedback signal from the ILPL generates a threshold signal through the D flip-flop when the injection signal's rising edge flips. The D flip-flop then resets when the reference signal is valid, causing the above operation to repeat in each reference cycle. Each D flip-flop generates a threshold signal, and the control terminal of the transmission gate receives the threshold signal generated by each D flip-flop and then controls the conduction of the transmission gate based on the threshold signal.

[0114] Furthermore, it is understandable that Figure 6 As shown, the output signal is the positive and negative oscillation signal output by the injection-locked phase-locked loop. After receiving the output signal, the reference signal and the injection signal, the digitally controlled threshold circuit generates a short gating time window near the injection time through the logic circuit. The single-particle effect will also produce a pulse similar to the injection signal, but the occurrence time and pulse width of this pulse are random, and the injection signal only occurs within the short gating window time of the threshold signal, so the threshold signal can eliminate most of the error injection caused by the single-particle effect, that is, only when the threshold signal is at a high level can the injection signal be successfully injected into the oscillator. When the threshold signal is at a low level, it means that the signal is an error signal caused by the single-particle effect, and the error signal will be filtered out and will not be injected into the oscillator. In this way, the strength of the injection signal is effectively improved, thereby reducing the clock jitter of the injection-locked phase-locked loop. In addition, the threshold circuit has a simple structure and does not introduce additional sensitive nodes, further improving the circuit's radiation resistance. As shown Figure 7As shown in the figure, the horizontal axis represents time (us), the vertical axis represents voltage (mV), the injection signal is the injection signal output by the pulse injection circuit, and the gate signal is the gate signal output by the digital control threshold circuit. A single particle effect outside the threshold is artificially introduced into the system, and it can be seen that the single particle effect is successfully filtered out.

[0115] In the embodiments of this application, Figure 2 As shown, the injection-locked phase-locked loop includes an injection-locked oscillator, a phase frequency detector, a charge pump, a low-pass filter and a frequency divider; the vertical axis represents voltage (mV)

[0116] The first input terminal of the injection-locked oscillator is connected to the output terminal of the digitally controlled threshold circuit, and the second input terminal is connected to the output terminal of the low-pass filter; the injection-locked oscillator is used to receive the injection signal and a fifth signal, and generate the second feedback signal based on the injection signal and the fifth signal, wherein the fifth signal is a DC control voltage signal output by the low-pass filter;

[0117] The input end of the frequency divider is connected to the output end of the injection locked oscillator, and the output end is connected to the second input end of the digitally controlled threshold circuit and the first input end of the phase frequency detector; the frequency divider is used to receive the second feedback signal and generate the second signal based on the second feedback signal;

[0118] The phase frequency detector is used to receive the reference signal and the second signal, and generate an error signal based on the reference signal and the second signal;

[0119] The first input terminal and the second input terminal of the charge pump are connected to the first output terminal and the second output terminal of the phase and frequency detector respectively, and the charge pump is used to receive the error signal and generate a controllable current based on the error signal;

[0120] An input end of the low-pass filter is connected to an output end of the charge pump. The low-pass filter is configured to receive the controllable current and generate the fifth signal based on the controllable current.

[0121] It can be understood that the divider will divide the positive and negative oscillation signals output by the injection-locked oscillator of the previous cycle according to the set ratio. The frequency division allows the phase-locked loop to operate at a higher frequency, and the divided signal is input into the phase frequency detector. The phase frequency detector then outputs an error signal by detecting the phase difference and frequency difference between the input reference signal and the output signal of the divider. After receiving the error signal output by the phase frequency detector, the charge pump converts the error signal into a controllable current, thereby driving the low-pass filter to generate a stable control voltage and output a fluctuating voltage signal to the low-pass filter. The low-pass filter will filter out the high-frequency noise and ripple output by the phase frequency detector and the charge pump, thereby generating a smooth DC control voltage signal.

[0122] The charge pump is used to convert the error signal output by the frequency and phase detector into a controllable current, drive the low-pass filter to generate a stable control voltage, and output a fluctuating voltage signal to the low-pass filter.

[0123] The low-pass filter is used to filter out high-frequency noise and ripples output by the frequency detector and the charge pump, and generate a smooth DC control voltage signal.

[0124] In this embodiment, the injection-locked oscillator includes a first injector, a second injector, a third injector, a first differential delay unit, a second differential delay unit, a third differential delay unit and a buffer;

[0125] Among them, the first injector, the second injector and the third injector are the eighth NMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor respectively; the differential delay unit can be implemented based on a differential delay inverter, which is common knowledge in the field of phase-locked loops and will not be described in detail;

[0126] The gates of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are all connected to the output end of the digital control threshold circuit for receiving the injection signal; the sources of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are respectively connected to the first input end of the first differential delay unit, the first input end of the second differential delay unit, and the first input end of the third differential delay unit; the drains of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are respectively connected to the second input end of the first differential delay unit, the second input end of the second differential delay unit, and the second input end of the third differential delay unit;

[0127] like Figure 2As shown, the first input terminal VN of the first differential delay unit is connected to the first output terminal Vop of the third differential delay unit, the second input terminal VP is connected to the second output terminal Von of the third differential delay unit, the first output terminal Vop is connected to the first input terminal VN of the second differential delay unit, and the second output terminal Von is connected to the second input terminal VP of the second differential delay unit;

[0128] The first output terminal Vop of the second differential delay unit is connected to the first input terminal VN of the third differential delay unit, and the second output terminal Von is connected to the second input terminal VP of the third differential delay unit;

[0129] The first output terminal Vop of the third differential delay unit is connected to the first input terminal of the buffer, and the second output terminal Von is connected to the second input terminal of the buffer;

[0130] The third input end of the first differential delay unit, the third input end of the second differential delay unit, and the third input end of the third differential delay unit are all connected to the output end of the low-pass filter and are all used to receive the fifth signal.

[0131] It is understandable that after the injection-locked oscillator receives the injection signal and the DC control voltage signal of the low-pass filter, the injection-locked oscillator directly and synchronously adjusts the operating frequency of the three differential delay units according to the DC control voltage signal; when the injection signal is injected, the injected voltage signal is converted into a current signal by the three injectors and injected into the three differential delay units. The increased current causes the operating frequency of the three differential delay units to change. Under the joint action of the injection signal and the DC control voltage signal, the injection-locked oscillator will operate at the desired operating frequency. The third differential delay unit outputs the positive and negative oscillation signals to the buffer. The buffer will enhance the driving capability of the positive and negative oscillation signals and output them.

[0132] A simulation experiment was conducted based on a radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology provided by the present invention:

[0133] The present invention uses Cadence tools to simulate the circuit of this embodiment, and simulates under SS, TT, and FF process corner conditions respectively, and obtains the following results: Figure 8The simulation results of the injection threshold under different process, voltage and temperature (PVT) conditions are shown in the figure, where the horizontal axis represents time (us) and the vertical axis represents voltage (mV). The curves of the threshold signal VC_ss under the SS process angle condition, the curve of the threshold signal VC_tt under the TT process angle condition, and the curve of the threshold signal VC_ff under the FF process angle condition are obtained respectively. From the simulation results, it can be seen that the threshold voltage is basically maintained within the usable range. This can ensure that erroneous pulse injection will not be injected into the circuit under different PVT conditions, thereby improving the anti-jitter and anti-radiation capabilities of the phase-locked loop.

[0134] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0135] The above embodiments are intended only to illustrate the technical solutions of the present application and are not intended to limit them. The present application is not limited to the precise structures described above and illustrated in the accompanying drawings, and it cannot be assumed that the specific implementation of the present application is limited to these descriptions. For those skilled in the art of the present application, any changes and modifications made without departing from the concept of the present application should be deemed to fall within the scope of protection of the present application.

Claims

1. A radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology, characterized in that: It includes a pulse calibration circuit, a pulse injection unit and an injection locked phase locked loop; The first input end of the pulse injection unit is connected to the output end of the pulse calibration circuit, the second input end is connected to the first output end of the injection locked phase locked loop, the first output end is connected to the first input end of the pulse calibration circuit, and the second output end is connected to the first input end of the injection locked phase locked loop; The second output terminal of the injection locked phase locked loop is connected to the second input terminal of the pulse calibration circuit; The pulse injection unit is used to receive a first signal, a second signal and a reference signal, and generate an injection signal and a threshold signal based on the first signal, the second signal and the reference signal, the first signal being the pulse calibration signal output by the pulse calibration circuit, the second signal being the first feedback signal output by the injection-locked phase-locked loop, and the threshold signal being used to determine whether to output the injection signal to the injection-locked phase-locked loop; The pulse injection unit includes a pulse injection circuit and a digital control threshold circuit; The input end of the pulse injection circuit is connected to the output end of the pulse calibration circuit, and is configured to receive the first signal and generate the injection signal based on the first signal; The first input end of the digital control threshold circuit is connected to the output end of the pulse injection circuit, the second input end is connected to the first output end of the injection locked phase locked loop, and the output end is connected to the first input end of the injection locked phase locked loop; The digitally controlled threshold circuit is used to receive the injection signal, the second signal and the reference signal, generate the threshold signal based on the injection signal, the second signal and the reference signal, and then control the conduction of the injection path of the injection signal based on the threshold signal; The digital control threshold circuit includes three D flip-flops and a transmission gate; The first input terminal of the D flip-flop is connected to the output terminal of the pulse injection circuit for receiving the injection signal; The second input terminal of the D trigger is connected to the first output terminal of the injection locked phase locked loop, and is used to receive the second signal; The third input terminal of the D flip-flop is connected to the reference signal; The output terminal of the D flip-flop is connected to both control terminals of the transmission gate, for outputting the threshold signal to the transmission gate; The input end of the transmission gate is connected to the output end of the pulse injection circuit for receiving the injection signal, and the output end is connected to the injection-locked phase-locked loop for outputting the injection signal; The D flip-flop is configured to generate the threshold signal based on the injection signal, the second signal and the reference signal; The transmission gate is used to determine whether to output the injection signal to the injection-locked phase-locked loop based on the threshold signal.

2. The radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology according to claim 1, characterized in that: The pulse injection circuit includes a first injection sub-circuit, a second injection sub-circuit and a third injection sub-circuit; The input end of the injection sub-circuit is connected to the output end of the pulse calibration circuit, and is configured to receive the first signal and generate the injection signal based on the first signal; Output terminals of the first injection sub-circuit and the second injection sub-circuit are both grounded; The output end of the third injection sub-circuit is connected to the first input end of the digitally controlled threshold circuit, and is used to transmit the injection signal to the digitally controlled threshold circuit.

3. The radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology according to claim 2, characterized in that: The injection subcircuit includes a first voltage-controlled delay line circuit, a second voltage-controlled delay line circuit and a two-input AND gate; An input end of the first voltage-controlled delay line circuit is connected to an output end of the pulse calibration circuit for receiving the first signal; The input end of the second voltage-controlled delay line circuit is connected to the output end of the first voltage-controlled delay line circuit; The first input end of the two-input AND gate is connected to the output end of the first voltage-controlled delay line circuit, and the second input end is connected to the output end of the second voltage-controlled delay line circuit; The two-input AND gate is used to receive a third signal and a fourth signal, and generate the injection signal based on the third signal and the fourth signal, wherein the third signal and the fourth signal are respectively the signal output by the first voltage-controlled delay line circuit and the signal output by the second voltage-controlled delay line circuit.

4. The radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology according to claim 3, characterized in that: The voltage-controlled delay line circuit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first resistor, a second resistor and a current source; The control signal input end of the voltage-controlled delay line circuit is commonly connected to the gates of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor; the positive input end of the voltage-controlled delay line circuit is connected to the gate of the fifth NMOS transistor, and the negative input end is connected to the gate of the sixth NMOS transistor; the positive output end of the voltage-controlled delay line circuit is commonly connected to one end of the first resistor and the drains of the first NMOS transistor and the third NMOS transistor; the negative output end of the voltage-controlled delay line circuit is commonly connected to one end of the second resistor and the drains of the second NMOS transistor and the fourth NMOS transistor; the other ends of the first resistor and the second resistor are both connected to a power supply; the drain of the fifth NMOS transistor is commonly connected to the source of the second NMOS transistor and the third NMOS transistor; the drain of the sixth NMOS transistor is commonly connected to the source of the first NMOS transistor and the fourth NMOS transistor; the input end of the current source is commonly connected to the source of the fifth NMOS transistor and the sixth NMOS transistor, and the output end of the current source is grounded.

5. The radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology according to claim 1, characterized in that: The transmission gate includes a first PMOS transistor and a seventh NMOS transistor; The gates of the first PMOS transistor and the seventh NMOS transistor are both connected to the output end of the D flip-flop for receiving the threshold signal; The source of the first PMOS transistor, the drain of the seventh NMOS transistor and the output end of the pulse injection circuit are commonly connected to receive the injection signal; The drain of the first PMOS transistor is connected to the source of the seventh NMOS transistor and the first input terminal of the injection-locked phase-locked loop.

6. The radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology according to claim 1, characterized in that: The pulse calibration circuit includes a comparator and an accumulator; The positive input terminal of the comparator is connected to the output terminal of the pulse injection circuit, and the negative input terminal is connected to the second output terminal of the injection locked phase locked loop; The comparator is configured to receive the injection signal and a second feedback signal output by the injection-locked phase-locked loop, and generate a phase difference signal based on the injection signal and the second feedback signal; The input end of the accumulator is connected to the output end of the comparator, and is configured to receive the phase difference signal and generate the first signal based on the phase difference signal.

7. The radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology according to claim 6, characterized in that: The injection locked phase locked loop includes an injection locked oscillator, a phase frequency detector, a charge pump, a low pass filter and a frequency divider; The first input end of the injection locked oscillator is connected to the output end of the digital control threshold circuit, and the second input end is connected to the output end of the low-pass filter; The injection-locked oscillator is configured to receive the injection signal and a fifth signal, and generate the second feedback signal based on the injection signal and the fifth signal, wherein the fifth signal is a DC control voltage signal output by the low-pass filter; The input end of the frequency divider is connected to the output end of the injection locked oscillator, and the output end is connected to the second input end of the digital control threshold circuit and the first input end of the frequency and phase detector; The frequency divider is configured to receive the second feedback signal and generate the second signal based on the second feedback signal; The phase frequency detector is used to receive the reference signal and the second signal, and generate an error signal based on the reference signal and the second signal; The first input terminal and the second input terminal of the charge pump are connected to the first output terminal and the second output terminal of the phase and frequency detector respectively, and the charge pump is used to receive the error signal and generate a controllable current based on the error signal; An input end of the low-pass filter is connected to an output end of the charge pump. The low-pass filter is configured to receive the controllable current and generate the fifth signal based on the controllable current.

8. The radiation-resistant low-jitter injection-locked phase-locked loop based on threshold filtering technology according to claim 7, characterized in that: The injection-locked oscillator includes an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a first differential delay unit, a second differential delay unit, a third differential delay unit and a buffer; The gates of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are all connected to the output end of the digital control threshold circuit for receiving the injection signal; the sources of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are respectively connected to the first input end of the first differential delay unit, the first input end of the second differential delay unit, and the first input end of the third differential delay unit; the drains of the eighth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are respectively connected to the second input end of the first differential delay unit, the second input end of the second differential delay unit, and the second input end of the third differential delay unit; The first input end of the first differential delay unit is connected to the first output end of the third differential delay unit, the second input end is connected to the second output end of the third differential delay unit, the first output end is connected to the first input end of the second differential delay unit, and the second output end is connected to the second input end of the second differential delay unit; The first output end of the second differential delay unit is connected to the first input end of the third differential delay unit, and the second output end is connected to the second input end of the third differential delay unit; The first output end of the third differential delay unit is connected to the first input end of the buffer, and the second output end is connected to the second input end of the buffer; The third input end of the first differential delay unit, the third input end of the second differential delay unit, and the third input end of the third differential delay unit are all connected to the output end of the low-pass filter and are all used to receive the fifth signal.

Images