Error correction coding constant matrix generation method and system
By preferentially screening binary codes with smaller Hamming weights to construct an error correction coding constant matrix, the problems of hardware resource waste and performance degradation in the existing technology are solved, and the optimization and security improvement of ECC encoding and decoding circuits are achieved.
Patent Information
- Application Number
- CN202510875422.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-27
- Publication Date
- 2025-09-16
AI Technical Summary
The existing error correction coding constant matrix construction method does not fully consider sparsity, resulting in hardware resource waste and performance degradation, and urgently needs optimization.
The error correction coding constant matrix is constructed by preferentially screening binary codes with smaller Hamming weights. A more sparse matrix is generated by adopting Hamming weight priority sorting and group selection method, thereby reducing the number of XOR gates in the ECC encoding circuit and the ECC decoding circuit.
Significantly reduce the number of XOR gates in the ECC encoding circuit and ECC decoding circuit, lower logic complexity, optimize circuit area and timing performance, improve error correction capability and resistance to side-channel attacks, and enhance security and adaptability.
Smart Images
Figure CN120658274A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of integrated circuit design, and in particular to a method and system for generating an error correction coding constant matrix. Background Art
[0002] In modern computing and communication systems, Error Correction Code (ECC) is an error detection and correction technology widely used to ensure data security in key modules such as CPUs and DDR. Its basic principle is to encode the input bit stream to generate redundant check bits at the transmitter, and then perform recalculation at the receiver to detect and correct errors.
[0003] The ECC encoding and decoding processes rely on a fixed error correction coding constant matrix, which determines which input bits are associated with each output check bit. In hardware implementation, the structure of this matrix directly affects the number of XOR gates and logic connection complexity of the ECC encoding and decoding circuits, thereby determining the circuit area and timing performance. However, existing methods for constructing error correction coding constant matrices often use sequential selection, failing to fully consider the sparsity of the matrix. This results in wasted hardware resources and reduced performance, necessitating urgent optimization. Summary of the Invention
[0004] The present invention provides a method and system for generating an error correction coding constant matrix. The error correction coding constant matrix is constructed by preferentially screening binary codes with smaller Hamming weights. Compared with the traditional sequential coding method, the generated error correction coding constant matrix is more sparse, which can significantly reduce the number of XOR gates in the ECC encoding circuit and the ECC decoding circuit, reduce the logic complexity, and facilitate the optimization of the area and timing performance of the ECC encoding circuit and the ECC decoding circuit.
[0005] An embodiment of the present invention provides a method for generating an error correction coding constant matrix, comprising: Setting the number of input bits and the number of redundant bits for error correction coding, wherein the number of input bits is the number of rows of the error correction coding constant matrix, and the number of redundant bits for error correction coding is the number of columns of the error correction coding constant matrix; Starting from a positive integer 1 and increasing in sequence according to the positive integers with a step size of 1, each of the positive integers is converted into a binary coded column vector, where the length of the binary coded column vector is the number of rows, and the increment is stopped when the number of generated binary coded column vectors reaches the number of columns, and all generated binary coded column vectors constitute a candidate column vector set; Filtering out binary-coded column vectors that meet the legal column screening condition and whose number is equal to the number of columns from the candidate column vector set as legal column vectors; The legal column vectors are weighted grouped according to Hamming weights, the legal column vectors with the same Hamming weight are divided into the same weight group, and all the weight groups are arranged in ascending order according to the Hamming weight values; According to the sorted weight grouping order, each legal column vector in each weight group is selected from front to back, one group at a time, as the column vector of the error correction coding constant matrix. Each bit in each column vector is mapped to the corresponding row of the error correction coding constant matrix in turn, until the number of selected column vectors is equal to the number of columns, thereby completing the construction of the error correction coding constant matrix.
[0006] Preferably, each of the binary coded column vectors includes at least one bit that is 1.
[0007] Preferably, the legal column screening condition is that the Hamming weight is an odd number and greater than 1.
[0008] Preferably, the legal column vectors within the same weight group are arranged in a random order.
[0009] Preferably, in the process of screening legal column vectors from the candidate column vector set, if the number of screened legal column vectors is less than the set number of error correction coding redundant bits, the number of error correction coding redundant bits is automatically increased and updated, and the candidate column vector set is regenerated based on the updated number of error correction coding redundant bits until the column number requirement for constructing the error correction coding constant matrix is met.
[0010] Preferably, the generated error correction coding constant matrix is used to configure an XOR gate connection structure in an error correction coding circuit.
[0011] Preferably, the generated error correction coding constant matrix is also used to construct the comprehensive value calculation logic of the error correction decoding circuit, and the XOR gate connection structure in the error correction decoding circuit is configured based on the comprehensive value calculation logic.
[0012] An embodiment of the present invention further provides a system for generating an error correction coding constant matrix, comprising: A parameter setting module for setting the number of input bits and the number of redundant bits of the error correction code, wherein the number of input bits is the number of rows of the error correction code constant matrix, and the number of redundant bits of the error correction code is the number of columns of the error correction code constant matrix; a candidate column vector set generating module, starting from a positive integer 1 and increasing in order of positive integers with a step size of 1, converting each of the positive integers into a binary-coded column vector, where the length of the binary-coded column vector is the number of rows, stopping the increment when the number of generated binary-coded column vectors reaches the number of columns, and all generated binary-coded column vectors constitute a candidate column vector set; a legal column vector screening module, screening out binary-coded column vectors that meet the legal column screening conditions and whose number is equal to the number of columns from the candidate column vector set as legal column vectors; A weight grouping and sorting module groups the legal column vectors according to Hamming weights, groups the legal column vectors with the same Hamming weights into the same weight group, and arranges all the weight groups in ascending order according to the Hamming weight values; The error correction coding constant matrix construction module selects each legal column vector in each weight group from front to back in accordance with the sorted weight grouping order as the column vector of the error correction coding constant matrix, and each bit in each column vector is mapped to the corresponding row of the error correction coding constant matrix in turn until the number of selected column vectors equals the number of columns, thereby completing the construction of the error correction coding constant matrix.
[0013] The present application provides an electronic device, including: processor; and, a memory for storing executable instructions of the processor; The processor is configured to perform any possible method described in the first aspect by executing the executable instructions.
[0014] The present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement any possible method described in the first aspect.
[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects: An embodiment of the present invention provides a method and system for generating an error correction coding constant matrix. The method includes: setting the number of input bits and the number of error correction coding redundant bits, wherein the number of input bits is the number of rows of the error correction coding constant matrix, and the number of error correction coding redundant bits is the number of columns of the error correction coding constant matrix; starting from a positive integer 1 and increasing the number of positive integers in sequence, with an increasing step of 1, converting each of the positive integers into a binary coded column vector, wherein the length of the binary coded column vector is the number of rows, and stopping the increment when the number of generated binary coded column vectors reaches the number of columns, wherein all generated binary coded column vectors constitute a candidate column vector set; and screening out the legal column vectors from the candidate column vector set. Screening conditions, and the number of binary coded column vectors equal to the number of columns, as legal column vectors; weight grouping the legal column vectors according to Hamming weights, dividing the legal column vectors with the same Hamming weights into the same weight group, and arranging all the weight groups in ascending order according to the Hamming weight values from small to large; according to the sorted weight grouping order, each legal column vector in each weight group is selected from front to back in turn as the column vector of the error correction coding constant matrix, and each bit in each column vector is mapped to the corresponding row of the error correction coding constant matrix in turn, until the number of selected column vectors is equal to the number of columns, and the construction of the error correction coding constant matrix is completed. The present invention constructs the error correction coding constant matrix by preferentially screening binary codes with smaller Hamming weights. The generated error correction coding constant matrix is more sparse, can significantly reduce the number of XOR gates in the ECC encoding circuit and the ECC decoding circuit, reduce the logic complexity, and is conducive to optimizing the area and timing performance of the ECC encoding circuit and the ECC decoding circuit; Furthermore, the legal column screening condition is that the Hamming weight is an odd number and greater than 1, which helps to improve the error correction capability of the error correction coding constant matrix, ensuring that the encoded data has stronger error detection and location characteristics, thereby enhancing the overall fault tolerance performance; Furthermore, the legal column vectors within the same weight group are arranged in a random order, which can increase the unpredictability of the error correction coding constant matrix and improve the ability to resist side channel attacks and security while maintaining consistent performance; Furthermore, in the process of screening legal column vectors from the candidate column vector set, if the number of screened legal column vectors is less than the set number of error correction coding redundant bits, the number of error correction coding redundant bits is automatically increased and updated, and the candidate column vector set is regenerated based on the updated number of error correction coding redundant bits until the column number requirement for constructing the error correction coding constant matrix is met. This can avoid the problems of construction failure or parameter conflict, ensure that the error correction coding constant matrix can be successfully generated under different parameter configurations, and enhance its adaptability and stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention, not all embodiments. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.
[0017] Figure 1 A schematic flow chart of a method for generating an error correction coding constant matrix provided in one embodiment of the present invention; Figure 2 A schematic diagram of a module of an error correction coding constant matrix generation system provided by one embodiment of the present invention; Figure 3 It is a structural diagram of an electronic device according to an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.
[0019] The technical solution of the present invention is described in detail below with reference to specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
[0020] Based on the problems existing in the prior art, the present invention provides a method and system for generating an error correction coding constant matrix. The error correction coding constant matrix is constructed by preferentially screening binary codes with smaller Hamming weights. Compared with the traditional sequential coding method, the generated error correction coding constant matrix is more sparse, which can significantly reduce the number of XOR gates in the ECC encoding circuit and the ECC decoding circuit, reduce the logic complexity, and is conducive to optimizing the area and timing performance of the ECC encoding circuit and the ECC decoding circuit.
[0021] ECC encoding typically generates redundant check bits by linearly transforming the input bits using a fixed constant matrix. Each element in this constant matrix determines the connection method of the exclusive-or logic. The Hamming weight of each column in the matrix (i.e., the number of "1s" in that column) directly reflects the number of exclusive-or gates required to connect that bit in the hardware implementation.
[0022] The expression of the error correction coding constant matrix A is as follows:
[0023] Then, the formula for ECC encoding redundancy check code is as follows:
[0024] in, It is the summation method of binary domain, that is, XOR operation; is the corresponding value in the error correction coding constant matrix; For the bit input bit.
[0025] The formula for ECC decoding redundancy check code is as follows:
[0026] in, It is the summation method of binary domain, that is, XOR operation; is the corresponding value in the error correction coding constant matrix; For the bit input bit; Redundancy check code for the i-th ECC code.
[0027] The input bits are decoded and passed through Perform error correction or check on the input bits.
[0028] in, is a sum in the binary domain, so and The value range of is 0 or 1. is a constant, if a certain position ,but , then it means that this item can be ignored in the XOR calculation. ECC encoding circuit and ECC decoding circuit are based on the effective bit, that is, , perform an XOR operation. If the sum of the Hamming weights of all values in the error correction coding constant matrix is S, and the area of an XOR gate is one basic unit, then the area of the EC coding circuit is:
[0029] Where: S is the Hamming weight sum of all values in the error correction coding constant matrix, and n is the number of ECC code bits.
[0030] The area of the ECC decoding circuit is:
[0031] Where: S is the Hamming weight sum of all values in the error correction coding constant matrix.
[0032] The area of the ECC encoding circuit and the ECC decoding circuit is:
[0033] Therefore, the larger the total Hamming weight of the matrix, the more logic gates are required, and the chip area and power consumption also increase accordingly.
[0034] Currently, existing error-correcting coding constant matrix construction methods mostly rely on sequential selection, lacking optimal control over overall logical complexity. Furthermore, the design of error-correcting coding constant matrices varies greatly between manufacturers and systems, and there is no unified optimal construction method. This paper proposes a method and system for generating error-correcting coding constant matrices. This method employs a universal construction strategy based on a Hamming weighted prioritization and grouping selection method, prioritizing the selection of coding vectors with smaller weights from a set of vectors that meet the legal column screening criteria, thereby generating an error-correcting coding constant matrix A with improved sparsity.
[0035] Figure 1 A flow chart of a method for generating an error correction coding constant matrix according to an embodiment of the present invention is provided. Figure 1 , an embodiment of the present invention provides a method for generating an error correction coding constant matrix, comprising: Step S101: setting the number of input bits and the number of redundant bits of error correction coding, wherein the number of input bits is the number of rows of the error correction coding constant matrix, and the number of redundant bits of error correction coding is the number of columns of the error correction coding constant matrix.
[0036] In this embodiment, the number of input bits, m, and the number of redundant bits for error correction coding, n, are first set. The number of rows in the error correction coding constant matrix is equal to the number of input bits, m, and the number of columns in the error correction coding constant matrix is equal to the number of redundant bits for error correction coding, n. The error correction coding constant matrix is then a matrix with m rows and n columns. The input bits after ECC encoding are then:
[0037] Among them, x m The mth input bit, encode[1] the first ECC encoding redundancy check code.
[0038] In this embodiment, the Hamming weight is calculated using a Python function. The Hamming weight is the number of 1s in a code, that is, the number of 1s obtained by traversing the code of n bits once. For example, the Hamming weight of 0b01011 is 3.
[0039] Step S102: Starting from a positive integer 1 and increasing in sequence according to the positive integers with a step size of 1, each of the positive integers is converted into a binary-coded column vector, where the length of the binary-coded column vector is the number of rows. When the number of generated binary-coded column vectors reaches the number of columns, the increment is stopped, and all generated binary-coded column vectors constitute a candidate column vector set.
[0040] In this embodiment, a set of candidate column vectors is constructed using a configuration where the number of input bits is 5 and the number of error correction code redundancy bits is 3. Each binary-coded column vector includes at least one bit that is 1, i.e., each binary-coded column vector is a non-all-zero binary-coded column vector.
[0041] When the number of input bits is set to m=5, the number of columns of the corresponding error correction coding constant matrix is 5. When the number of redundant bits of error correction coding is set to n=3, the number of rows of the corresponding error correction coding constant matrix is 3. According to step S102, starting from the positive integer 1, 1, 2, 3, 4, and 5 are taken in sequence, and each positive integer is converted into a binary code column vector of length 3. The obtained binary code column vectors are shown in Table 1: Table 1 Construction of binary coded column vectors
[0042] The candidate column vector set thus constructed is:
[0043] Step S103: Binary-coded column vectors that meet the legal column screening condition and whose number is equal to the number of columns are selected from the candidate column vector set as legal column vectors.
[0044] In this embodiment, taking the configuration where the number of input bits is 5 and the number of error correction coding redundant bits is 3 as an example, when m=5 and n=3, the constructed candidate column vector set is:
[0045] From the constructed candidate column vector set, the vectors that meet the legal column screening condition are selected as legal column vectors. The legal column screening condition is that the Hamming weight is an odd number and greater than 1. The screening results are shown in Table 2: Table 2 Constructing legal column vectors based on the set number of redundant bits of error correction coding
[0046] Therefore, according to the configuration that the number of input bits is set to 5 and the number of error correction coding redundant bits is set to 3, it is impossible to select a binary coded column vector with 5 error correction coding redundant bits as a legal column vector from the candidate column vector set.
[0047] In this embodiment, during the process of screening legal column vectors from the set of candidate column vectors, if the number of screened legal column vectors is less than the set number of error correction code redundant bits, the number of error correction code redundant bits is automatically increased and updated, and the set of candidate column vectors is regenerated based on the updated number of error correction code redundant bits until the column number requirement for constructing the error correction code constant matrix is met. Legal column vectors are then constructed based on the updated number of error correction code redundant bits n, as shown in Table 3: Table 3. Constructing legal column vectors based on the updated number of redundant bits of error correction coding
[0048] Therefore, the number of redundant bits of the error correction code is automatically increased and updated to 5. The legal column vector reconstructed based on the updated redundant bits of the error correction code is:
[0049] Step S104: weight grouping the legal column vectors according to Hamming weights, dividing the legal column vectors with the same Hamming weight into the same weight group, and arranging all the weight groups in ascending order according to the Hamming weight values.
[0050] In this embodiment, weight grouping involves grouping elements with the same Hamming weight. For example, for x1=0b0001, x2=0b0010, x3=0b0111, and x4=0b1011, their Hamming values are H(x1)=H(x2)=1 and H(x3)=H(x4)=2, respectively. x1 and x2 are grouped into weight group 1 G1, and x3 and x4 are grouped into weight group 2 G2. Groups G1 and G2 are then sorted in ascending order, so that H(G1) < H(G2).
[0051] Step S105: According to the sorted weight grouping order, each legal column vector in each weight group is selected from front to back, one by one, as the column vector of the error correction coding constant matrix, and each bit in each column vector is mapped to the corresponding row of the error correction coding constant matrix in turn, until the number of selected column vectors is equal to the number of columns, thereby completing the construction of the error correction coding constant matrix.
[0052] In this embodiment, the legal column vectors within the same weight group are arranged in a random order.
[0053] Taking weight groups G1 and G2 as an example, after sorting the legal column vectors in ascending order from smallest to largest, the order of x1 and x2 in the same weight group G1 can be randomly arranged, that is, x1, x2, or x2, x1. After sorting, select each position code starting from weight group G1. After selecting weight group G1, select from weight group G2, and so on.
[0054] Compared with the method of arranging the legal column vectors in a random order within the weight group, when the attacker knows the construction rules of the error correction coding constant matrix, he still cannot directly infer the mapping relationship between the input bits and the specific column vectors based on the arrangement position of the error correction coding constant matrix.
[0055] By introducing a random order arrangement mechanism within the weight grouping, the unpredictability of the error correction coding constant matrix can be effectively increased, thereby enhancing the anti-analysis capability against threats such as channel attacks and structural leakage, and improving the security of the overall coding scheme.
[0056] In this embodiment, the generated error correction coding constant matrix is used to configure the XOR gate connection structure in the error correction coding circuit. The generated error correction coding constant matrix is also used to construct the comprehensive value calculation logic of the error correction decoding circuit, and the XOR gate connection structure in the error correction decoding circuit is configured based on the comprehensive value calculation logic.
[0057] The error correction coding constant matrix generation method proposed in the present invention is compared with the error correction coding constant matrix generated by the sequential coding method. The area comparison data of the ECC encoding circuit and the ECC decoding circuit are shown in Table 4: Table 4 Area comparison data of ECC encoding circuit and ECC decoding circuit
[0058] From the comparison results, it can be seen that compared with the traditional sequential coding method, the error correction coding constant matrix generation method proposed in the present invention achieves an optimization of about 22% to 31% in the area of the ECC encoding circuit and the ECC decoding circuit, effectively reducing the consumption of hardware logic resources and improving the timing performance of the ECC encoder and ECC decoder.
[0059] Figure 2 A schematic diagram of a module of an error correction coding constant matrix generation system provided by an embodiment of the present invention. Figure 2 , an embodiment of the present invention provides an error correction coding constant matrix generation system 200, comprising: Parameter setting module 201, setting the number of input bits and the number of error correction code redundant bits, wherein the number of input bits is the number of rows of the error correction code constant matrix, and the number of error correction code redundant bits is the number of columns of the error correction code constant matrix; a candidate column vector set generating module 202, starting from a positive integer 1 and increasing in order of positive integers with a step size of 1, converting each positive integer into a binary-coded column vector, where the length of the binary-coded column vector is the number of rows, stopping the increment when the number of generated binary-coded column vectors reaches the number of columns, and all generated binary-coded column vectors constitute a candidate column vector set; A legal column vector screening module 203 is configured to screen out binary-coded column vectors that meet the legal column screening conditions and whose number is equal to the number of columns from the candidate column vector set as legal column vectors; The weight grouping and sorting module 204 groups the legal column vectors according to Hamming weights, groups the legal column vectors with the same Hamming weights into the same weight group, and sorts all the weight groups in ascending order according to the Hamming weight values; The error correction coding constant matrix construction module 205 selects each legal column vector in each weight group from front to back in accordance with the sorted weight grouping order as the column vector of the error correction coding constant matrix, and maps each bit in each column vector to the corresponding row of the error correction coding constant matrix in turn until the number of selected column vectors equals the number of columns, thereby completing the construction of the error correction coding constant matrix.
[0060] Figure 3 FIG. 1 is a schematic diagram of the structure of an electronic device according to an exemplary embodiment of the present application. Figure 3 As shown, an electronic device 300 provided in this embodiment includes: a processor 301 and a memory 302; wherein: The memory 302 is used to store computer programs. The memory may also be a flash memory.
[0061] The processor 301 is configured to execute the execution instructions stored in the memory to implement each step in the above method. For details, please refer to the relevant description in the above method embodiment.
[0062] Optionally, the memory 302 may be independent or integrated with the processor 301 .
[0063] When the memory 302 is a device independent of the processor 301, the electronic device 300 may further include: The bus 303 is used to connect the memory 302 and the processor 301 .
[0064] This embodiment further provides a readable storage medium, in which a computer program is stored. When at least one processor of an electronic device executes the computer program, the electronic device executes the methods provided in the various aforementioned embodiments.
[0065] This embodiment further provides a program product, which includes a computer program stored in a readable storage medium. At least one processor of an electronic device can read the computer program from the readable storage medium, and at least one processor can execute the computer program to cause the electronic device to implement the methods provided in the various embodiments described above.
[0066] In summary, an embodiment of the present invention provides a method and system for generating an error correction coding constant matrix, the method comprising: setting the number of input bits and the number of error correction coding redundant bits, wherein the number of input bits is the number of rows of the error correction coding constant matrix, and the number of error correction coding redundant bits is the number of columns of the error correction coding constant matrix; starting from a positive integer 1 and increasing in sequence according to the positive integer order, with an increasing step of 1, each of the positive integers is converted into a binary coded column vector, the length of the binary coded column vector being the number of rows, and when the number of generated binary coded column vectors reaches the number of columns, the increment is stopped, and all generated binary coded column vectors constitute a candidate column vector set; screening out the candidate column vectors that meet the requirements from the candidate column vector set. Legal column screening conditions, and binary coded column vectors equal in number to the number of columns, as legal column vectors; weight grouping the legal column vectors according to Hamming weights, dividing the legal column vectors with the same Hamming weights into the same weight group, and arranging all the weight groups in ascending order from small to large according to the Hamming weight values; according to the sorted weight grouping order, selecting each legal column vector in each weight group in turn from front to back as the column vector of the error correction coding constant matrix, and mapping each bit in each column vector to the corresponding row of the error correction coding constant matrix in turn, until the number of selected column vectors is equal to the number of columns, completing the construction of the error correction coding constant matrix. The present invention constructs the error correction coding constant matrix by preferentially screening binary codes with smaller Hamming weights. The generated error correction coding constant matrix is more sparse, can significantly reduce the number of XOR gates in the ECC encoding circuit and the ECC decoding circuit, reduce the logic complexity, and is conducive to optimizing the area and timing performance of the ECC encoding circuit and the ECC decoding circuit; Furthermore, the legal column screening condition is that the Hamming weight is an odd number and greater than 1, which helps to improve the error correction capability of the error correction coding constant matrix, ensuring that the encoded data has stronger error detection and location characteristics, thereby enhancing the overall fault tolerance performance; Furthermore, the legal column vectors within the same weight group are arranged in a random order, which can increase the unpredictability of the error correction coding constant matrix and improve the ability to resist side channel attacks and security while maintaining consistent performance; Furthermore, in the process of screening legal column vectors from the candidate column vector set, if the number of screened legal column vectors is less than the set number of error correction coding redundant bits, the number of error correction coding redundant bits is automatically increased and updated, and the candidate column vector set is regenerated based on the updated number of error correction coding redundant bits until the column number requirement for constructing the error correction coding constant matrix is met. This can avoid the problems of construction failure or parameter conflict, ensure that the error correction coding constant matrix can be successfully generated under different parameter configurations, and enhance its adaptability and stability.
[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for generating an error correction coding constant matrix, characterized in that: include: Setting the number of input bits and the number of redundant bits for error correction coding, wherein the number of input bits is the number of rows of the error correction coding constant matrix, and the number of redundant bits for error correction coding is the number of columns of the error correction coding constant matrix; Starting from a positive integer 1 and increasing in sequence according to the positive integers with a step size of 1, each of the positive integers is converted into a binary coded column vector, where the length of the binary coded column vector is the number of rows, and the increment is stopped when the number of generated binary coded column vectors reaches the number of columns, and all generated binary coded column vectors constitute a candidate column vector set; Filtering out binary-coded column vectors that meet the legal column screening condition and whose number is equal to the number of columns from the candidate column vector set as legal column vectors; The legal column vectors are weighted grouped according to Hamming weights, the legal column vectors with the same Hamming weight are divided into the same weight group, and all the weight groups are arranged in ascending order according to the Hamming weight values; According to the sorted weight grouping order, each legal column vector in each weight group is selected from front to back, one group at a time, as the column vector of the error correction coding constant matrix. Each bit in each column vector is mapped to the corresponding row of the error correction coding constant matrix in turn, until the number of selected column vectors is equal to the number of columns, thereby completing the construction of the error correction coding constant matrix.
2. The method for generating an error correction coding constant matrix according to claim 1, wherein: Each of the binary coded column vectors includes at least one bit that is 1.
3. The method for generating an error correction coding constant matrix according to claim 1, wherein: The legal column screening condition is that the Hamming weight is an odd number and greater than 1.
4. The method for generating an error correction coding constant matrix according to claim 1, wherein: The legal column vectors within the same weight group are arranged in a random order.
5. The method for generating an error correction coding constant matrix according to claim 1, wherein: In the process of screening legal column vectors from the set of candidate column vectors, if the number of screened legal column vectors is less than the set number of error correction coding redundant bits, the number of error correction coding redundant bits is automatically increased and updated, and the set of candidate column vectors is regenerated based on the updated number of error correction coding redundant bits until the column number requirement for constructing the error correction coding constant matrix is met.
6. The method for generating an error correction coding constant matrix according to any one of claims 1 to 5, wherein: The generated error correction coding constant matrix is used to configure the XOR gate connection structure in the error correction coding circuit.
7. The method for generating an error correction coding constant matrix according to any one of claims 1 to 5, wherein: The generated error correction coding constant matrix is also used to construct the comprehensive value calculation logic of the error correction decoding circuit, and the XOR gate connection structure in the error correction decoding circuit is configured based on the comprehensive value calculation logic.
8. A system for generating an error correction coding constant matrix, characterized in that: include: A parameter setting module for setting the number of input bits and the number of redundant bits of the error correction code, wherein the number of input bits is the number of rows of the error correction code constant matrix, and the number of redundant bits of the error correction code is the number of columns of the error correction code constant matrix; a candidate column vector set generating module, starting from a positive integer 1 and increasing in order of positive integers with a step size of 1, converting each of the positive integers into a binary-coded column vector, where the length of the binary-coded column vector is the number of rows, stopping the increment when the number of generated binary-coded column vectors reaches the number of columns, and all generated binary-coded column vectors constitute a candidate column vector set; a legal column vector screening module, screening out binary-coded column vectors that meet the legal column screening conditions and whose number is equal to the number of columns from the candidate column vector set as legal column vectors; A weight grouping and sorting module groups the legal column vectors according to Hamming weights, groups the legal column vectors with the same Hamming weights into the same weight group, and arranges all the weight groups in ascending order according to the Hamming weight values; The error correction coding constant matrix construction module selects each legal column vector in each weight group from front to back in accordance with the sorted weight grouping order as the column vector of the error correction coding constant matrix, and each bit in each column vector is mapped to the corresponding row of the error correction coding constant matrix in turn until the number of selected column vectors equals the number of columns, thereby completing the construction of the error correction coding constant matrix.
9. An electronic device, characterized in that: include: processor; as well as, a memory for storing executable instructions of the processor; The processor is configured to perform the method according to any one of claims 1 to 7 by executing the executable instructions.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.