Bit error rate measurement device and signal detection method

Abstract

The invention provides an error rate measurement device and a signal detection method. This error rate measurement device is provided with: a display unit (40); and an internal signal generation circuit (22) that generates an internal signal comprising a specific code pattern expected to be output from the DUT in accordance with the state of the LTSSM, the error rate measurement device (100) being provided with: a reference signal holding unit (23) that holds a part of the start of the internal signal as a reference signal; a start detection unit (24) that compares the reference signal with an input signal from the DUT and detects the start of a specific code pattern in the input signal; a detection signal output unit (25) that outputs a detection signal synchronized with the timing at which the start of the specific code pattern is detected by the start detection unit (24); a latch unit (26) that holds the detection signal; and a control unit (42) that displays, on a display unit, a detection notification image indicating that the start of the specific code pattern has been detected by the start detection unit (24) while the detection signal is held by the latch unit (26).

Description

Technical Field

[0001] The present invention relates to a bit error rate measurement device and a signal detection method, and in particular to a bit error rate measurement device and a signal detection method for detecting the start of a code type of an input signal. Background Art

[0002] Protocols such as PCIe (registered trademark) and USB (registered trademark) require control of the Link Training and Status State Machine (LTSSM) and the execution of sequential operations to switch device states. By sending multiple, predetermined data patterns (hereafter referred to as "sequence blocks") to a device in the correct order, the device state can be changed arbitrarily.

[0003] For example, PCIe has standards ranging from Gen1 to Gen6, with communication speeds varying from 2.4 GT / s to 32 GT / s for each standard. PCIe devices are backward compatible and can switch communication speeds. State switching also enables this communication speed switching.

[0004] For example, in PCIe, the state transition diagram of LTSSM is as follows: Figure 6 As shown in the figure, L0, L0s, L1, L2, Detect, Polling, Configuration, Disabled, Hot Reset, Loopback, and Recovery are defined as states.

[0005] During device development testing, manufacturers of PCIe or USB devices, as well as those who develop these controllers, need to confirm that the devices can correctly transmit and receive sequence blocks. This verification is typically performed using, for example, a logic analyzer or protocol analyzer. However, these measurement devices often lack real-time performance and are unable to simultaneously acquire and analyze data. Furthermore, sequence blocks contain patterns with very long periods, which can sometimes take time to analyze using these measurement devices.

[0006] As a measurement device capable of simultaneously acquiring and analyzing data in real time, a bit error rate measurement device is known (for example, see Patent Document 1).

[0007] Patent Document 1: Japanese Patent No. 7132964

[0008] Device manufacturers need to confirm whether the developed device performs the correct state transition according to the sequence block input. The data output from the device is fixed according to the state, so by judging the data output from the device, the status of the device can be understood.

[0009] However, conventional bit error rate measurement devices can measure the bit error rate of continuous data, but do not have a structure capable of detecting instantaneous data of approximately 1 ms and notifying the user of the detection.

[0010] A bit error rate measurement device doesn't measure the bit error rate unless it detects data. This allows users to identify detected data based on whether or not the bit error rate has been measured. However, the graphical user interface (GUI) update cycle of existing bit error rate measurement devices is approximately 100 milliseconds, which poses a problem: users cannot visually identify data detection unless the data is several hundred milliseconds long. Furthermore, even for data of several hundred milliseconds or longer, if the sequence continues for a long time, it is impractical for users to confirm when the display for several hundred milliseconds has occurred. Summary of the Invention

[0011] The present invention has been made to solve such conventional problems, and its object is to provide a bit error rate measurement device and a signal detection method that can detect a specific code pattern such as a sequence block in real time and notify the user.

[0012] To solve the above-mentioned problems, the bit error rate measurement device according to the present invention has the following structure, namely, it includes: a display unit 40; and an internal signal generation circuit 22, which generates an internal signal composed of a specific code pattern expected to be output from the device under test 200 according to the status of a link status management mechanism, and the bit error rate measurement device 100 that measures the bit error rate of the input signal from the device under test includes: a reference signal holding unit 23, which holds a starting portion of the internal signal as a reference signal; a start detection unit 24, which compares the reference signal with the input signal and detects the start of the specific code pattern in the input signal; a detection signal output unit 25, which outputs a detection signal synchronized with the timing of detection of the start of the specific code pattern by the start detection unit; a latch unit 26, which holds the detection signal; and a control unit 42, which displays a detection notification image 61 on the display unit, indicating that the start of the specific code pattern has been detected by the start detection unit, while the detection signal is held by the latch unit.

[0013] With this configuration, the bit error rate measurement device according to the present invention detects the start of a specific code pattern, such as a sequence block, in the input signal, and displays the detection of the specific code pattern on the display unit. This allows the bit error rate measurement device according to the present invention to detect specific code patterns, such as sequence blocks, in real time and notify the user.

[0014] That is, the present invention has a structure in which a detection function for sequence blocks such as PCIe or USB is added to a bit error rate measurement device capable of measuring bit error rates in real time. Therefore, the user can instantly confirm the existence of a specific sequence block without the time required for analysis, thereby improving usability.

[0015] Furthermore, the bit error rate measurement device according to the present invention may be configured such that the display unit further displays a hold release instruction unit 62 for releasing the latch unit from holding the detection signal.

[0016] According to this configuration, the bit error rate measurement device according to the present invention can restart detection of a specific code pattern by releasing the latch portion from holding the detection signal when the user operates the hold release instruction portion.

[0017] Furthermore, the bit error rate measurement device involved in the present invention may be configured as follows, that is, further comprising: a delay circuit 27 for delaying the input signal in which the start of the specific code type is detected by the start detection unit, so that the internal signal output from the internal signal generation circuit is synchronized with the specific code type in the input signal; and a bit error rate measurement unit 28 for measuring the bit error rate of the specific code type in the input signal by sequentially comparing the internal signal output from the internal signal generation circuit with the input signal output from the delay circuit, wherein the internal signal generation circuit generates the internal signal triggered by the detection signal.

[0018] With this configuration, the bit error rate measurement device according to the present invention can measure the bit error rate of the specific code pattern in the input signal by synchronizing the internal signal output from the internal signal generation circuit with the specific code pattern in the input signal.

[0019] Furthermore, the bit error rate measurement apparatus according to the present invention may be configured to further include a pulse pattern generator 21 that transmits a sequence block for causing the link state management unit to transition to an arbitrary state to the device under test.

[0020] With this configuration, the bit error rate measurement device according to the present invention includes a pulse pattern generator, enabling a single device to both send a sequence block for bit error rate measurement and verify its operation. Consequently, the bit error rate measurement device according to the present invention can reduce the time and cost required for the bit error rate measurement test process, thereby improving the efficiency of the test process.

[0021] Furthermore, the signal detection method according to the present invention is configured as follows, namely, to be executed by a bit error rate measurement device 100, the signal detection method comprising: an internal signal generating step (S3) of generating an internal signal composed of a specific code pattern expected to be output from the device under test 200 according to the state of a link state management mechanism, the signal detection method comprising: a reference signal holding step (S4) of holding a portion of the start of the internal signal as a reference signal; a start detection step (S6) of comparing the reference signal with the input signal and detecting the start of the specific code pattern in the input signal; a detection signal output step (S7) of outputting a detection signal synchronized with the timing at which the start of the specific code pattern is detected by the start detection step; a latching step (S8) of holding the detection signal by a latch unit 26; and a displaying step (S9) of displaying a detection notification image 61 indicating that the start of the specific code pattern has been detected by the start detection step while the detection signal is held by the latch unit.

[0022] Furthermore, the signal detection method according to the present invention may be configured such that the display step further displays a hold release instruction section 62 for releasing the latch section from holding the detection signal.

[0023] Furthermore, the signal detection method involved in the present invention may be structured as follows, namely, the input signal in which the start of the specific code type is detected by the start detection step is delayed, and the internal signal output in the internal signal generation step is synchronized with the specific code type in the input signal, and the bit error rate of the specific code type in the input signal is measured by sequentially comparing the internal signal output in the internal signal generation step with the input signal, and the internal signal generation step generates the internal signal triggered by the detection signal.

[0024] Furthermore, the signal detection method according to the present invention may be configured such that a sequence block for causing the link state management unit to transition to an arbitrary state is transmitted to the device under test.

[0025] Furthermore, the signal detection method according to the present invention may be configured such that a sequence block for causing the link state management unit to transition to an arbitrary state is transmitted to the device under test.

[0026] Effects of the Invention

[0027] The present invention provides a bit error rate measurement device and a signal detection method capable of detecting specific code patterns such as sequence blocks in real time and notifying the user. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1This is a block diagram showing the configuration of a bit error rate measurement device according to an embodiment of the present invention.

[0029] Figure 2 This is a block diagram showing the functional configuration of an FPGA included in the bit error rate measurement device according to the embodiment of the present invention.

[0030] Figure 3 This is a diagram showing an example of a result display screen displayed on a display unit included in the bit error rate measurement device according to the embodiment of the present invention.

[0031] Figure 4 This is a diagram showing an example of a code type setting screen displayed on a display unit included in the bit error rate measurement device according to the embodiment of the present invention.

[0032] Figure 5 This is a flowchart showing the processing of a signal detection method using the bit error rate measurement device according to the embodiment of the present invention.

[0033] Figure 6 This is a diagram showing the state transition of LTSSM. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of a bit error rate measurement device and a signal detection method according to the present invention will be described with reference to the accompanying drawings.

[0035] like Figure 1 As shown, the bit error rate measurement device 100 according to this embodiment measures the bit error rate of an input signal from a device under test (DUT) 200 , and includes a signal processing unit 10 , an FPGA 20 , a data storage unit 30 , a display unit 40 , an operation unit 41 , and a control unit 42 .

[0036] The control unit 42 is composed of a control device such as a computer including a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), an HDD (Hard Disk Drive), etc., and controls the display unit 40 and the operation unit 41 and controls the FPGA 20 through the control software 43.

[0037] The control unit 42 is also equipped with firmware 44 for mediating between the FPGA 20 and the control software 43. The control software 43 includes a GUI and processes input from the user in the operation unit 41 and displays information to the user in the display unit 40.

[0038] The display unit 40 is composed of a display device such as an LCD (Liquid Crystal Display) that displays various display screens, a GUI such as soft keys, and the like.

[0039] The operation unit 41 is used to receive operation inputs from the user and is composed of a user interface such as an operation knob, various keys, switches, buttons, or a touch panel, mouse, or keyboard provided on the main body of the bit error rate measurement device 100 for operating the GUI of the display unit 40 .

[0040] The DUT 200 is equipped with an LTSSM and in the LTSSM transition to, for example, Figure 6 In each of the states shown, a data pattern, such as a sequence block, corresponding to that state is output as an input signal to bit error rate measurement device 100. For example, when DUT 200 transitions to the loopback state ("LOOPBACK_ACTIVE_MASTER"), it outputs (loops back) the output signal from pulse pattern generator (PPG) 21 (described later) as an input signal to bit error rate measurement device 100. Examples of standards supported by DUT 200 include PCIe Gen 1 to 6 and USB 1.0 to 4.

[0041] The signal processing section 10 converts an input signal from the DUT 200 from an analog signal to a digital signal, and converts an output signal from the FPGA 20 from a digital signal to an analog signal.

[0042] The data storage unit 30 is composed of a memory such as RAM, and stores a specific pattern expected to be output from the DUT 200 when the LTSSM of the DUT 200 transitions to a certain state. The data storage unit 30 stores the specific pattern in advance in file units.

[0043] The specific pattern is, for example, a sequence block that controls state transitions between a plurality of states managed by the LTSSM of the DUT 200. The data storage unit 30 stores in advance, in file units, known sequence blocks output when the DUT 200 transitions to each state.

[0044] For example, if the standard is PCIe Gen5 and the status of DUT 200 is "LOOPBACK_ENTRY_MASTER_TS1", the sequence block output from DUT 200 is recorded in a file named "PCIe5_LOOPBACK_ENTRY_MASTER_TS1". The naming method of the file name is not limited to the above, and any name that allows the user to easily understand the combination of the specification and status can be used.

[0045] Alternatively, the specific pattern may be a PRBS (Pseudo Random Binary Sequence) pattern or an arbitrary data pattern set by a user.

[0046] For example, when the state of the DUT 200 is "LOOPBACK_ACTIVE_MASTER", the data storage unit 30 may store information on a file basis for causing the PPG 21 and the internal signal generation circuit 22 described later to generate a known pattern such as a PRBS pattern or an arbitrary data pattern set by the user.

[0047] like Figure 2 As shown, the FPGA 20 includes a PPG 21 , an internal signal generating circuit 22 , a reference signal holding unit 23 , a start detecting unit 24 , a detection signal output unit 25 , a latch unit 26 , a delay circuit 27 , and a bit error rate measuring unit 28 .

[0048] The PPG 21 transmits a sequence block for transitioning the LTSSM of the DUT 200 to a desired state as an output signal to the DUT 200. Furthermore, when the state of the DUT 200 is "LOOPBACK_ACTIVE_MASTER," the PPG 21 reads data of a specific pattern stored in the data storage unit 30 from the data storage unit 30, performs appropriate encoding processing, etc. on the read data of the specific pattern, generates a test signal composed of repetitions of the specific pattern, and transmits the test signal as an output signal to the DUT 200. The specific pattern read from the data storage unit 30 by the PPG 21 is set using the pattern setting screen 70 described later.

[0049] The internal signal generation circuit 22 is a circuit that reads data of a specific pattern expected to be output from the DUT 200 based on the state of the LTSSM of the DUT 200 from the data storage unit 30, performs encoding processing, etc. as appropriate on the read data of the specific pattern, and generates an internal signal composed of repetitions of the specific pattern. The specific pattern read from the data storage unit 30 by the internal signal generation circuit 22 is set using the pattern setting screen 70 described later.

[0050] The internal signal generating circuit 22 generates an internal signal using a detection signal output from a detection signal output section 25 described later as a trigger, and outputs the generated internal signal to a subsequent bit error rate measuring section 28 .

[0051] When the state of the DUT 200 is “LOOPBACK_ACTIVE_MASTER”, the control unit 42 performs control to cause the PPG 21 and the internal signal generation circuit 22 to generate the same specific pattern.

[0052] The reference signal storage unit 23 stores a portion of the beginning of an internal signal composed of a specific pattern set on a pattern setting screen 70 described later, for example, several tens of bits at the beginning of the specific pattern, as a reference signal.

[0053] The start detection unit 24 compares the reference signal held by the reference signal holding unit 23 with the input signal from the DUT 200 that has been signal-processed by the signal processing unit 10 , and detects the start of a specific pattern in the input signal.

[0054] The detection signal output unit 25 outputs a detection signal synchronized with the timing at which the start detection unit 24 detects the start of the specific pattern to the internal signal generation circuit 22. Furthermore, the detection signal output unit 25 outputs the pattern of the input signal at which the start detection unit 24 detects the start of the specific pattern to the delay circuit 27.

[0055] Latch unit 26 holds the detection signal output from detection signal output unit 25. Furthermore, if the bit error rate measured by bit error rate measurement unit 28 (described later) exceeds a predetermined value, latch unit 26 releases the held detection signal. This is because data identical to the beginning of the specific pattern may be contained in a portion of the input signal that differs from the specific pattern. In this case, subsequent bits of the input signal will not match the specific pattern, resulting in a high bit error rate.

[0056] Furthermore, when the "History Reset" button 62 is pressed on the result display screen 60 described later, the latch unit 26 also releases the detection signal held. After the detection signal held by the latch unit 26 is released, the start detector 24 again detects the start of the specific code pattern included in the input signal.

[0057] The delay circuit 27 delays the input signal in which the start of the specific pattern is detected by the start detection unit 24 , thereby synchronizing the internal signal output from the internal signal generation circuit 22 with the specific pattern in the input signal.

[0058] That is, the internal signal generation circuit 22 generates an internal signal triggered by the detection signal, and the delay circuit 27 delays the input signal in which the start of a specific pattern is detected, thereby outputting an internal signal synchronized with the input signal to the subsequent bit error rate measurement unit 28.

[0059] The bit error rate measurement unit 28 measures the bit error rate of a specific pattern in the input signal by sequentially comparing the internal signal output from the internal signal generation circuit 22 with the input signal output from the delay circuit 27. When the input signal is an NRZ (Non Return to Zero) signal, the bit error rate in this embodiment is the bit error rate (BER). When the input signal is a PAM4 (Pulse Amplitude Modulation 4) signal, the symbol error rate (SER) is used.

[0060] Figure 3 The result display screen 60 displayed on the display unit 40 is shown when the “Result” tab 51 a is pressed by the operation unit 41 in the screen selection tabs 51 on the main display screen 50 displayed on the display unit 40 .

[0061] The result display screen 60 includes a “SyncGain (synchronous channel gain)” image 61 , a “History Reset” button 62 , and a text box 63 .

[0062] The “SyncGain” image (hereinafter also referred to as “detection notification image”) 61 on the result display screen 60 is an image simulating an LED.

[0063] When the start of a specific code pattern set on the code pattern setting screen 70 (described later) is detected continuously for the number of detections set in the text box 63, the detection notification image 61 changes from a black off state to a green lit state. Here, the text box 63 is used to set the number of detections required for the detection notification image 61 to change from an off state to a lit state, and is located, for example, near the detection notification image 61 on the result display screen 60.

[0064] When the "History Reset" button 62 is pressed through the operation unit 41, the detection notification image 61 turns black and turns off, and the detection signal held by the latch unit 26 is released. The "History Reset" button 62 constitutes a hold release instruction unit for releasing the latch unit 26 from holding the detection signal.

[0065] That is, while the detection signal is being held by the latch unit 26, the detection notification image 61 is lit green to indicate that the start detection unit 24 has detected the start of the specific pattern. The colors of the detection notification image 61 are not limited to the black and green colors described above, and may be any combination of colors.

[0066] Furthermore, the latch unit 26 can release the detection signal from being held not only by pressing the "History Reset" button 62 on the operation unit 41 but also by remote control from an external control device.

[0067] Furthermore, the result display screen 60 may include a text box 64 indicating the number of detections near the detection notification image 61 . The number of detections indicates how many times the detection signal has been continuously detected by the latch unit 26 .

[0068] Furthermore, while the detection signal is being held by latch unit 26, if the bit error rate of the specific pattern measured by bit error rate measurement unit 28 falls below a predetermined bit error rate, detection notification image 61 can be changed from its black, off state to its green, lit state. This has the advantage of improving the reliability of detecting the specific pattern. Therefore, result display screen 60 may include a text box 65 for setting the predetermined bit error rate at which detection notification image 61 turns green.

[0069] In addition, depending on the bit error rate set in the text box 65, it may take more than 1 ms from the time the detection signal is held by the latch unit 26 to the time the notification image 61 is detected to be lit green (for example, to ensure that the bit error rate is 1E-9 or less, at least 1E9 bits of data are required).

[0070] In practice, the bit error rate measurement device 100 according to this embodiment detects sequence blocks of, for example, 1 ms or longer. However, synchronization by delay circuit 27 is completed within tens to hundreds of μs (less than 1 ms) from the time the input signal from DUT 200 is received. This represents the delay time from the time the input signal is received until synchronization. However, since the final notification method to the user is displayed on the GUI of display unit 40, the actual update cycle of the GUI of display unit 40 represents the final delay time.

[0071] Figure 4 The pattern setting screen 70 is shown, which is displayed when the “Pattern” tab 51 b is pressed through the operation unit 41 in the screen selection tab 51 on the main display screen 50 of the display unit 40 .

[0072] The pattern setting screen 70 is a screen for setting a specific pattern, and includes a “Test Pattern” pull-down menu 71 , an edit button 72 , and an “Edit File Name” tab 73 .

[0073] The pull-down menu 71 of “Test Pattern” allows selection of, for example, a sequence block, a PRBS pattern, an arbitrary data pattern, etc. as a specific pattern through the operation unit 41 . Figure 4The state in which "HSSB Data" indicating data of a sequence block is selected is shown.

[0074] Edit button 72 is used to select a file containing a specific test pattern selected from "Test Pattern" drop-down menu 71 from among the multiple files stored in data storage unit 30. Pressing edit button 72 via operation unit 41 opens another screen (not shown) where files can be read, saved, and edited bit by bit.

[0075] The “Edit File Name” label 73 displays the file name of the file designated by the edit button 72 among the plurality of files stored in the data storage unit 30 . That is, the specific pattern recorded in the file displayed here is set in the PPG 21 and the internal signal generation circuit 22 . Figure 4 A state in which the file name “PCIe5_LOOPBACK_ENTRY_MASTER_TS1” is displayed is shown.

[0076] like Figure 3 and Figure 4 As shown, the main display screen 50 has a measurement start button 53 for designating the start of measurement and a measurement stop button 54 for designating the stop of measurement.

[0077] When the measurement start button 53 is pressed via the operation unit 41, the PPG 21 sequentially outputs sequence blocks that control the state transition of the DUT 200 to the DUT 200. Then, when the DUT 200 sequentially performs state transitions and outputs a specific pattern recorded in the file displayed on the "Edit File Name" tab 73, the start detection unit 24 detects the start of the specific pattern, and the detection signal output unit 25 outputs a detection signal.

[0078] For example, Figure 4 As shown, when "HSSB Data" is selected in the drop-down menu 71 of "Test Pattern" and "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" is specified in the label 73 of "Edit File Name", if DUT200 reaches the "LOOPBACK_ENTRY_MASTER_TS1" state of PCIe Gen5 and outputs a sequence block of this state, the start detection unit 24 detects the start of the sequence block, and the detection signal output unit 25 outputs a detection signal.

[0079] The following is a description of the signal detection method using the bit error rate measurement apparatus 100 of this embodiment. Figure 5An example of the processing will be described with reference to the flowchart of FIG. Note that any description overlapping with the description of the configuration of the bit error rate measurement apparatus 100 described above will be omitted as appropriate.

[0080] First, the control unit 42 displays the main display screen 50 on the display unit 40 (step S1 ).

[0081] Next, the user selects, for example, a file named “PCIe5_LOOPBACK_ENTRY_MASTER_TS1” on the pattern setting screen 70 via the operation unit 41 , thereby setting a specific pattern to be detected (step S2 ).

[0082] Next, when the user presses the measurement start button 53 via the operation unit 41 , the internal signal generation circuit 22 generates an internal signal composed of a sequence block, which is a specific pattern recorded in the file “PCIe5_LOOPBACK_ENTRY_MASTER_TS1” (internal signal generation step S3 ).

[0083] Next, the reference signal storage unit 23 stores a portion of the beginning of the sequence block recorded in the file “PCIe5_LOOPBACK_ENTRY_MASTER_TS1” as a reference signal (reference signal storage step S4 ).

[0084] Next, the PPG 21 sequentially sends sequence blocks for controlling state transitions to the DUT 200 (step S5 ).

[0085] Next, if the start detection unit 24 compares the reference signal with the input signal from the DUT 200 and detects the start of the sequence block recorded in the file "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" in the input signal (start detection step S6: "Yes"), the detection signal output unit 25 outputs a detection signal synchronized with the timing at which the start of the sequence block is detected in the start detection step S6 to the internal signal generation circuit 22 (detection signal output step S7).

[0086] Next, the latch unit 26 holds the detection signal output from the detection signal output unit 25 (latching step S8 ).

[0087] Next, while the latch unit 26 holds the detection signal, the display unit 40 changes the detection notification icon 61 from off to on on the result display screen 60 to indicate that the start of the specific pattern has been detected in the start detection step S6 (display step S9 ).

[0088] Next, when the user presses the “History Reset” button 62 via the operation unit 41 (step S10 : Yes), the latch unit 26 releases the holding of the detection signal (step S11 ).

[0089] Next, the display unit 40 changes the detection notification image 61 on the result display screen 60 from the lit state to the unlit state (step S12 ).

[0090] Next, if the user presses the measurement stop button 54 via the operation unit 41 (step S13: "Yes"), the process of this flowchart ends. On the other hand, if the user does not press the measurement stop button 54 via the operation unit 41 (step S13: "No"), the process from step S6 onward is executed again.

[0091] As described above, when the bit error rate measurement device 100 according to this embodiment detects the start of a specific code pattern, such as a sequence block, in the input signal, the detection of the specific code pattern is displayed on the display unit 40. Thus, the bit error rate measurement device 100 according to this embodiment can detect a specific code pattern, such as a sequence block, in real time and notify the user.

[0092] That is, the present invention has a structure in which a detection function for sequence blocks such as PCIe or USB is added to a bit error rate measurement device capable of measuring bit error rates in real time. Therefore, the user can instantly confirm the existence of a specific sequence block without the time required for analysis, thereby improving usability.

[0093] Furthermore, the bit error rate measurement device 100 according to this embodiment releases the latch unit 26 from holding the detection signal when the user presses the "History Reset" button 62 as the hold release instruction unit, thereby restarting the detection of a specific pattern.

[0094] Furthermore, the bit error rate measurement device 100 according to this embodiment can measure the bit error rate of the specific code pattern in the input signal by synchronizing the internal signal output from the internal signal generation circuit 22 with the specific code pattern in the input signal.

[0095] Furthermore, the bit error rate measurement apparatus 100 according to this embodiment includes the pulse pattern generator 21, thereby enabling the transmission of sequence blocks used for bit error rate measurement and verification of operation to be performed using a single device. Consequently, the bit error rate measurement apparatus 100 according to this embodiment can reduce the time and cost required for the test process related to bit error rate measurement, thereby improving the efficiency of the test process.

[0096] Explanation of symbols

[0097] 20-FPGA, 21-PPG, 22-Internal signal generation circuit, 23-Reference signal holding unit, 24-Start detection unit, 25-Detection signal output unit, 26-Latch unit, 27-Delay circuit, 28-Bit error rate measurement unit, 30-Data storage unit, 40-Display unit, 41-Operation unit, 42-Control unit, 43-Control software, 44-Firmware, 50-Main display screen, 60-Result display screen, 61-Detection notification image, 62-Button, 63-65-Text boxes, 70-Code pattern setting screen, 71-Pull-down menu, 72-Edit button, 73-Label, 100-Bit error rate measurement device, 200-DUT

Claims

1. A bit error rate measurement device comprising: Display unit (40); and An internal signal generating circuit (22) generates an internal signal composed of a specific code pattern expected to be output from a device under test (200) according to the state of a link state management mechanism, and a bit error rate measurement device (100) for measuring the bit error rate of an input signal from the device under test is characterized in that: have: A reference signal holding unit (23) holds a starting portion of the internal signal as a reference signal; a start detection unit (24) for comparing the reference signal with the input signal and detecting the start of the specific code pattern in the input signal; a detection signal output unit (25) for outputting a detection signal synchronized with the timing at which the start of the specific code pattern is detected by the start detection unit; a latch unit (26) for holding the detection signal; and The control unit (42) displays a detection notification image (61) indicating that the start of the specific code pattern has been detected by the start detection unit on the display unit while the detection signal is held by the latch unit.

2. The bit error rate measurement device according to claim 1, characterized in that The display unit further displays a hold release instruction unit (62) for releasing the latch unit from holding the detection signal.

3. The bit error rate measurement device according to claim 1, wherein: Also features: a delay circuit (27) for delaying the input signal in which the start of the specific code pattern is detected by the start detection unit, so as to synchronize the internal signal output from the internal signal generation circuit with the specific code pattern in the input signal; and A bit error rate measuring unit (28) measures a bit error rate of the specific code pattern in the input signal by sequentially comparing the internal signal output from the internal signal generating circuit with the input signal output from the delay circuit. The internal signal generating circuit generates the internal signal using the detection signal as a trigger.

4. The bit error rate measurement device according to claim 1, wherein: Also features: A pulse pattern generator (21) sends a sequence block for causing the link state management mechanism to transition to an arbitrary state to the device under test.

5. The bit error rate measurement device according to claim 2, characterized in that: Also features: A pulse pattern generator (21) sends a sequence block for causing the link state management mechanism to transition to an arbitrary state to the device under test.

6. A signal detection method, which is performed by a bit error rate measurement device (100), the signal detection method comprising: An internal signal generating step (S3) generates an internal signal composed of a specific code pattern expected to be output from the object under test (200) according to the state of the link state management mechanism. The signal detection method is characterized by comprising: a reference signal holding step (S4), holding a starting portion of the internal signal as a reference signal; a start detection step (S6), comparing the reference signal with the input signal, and detecting the start of the specific code pattern in the input signal; a detection signal outputting step (S7) of outputting a detection signal synchronized with the timing at which the start of the specific code pattern is detected in the start detecting step; a latching step (S8), holding the detection signal by a latching unit (26); and A display step (S9) displays a detection notification image (61) indicating that the start of the specific code pattern has been detected by the start detection step while the detection signal is held by the latch unit.

7. The signal detection method according to claim 6, characterized in that: The display step further displays a hold release indication unit (62) for releasing the latch unit from holding the detection signal.

8. The signal detection method according to claim 6, wherein: delaying the input signal in which the start of the specific code pattern is detected in the start detection step, and synchronizing the internal signal output in the internal signal generation step with the specific code pattern in the input signal, By sequentially comparing the internal signal output in the internal signal generating step with the input signal, a bit error rate of the specific code pattern in the input signal is measured, The internal signal generating step generates the internal signal using the detection signal as a trigger.

9. The signal detection method according to claim 6, wherein: A sequence block for causing the link state management mechanism to transition to an arbitrary state is sent to the device under test.

10. The signal detection method according to claim 7, wherein: A sequence block for causing the link state management mechanism to transition to an arbitrary state is sent to the device under test.

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