Hybrid serial receiver circuit

Abstract

The invention relates to a hybrid serial receiver circuit. Hybrid receiver circuits included in a computer system may include both analog and ADC-based receiver circuits. The front-end circuit generates different equalized signals based on a received signal encoding a serial data stream comprising a plurality of data symbols. Depending on the Baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide desired performance and power consumption over a possible Baud rate range. The ADC-based receiver circuit may include a plurality of analog-to-digital converter circuits having different resolutions that may be selected for different baud rates.

Description

[0001] This application is a divisional application of the invention patent application with an international application date of September 6, 2022, a national application number of 202280064123.4 (international application number PCT / US2022 / 042619), and an invention name of “Hybrid Serial Receiver Circuit”. Technical Field

[0002] The present disclosure relates to the field of high-speed communication interface design, and more particularly to the use of hybrid analog / analog-to-digital converter (ADC) based receiver circuits. Background Art

[0003] Computing systems often include multiple interconnected integrated circuits. In some cases, the integrated circuits may communicate by transmitting and receiving data bits using communication channels or links. Communication channels can support parallel communication, where multiple data bits are transmitted in parallel, or serial communication, where data bits are transmitted one at a time in a serial manner.

[0004] Data transmitted between integrated circuits can be encoded to aid transmission. For example, in the case of serial communication, the data can be encoded to provide transitions between logic states sufficient to allow clock and data recovery circuitry to operate. Alternatively, in the case of parallel communication, the data can be encoded to reduce switching noise or improve signal integrity.

[0005] During data transmission, the physical characteristics of the communication channel may attenuate the transmitted signal associated with a particular data bit. For example, the impedance of the wiring included in the communication channel or link may attenuate certain frequency ranges of the transmitted signal. In addition, impedance mismatches between the wiring included in the communication channel and devices coupled to the communication channel may cause reflections of the transmitted signal, which may degrade subsequent transmitted signals corresponding to other data bits. Summary of the Invention

[0006] Various embodiments for processing a serial data stream are disclosed. Broadly speaking, a hybrid receiver circuit includes a front-end circuit, an ADC-based receiver circuit, an analog receiver circuit, and a clock circuit. The front-end circuit can be configured to generate an equalized signal using at least one signal that encodes a serial data stream including a plurality of data symbols. The ADC-based receiver circuit can include at least one analog-to-digital converter circuit and can be configured to generate a first plurality of recovered data symbols based on the baud rate of the serial data stream using a first equalized signal and a plurality of first clock signals. The analog receiver circuit can be configured to generate a second plurality of recovered data symbols based on the baud rate of the serial data stream using a second equalized signal and a plurality of second clock signals. The clock circuit can be configured to generate a plurality of first clock signals using first control information determined during the generation of the first plurality of recovered data symbols, and to generate a plurality of second clock signals using second control information determined during the generation of the second plurality of recovered data symbols. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of an embodiment of a hybrid receiver circuit for a computer system.

[0008] Figure 2 is a block diagram of an implementation of an analog front-end circuit.

[0009] Figure 3 is a block diagram of an embodiment of an ADC-based receiver circuit for a hybrid receiver circuit.

[0010] Figure 4 is a block diagram of an embodiment of an analog receiver circuit for a hybrid receiver circuit.

[0011] Figure 5 is a block diagram of an embodiment of a sampling circuit for an ADC-based receiver circuit.

[0012] Figure 6 is a block diagram of an embodiment of a clock circuit for a hybrid receiver circuit.

[0013] Figure 7 is a block diagram of a computer system that includes transmitter circuitry and receiver circuitry.

[0014] Figure 8 is a flow chart of an embodiment of a method for operating a hybrid receiver circuit.

[0015] Figure 9 is a block diagram of one embodiment of a system on a chip that includes a receiver circuit.

[0016] Figure 10 is a block diagram of various embodiments of a computer system that may include a receiver circuit.

[0017] Figure 11 An example of a non-transitory computer-readable storage medium storing circuit design information is shown. DETAILED DESCRIPTION

[0018] A computing system may include one or more integrated circuits, such as, for example, a central processing unit (CPU) and memory. Each of the integrated circuits in the computing system may communicate via a serial or parallel interface. In a parallel interface, multiple data bits are transmitted simultaneously, while in a serial interface, data is transmitted as a series of sequential single data bits. When a serial interface is used to transmit data between two devices included in the computing system, the data may be transmitted according to various protocols. For example, data may be transmitted using return-to-zero (RZ), non-return-to-zero (NRZ), pulse amplitude modulation (PAM), or any suitable combination thereof.

[0019] Serial data streams are often transmitted without an accompanying clock signal. In this case, a clock signal is recovered from the serial data stream (in a process known as "clock recovery") and used to sample the serial data stream to determine the values ​​of the included data symbols (in a process known as "data recovery"). Various techniques can be employed to recover both the data and clock signals. For example, a receiver circuit can generate a clock signal with a frequency approximately the same as the frequency of the clock signal used to create the data stream. A phase-locked loop circuit can then be used to phase-align the clock signal with the transitions in the serial data stream. Alternatively, the serial data stream can be oversampled, i.e., sampled at a higher frequency than the frequency of the clock signal used to generate the serial data stream.

[0020] Receiver circuits for serial data streams can be analog based, or they can employ analog-to-digital converter (ADC) circuits. ADC-based receiver circuits convert an equalized version of the input data signal into bits in the digital domain, allowing additional processing (e.g., feed-forward equalization) to be performed as digital signal processing operations.

[0021] In the new interconnection standard, the receiver circuit is required to support a wide range of baud rates. As used and defined herein, the baud rate (or "symbol rate") is the rate at which information is transmitted via a communication channel. For example, in PCIE, the data rate can vary from 2.5Gbaudps to 32Gbaudps. At the lower end of such a range, analog-based receiving circuits can provide a power-efficient solution for sampling signals transmitted along the communication channel. However, as the baud rate of the signal increases, the analog-based receiver circuit may not provide the performance required to consistently recover the data. At high baud rates, ADC-based receiver circuits can provide the performance required to sample the signal, but are power-inefficient at lower baud rates. No single receiver circuit topology covers the required data rate range without sacrificing performance or power.

[0022] The embodiments shown in the accompanying drawings and described below may provide a technique for sampling a signal encoding a serial data stream using a hybrid receiver circuit comprising both an analog-based receiver circuit and an ADC-based receiver circuit. Under certain conditions (e.g., a low baud rate, a low-loss communication channel, etc.), the analog-based receiver circuit may be enabled to sample the signal in a power-efficient manner. In response to a change in conditions (e.g., an increase in the baud rate of the received data stream), the analog-based receiver circuit may be disabled and the ADC-based receiver circuit enabled to provide the desired performance under the new conditions.

[0023] Figure 1 A block diagram depicting an embodiment of a hybrid receiver circuit is depicted in As shown, the hybrid receiver circuit 100 includes a front-end circuit 101 , an ADC-based receiver circuit 102 , an analog receiver circuit 103 , a clock circuit 104 , and a multiplexing circuit 105 .

[0024] Front-end circuit 101 is configured to generate equalized signal 108 using signal 106. In various implementations, signal 106 encodes a serial data stream including data symbols 107. Although front-end circuit 101 is depicted as generating a single equalized signal for use by both ADC-based receiver circuit 102 and analog receiver circuit 103, in other implementations, front-end circuit 101 can be configured to generate a different equalized signal for each of ADC-based receiver circuit 102 and analog receiver circuit 103.

[0025] In some embodiments, signal 106 may encode data symbols 107 according to one of a variety of symbol encodings. For example, signal 106 may be transmitted according to RZ, NRZ, PAM3, or any other suitable symbol encoding. Note that while a single signal is depicted as encoding data symbols 107, in other embodiments, multiple signals may be employed to encode data symbols 107. For example, in some cases, when a differential signaling standard is used, two signals may be employed to encode data symbols 107.

[0026] The ADC-based receiver circuit 102 includes an analog-to-digital converter circuit 116 and is configured to generate recovered data symbols 110 using a clock signal 114 and an equalized signal 108 based on the baud rate of the serial data stream including the data symbols 107. As described below, the ADC-based receiver circuit 102 may include multiple analog-to-digital converter circuits that sample the equalized signal 108 at different resolutions. In various embodiments, different ones of the multiple analog-to-digital converter circuits may be employed based on the baud rate of the serial data stream including the data symbols 107.

[0027] The analog receiver circuit 103 is configured to generate recovered data symbols 111 using a clock signal 115 and an equalization signal 108 based on the baud rate of the serial data stream including the data symbols 107. As described below, the analog receiver circuit 103 may be primarily implemented using analog circuits that perform various functions (e.g., decision feedback equalization) in the analog domain. Note that when the baud rate is less than a threshold, the power consumption of the analog receiver circuit 103 may be less than that of the ADC-based receiver circuit 102. Although Figure 1 Only a single analog receiver circuit is depicted in the embodiment of FIG, but in other embodiments additional analog receiver circuits may be employed, each configured to be activated under a corresponding set of conditions (e.g., input data stream baud rate, channel conditions, etc.).

[0028] Clock circuit 104 is configured to generate clock signal 114 using control information 112 and to generate clock signal 115 using control information 113. In some embodiments, clock circuit 104 may be configured to generate clock signal 114 or clock signal 115 based on mode signal 120. For example, clock circuit 104 may be configured to generate clock signal 114 in response to determining that mode signal 120 is a particular value. Alternatively, clock circuit 104 may be configured to generate clock signal 115 in response to determining that mode signal 120 is a different value. Although clock signal 114 and clock signal 115 are depicted as a single line, in various embodiments, clock signal 114 and clock signal 115 may include multiple clock signals having respective phases. Note that the value of mode signal 104 may correspond to a particular set of conditions (e.g., input data stream baud rate, channel conditions, etc.). Changes in one or more of these conditions may result in different values ​​for mode signal 104.

[0029] Clock circuit 104 can be configured to generate clock signal 114 in response to determining that the baud rate of the serial data stream is equal to a specific baud rate value, and otherwise generate clock signal 115. In various embodiments, the determination of the baud rate can be performed during an initialization process associated with the communication channel to which hybrid receiver circuit 100 is coupled.

[0030] In various embodiments, ADC-based receiver circuitry 102 is configured to determine control information 112 during generation of recovered data symbols 110. In a similar manner, analog receiver circuitry 103 is also configured to determine control information 113 during generation of recovered data symbols 111. Control information 112 may include information indicative of a phase error detected during generation of recovered data symbols 110, and control information 113 may include information indicative of a phase error detected during generation of recovered data symbols 111.

[0031] In various embodiments, multiplexing circuit 105 is configured to generate output data symbols 121 by selecting either recovered data symbol 110 or recovered data symbol 111 using mode signal 120. Multiplexing circuit 105 can be implemented using a plurality of logic gates, a plurality of pass gates coupled together in a wired-OR fashion, or any other suitable circuit configured to select between the two sets of recovered data symbols. Note that multiplexing circuit 105 can be optional, as in some embodiments, a load circuit can directly receive recovered data symbols 110 and 111.

[0032] Go to Figure 2 , depicts a block diagram of an embodiment of front-end circuit 101. As shown, front-end circuit 101 includes filter circuit 201 and automatic gain control circuit 202A. Although front-end circuit 101 is depicted as generating a single equalized signal, in other embodiments, front-end circuit 101 can be configured to generate any suitable number of equalized signals using signal 106.

[0033] Filter circuit 201 is configured to generate filtered signal 203 using signal 106. In various embodiments, to generate filtered signal 203, filter circuit 201 may also be configured to attenuate high-frequency noise in signal 106. In some cases, filter circuit 201 may also be configured to attenuate low-frequency components in signal 106 at or near a DC level.

[0034] Automatic gain control circuit 202 is configured to generate equalized signal 108 using filtered signal 203. In various embodiments, automatic gain control circuit 202 can be implemented as a closed-loop control circuit that uses feedback from equalized signal 108 to maintain the amplitude of data symbols at an optimal level for sampling. In various embodiments, automatic gain control circuit 202 can include any suitable combination of attenuator and amplifier circuits that can be dynamically activated or deactivated to maintain the amplitude of data symbols.

[0035] Although Figure 2 While a single automatic gain circuit is described in the embodiment of FIG, additional automatic gain control circuits may be employed in other embodiments where multiple equalized signals are desired. In this case, the additional automatic gain circuits may apply different amounts of gain and / or attenuation to their respective equalized signals.

[0036] Go to Figure 3 , depicts a block diagram of an embodiment of an ADC-based receiver circuit 102. As shown, the ADC-based receiver circuit 102 includes a sampling circuit 301 and a recovery circuit 302.

[0037] Sampling circuit 301 is configured to generate samples 303 using equalized signal 108 and clock signal 114. As described below, in various embodiments, sampling circuit 301 may include multiple analog-to-digital converter circuits. In this case, sampling circuit 301 may also be configured to select a first analog-to-digital converter circuit from the multiple analog-to-digital converter circuits based on the baud rate of the serial data stream including data symbols 107. The first analog-to-digital converter circuit may be configured to sample equalized signal 108 using clock signal 114 to generate samples 303.

[0038] Sampling circuit 301 may also be configured to select a second ADC circuit from the plurality of ADC circuits based on the baud rate of the serial data stream comprising data symbols 107. The second ADC circuit is configured to sample equalized signal 108 using clock signal 114 to generate sampled signal 303. Note that sampled signal 303 may include a plurality of sampled streams. In various embodiments, the resolution of the second ADC circuit is greater than the resolution of the first ADC circuit. As used and described herein, the resolution of an ADC circuit refers to the minimum incremental voltage that causes the digital output of the ADC circuit to change. In some cases, a sampling circuit such as sampling circuit 301 may include multiple groups of ADC circuits coupled in parallel and activated sequentially (referred to as "sub-ADC circuits" or "sub-ADCs") to improve resolution.

[0039] Recovery circuit 302 is configured to generate recovered data symbols 110 and control information 112 using samples 303. To generate recovered data symbols 110 and control information 112, recovery circuit 302 can be configured to perform equalization operations such as feed-forward equalization (FFE) and decision feedback equalization (DFE). In other embodiments, recovery circuit 302 can also be configured to correct for mismatches in samples 303 and multiply samples 303 by a gain factor. In various embodiments, recovery circuit 302 can be implemented as a digital signal processor (DSP) or other suitable processing circuitry.

[0040] Go to Figure 4 , depicts a block diagram of an embodiment of the analog receiver circuit 103. As shown, the analog receiver circuit 103 includes a divider circuit 401 and a restoration circuit 402.

[0041] The divider circuit 401 is configured to generate samples using the equalized signal 109 and the clock signal 115. In various embodiments, the divider circuit 401 is configured to compare the equalized signal 109 to a plurality of thresholds. Such thresholds may correspond to voltage levels associated with leading or lagging effects. In various embodiments, the divider circuit 401 may also be configured to generate one or more error signals that may be included in the control information 113. In some embodiments, the divider circuit 401 may also be configured to perform equalization, such as decision feedback equalization (DFE).

[0042] Recovery circuit 402 is configured to generate recovered data symbols 111 and control information 113 using sampled signal 403. Note that sampled signal 403 may include a stream of samples generated by slicer circuit 401. To generate control information 113, recovery circuit 402 may be configured to perform phase detection. For example, in various embodiments, recovery circuit 402 may be configured to perform Mueller-Muller phase detection or Alexander phase detection. In various embodiments, recovery circuit 402 may be configured to perform such phase detection in the analog domain.

[0043] Steering Figure 5 , depicts an embodiment of a sampling circuit 301. As shown, the sampling circuit 301 includes sampling buffers 501A-501D, sub-analog-to-digital converter circuits (denoted as "sub-ADC 502A-502D"), switches 503A-503D, and a clock generation circuit 504. Note that although Figure 5 While four sampling buffers, four switches, and four sub-ADCs are depicted in the embodiment of FIG, different numbers of sampling buffers, switches, and sub-ADCs may be employed in other embodiments.

[0044] Switches 503A-503D are configured to couple equalized signal 108 to corresponding ones of sampling buffers 501A-501D using buffer clock 505. In various embodiments, each of buffer clocks 505 can be phase-shifted relative to one another so that only one of switches 503A-503D is closed at any given time. In various embodiments, the respective frequencies of buffer clocks 505 can be based on the frequency of recovered clock signal 512 and the number of sampling buffers and sub-ADCs included in sampling circuit 301.

[0045] In various embodiments, switches 503A-503D may be implemented using one or more switching metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), gate all around field effect transistors (GAAFETs), or any other suitable switching devices.

[0046] Each of the sampling buffers 501A-501D is configured to buffer the equalized signal 108 and drive the analog-to-digital converter circuit included in a corresponding one of the sub-ADCs 502A-502D. In various embodiments, the sampling buffers 501A-501D can be implemented as unity-gain amplifier circuits, or any other suitable circuit configured to buffer analog signals and provide additional drive to enable driving multiple analog-to-digital converter circuits.

[0047] Each of the sub-ADCs 502A-502D includes a plurality of analog-to-digital converter circuits coupled to a corresponding one of the sample buffers 501A-501D and configured to generate sample signals 507A-507D based on the voltage level of the output of the corresponding one of the sample buffers 501A-501D. In various embodiments, the sample signals 507A-507D each include a corresponding sample stream generated by the corresponding one of the sub-ADCs 502A-502D. The analog-to-digital circuits included in a given one of the sub-ADCs 502A-502D are sequentially activated by ADC clocks 506A and 506B. In various embodiments, the number of analog-to-digital converter circuits included in a sub-ADC determines the interleaving factor of the sub-ADC.

[0048] As described above, sub-ADCs 502A-502D can be activated sequentially. Once a particular one of sub-ADCs 502A-502D has been activated, the included analog-to-digital converter circuits can then be activated sequentially. In this case, the samples generated by sub-ADCs 502A-502D can be interleaved with each other. Recovery circuitry (e.g., recovery circuit 302) can be configured to correctly align the samples and retime the data to a different, potentially slower, clock domain.

[0049] When a given ADC circuit is activated, it samples the output of its corresponding sampling buffer. Once the output has been sampled, there is a period of time (referred to as a "resolution period" or "resolving period") during which the ADC circuit generates a number of bits whose combined value corresponds to the voltage level of the sampled output. The duration of the resolution period and the number of bits generated vary depending on the type of ADC circuit employed. In various embodiments, the sum of the sampling period and the resolution period for an ADC circuit included in a given sub-ADC may be less than or equal to the active time of a corresponding one of the buffer clocks 505.

[0050] The individual analog-to-digital converter circuits included in sub-ADCs 502A-502D can be implemented as flash ADCs, successive approximation ADCs, or any other suitable type of analog-to-digital converter circuit. Although only four ADCs are depicted as included in sub-ADCs 502A-502D, any suitable number of analog-to-digital converter circuits may be employed in other embodiments. In such cases, clock generator circuit 504 would be configured to generate the necessary number of ADC clock signals.

[0051] Clock generator circuit 504 is configured to generate buffer clock 505 and ADC clocks 506A and 506B. In various embodiments, clock generator circuit 504 may be implemented using phase-locked loop circuitry, delay-locked loop circuitry, delay circuitry, or any other type of circuitry suitable for generating multiple clock signals with different phases.

[0052] Go to Figure 6 , depicts a block diagram of an embodiment of clock circuit 104. As shown, clock circuit 104 includes multiplexing circuit 601, multiplexing circuit 602, oscillator circuit 603, oscillator circuit 604, logic circuit 605, logic circuit 606, buffer circuit 607, multiplexing circuit 608, clock generator circuit 609, and buffer circuit 610.

[0053] Multiplexing circuit 601 is configured to select one of control information 112 or control information 113 to generate a tuning signal on node 612. In various implementations, multiplexing circuit 601 can be configured to use mode signal 120 to select the one of control information 112 or control information 113. In a similar manner, multiplexing circuit 602 is configured to select one of control information 112 or control information 113 to generate a tuning signal on node 613.

[0054] In various implementations, multiplexing circuits 601 and 602 may be implemented using multiple logic gates. In other implementations, multiplexing circuits 601 and 602 may be implemented using multiple pass gates coupled together in a wired-OR fashion.

[0055] Oscillator circuit 603 is configured to generate one or more clock phases at node 614 using a tuning signal at node 612. In various embodiments, oscillator circuit 603 can be an inductor-capacitor oscillator circuit (referred to as an "LC oscillator circuit"). In a similar manner, oscillator circuit 604 is configured to generate one or more clock phases at node 615 using a tuning signal at node 613. In various embodiments, oscillator circuit 604 can be implemented as a ring oscillator circuit.

[0056] Logic circuit 605 is configured to generate one or more clock phases at node 616 and node 621 using the clock phase at node 614 and test clock 620. In various embodiments, logic circuit 605 can be configured to use test clock 620 during test mode instead of the clock phase at node 614. To generate the clock phases at node 621 and node 616, logic circuit 605 can also be configured to adjust for skew of the clock phases and buffer the clock phases.

[0057] Logic circuit 606 is configured to generate a clock phase on node 618 using the clock phase on node 615 and test clock 620. To generate the clock phase on node 618, logic circuit 606 may also be configured to perform frequency division using at least one of the clock phases on node 615. In other embodiments, logic circuit 606 may be configured to delay one or more of the clock phases on node 615 to generate the clock phase on node 618.

[0058] Multiplexing circuit 608 is configured to select a clock phase from node 621, node 616, or node 618 to generate a clock phase at node 619. In various embodiments, multiplexing circuit 608 can be configured to make the selection using mode signal 120 or based on the baud rate of the serial data stream including data symbols 107. In various embodiments, multiplexing circuit 608 can be implemented using a plurality of logic gates, a plurality of pass gates coupled together in a wired-OR fashion, or any other suitable circuit.

[0059] Clock generator circuit 609 is configured to generate clock signal 114 using the clock phases on node 619. In various embodiments, the number of clock signals included in clock signal 114 may be greater than the number of clock phases on node 619. In such a case, clock generator circuit 609 may also be configured to delay different ones of the clock phases on node 619 to generate clock signal 114, such that the individual clock signals in clock signal 114 have respective phase shifts.

[0060] Multiplexing circuit 610 is configured to select the clock phase from either node 616 or node 618 to generate clock signal 115. In various embodiments, multiplexing circuit 610 can be configured to make the selection using mode signal 120 or based on the baud rate of the serial data stream including data symbols 107. In various embodiments, multiplexing circuit 610 can be implemented using a plurality of logic gates, a plurality of pass gates coupled together in a wired-OR fashion, or any other suitable circuit.

[0061] As described above, a receiver circuit, such as hybrid receiver circuit 100 , may be employed in a computer system. Figure 7A block diagram of an embodiment of such a computer system is depicted in As shown, computer system 700 includes devices 701 and 702 coupled via a communication bus 707 .

[0062] Device 701 includes circuit block 703 and transmitter circuit 704. In various embodiments, device 701 can be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block that can be included on an integrated circuit in a computer system. Note that while device 701 depicts only a single circuit block and a single transmitter circuit, in other embodiments, additional circuit blocks and additional transmitter circuits can be employed.

[0063] Transmitter circuit 704 is configured to serially transmit a signal corresponding to data received from circuit block 703 via communication bus 707. Such a signal may differentially encode one or more bits, such that at a particular point in time, the difference between the respective voltage levels of lines 708A and 708B corresponds to a particular bit value. In some cases, the generation of the signal may include encoding the bits prior to transmission. Note that while communication bus 707 is depicted as including two lines, any suitable number of lines may be employed in other embodiments.

[0064] Device 702 includes a receiver circuit 705 and a circuit block 706. Similar to device 701, device 702 may be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block configured to receive data from transmitter circuit 704. In various embodiments, receiver circuit 705 may correspond to Figure 1 A hybrid receiver circuit 100 is depicted.

[0065] In some embodiments, devices 701 and 702 may be fabricated on a common integrated circuit. In other embodiments, devices 701 and 702 may be located on different integrated circuits mounted on a common substrate or circuit board. In such cases, communication bus 707 may include metal or other conductive traces on the substrate or circuit board. Although only two devices are depicted in computer system 700, any suitable number of devices may be employed in other embodiments.

[0066] Go to Figure 8 , a flow chart depicting an embodiment of a method for operating a hybrid receiver circuit is shown. The method, which may be applicable to various hybrid receiver circuits, such as the hybrid receiver circuit 100 , begins at block 801 .

[0067] The method includes generating an equalized signal using at least one signal that encodes a serial data stream including a plurality of data symbols (block 802). In some embodiments, generating the equalized signal includes filtering the plurality of signals to generate a filtered signal. In such cases, the method may include buffering the filtered signal with a gain factor to generate the equalized signal. In various embodiments, the method may also include generating a plurality of equalized signals using the at least one signal.

[0068] The method also includes activating a specific receiver circuit in a plurality of receiver circuits based on an operating condition, wherein the specific receiver circuit includes at least one analog-to-digital converter circuit (block 803). In various embodiments, the plurality of receiver circuits include a plurality of ADC-based receiver circuits and a plurality of analog receiver circuits activated in response to detecting corresponding operating conditions. As used and defined herein, operating conditions refer to a set of physical and electrical parameters that affect the transmission of a signal encoding a serial data stream and the characteristics of the signal itself. For example, a specific operating condition may include the baud rate of the serial data stream and the electrical characteristics (e.g., impedance) of the channel through which the serial data stream is transmitted. In various embodiments, activating a specific receiver circuit based on the baud rate of the serial data stream includes comparing the baud rate of the serial data stream with a threshold value and activating the specific receiver circuit in response to determining that the baud rate of the serial data stream is greater than the threshold value.

[0069] In some embodiments, the method further includes activating a different receiver circuit among a plurality of receiver circuits including an analog receiver circuit in response to detecting a different operating condition. In this case, the method may further include generating a second plurality of recovered data symbols by the different receiver circuit using a second equalized signal and a different set of clock signals, and generating the different set of clock signals by the clock circuit using different control information determined during generation of the second plurality of recovered data symbols.

[0070] In other embodiments, activating in response to detecting the different operating condition includes receiving baud rate information of the serial data stream by the different receiver circuit. In various embodiments, the different receiver circuit may receive the baud rate information during an initialization or startup process associated with the communication channel. In such a case, the method may also include deactivating the particular receiver circuit in response to detecting the different operating condition.

[0071] The method also includes generating, by the particular receiver circuit, a first plurality of recovered data symbols using the first equalized signal and a particular set of clock signals (block 804). In some embodiments, the particular receiver circuit includes a plurality of analog-to-digital converter circuits. In such a case, generating, by the particular receiver circuit, the first plurality of recovered data symbols includes selecting a first analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits based on a baud rate of the serial data stream, and sampling, by the first analog-to-digital converter circuit, the first equalized signal using the particular set of clock signals to generate a plurality of samples. The method may also include generating the first plurality of recovered data symbols using the plurality of samples.

[0072] In other embodiments, the method may further include selecting a second ADC circuit from the plurality of ADC circuits based on the baud rate of the serial data stream. In various embodiments, the second ADC circuit has a resolution greater than a resolution of the first ADC circuit. In this case, the method further includes sampling the first equalized signal using the specific set of clock signals by the second ADC circuit to generate a plurality of interleaved samples, and generating a first plurality of recovered data symbols using the plurality of interleaved samples.

[0073] The method further includes generating, by a clock circuit, the specific set of clock signals using specific control information determined during generation of the first plurality of recovered data symbols (block 805). In some embodiments, the clock circuit may include multiple oscillator circuits. In such a case, generating the specific set of clock signals includes adjusting the frequency of at least one oscillator circuit in the multiple oscillator circuits using the specific control information. The method ends at block 806.

[0074] exist Figure 9 900. In the illustrated embodiment, SoC 900 includes processor circuitry 901, memory circuitry 902, analog / mixed-signal circuitry 903, and input / output circuitry 904, each of which is coupled to a communication bus 905. In various embodiments, SoC 900 can be configured for use in a desktop computer, a server, or in mobile computing applications such as, for example, a tablet computer, a laptop computer, or a wearable computing device.

[0075] In various embodiments, the processor circuit 901 may represent a general-purpose processor that performs computing operations. For example, the processor circuit 901 may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).

[0076] In various embodiments, memory circuit 902 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Figure 9 A single memory circuit is shown in FIG, but in other embodiments, any suitable number of memory circuits may be employed.

[0077] The analog / mixed signal circuit 903 may include a crystal oscillator circuit, a phase-locked loop (PLL) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown). In other embodiments, the analog / mixed signal circuit 903 may be configured to perform power management tasks by including an on-chip power supply and voltage regulator.

[0078] Input / output circuitry 904 may be configured to coordinate data transfers between SoC 900 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., magnetic or optical media-based storage devices, including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 904 may be configured to implement the Universal Serial Bus (USB) protocol or IEEE 1394. The version of the agreement, and include Figure 1 1. In this case, the input / output circuit 904 may further include a mode control circuit 906 configured to generate a mode signal 120. In some cases, the mode control circuit 906 may be configured to set the value of the mode signal 120 based on the rate at which the hybrid receiver circuit 100 receives data. In other cases, the mode control circuit 906 may be configured to set the value of the mode signal 120 during initialization or boot operation of the SoC 900.

[0079] The input / output circuitry 904 may also be configured to coordinate data transfers between the SoC 900 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the SoC 900 via a network. In one embodiment, the input / output circuitry 904 may be configured to perform the data processing required to implement an Ethernet (IEEE 802.3) networking standard, such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, but it is contemplated that any suitable networking standard may be implemented. In some embodiments, the input / output circuitry 904 may be configured to implement multiple discrete network interface ports.

[0080] Now go to Figure 10, shows various types of systems that may include any of the circuits, devices, or systems described above. System or device 1000, which may incorporate or otherwise utilize one or more of the techniques described herein, may be used in a wide variety of fields. For example, system or device 1000 may be used as part of the hardware of a system such as a desktop computer 1010, a laptop computer 1020, a tablet computer 1030, a cellular or mobile phone 1040, or a television 1050 (or a set-top box coupled to a television).

[0081] Similarly, the disclosed elements can be used in wearable devices 1060, such as smart watches or health monitoring devices. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring the user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0082] The system or device 1000 may also be used in a variety of other environments. For example, the system or device 1000 may be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements cloud-based services 1070. Furthermore, the system or device 1000 may be implemented in a wide range of dedicated everyday devices, including devices 1080 commonly found in homes, such as refrigerators, thermostats, security cameras, and the like. The interconnection of such devices is often referred to as the "Internet of Things" (IoT). Components may also be implemented in various modes of transportation. For example, the system or device 1000 may be used in control systems, guidance systems, entertainment systems, and the like in various types of vehicles 1090.

[0083] Figure 10 The applications shown in the examples are merely exemplary and are not intended to limit potential future applications of the disclosed systems or devices. Other exemplary applications include, but are not limited to, portable gaming devices, music players, data storage devices, unmanned aerial vehicles, and the like.

[0084] Figure 11 1 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1120 is configured to process design information 1115 stored on a non-transitory computer-readable storage medium 1110 and to manufacture an integrated circuit 1130 based on the design information 1115.

[0085] The non-transitory computer-readable storage medium 1110 may include any of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1110 may be an installation medium, such as a CD-ROM, floppy disk, or tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, magnetic media, such as a hard drive or optical storage device; a register, or other similar type of memory element; etc. The non-transitory computer-readable storage medium 1110 may include other types of non-transitory memory or a combination thereof. The non-transitory computer-readable storage medium 1110 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0086] Design information 1115 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, and the like. Design information 1115 can be used by semiconductor manufacturing system 1120 to manufacture at least a portion of integrated circuit 1130. The format of design information 1115 can be recognizable by at least one semiconductor manufacturing system, such as, for example, semiconductor manufacturing system 1120. In some embodiments, design information 1115 can include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit 1130 can also be included in design information 1115. Such cell libraries can include information indicating device or transistor-level netlists, mask design data, characterization data, and the like for cells included in the cell library.

[0087] In various embodiments, integrated circuit 1130 may include one or more custom macrocells, such as memory, analog or mixed-signal circuits, and the like. In this case, design information 1115 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to Graphics Data System II (GDSII) or any other suitable format.

[0088] Semiconductor manufacturing system 1120 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1120 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0089] In various embodiments, integrated circuit 1130 is configured to operate according to the circuit design specified by design information 1115, which may include performing any of the functions described herein. For example, integrated circuit 1130 may include any of the various components shown or described herein. Additionally, integrated circuit 1130 may be configured to perform various functions described herein in conjunction with other components. Furthermore, the functionality described herein may be performed by multiple connected integrated circuits.

[0090] As used herein, phrases of the form "design information specifying a design of a circuit configured to..." do not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0091] ***

[0092] This disclosure includes references to "embodiments," which are non-limiting, specific implementations of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," "some embodiments," "various embodiments," etc., do not necessarily refer to the same embodiment. Numerous possible embodiments are contemplated, including the specific embodiments detailed, as well as modifications or alternatives that fall within the spirit or scope of this disclosure. Not all such embodiments will necessarily exhibit any or all of the potential advantages described herein.

[0093] Unless otherwise indicated, the detailed description is not intended to limit the scope of claims drafted based on the disclosure of the present disclosure, even if only a single example is described for a particular feature. Therefore, the disclosed embodiments are intended to be illustrative rather than restrictive, without any statement to the contrary. This patent application is intended to cover such alternatives, modifications, and equivalents as will be apparent to those skilled in the art having the benefit of this disclosure.

[0094] The particular features, structures or characteristics may be combined in any suitable manner consistent with the present disclosure. Accordingly, the present disclosure is intended to include any feature or combination of features disclosed herein (explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be made during the prosecution of this patent application (or a patent application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features of the dependent claims may be combined with features of the independent claims, and features from the corresponding independent claims may be combined in any suitable manner and not merely by the specific combinations recited in the appended claims.

[0095] For example, although the appended dependent claims are drafted so that each dependent claim is dependent on a single other claim, additional dependencies are contemplated. It is also contemplated that a claim drafted in one legal type (e.g., apparatus) may inspire a corresponding claim of another legal type (e.g., method), where appropriate.

[0096] ***

[0097] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how claims drafted based on this disclosure are to be interpreted.

[0098] Unless the context clearly dictates otherwise, references to singular forms such as “a,” “an,” and “the” are intended to mean “one or more.” Thus, reference to “an item” in a claim does not preclude additional instances of that item.

[0099] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0100] The terms "include" and "including" and their forms are open ended and mean "including, but not limited to."

[0101] When the term "or" is used in this disclosure with respect to a list of options, unless the context provides otherwise, it will generally be understood to be used in an inclusive sense. Thus, the expression "x or y" is equivalent to "x or y, or both," encompassing x but not y, y but not x, and both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0102] The expression "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" is intended to encompass all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases encompass any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase "... at least one of w, x, y, and z" refers to at least one element of the elements in the set [w, x, y, z], thereby encompassing all possible combinations in this list of options. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0103] In this disclosure, various "labels" may precede nouns. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to specific features.

[0104] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing, such as a device, a circuit, a memory storing executable program instructions, etc., that is used to implement the task. The phrase is not used herein to refer to an intangible thing.

[0105] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA could be "configurable to" perform that function.

[0106] The phrase "configured to" in the appended claims is expressly intended to define the claim elements. No Invoking 35 U.S.C. § 112(f). If an applicant wishes to invoke section 112(f) during the prosecution of a patent application, it would use the “means for [performing the function]” construct to describe the claim elements.

[0107] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, a determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover embodiments in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0108] The phrase "in response to" describes one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect. That is, the effect may be responsive only to these factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." The phrase specifies that B is the factor that triggers the performance of A. The phrase does not exclude that the performance of A may also be responsive to some other factor, such as C. The phrase is also intended to encompass embodiments in which A is performed only in response to B.

Claims

1. A device comprising: A front-end circuit, wherein the front-end circuit is configured to: generating a first equalized signal based on a first input signal encoding a first serial data stream, wherein the first serial data stream includes a plurality of data symbols and has a first baud rate; and generating a second equalized signal based on a second input signal encoding a second serial data stream, wherein the second serial data stream includes a plurality of data symbols and has a second baud rate; as well as A sampling circuit, the sampling circuit comprising: a first analog-to-digital converter (ADC) circuit having a first resolution; and a second ADC circuit having a second resolution; and A control circuit, the control circuit being configured to: selecting the first ADC circuit to sample the first equalized signal based on the first baud rate to generate a first set of output data symbols; The second ADC circuit is selected based on the second baud rate to sample the second equalized signal to generate a second set of output data symbols.

2. The apparatus of claim 1 , wherein the first ADC circuit comprises: a first sub-ADC circuit; a second sub-ADC circuit; as well as A control circuit, the control circuit being configured to: sequentially operating the first sub-ADC circuit and the second sub-ADC circuit to sample the first equalized signal; as well as The outputs of the first sub-ADC circuit and the second sub-ADC circuit are interleaved to generate the first set of output data symbols.

3. The device according to claim 1, wherein: The first resolution is greater than the second resolution; and The first ADC circuit has a power consumption greater than that of the first ADC circuit.

4. The device according to claim 1, wherein To select the first ADC circuit, the control circuit is configured to provide a clock signal to the first ADC circuit and to gate a clock signal of the second ADC circuit. 5 . The apparatus of claim 1 , wherein the second ADC circuit has a resolution cycle duration longer than that of the first ADC circuit.

6. The apparatus according to claim 1, further comprising: An analog receiver circuit wherein: The front-end circuit is configured to generate a third equalized signal based on a third input signal encoding a third serial data stream, wherein the third serial data stream includes a plurality of data symbols and has a third baud rate; and The control circuit is configured to select the analog receiver circuit to sample the third equalized signal based on the third baud rate to generate a third set of output data symbols.

7. The apparatus of claim 6, wherein the analog receiver circuit comprises a divider circuit and a restoration circuit. 8 . The apparatus of claim 1 , further comprising a clock circuit configured to provide a clock signal to the selected ADC circuit. 9 . The apparatus of claim 8 , wherein the clock circuit is configured to generate the clock signal based on phase error information generated by the selected ADC circuit.

10. The apparatus of claim 1, wherein the front-end circuit comprises a filter circuit and a gain control circuit.

11. A method comprising: generating, by the front-end circuit, a first equalized signal based on a first input signal encoding a first serial data stream, wherein the first serial data stream includes a plurality of data symbols and has a first baud rate; generating, by the front-end circuit, a second equalized signal based on a second input signal encoding a second serial data stream, wherein the second serial data stream includes a plurality of data symbols and has a second baud rate; selecting, by control circuitry, a first analog-to-digital converter (ADC) circuit having a first resolution based on the first baud rate to sample the first equalized signal to generate a first set of output data symbols; as well as A second ADC circuit is selected by the control circuit based on the second baud rate to sample the second equalized signal to generate a second set of output data symbols.

12. The method of claim 11 , wherein the first ADC circuit comprises: a first sub-ADC circuit; as well as a second sub-ADC circuit; The method further comprises: sequentially operating the first sub-ADC circuit and the second sub-ADC circuit to sample the first equalized signal; as well as The outputs of the first sub-ADC circuit and the second sub-ADC circuit are interleaved to generate the first set of output data symbols.

13. The method of claim 11, wherein sampling the first equalized signal to generate a first set of output data symbols utilizes more power than sampling the second equalized signal to generate a second set of output data symbols. 14 . The method of claim 11 , wherein selecting the first ADC circuit comprises providing a clock signal to the first ADC circuit and gating a second clock signal to the second ADC circuit.

15. The method of claim 11, wherein the second ADC circuit has a longer resolution cycle duration than the first ADC circuit.

16. The method according to claim 11, further comprising: generating, by the front-end circuit, a third equalized signal based on a third input signal encoding a third serial data stream, the third serial data stream including a plurality of data symbols and having a third baud rate; as well as An analog receiver circuit is selected by the control circuit based on the third baud rate to sample the third equalized signal to generate a third set of output data symbols.

17. The method according to claim 11, further comprising: generating a first clock signal for the first ADC circuit based on first error information from the first ADC circuit; as well as A second clock signal is generated for the second ADC circuit based on second error information from the second ADC circuit.

18. A system comprising: A first component, wherein the first component is configured to: generating a first serial data stream comprising a plurality of data symbols and having a first baud rate; generating a second serial data stream comprising a plurality of data symbols and having a second baud rate; transmitting a first signal, wherein the first signal encodes the first serial data stream; as well as transmitting a second signal, wherein the second signal encodes the second serial data stream; as well as A second component, wherein the second component is configured to: receiving the first signal and the second signal; generating a first equalized signal based on the first signal; activating a first analog-to-digital converter (ADC) circuit having a first resolution based on the first baud rate to sample the first equalized signal to generate a first set of output data symbols; generating a second equalized signal based on the second signal; as well as A second ADC circuit is activated based on the second baud rate to sample the second equalized signal to generate a second set of output data symbols.

19. The system of claim 18, wherein the first ADC circuit comprises: a first sub-ADC circuit; a second sub-ADC circuit; as well as A control circuit, the control circuit being configured to: sequentially operating the first sub-ADC circuit and the second sub-ADC circuit to sample the first equalized signal; as well as The outputs of the first sub-ADC circuit and the second sub-ADC circuit are interleaved to generate the first set of output data symbols.

20. The system of claim 18, wherein: The first component is further configured to: generating a third serial data stream, wherein the third serial data stream includes a plurality of data symbols and has a third baud rate; as well as transmitting a third signal, said third signal encoding said third serial data stream; said second component comprising an analog receiver circuit; The second component is configured to: receiving the third signal; generating a third equalized signal based on the third signal; and The analog receiver circuit is selected based on the third baud rate to sample the third equalized signal to generate a third set of output data symbols.

21. A device comprising: a front-end circuit configured to generate an equalized signal using at least one signal encoding a serial data stream, the serial data stream comprising a plurality of data symbols; an ADC-based receiver circuit comprising a plurality of analog-to-digital converter circuits, wherein the ADC-based receiver circuit is configured to generate a first plurality of recovered data symbols using the equalized signal and a plurality of first clock signals based on a baud rate of the serial data stream; a first analog receiver circuit configured to generate a second plurality of recovered data symbols based on the baud rate of the serial data stream using the equalized signal and a plurality of second clock signals; as well as A multiplexing circuit is configured to select the first plurality of recovered data symbols or the second plurality of recovered data symbols based on the baud rate of the serial data stream to generate a plurality of output data symbols.

22. The apparatus of claim 21 , wherein to generate the plurality of recovered data symbols, the ADC-based receiver circuit is further configured to select a first analog-to-digital converter circuit of the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream; wherein the first analog-to-digital converter circuit is configured to sample the equalized signal using the plurality of first clock signals to generate a first plurality of samples; as well as Wherein the ADC-based converter circuit is further configured to generate the first plurality of recovered data symbols using the first plurality of samples.

23. The apparatus of claim 21, further comprising a second analog receiver circuit configured to generate a third plurality of recovered data symbols using the equalized signal and a plurality of third clock signals based on the baud rate of the serial data stream.

24. A method comprising: generating an equalized signal using at least one signal encoding a serial data stream, wherein the serial data stream includes a plurality of data symbols; activating a specific receiver circuit among a plurality of receiver circuits in response to determining that the baud rate of the serial data stream has a first value, wherein the specific receiver circuit includes at least one analog-to-digital converter circuit; generating, by the particular receiver circuit, a first plurality of recovered data symbols using the equalized signal and a particular set of clock signals; activating a different receiver circuit in a subset of the plurality of receiver circuits, the plurality of receiver circuits including a corresponding analog receiver circuit, in response to determining that the baud rate of the serial data stream has a second value different than the first value; generating, by the different receiver circuit, a second plurality of recovered data symbols using the equalized signal and a different set of clock signals; as well as The first plurality of recovered data symbols or the second plurality of recovered data symbols are selected based on the baud rate of the serial data stream to generate a plurality of output data symbols.

25. The method of claim 24, further comprising generating, by a clock circuit, the specific set of clock signals using specific control information determined during generation of the first plurality of recovered data symbols.

26. The method of claim 24, wherein the particular receiver circuit comprises a plurality of analog-to-digital converter circuits, and wherein, Generating, by the particular receiver circuit, the first plurality of recovered data symbols comprises: selecting a first analog-to-digital converter circuit from the plurality of analog-to-digital converter circuits based on the baud rate of the serial data stream; sampling the equalized signal using the particular set of clock signals via the first analog-to-digital converter circuit to generate a first plurality of samples; and The first plurality of recovered data symbols is generated using the first plurality of samples.

27. A device comprising: A first device, comprising a first functional circuit block, wherein the first device is configured to: receiving a serial data stream comprising a plurality of data symbols from the first functional circuit block; generating a plurality of signals encoding the serial data stream; as well as transmitting the plurality of signals via a communication channel; and a second device comprising a plurality of receiver circuits, wherein the second device is configured to: receiving the plurality of signals via the communication channel; generating an equalized signal using the plurality of signals; activating a specific receiver circuit among the plurality of receiver circuits based on a baud rate of the serial data stream, wherein the specific receiver circuit includes at least one analog-to-digital converter circuit; generating, by the particular receiver circuit, a first plurality of recovered data symbols using the equalized signal and a particular set of clock signals; activating a different receiver circuit in a subset of the plurality of receiver circuits including a corresponding analog receiver circuit based on the baud rate of the serial data stream; generating, by the different receiver circuit, a second plurality of recovered data symbols using the equalized signal and a different set of clock signals; as well as Based on the baud rate of the serial data stream, either the first plurality of recovered data symbols or the second plurality of recovered data symbols are selected to generate a plurality of output data symbols.

28. The apparatus of claim 27, wherein the second device is further configured to generate the specific set of clock signals using specific control information determined during generation of the first plurality of recovered data symbols.

29. The apparatus of claim 28, wherein the second device is further configured to generate the different sets of clock signals using different control information determined during generation of the second plurality of recovered data symbols.

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