Imaging control method of integral detector

Abstract

The invention provides an imaging control method of an integral detector, the detector comprises a logic control module and a pixel array formed by a plurality of pixels, each pixel comprises a first switch, a second switch, a third switch and an integrator, the first switch selectively connects the pixel to a reference voltage or an input voltage, and the second switch selectively connects the pixel to a reference voltage or an input voltage. The second switch is connected between an input voltage and a ground voltage, and the third switch is connected in parallel with an integrating capacitor of the integrator, the method comprising: closing the second and third switches before starting to perform an integrating step; connecting the first switch to an input voltage based on an exposure control signal and a clock signal; after one period of the clock signal, the second switch and the third switch are switched off; charges of the input voltage are accumulated in the capacitor to charge the capacitor until the voltage of the capacitor is stable; performing data sampling on the voltage of the capacitor; performing analog-to-digital conversion on sampling data of a row of pixels and performing effective sampling; and shaping, serializing and outputting the data subjected to analog-to-digital conversion.

Description

Technical Field

[0001] The present invention relates to a detector in the field of sensing and detection, and in particular to an imaging control method of a non-standard QVGA integral detector. Background Art

[0002] X-ray detectors are typically used for sensing, detecting, and imaging objects, non-destructively acquiring information about their internal structure. Integrating analog-to-digital converters (ADCs) are often used in these detectors due to their simple structure, high accuracy, and ease of implementing multi-column parallel processing. Therefore, integrating or dual-integrating detectors are commonly used in this field to acquire X-ray imaging information and generate corresponding grayscale images.

[0003] The dual-integration detector includes a dual-integration analog-to-digital converter, which integrates the input analog voltage and the reference voltage respectively, converts the average value of the input voltage into a time interval proportional to the average value, and then measures the time interval through a clock pulse and a counter, thereby outputting a digital value corresponding to the input analog voltage at the output end.

[0004] The standard resolution of QVGA (Quarter Video Graphics Array) commonly used in the art is 320×240 pixels, that is, a horizontal array row includes 320 pixels and a vertical array column includes 240 pixels. Figure 1 The figure shows the structure of the universal dual-integral analog-to-digital conversion circuit.

[0005] like Figure 1 As shown, the clock signal CLK is input into the logic control module to logically control switches S0 and S1 and the counter. The reference voltage Vref and the input analog voltage V1 are respectively input into the analog-to-digital conversion circuit through switch S1. By switching the input analog voltage V1 and the reference voltage Vref, the integrator integrates the voltages V1 and Vref twice. When the comparator detects that the integrator output reaches a threshold (e.g., zero level or a reference level), the integration stops, and the analog signal is sampled, counted, and converted to digital. Summary of the Invention

[0006] Technical problem to be solved by the invention

[0007] The present invention aims to provide an imaging control method, so that the input current charge is completely accumulated in the integrator capacitor during the integration operation, thereby ensuring the charge integrity of the input current to be measured.

[0008] Furthermore, unlike existing integrating detectors, the QVGA integrating detector in this invention utilizes a non-standard QVGA resolution of 320x256 pixels. Therefore, its integrating analog-to-digital converter requires a unique internal control method that differs from conventional analog-to-digital conversion. Consequently, the array imaging logic in this invention also differs from general imaging control logic. Based on this, the present invention provides a control method that matches the requirements of this non-standard QVGA integrating detector.

[0009] In addition, in the control method of the present invention, by making two adjacent rows of pixels perform analog-to-digital conversion operations and serial output operations respectively and simultaneously, the physical time of exposure waiting can be effectively reduced.

[0010] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0011] The present invention provides an imaging control method for an integrating detector, wherein the integrating detector includes a logic control module and a pixel array consisting of a plurality of pixels, wherein the pixels include a first switch, a second switch, a third switch, and an integrator, wherein the first switch can selectively connect the pixel to a reference voltage or an input voltage, the second switch is connected between the input voltage and a ground voltage, and the third switch is connected in parallel with an integrating capacitor of the integrator. The method comprises: closing the second and third switches before starting an integration step; connecting the first switch to the input voltage based on an externally input exposure control signal and a clock signal input to the logic control module; opening the second and third switches after one cycle of the clock signal; accumulating charge of the input voltage in the capacitor to charge the capacitor until the voltage of the capacitor stabilizes; sampling the voltage of the capacitor; performing analog-to-digital conversion on the sampled data of a row of pixels and performing effective sampling; and shaping, serializing, and outputting the analog-to-digital converted data.

[0012] According to one aspect of the present invention, the exposure control signal synchronizes the integration control time with the exposure time of a system light source illuminating the pixel.

[0013] According to another aspect of the present invention, the first switch is turned off one cycle after the integral control time ends, so that the voltage of the capacitor remains stable.

[0014] According to another aspect of the present invention, at the end of the integration control time, the capacitance latching of pixels in all pixel rows is completed simultaneously, and analog-to-digital conversion is performed on the pixel array row by row.

[0015] According to yet another aspect of the present invention, a row selection signal for selecting a pixel row is enabled row by row, thereby performing analog-to-digital conversion on the pixel array row by row.

[0016] According to another aspect of the present invention, the data after analog-to-digital conversion has 16 bits, wherein the upper 4 bits of data are completed in an asynchronous form within the pixel, and the lower 12 bits of data are completed in a column of the pixels.

[0017] According to another aspect of the present invention, frame header information and a frame tail cyclic redundancy check code are inserted into the data after analog-to-digital conversion to perform the shaping process.

[0018] According to yet another aspect of the present invention, while analog-to-digital conversion is being performed on sampled data of one row of pixels, a serialization process and output operation are synchronously performed on the pixels of the previous row.

[0019] According to yet another aspect of the present invention, the output operation is performed through one of a parallel interface, a serial peripheral interface, a MIPI CSI-2 interface, a USB video class protocol, and a low voltage differential signaling interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0021] Figure 1 The diagram shows the structure of a general integral analog-to-digital conversion circuit.

[0022] Figure 2 is a block diagram showing the structure of an integrating type detector in the present invention.

[0023] Figure 3 The figure shows the structure of the integral analog-to-digital conversion circuit in the present invention.

[0024] Figure 4 The jump diagram of the imaging control process of the integral detector in the present invention is shown.

[0025] Figure 5 The figure shows a timing diagram of imaging control in the integrating detector of the present invention.

[0026] Figure 6 The figure shows a timing diagram of analog-to-digital conversion control within one analog-to-digital conversion cycle in the integrating detector of the present invention.

[0027] Figure 7 FIG. 4 shows a timing diagram of a readout operation for a row of pixels in the present invention. DETAILED DESCRIPTION

[0028] The present invention provides a control method for a QGVA integrating detector to meet the imaging control requirements and imaging data readout requirements of an integrating detector with a non-standard QVGA (320x256) resolution.

[0029] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. In the following description, the "rising edge" of a signal refers to the point at which the signal suddenly changes from a low level to a high level, and the "falling edge" of a signal refers to the point at which the signal suddenly changes from a high level to a low level.

[0030] Figure 2 FIG. 1 is a block diagram showing the structure of the integral type detector in the present invention. Figure 2 As shown, the integral detector of the present invention mainly includes: a register, a logic control module, a pixel array, a readout control circuit, an LVDS (Low Voltage Differential Signaling) interface and other modules, wherein the logic control module may include modules for integral control, analog-to-digital conversion control, and readout control, and the pixel array may specifically be an imaging array with pixels having a QVGA (320x256) resolution.

[0031] In the following embodiments of the present invention, the pixel is specifically described as an integral type digital-to-analog conversion pixel.

[0032] Figure 3 The structure of the integral analog-to-digital conversion circuit as the integral digital-to-analog conversion pixel in the present invention is shown.

[0033] Different from Figure 1 Compared to the prior art shown in FIG. 1 , the analog-to-digital conversion circuit in the present invention includes three switches TX, RST1, and RST2. The control logic performs logical control on the switches TX, RST1, RST2, and the counter. The switch TX can selectively connect the pixel to the reference voltage Vref or the input analog voltage V1. The switch RST1 is connected between the input analog voltage V1 and the ground voltage Vss. The switch RST2 is connected in parallel with the capacitor C in the counter to reset the capacitor C in the integrator.

[0034] In addition, although the counter described in the figure is an n-bit binary counter, those skilled in the art can use an appropriate counter according to actual needs.

[0035] Before the integrating DAC pixel begins its integration operation, switches RST1 and RST2 are closed, resetting the voltage across switch RST1 and capacitor C. The externally input exposure control signal (SYNC signal) then controls the duration of the integration operation. Based on the system clock CLK, the control logic connects switch TX to the input analog voltage V1 and then opens switches RST1 and RST2, allowing the integration operation to proceed.

[0036] In the existing operation method of the logic control module, such as Figure 1 As shown in the figure, when switches S1 and S0 are closed, since there are only two switches, no matter whether the two switches are opened and closed simultaneously or in sequence, there may be charge leakage at the switch or the current may suddenly increase, resulting in large jitter noise at the switch, affecting the integration operation in capacitor C, and failing to completely store the charge input during the integration period in capacitor C.

[0037] In contrast, in the present invention, switches RST1 and RST2 are first closed, causing the voltage at switch RST1 to be grounded and the charge across capacitor C in the integrator to be cleared (the voltage is zero). Switch TX is then closed to input analog voltage V1, allowing the current flowing in during the integration period to charge capacitor C. This allows the inflowing current to be fully accumulated in capacitor C to complete the integration operation. This ensures the charge integrity of the current to be measured.

[0038] In addition, in this control method, switches RST1 and RST2 make the current flowing into the pixel from the input analog voltage V1 zero. After the integration operation begins, the current slowly increases, so the jitter noise generated is negligible.

[0039] Hereinafter, an imaging control method including integration control, analog-to-digital conversion control, and readout control performed in an integrating digital-to-analog conversion pixel will be described based on a process jump diagram and a timing diagram.

[0040] Figure 4 FIG. 1 shows a jump diagram of the imaging control process in the integral detector of the present invention. Figure 4 As shown, the imaging control method includes an integration operation step, an analog-to-digital conversion operation step, and a data readout operation step.

[0041] First, the analog-to-digital conversion pixel is initially in the idle state S_IDLE, and then the integration operation is synchronized with the exposure time of the external light source to complete the integration operation. When the integration operation is completed, the analog-to-digital conversion pixel is in the S_INTEG state.

[0042] Subsequently, after the integration operation is completed, after waiting for 64 cycles (64T), the analog-to-digital conversion operation is performed on the integrated information of the pixels row by row.

[0043] At this time, the selection time (A / D conversion time) for each row of pixels is 2560 cycles T (2560T). After the A / D conversion operation of one row of pixels is completed, wait for 64 cycles T (64T) before performing the A / D conversion operation on the next row of pixels, until the A / D conversion operation of 256 rows of pixels is completely completed. The total time required to complete the A / D conversion operation of 256 rows of pixels is 671744 cycles T (671744T). At this time, the pixels are in Figure 4 The state of S-CONV in .

[0044] Subsequently, the converted data after analog-to-digital conversion is sampled, shaped (signal conditioning) and serialized to complete the output frame (FRAME_DONE) image and output it.

[0045] Subsequently, the analog-to-digital conversion pixel is reset to the idle state S_IDLE, and by performing the above-mentioned integration operation, analog-to-digital conversion operation and data readout operation steps row by row, a frame of image is generated for each row of pixels row by row until the last frame of image is output, thereby completing the imaging processing of the integral detector.

[0046] Figure 5 FIG. 1 shows a timing diagram of imaging control in an integral detector according to the present invention. Figure 5 As shown, imaging control for the pixel array is performed according to the following control steps.

[0047] First, the operation and time of integration in the integrating detector are controlled by an externally input SYNC signal, so that the integration control operation is synchronized with the exposure time of the system light source illuminating the pixel.

[0048] The integral control time is between the rising edge and the falling edge of the SYNC signal, wherein the integral control time of the detector starts from the rising edge of the SYNC signal and ends at the falling edge of the SYNC signal.

[0049] Specifically, signal sampling is started at the rising edge of the SYNC signal, and based on the CLK clock cycle, a turn-on signal (TX_i) of the switch TX is generated with a delay of one cycle T, so that the switch TX is closed.

[0050] Subsequently, when delayed by two cycles (2T) from the rising edge of the SYNC signal, a reset signal (RST1_i) of the switch RST1 is generated, and a reset signal (RST2_i) of the switch RST2 is generated at the same time, so that the switches RST1 and RST2 are disconnected.

[0051] At this time, if Figure 5As shown in the timing diagram, after the rising edge of the SYNC signal is delayed by two cycles (2T), the charge of the input analog voltage V1 is accumulated in capacitor C, which begins to charge, and the voltage VC across it continues to rise. The integration control time ends at the falling edge of the SYNC signal. One cycle T later, the shutdown signal for switch TX is generated, turning off switch TX, and the voltage VS across capacitor C begins to stabilize.

[0052] At the falling edge of the SYNC signal, the integral capacitors of all pixel rows are latched simultaneously to implement a global shutter, which can be synchronized with the system exposure.

[0053] Based on the above control process, switches RST1 and RST2 are closed before the SYNC signal is input, resetting the voltages at the input node of input voltage V1 and integrating capacitor C (i.e., the input node of input voltage V1 is at ground voltage, and the voltage across integrating capacitor C is zero). Switch TX is then closed to allow input voltage V1 to enter. Therefore, the charge of the input current to be measured can be completely stored in capacitor C, ensuring the integrity of the charge.

[0054] Afterwards, when the integration operation is completed, data sampling is performed on the stable voltage VS, and the analog-to-digital conversion operation and data readout operation described later are performed on the sampled data. During the analog-to-digital conversion operation and data readout operation, changes in the SYNC signal have no effect on the analog-to-digital conversion operation and data readout operation.

[0055] After performing data conversion on a row of pixels and reading out a frame of image, the SYNC signal is resampled and the next integration instruction is awaited.

[0056] The above-mentioned integration operation, analog-to-digital conversion operation and data readout operation are repeatedly performed row by row to complete the imaging control of all pixel rows.

[0057] Figure 6 The timing diagram of analog-to-digital conversion control within one analog-to-digital conversion cycle in the integrating detector of the present invention is specifically described.

[0058] like Figure 6 As shown, 64 cycles (64T) after the integration operation for a row of pixels is completed, analog-to-digital conversion is started on the analog integrated signal obtained by integrating the pixels in the row.

[0059] It should be noted that in the present invention, the row select signal (RSi) used to select each pixel row is asserted row by row, thereby performing analog-to-digital conversion on the pixel array row by row. Before performing analog-to-digital conversion, the reset counter control signal (RSTN_CNT) goes low one cycle T after the row select signal becomes asserted, clearing the counter. This low state persists for one cycle T before returning to a high state to resume counting.

[0060] As described above, the integral capacitors of all pixel rows are latched at the falling edge of the SYNC signal, and the analog-to-digital conversion is performed on the pixel array row by row. The charge in the integral capacitor C of the current pixel row is gradually released during the analog-to-digital conversion process, that is, the reset signal RST2_i of the switch RST2 is pulled high row by row, as shown in FIG. Figure 5 As shown in .

[0061] The integrated signal after analog-to-digital conversion has a 16-bit bit size, of which the upper 4 bits are completed asynchronously within the pixel, so there is no need to wait for the global clock, resulting in a faster conversion speed.

[0062] The lower 12-bit data is completed in the analog-to-digital conversion pixel column, which depends on the system clock CLK, so the timing is strictly controllable. Figure 6 The ramp voltage reset signal RST_RAMP shown controls the resetting of the ramp voltage in the analog-to-digital conversion pixel column, and cooperates with the counter in the analog-to-digital conversion pixel column to complete the conversion of the lower 12-bit data.

[0063] During the conversion of the lower 12 bits of data, the Synchronize Most Significant Bits (SMSB) signal also samples the upper 4 bits of data into the column analog-to-digital conversion register, thereby combining the upper 4 bits of data with the lower 12 bits of data and sending them to the readout circuit.

[0064] Next, refer to Figure 7 The following describes the readout operation of the pixel integrated signal after analog-to-digital conversion. Figure 7 The timing diagram of the readout operation for a row of pixels in the present invention is shown, wherein the readout operation includes data sampling, shaping processing and serial output.

[0065] Similar to the analog-to-digital conversion operation, the readout operation is also performed row by row for each pixel row. After a delay of 12 clock cycles (12T) from the second rising edge of the ramp voltage reset signal RST_RAMP, the analog-to-digital conversion data of the current pixel row remains stable. At this time, the analog-to-digital conversion data is effectively sampled. In the present invention, the data volume of a row is 320x16 bits, that is, Figure 6 D[5119:0] shown in .

[0066] Next, the analog-to-digital conversion data of the current pixel row is latched (ie, the latch signal DIN[5119:0]) until the analog-to-digital conversion data of the next row is effectively sampled.

[0067] After the analog-to-digital conversion data of a row of pixels is effectively sampled, frame header information and a cyclic redundancy check code (CRC code) at the end of the frame are inserted into the sampled data for shaping processing.

[0068] Then, within the period of the row selection signal RS, the shaped data is serialized row by row, and the serialized data is outputted via the LVDS interface.

[0069] During the analog-to-digital conversion and readout processes described above, the analog-to-digital conversion and serial output operations (serialization and output) are performed alternately based on the row select signal RS. This means that while the current pixel row is undergoing analog-to-digital conversion, the previous pixel row is also undergoing serial output. This eliminates the need to wait for the entire pixel array to complete analog-to-digital conversion before performing serial output, thus reducing the physical exposure waiting time.

[0070] In the design of the present invention, the exposure frame rate is 70 fps, wherein the system clock is 50 MHz and one frame is approximately 70W cycles (671744T).

[0071] Although the above embodiment describes outputting pixel frames via an LVDS interface in the readout operation process, multiple output protocols can be selected based on different requirements, as follows:

[0072] 1. When pursuing cost-effectiveness and simplicity: Prefer a parallel interface (DVP) or SPI (Serial Peripheral Interface) (in low-speed scenarios).

[0073] 2. For miniaturization and low power consumption: The best choice is the MIPI CSI (Camera Serial Interface)-2 interface (especially for mobile devices).

[0074] 3. When pursuing peripheral compatibility: USB UVC (Video Class) protocol is more convenient.

[0075] 4. In harsh environments or long distances: LVDS interface is preferred due to its anti-interference advantage.

[0076] Although the control method is described in the above embodiment for a non-standard QVGA integrating detector with a resolution of 320x256 pixels, it is also applicable to full-frame integrating detectors with other resolutions. It is only necessary to appropriately change the sampling frame rate in the above embodiment.

[0077] The above is only a preferred specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any modification, equivalent replacement or change based on the technical solution and inventive concept of the present application by any technician familiar with the technical field within the technical scope disclosed in the present application should be covered by the scope of protection of the present application.

Claims

1. An imaging control method for an integrating detector, wherein: The integrating detector includes a logic control module and a pixel array consisting of a plurality of pixels, wherein the pixels include a first switch, a second switch, a third switch and an integrator, wherein the first switch can selectively connect the pixel to a reference voltage or an input voltage, the second switch is connected between the input voltage and a ground voltage, and the third switch is connected in parallel with an integrating capacitor of the integrator. The method comprises: Before starting the integration step, closing the second switch and the third switch; connecting the first switch to the input voltage based on an externally input exposure control signal and a clock signal input to the logic control module; After one cycle of the clock signal, turning off the second switch and the third switch; The charge of the input voltage is accumulated in the capacitor, and the capacitor is charged until the voltage of the capacitor is stable; performing data sampling on the voltage of the capacitor; Performing analog-to-digital conversion on the sampled data of a row of pixels and performing effective sampling; and Perform shaping, serialization and output operations on the data after analog-to-digital conversion.

2. The imaging control method of the integrating detector according to claim 1, wherein: The exposure control signal synchronizes the integration control time with the exposure time of a system light source illuminating the pixel.

3. The imaging control method of the integral detector according to claim 2, wherein: One cycle after the integral control time ends, the first switch is turned off, so that the voltage of the capacitor is kept stable.

4. The imaging control method of the integrating detector according to claim 2, wherein: When the integration control time ends, the capacitance latching of pixels in all pixel rows is completed simultaneously, and analog-to-digital conversion is performed on the pixel array row by row.

5. The imaging control method of the integrating detector according to claim 1, wherein: The row selection signal for selecting a pixel row is enabled row by row, thereby performing analog-to-digital conversion on the pixel array row by row.

6. The imaging control method of the integrating detector according to claim 1, wherein: The data after analog-to-digital conversion has 16 bits, wherein the upper 4 bits of data are completed in an asynchronous form within the pixel, and the lower 12 bits of data are completed in a column of the pixels.

7. The imaging control method of an integrating detector according to claim 1, wherein: Frame header information and a frame tail cyclic redundancy check code are inserted into the data after analog-to-digital conversion to perform the shaping process.

8. The imaging control method of the integrating detector according to claim 1, wherein: While analog-to-digital conversion is being performed on the sampled data of one row of pixels, the previous row of pixels is synchronously serialized and output.

9. The imaging control method of an integrating detector according to claim 1, wherein: The output operation is performed through one of a parallel interface, a serial peripheral interface, a MIPI CSI-2 interface, a USB video class protocol, and a low voltage differential signaling interface.

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