Semiconductor structure, forming method thereof and semiconductor device
By designing recesses and doping ions in the semiconductor structure, the process flow is simplified, production costs are reduced, conductivity and charge transfer efficiency are improved, and the problems of complexity and high cost in manufacturing vertical channel transistors are solved.
Patent Information
- Application Number
- CN202510788301.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-12
- Publication Date
- 2025-09-16
AI Technical Summary
The manufacturing process of existing vertical channel transistors is complex and costly, making it difficult to effectively reduce contact resistance and improve conductivity.
A semiconductor structure is designed, including a substrate and a contact structure. The substrate consists of a base and an isolation layer. Active pillars are spaced apart on the base. The isolation layer is located between the active pillars to form a recess. The contact portion of the contact structure is located within the recess and has an area larger than the active pillar. Doping ions are used to improve conductivity, and the process flow is simplified by a self-aligned and limited isolation layer.
The process flow is simplified, production costs are reduced, the safety window of capacitance is ensured, contact resistance is reduced, and charge transfer efficiency and signal integrity are improved.
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Figure CN120659316A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a semiconductor device. Background Art
[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and fast transmission speed. With the development of semiconductor technology, semiconductor devices have gradually transformed from planar channel transistors to vertical channel transistors. However, the existing vertical channel transistor process is relatively complex and the production cost is high.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention
[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, as well as a semiconductor device, which can simplify the process and reduce production costs. In addition, the semiconductor structure can ensure a safe window for capacitance, reduce contact resistance, and improve conductivity.
[0005] According to one aspect of the present disclosure, there is provided a semiconductor structure comprising:
[0006] A substrate comprising a base and an isolation layer, wherein the base has a plurality of active pillars distributed at intervals; the isolation layer is located between the active pillars, the top surface of the active pillars is lower than the top surface of the isolation layer, and the active pillars and the isolation layer together form a plurality of recesses;
[0007] A contact structure includes a connected epitaxial portion and a contact portion, wherein the epitaxial portion is located on the active pillar and at least partially located within the recess; the contact portion is located on a side of the epitaxial portion away from the active pillar, and the area of the orthographic projection of the top surface of the contact portion on the surface of the substrate is greater than the area of the orthographic projection of the active pillar on the surface of the substrate; the contact portion is used to connect a capacitor.
[0008] In an exemplary embodiment of the present disclosure, in a direction parallel to the surface of the substrate, the ratio of the area of the orthographic projection of the active pillar on the surface of the substrate to the area of the orthographic projection of the top surface of the contact portion on the surface of the substrate is 1:1.5 to 1:3.
[0009] In an exemplary embodiment of the present disclosure, the top of the contact portion is higher than the top surface of the isolation layer; and in the length direction of the active pillar, the distance between the top of the contact portion and the top surface of the isolation layer is less than or equal to 30 nm.
[0010] In an exemplary embodiment of the present disclosure, the contact portion and the epitaxial portion both include doping ions, wherein the doping ions include at least one of P, B, As, C, and Ge; and / or the doping concentration of the doping ions is greater than 0 and less than or equal to 2×e 22 atom / cm3.
[0011] In an exemplary embodiment of the present disclosure, in the length direction of the active pillar, the depth of the recess is 5 nm to 30 nm.
[0012] In an exemplary embodiment of the present disclosure, in a direction parallel to the surface of the substrate, a bottom surface of the recess is a plane.
[0013] In an exemplary embodiment of the present disclosure, in a direction parallel to the surface of the substrate, the bottom surface of the recess is a concave surface, wherein the distance between the top end of the recess and the bottom end of the recess is greater than 0 nm and less than or equal to 30 nm; and / or, the bottom surface of the recess is a V-shaped surface, and the opening angle of the V-shaped surface is greater than 0° and less than or equal to 75°.
[0014] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:
[0015] The insulating layer is located between the contact structures.
[0016] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:
[0017] forming a substrate comprising a base and an isolation layer, wherein the base has a plurality of active pillars spaced apart from each other; the isolation layer is located between the active pillars, a top surface of the active pillar is lower than a top surface of the isolation layer, and the active pillars and the isolation layer together form a plurality of recesses;
[0018] A contact structure is formed, the contact structure comprising a connected epitaxial portion and a contact portion, the epitaxial portion being located on the active pillar and at least partially located within the recess; the contact portion being located on a side of the epitaxial portion away from the active pillar, and an orthographic projection area of a top surface of the contact portion on the surface of the substrate being larger than an orthographic projection area of the active pillar on the surface of the substrate; and the contact portion being used to connect a capacitor.
[0019] In an exemplary embodiment of the present disclosure, a substrate is formed, the substrate including a base and an isolation layer, the base having a plurality of active pillars distributed at intervals; the isolation layer is located between the active pillars, the top surface of the active pillars is lower than the top surface of the isolation layer, and the active pillars and the isolation layer together enclose a plurality of recesses, including:
[0020] Etching the substrate to form a plurality of initial active pillars spaced apart in the substrate;
[0021] forming the isolation layer to fill the gaps between the initial active pillars, wherein the top surface of the isolation layer is flush with the top surface of the initial active pillars;
[0022] The initial active pillars are etched so that the top surfaces of the remaining initial active pillars are lower than the top surface of the isolation layer; the remaining initial active pillars are used as the active pillars, and the space enclosed by the active pillars and the isolation layer is used as the recessed portion.
[0023] In an exemplary embodiment of the present disclosure, an insulating layer is formed between the contact structures, and a method of forming the contact structures and the insulating layer includes:
[0024] forming an epitaxial layer on top of the active pillar using an epitaxial growth process, wherein the top of the epitaxial layer is higher than the top surface of the isolation layer, and the area of the orthographic projection of the top surface of the epitaxial layer on the surface of the substrate is larger than the area of the orthographic projection of the active pillar on the surface of the substrate;
[0025] forming the insulating layer between the epitaxial layers;
[0026] forming a metal layer on the epitaxial layer;
[0027] The metal layer is heat-treated so that the metal layer reacts with the epitaxial layer to form the contact portion, wherein the top of the contact portion is higher than the top surface of the isolation layer, and the area of the orthographic projection of the top surface of the contact portion on the surface of the substrate is larger than the area of the orthographic projection of the active pillar on the surface of the substrate; the epitaxial layer that has not reacted with the metal layer is used as the epitaxial portion, and the epitaxial portion is at least partially located in the recess;
[0028] removing the unreacted metal layer;
[0029] Alternatively, the method of forming the contact structure and forming the insulating layer includes:
[0030] forming an epitaxial layer on top of the active pillar using an epitaxial growth process, wherein the top of the epitaxial layer is higher than the top surface of the isolation layer, and the area of the orthographic projection of the top surface of the epitaxial layer on the surface of the substrate is larger than the area of the orthographic projection of the active pillar on the surface of the substrate;
[0031] forming a metal layer on a surface of a structure formed by the epitaxial layer and the isolation layer;
[0032] performing heat treatment on the metal layer so that the metal layer reacts with the epitaxial layer to form the contact portion; using the epitaxial layer that has not reacted with the metal layer as the epitaxial portion, wherein the epitaxial portion is at least partially located in the concave portion;
[0033] removing the unreacted metal layer;
[0034] The insulating layer is formed between the contact portions.
[0035] In an exemplary embodiment of the present disclosure, the precursor of the epitaxial growth process includes a doping gas, so that the epitaxial layer includes doping ions, wherein the doping ions include at least one of P, B, As, C and Ge; and / or the doping concentration of the doping ions is greater than 0 and less than or equal to 2×e 22 atom / cm3.
[0036] In an exemplary embodiment of the present disclosure, in the length direction of the active pillar, a distance between the top of the contact portion and the top surface of the isolation layer is less than or equal to 30 nm.
[0037] In an exemplary embodiment of the present disclosure, in a direction parallel to the surface of the substrate, the bottom surface of the recess is a plane or a concave surface.
[0038] According to one aspect of the present disclosure, a semiconductor device is provided, which is obtained by bonding any one of the semiconductor structures described above to a target wafer.
[0039] The semiconductor structure and its formation method, as well as the semiconductor device disclosed herein, have a contact structure comprising a connected epitaxial portion and a contact portion. Since the area of the orthographic projection of the top surface of the contact portion for connecting to the capacitor on the surface of the substrate is larger than the area of the orthographic projection of the active column on the surface of the substrate, the contact area between the contact portion and the capacitor is relatively large, which can ensure the safety window of the capacitor, help reduce the contact resistance between the capacitor and the contact portion, improve the charge transfer efficiency and signal integrity, and enhance the conductivity. At the same time, since the periphery of the recess is surrounded by the isolation layer, in the process of forming the epitaxial portion and the contact portion, the isolation layer can play a role of self-alignment and limiting, which can not only accurately control the lateral dimensions of the epitaxial growth of the epitaxial portion and the contact portion, but also avoid the steps of multiple mask alignment and multiple etching required in the traditional process. That is, the semiconductor structure disclosed herein can reduce the probability of short circuit between two adjacent contact portions due to connection without going through multiple mask and multiple etching processes, and the preparation process is relatively simple and the production cost is low.
[0040] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.
[0042] Figure 1 FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.
[0043] Figure 2 FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.
[0044] Figure 3 FIG. 1 is a schematic diagram of a semiconductor structure in an embodiment of the present disclosure.
[0045] Figure 4 1 is a top view of the substrate in an embodiment of the present disclosure.
[0046] Figure 5 In one embodiment of the present disclosure Figure 4 Cross-sectional view taken along the aa' direction.
[0047] Figure 6 In one embodiment of the present disclosure Figure 4 Cross-sectional view taken along the aa' direction.
[0048] Figure 7 Schematic diagram of an insulating layer in one embodiment of the present disclosure.
[0049] Figure 8 Schematic diagram of an insulating layer in one embodiment of the present disclosure.
[0050] Figure 9 Schematic diagram of an insulating layer in one embodiment of the present disclosure.
[0051] Figure 10 Schematic diagram of the connection between the capacitor and the contact structure in one embodiment of the present disclosure.
[0052] Figure 11 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.
[0053] Figure 12 To form the initial active column trailing edge in the embodiment of the present disclosure Figure 4 Schematic diagram of the section taken along the aa' direction.
[0054] Figure 13 Schematic diagram of an epitaxial layer in one embodiment of the present disclosure.
[0055] Figure 14 Schematic diagram of an epitaxial layer in one embodiment of the present disclosure.
[0056] Figure 15 Schematic diagram of an epitaxial layer in one embodiment of the present disclosure.
[0057] Figure 16 Schematic diagram of forming a metal layer after forming an insulating layer in an embodiment of the present disclosure.
[0058] Figure 17 This is a schematic diagram of forming a metal layer after forming an insulating layer in another embodiment of the present disclosure.
[0059] Figure 18 This is a schematic diagram of forming a metal layer after forming an insulating layer in another embodiment of the present disclosure.
[0060] Figure 19 3 is a schematic diagram of a structure after completing step S350 in an embodiment of the present disclosure.
[0061] Figure 20 3 is a structural diagram after completing step S350 in another embodiment of the present disclosure.
[0062] Figure 21 3 is a structural diagram after completing step S350 in another embodiment of the present disclosure.
[0063] Figure 22 Schematic diagram of forming a metal layer after forming an epitaxial layer in an embodiment of the present disclosure.
[0064] Figure 23This is a schematic diagram of forming a metal layer after forming an epitaxial layer in another embodiment of the present disclosure.
[0065] Figure 24 This is a schematic diagram of forming a metal layer after forming an epitaxial layer in another embodiment of the present disclosure.
[0066] Description of reference numerals:
[0067] 1. Substrate; 101. First trench; 102. Second trench; 103. Initial active pillar; 11. Base; 111. Active pillar; 110. Active pillar group; 12. Isolation layer; 13. Recess; 2. Contact structure; 21. Epitaxial portion; 22. Contact portion; 3. Insulating layer; 4. Epitaxial layer; 5. Metal layer; 6. Word line; 7. Capacitor; 81. First support layer; 82. Second support layer; 9. Insulating dielectric layer; θ, opening angle; x, first direction; y, second direction. DETAILED DESCRIPTION
[0068] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0069] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.
[0070] The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first" and "second" are used only as labels and are not intended to limit the quantity of their objects.
[0071] With the development of semiconductor technology, the size requirements of semiconductor devices are getting higher and higher, that is, the size of transistor units integrated on the substrate is getting smaller and smaller, thus gradually proposing 4F with vertical channel. 2 (F represents the minimum feature size) vertical channel transistor. Compared with the planar 6F 2 Architecture transistor, 4F 2 The vertical transistor unit of the architecture is smaller in area, allowing more transistor units to be arranged within the same area. However, the contact structure process between the active pillar and the capacitor of the vertical channel transistor is complex in manufacturing and has high production costs.
[0072] Based on this, the present disclosure provides a semiconductor structure, such as Figure 1-Figure 3 As shown, the semiconductor structure includes a substrate 1 and a contact structure 2, wherein:
[0073] The substrate 1 includes a base 11 and an isolation layer 12. The base 11 has a plurality of active pillars 111 spaced apart from each other. The isolation layer 12 is located between the active pillars 111. The top surface of the active pillars 111 is lower than the top surface of the isolation layer 12. The active pillars 111 and the isolation layer 12 together form a plurality of recesses.
[0074] The contact structure 2 includes a connected extension portion 21 and a contact portion 22, wherein the extension portion 21 is located on the active pillar 111, and at least partially located in the recess; the contact portion 22 is located on the side of the extension portion 21 away from the active pillar 111, and the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1; the contact portion 22 is used to connect the capacitor.
[0075] The semiconductor structure disclosed in the present invention has a contact structure 2 including a connected epitaxial portion 21 and a contact portion 22. Since the area of the top surface of the contact portion 22 for connecting to the capacitor on the surface of the substrate 1 is larger than the area of the active column 111 on the surface of the substrate 1, the contact area between the contact portion 22 and the capacitor is relatively large, which can ensure the safety window of the capacitor, help reduce the contact resistance between the capacitor and the contact portion 22, improve the charge transfer efficiency and signal integrity, and improve the conductivity. At the same time, since the periphery of the recess is surrounded by the isolation layer 12, in the process of forming the epitaxial portion 21 and the contact portion 22, the isolation layer 12 can play a self-alignment and limiting role, which can not only accurately control the lateral dimensions of the epitaxial growth of the epitaxial portion 21 and the contact portion 22, but also avoid the steps of multiple mask alignment and multiple etching required in the traditional process. That is, the semiconductor structure disclosed in the present invention can reduce the probability of short circuit between two adjacent contact portions 22 due to connection without going through multiple mask and multiple etching processes. The preparation process is relatively simple and the production cost is low.
[0076] The following describes in detail the various parts of the semiconductor structure disclosed herein and their specific details:
[0077] The substrate 1 may include a base 11 and an isolation layer 12, wherein:
[0078] The substrate 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is imposed on the shape and material of the substrate 11.
[0079] like Figure 4 As shown, the substrate 11 may include a plurality of first grooves 101 and a plurality of second grooves 102, wherein the first grooves 101 may be strip-shaped, the plurality of first grooves 101 may be spaced apart along a first direction x, and each first groove 101 may extend along a second direction y. The second grooves 102 may also be strip-shaped, the second grooves 102 may extend along the first direction x, and the plurality of second grooves 102 may be spaced apart along the second direction y.
[0080] In some embodiments of the present disclosure, the second direction y may intersect with the first direction x; for example, the first direction x and the second direction y may be perpendicular to each other. It should be noted that perpendicularity can be absolutely perpendicular or approximately perpendicular. Deviations are inevitable during the manufacturing process. In the present disclosure, the angle deviation may be caused by manufacturing process limitations, resulting in a certain deviation in the angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within a preset range, the first direction x and the second direction y can be considered perpendicular. For example, the preset range can be 10°, that is, the first direction x and the second direction y can be considered perpendicular when the angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°.
[0081] Please continue to see Figure 4 As shown, each first trench 101 and each second trench 102 can divide the substrate 11 into a plurality of spaced-apart active pillars 111. The active pillars 111 can extend in a direction perpendicular to the surface of the substrate 11. The plurality of active pillars 111 can form a plurality of active pillar groups 110 spaced-apart along the second direction y. Each active pillar group 110 can include a plurality of active pillars 111 spaced-apart along the first direction x. It should be noted that a first trench 101 is formed between two adjacent active pillars 111 in the same active pillar group 110, and a second trench 102 is formed between two adjacent active pillar groups 110.
[0082] In some embodiments of the present disclosure, the active pillar 111 may include a first source / drain region, a channel region, and a second source / drain region distributed sequentially from bottom to top along its length. In an exemplary embodiment of the present disclosure, each active pillar group 110 is provided with a corresponding word line 6. The word line 6 may extend along a first direction x and may wrap around the periphery of the channel region of all active pillars 111 in the same active pillar group 110. An insulating dielectric layer 9 may be provided below the word line 6. The insulating dielectric layer 9 may be used to insulate and isolate the word line 6 from a bit line (not shown) provided at the bottom of the active pillar 111, thereby helping to improve device reliability.
[0083] The isolation layer 12 may be located between the active pillars 111 and may fill the gaps between the active pillars 111. It should be noted that when word lines 6 are provided in the substrate 1, the isolation layer 12 may cover the word lines 6 and fill the spaces between adjacent word lines 6.
[0084] The material of the isolation layer 12 may be an insulating material, for example, silicon nitride or silicon oxide. Figure 5 and Figure 6 As shown, the top surface of the active column 111 may be lower than the top surface of the isolation layer 12, and the active column 111 and the isolation layer 12 together form a plurality of recesses 13, that is, the top surface of each active column 111 may form a recess 13 with the isolation layer 12, and a recess 13 is provided at the top of each active column 111, and the bottom surface of the recess 13 is the top surface of the active column 111, and the side walls of the recess 13 are surrounded by the isolation layer 12.
[0085] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 5 As shown, in the direction parallel to the surface of the substrate 1, the bottom surface of the recess 13 may be a plane, that is, the top surface of the active pillar 111 is a plane; in another exemplary embodiment of the present disclosure, please continue to refer to Figure 6 As shown, the bottom surface of the recess 13 may be a concave surface, that is, the top surface of the active pillar 111 may be a concave surface. For example, the distance between the top and bottom of the concave surface may be greater than 0 nm and less than or equal to 30 nm. For example, the distance between the top and bottom of the concave surface may be 2 nm, 5 nm, 10 nm, 20 nm, or 30 nm. Of course, the distance between the top and bottom of the concave surface may also be other values, which are not particularly limited here.
[0086] In an exemplary embodiment of the present disclosure, the depth of the recess 13 in the length direction of the active pillar 111 can be 5nm to 30nm. Within this range, it can be ensured that in the subsequent epitaxial growth process, the epitaxially grown film layer can fill the recess 13, so that the shape of the subsequent film layer epitaxially grown above the isolation layer 12 will not be affected by the shape of the recess 13 and will present a smaller projected area on the substrate 1; at the same time, it can also ensure that the subsequent film layer epitaxially grown above the isolation layer 12 can be in close contact with the isolation layer 12 adjacent to the recess 13, reducing the probability of gaps between the epitaxially grown film layer and the isolation layer 12, which helps to reduce structural defects.
[0087] It should be noted that the depth of the recess 13 may be the distance from the top surface of the isolation layer 12 to the lowest point in the bottom surface of the recess 13. For example, when the recess 13 is a concave surface and the depth of the recess 13 is 5nm, the distance between the top of the concave surface of the recess 13 and the top surface of the isolation layer 12 may be 3nm, and at the same time, the distance between the top of the concave surface of the recess 13 and the bottom of the concave surface may be 2nm; when the recess 13 is a concave surface and the depth of the recess 13 is 10nm, the distance between the top of the concave surface of the recess 13 and the top surface of the isolation layer 12 may be 5nm, and at the same time, the distance between the top of the concave surface of the recess 13 and the bottom of the concave surface may be 5nm; when the recess 13 is a concave surface and the depth of the recess 13 is 20nm, the distance between the top of the concave surface of the recess 13 and the top surface of the isolation layer 12 may be 10nm, and at the same time, the distance between the top of the concave surface of the recess 13 and the bottom of the concave surface may be 5nm. When the recess 13 is concave, the distance between the top of the concave surface of the recess 13 and the bottom of the concave surface may be 10 nm; when the recess 13 is concave, the depth of the recess 13 is 25 nm, the distance between the top of the concave surface of the recess 13 and the top surface of the isolation layer 12 may be 5 nm, and at the same time, the distance between the top of the concave surface of the recess 13 and the bottom of the concave surface may be 20 nm; when the recess 13 is concave, the depth of the recess 13 is 30 nm, the distance between the top of the concave surface of the recess 13 and the top surface of the isolation layer 12 may be 0 nm, and at the same time, the distance between the top of the concave surface of the recess 13 and the bottom of the concave surface may be 30 nm, that is, the recess 13 may start to be recessed downward from a position flush with the isolation layer 12.
[0088] In an exemplary embodiment of the present disclosure, the bottom surface of the recess 13 may be a "V"-shaped surface, and the opening angle θ of the "V"-shaped surface may be greater than 0° and less than or equal to 75°. It should be noted that the smaller the "V"-shaped opening angle θ, the easier it is for the interior of the recess 13 to be filled during the subsequent epitaxial growth process therein, which can further ensure that the shape of the film layer subsequently epitaxially grown above the isolation layer 12 will not be affected by the shape of the recess 13 and present a smaller projected area on the substrate 1. Preferably, the opening angle θ of the "V"-shaped surface may be greater than 0° and less than or equal to 45°. For example, the opening angle θ of the "V"-shaped surface may be 10°, 20°, 30°, 40° or 45°. Of course, it may also be other opening angles θ, which are not listed here one by one.
[0089] Please continue to see Figure 1-Figure 3 As shown, the contact structure 2 may include an epitaxial portion 21 and a contact portion 22 connected to each other, wherein the epitaxial portion 21 may be located on the active pillar 111, and the epitaxial portion 21 is at least partially located in the recess 13, and the contact portion 22 is located on a side of the epitaxial portion 21 away from the active pillar 111, and the contact portion 22 is located above the isolation layer 12. That is, the top surface of the contact portion 22 is higher than the top surface of the isolation layer 12. In addition, in the length direction of the active pillar 111, the distance between the top of the contact portion 22 and the top surface of the isolation layer 12 is less than or equal to 30 nm. For example, the distance between the top of the contact portion 22 and the top surface of the isolation layer 12 may be 15 nm, 18 nm, 21 nm, 24 nm, 27 nm, or 30 nm.
[0090] Please continue to see Figure 1-Figure 3 As shown, the epitaxial portion 21 may fill the recess 13, and at least a portion of the epitaxial portion 21 may be located above the isolation layer 12. The contact portion 22 is in contact with the end of the epitaxial portion 21 away from the active pillar 111, and the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1. For example, in a direction parallel to the surface of the substrate 1, the ratio of the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1 to the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 may be 1:1.5 to 1:3. For example, in the direction parallel to the surface of the substrate 1, the ratio of the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1 to the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 may be 1:1.5, 1:2, 1:2.5 or 1:3. Of course, other ratios may also be possible, as long as the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1.
[0091] In an exemplary embodiment of the present disclosure, both the contact portion 22 and the epitaxial portion 21 may include dopant ions. Doping with ions can improve the electrical conductivity of the contact portion 22 and the epitaxial portion 21, thereby improving charge transfer performance. For example, the dopant ions may include at least one of P (phosphorus), B (boron), As (arsenic), C (carbon), and Ge (germanium).
[0092] In an exemplary embodiment of the present disclosure, the doping concentration of the doping ions may be greater than 0 and less than or equal to 2×e 22 atom / cm3. It should be noted that when the doping concentration is 0, it can be considered that there is no doping in the contact portion 22 and the epitaxial portion 21. When the doping concentration is greater than 0, both the contact portion 22 and the epitaxial portion 21 contain doping ions, and the greater the doping concentration, the better the conductive properties of the contact portion 22 and the epitaxial portion 21. For example, the doping concentration can be 1×e 10 atom / cm3、2×e 10 atom / cm3、1×e 15 atom / cm3、2×e 15 atom / cm3、1×e 20 atom / cm3、2×e 20 atom / cm3、1×e 22 atom / cm3 or 2×e 22 atom / cm3, etc.
[0093] In an exemplary embodiment of the present disclosure, the active pillar 111 may be made of single crystal silicon. In the absence of doping, the epitaxial portion 21 may be made of single crystal silicon. In the absence of doping, the epitaxial portion 21 may be made of silicon phosphide, silicon boride, silicon arsenide, silicon carbide, or silicon germanium. The contact portion 22 may be made of a metal silicide, such as nickel silicide or cobalt silicide. If the contact portion 22 includes dopant ions, the contact portion 22 may be made of nickel silicide or cobalt silicide containing the dopant ions.
[0094] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 7-Figure 9 As shown, the semiconductor structure of the present disclosure may further include an insulating layer 3, which is located between the contact structures 2 and exposes the top surface of the contact portion 22. The insulating layer 3 may be made of silicon nitride. The insulating layer 3 may fill the gaps between the contact structures 2 and isolate adjacent contact structures 2 via the insulating layer 3, thereby reducing the probability of coupling between adjacent contact structures 2.
[0095] In an exemplary embodiment of the present disclosure, Figure 10As shown, the contact portion 22 can be used to connect to the capacitor 7. Since the material of the contact portion 22 is metal silicide, the contact resistance between the contact portion 22 and the capacitor 7 is small, which helps to reduce power consumption, shorten the RC delay, and improve the switching speed of the transistor. At the same time, since the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1, the contact area between the contact portion 22 and the capacitor 7 is relatively large, which helps to reduce the contact resistance between the capacitor 7 and the contact portion 22, thereby improving the charge transfer efficiency and signal integrity, and enhancing the conductivity.
[0096] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 10 As shown, there are multiple capacitors 7, that is, each contact portion 22 is respectively provided with a capacitor 7, and a support layer is provided between adjacent capacitors 7. For example, a first support layer 81 is provided on the outer periphery of the bottom of adjacent capacitors 7, and the other parts between adjacent capacitors 7 are filled with a second support layer 82. Each capacitor 7 can be supported by the first support layer 81 and the second support layer 82 to prevent the capacitor 7 from collapsing, which helps to improve product yield.
[0097] The present disclosure also provides a method for forming a semiconductor structure, which is used to form the semiconductor structure in any of the above embodiments, such as Figure 11 As shown, the forming method includes step S110 and step S120, wherein:
[0098] Step S110, forming a substrate, the substrate including a base and an isolation layer, the base having a plurality of active pillars spaced apart; the isolation layer being located between the active pillars, the top surface of the active pillars being lower than the top surface of the isolation layer, and the active pillars and the isolation layer together forming a plurality of recesses;
[0099] Step S120, forming a contact structure, the contact structure includes a connected epitaxial portion and a contact portion, the epitaxial portion is located on the active pillar, and the epitaxial portion is at least partially located in the recess; the contact portion is located on the side of the epitaxial portion away from the active pillar, and the area of the orthographic projection of the top surface of the contact portion on the surface of the substrate is larger than the area of the orthographic projection of the active pillar on the surface of the substrate; the contact portion is used to connect a capacitor.
[0100] Compared with the prior art, the beneficial effects of the method for forming a semiconductor structure provided by the present disclosure are the same as the beneficial effects of the semiconductor structure provided by the above-mentioned example embodiments, and are not described in detail here.
[0101] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:
[0102] In an exemplary embodiment of the present disclosure, a substrate 1 is formed, the substrate 1 including a base 11 and an isolation layer 12, the base 11 having a plurality of spaced active pillars 111; the isolation layer 12 is located between the active pillars 111, the top surface of the active pillars 111 is lower than the top surface of the isolation layer 12, and the active pillars 111 and the isolation layer 12 together enclose a plurality of recesses 13 (i.e., step S110), which may include steps S210 to S230, wherein:
[0103] In step S210 , the substrate 11 is etched to form a plurality of initial active pillars 103 spaced apart in the substrate 11 .
[0104] The substrate 11 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be a semiconductor material, for example, its material may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is imposed on the shape and material of the substrate 11.
[0105] Please continue to see Figure 4 As shown, the substrate 11 can be etched by an etching process to form a plurality of semiconductor rectangular blocks extending along the second direction y and a plurality of first trenches 101 extending along the second direction y, and the plurality of semiconductor rectangular blocks and the plurality of first trenches 101 are alternately distributed along the first direction x. An isolation material can be filled in each first trench 101 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the isolation material can fill the first trench 101, and the top surface of the isolation material is flush with the top surface of the semiconductor rectangular block. The structure composed of each semiconductor rectangular block and the isolation material is etched to form a plurality of second trenches 102 extending along the first direction x and spaced apart along the second direction y; the first trenches 101 and the second trenches 102 divide the substrate 11 into a plurality of initial active pillars 103, as shown in FIG. Figure 12 shown.
[0106] Step S220 , forming an isolation layer 12 to fill the gaps between the initial active pillars 103 , wherein the top surface of the isolation layer 12 is flush with the top surface of the initial active pillars 103 .
[0107] The second trench 102 may be filled with an isolation material by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The isolation material may completely fill the second trench 102, and the top surface of the isolation material may be flush with the top surface of the initial active pillar 103. The isolation material in the first trench 101 and the isolation material in the second trench 102 may be collectively defined as an isolation layer 12.
[0108] In step S230 , the initial active pillars 103 are etched so that the top surface of the remaining initial active pillars 103 is lower than the top surface of the isolation layer 12 ; the remaining initial active pillars 103 are used as active pillars 111 , and the space enclosed by the active pillars 111 and the isolation layer 12 is used as the recess 13 .
[0109] Please continue to see Figure 5 and Figure 6 As shown, after forming the isolation layer 12, the initial active pillar 103 can be etched back to form an active pillar 111. The space formed by the top surface of the active pillar 111 formed after the back etching and the isolation layer 12 can be used as a recess 13. It should be noted that the top surface of each active pillar 111 can form a recess 13 with the isolation layer 12, that is, a recess 13 is provided on the top of each active pillar 111, and the bottom surface of the recess 13 is the top surface of the active pillar 111, and the sidewalls of the recess 13 are formed by the isolation layer 12.
[0110] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 5 As shown, in the direction parallel to the surface of the substrate 1, the bottom surface of the recess 13 may be a plane, that is, the top surface of the active pillar 111 is a plane; in another exemplary embodiment of the present disclosure, please continue to refer to Figure 6 As shown, the bottom surface of the recess 13 may be a concave surface, that is, the top surface of the active pillar 111 may be a concave surface. For example, the distance between the top and bottom of the concave surface may be greater than 0 nm and less than or equal to 30 nm. For example, the distance between the top and bottom of the concave surface may be 2 nm, 5 nm, 10 nm, 20 nm, or 30 nm. Of course, the distance between the top and bottom of the concave surface may also be other values, which are not particularly limited here.
[0111] In an exemplary embodiment of the present disclosure, the depth of the recess 13 in the length direction of the active pillar 111 can be 5nm to 30nm. Within this range, it can be ensured that in the subsequent epitaxial growth process, the epitaxially grown film layer can fill the recess 13, so that the shape of the subsequent film layer epitaxially grown above the isolation layer 12 will not be affected by the shape of the recess 13 and will present a smaller projected area on the substrate 1; at the same time, it can also ensure that the subsequent film layer epitaxially grown above the isolation layer 12 can be in close contact with the isolation layer 12 adjacent to the recess 13, reducing the probability of gaps between the epitaxially grown film layer and the isolation layer 12, which helps to reduce structural defects.
[0112] In an exemplary embodiment of the present disclosure, the bottom surface of the recess 13 may be a "V"-shaped surface, and the opening angle θ of the "V"-shaped surface may be greater than 0° and less than or equal to 75°. It should be noted that the smaller the "V"-shaped opening angle θ, the easier it is for the interior of the recess 13 to be filled during the subsequent epitaxial growth process therein, which can further ensure that the shape of the film layer subsequently epitaxially grown above the isolation layer 12 will not be affected by the shape of the recess 13 and present a smaller projected area on the substrate 1. Preferably, the opening angle θ of the "V"-shaped surface may be greater than 0° and less than or equal to 45°. For example, the opening angle θ of the "V"-shaped surface may be 10°, 20°, 30°, 40° or 45°. Of course, it may also be other opening angles θ, which are not listed here one by one.
[0113] In step S120, a contact structure 2 is formed, which includes a connected extension portion 21 and a contact portion 22. The extension portion 21 is located on the active pillar 111, and the extension portion 21 is at least partially located in the recess 13; the contact portion 22 is located on the side of the extension portion 21 away from the active pillar 111, and the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1; the contact portion 22 is used to connect the capacitor.
[0114] Please continue to see Figure 1-Figure 3 As shown, the epitaxial portion 21 can fill the recess 13, and at least a portion of the epitaxial portion 21 can be located above the isolation layer 12. The contact portion 22 is in contact with the end of the epitaxial portion 21 away from the active pillar 111, and the top surface of the contact portion 22 is higher than the top surface of the isolation layer 12. In addition, along the length direction of the active pillar 111, the distance between the top of the contact portion 22 and the top surface of the isolation layer 12 is less than or equal to 30 nm. For example, the distance between the top of the contact portion 22 and the top surface of the isolation layer 12 can be 15 nm, 18 nm, 21 nm, 24 nm, 27 nm, or 30 nm.
[0115] Please continue to see Figure 1-Figure 3 As shown, the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1. For example, in a direction parallel to the surface of the substrate 1, the ratio of the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1 to the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 may be 1:1.5 to 1:3. For example, in a direction parallel to the surface of the substrate 1, the ratio of the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1 to the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 may be 1:1.5, 1:2, 1:2.5, or 1:3. Of course, other ratios are also possible, as long as the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1.
[0116] In an exemplary embodiment of the present disclosure, Figure 10 As shown, contact portion 22 can be used to connect capacitor 7. Because contact portion 22 is made of metal silicide, the contact resistance between contact portion 22 and capacitor 7 is low, which helps reduce power consumption, shortens RC delay, and improves the switching speed of the transistor. At the same time, because the orthographic projection area of the top surface of contact portion 22 on the surface of substrate 1 is larger than the orthographic projection area of active pillar 111 on the surface of substrate 1, the contact area between contact portion 22 and capacitor 7 is relatively large, which helps reduce the contact resistance between capacitor 7 and contact portion 22, thereby improving charge transfer efficiency and signal integrity.
[0117] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 7-Figure 9 As shown, an insulating layer 3 is formed between each contact structure 2, and the insulating layer 3 can expose the top surface of the contact portion 22. The insulating layer 3 can be made of silicon nitride and can fill the gaps between the contact structures 2. The insulating layer 3 can be used to isolate adjacent contact structures 2, thereby reducing the probability of coupling between adjacent contact structures 2.
[0118] In an exemplary embodiment of the present disclosure, the method for forming the contact structure 2 and the insulating layer 3 includes steps S310 to S350, wherein:
[0119] In step S310, an epitaxial layer 4 is formed on the top of the active pillar 111 using an epitaxial growth process. The top of the epitaxial layer 4 is higher than the top surface of the isolation layer 12, and the area of the orthographic projection of the top surface of the epitaxial layer 4 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1.
[0120] In an exemplary embodiment of the present disclosure, the material of the active pillar 111 may be single crystal silicon, and the material of the isolation layer 12 may be silicon nitride or silicon oxide, such as Figure 13-15 As shown, an epitaxial growth process can be used to form an epitaxial layer 4 on top of the active pillar 111. The epitaxial layer 4 can fill the recess 13 and extend above the isolation layer 12. During this process, due to the lattice mismatch between single crystal silicon and silicon nitride, the difference in surface chemical bonds, and selective etching, the epitaxial growth occurs only on the surface of the single crystal silicon. Therefore, during the epitaxial growth process, the isolation layer 12 can be used to self-align and limit the epitaxial layer 4, thereby precisely controlling the lateral size of the epitaxial layer 4. The preparation process is relatively simple and the production cost is low.
[0121] In an exemplary embodiment of the present disclosure, during the epitaxial growth process to form the epitaxial layer 4, the shape of the epitaxial layer 4 can be controlled by controlling the temperature, pressure, and etchant concentration in the epitaxial equipment. Experimental findings show that the higher the temperature, the more rounded the surface of the epitaxial layer 4, the greater the pressure, the more rounded the surface of the epitaxial layer 4, and the greater the etchant concentration, the more distinct the edges and corners of the surface of the epitaxial layer 4. The shape of the epitaxial layer 4 can be adjusted by coordinating the etchant concentration, pressure, and temperature. For example, the shape of the portion of the epitaxial layer 4 that is higher than the isolation layer 12 can be triangular, rhombus, semicircular, circular, elliptical, polygonal, or irregular by adjusting the etchant concentration, temperature, and pressure.
[0122] In an exemplary embodiment of the present disclosure, during the epitaxial growth process, a doping gas may be added to the precursor (i.e., the epitaxial process precursor includes a doping gas), so that the ultimately formed epitaxial layer 4 includes doping ions. The doping ions can improve the conductivity of the contact portion 22 and the epitaxial portion 21, thereby improving the charge transfer performance. For example, the doping ions may include at least one of P (phosphorus), B (boron), As (arsenic), C (carbon), and Ge (germanium).
[0123] In an exemplary embodiment of the present disclosure, the doping concentration of the doping ions may be greater than 0 and less than or equal to 2×e 22 atom / cm3. It should be noted that when the doping concentration is 0, it can be considered that there is no doping in the contact portion 22 and the epitaxial portion 21. When the doping concentration is greater than 0, both the contact portion 22 and the epitaxial portion 21 contain doping ions, and the greater the doping concentration, the better the conductive properties of the contact portion 22 and the epitaxial portion 21. For example, the doping concentration can be 1×e 10 atom / cm3、2×e 10 atom / cm3、1×e 15 atom / cm3、2×e 15 atom / cm3、1×e 20 atom / cm3、2×e 20 atom / cm3、1×e 22 atom / cm3 or 2×e 22 atom / cm3, etc.
[0124] Step S320 , forming an insulating layer 3 between each epitaxial layer 4 .
[0125] An insulating material can be deposited on the surface of the structure formed by the epitaxial layer 4 and the substrate 1 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. This insulating material can fill the gaps between adjacent epitaxial layers 4. The insulating material can then be etched back to expose the top surface of the epitaxial layer 4. The area of the orthographic projection of this top surface on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1. For example, the area of the orthographic projection of the top surface of the epitaxial layer 4 on the surface of the substrate 1 can be 1.5 to 3 times the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1. The insulating material remaining after the etch back can be used as the insulating layer 3. Alternatively, a chemical mechanical polishing process can be used to polish the insulating material and the epitaxial layer 4, and the surface of the remaining epitaxial layer 4 after polishing is no longer covered by the insulating material, and the area of the orthographic projection of the top surface of the remaining epitaxial layer 4 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1; for example, the area of the orthographic projection of the top surface of the remaining epitaxial layer 4 on the surface of the substrate 1 can be 1.5 times to 3 times the area of the orthographic projection of the active pillar 111 on the surface of the substrate 1, and the insulating material remaining after polishing can be used as the insulating layer 3.
[0126] Step S330 , forming a metal layer 5 on the epitaxial layer 4 .
[0127] The material of the metal layer 5 can be cobalt or nickel, such as Figure 16-Figure 18 As shown, a metal layer 5 can be formed on the exposed surface of the epitaxial layer 4 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the metal layer 5 can conformally cover the surface of the structure composed of the epitaxial layer 4 and the insulating layer 3.
[0128] In step S340, the metal layer 5 is heat-treated so that the metal layer 5 reacts with the epitaxial layer 4 to form a contact portion 22. The top of the contact portion 22 is higher than the top surface of the isolation layer 12, and the area of the orthographic projection of the top surface of the contact portion 22 on the surface of the substrate 1 is larger than the area of the orthographic projection of the active column 111 on the surface of the substrate 1. The epitaxial layer 4 that has not reacted with the metal layer 5 is used as the epitaxial portion 21, and the epitaxial portion 21 is at least partially located in the recess 13.
[0129] During the heat treatment process, the metal ions in the metal layer 5 can diffuse into the epitaxial layer 4, and then react with the silicon in the epitaxial layer 4 to form metal silicide. The metal silicide can be used as the contact part 22, and the part of the epitaxial layer 4 that does not react with the metal ions can be used as the epitaxial part 21.
[0130] Step S350 , removing the unreacted metal layer 5 .
[0131] The metal layer 5 that has not reacted with the epitaxial layer 4 can be removed by etching, thereby exposing the surface of the formed contact portion 22 so as to facilitate the subsequent formation of the capacitor 7 thereon. In the present disclosure, the structure after completing step S350 is as follows Figures 19-21 shown.
[0132] In another exemplary embodiment of the present disclosure, Figure 22-Figure 24 As shown, after the epitaxial layer 4 is formed (i.e., after step S310 is performed), a metal layer 5 can be formed on the surface of the structure formed by the epitaxial layer 4 and the isolation layer 12. The metal layer 5 can conformally cover the surface of the structure formed by the epitaxial layer 4 and the isolation layer 12. The metal layer 5 can be heat-treated to react with the epitaxial layer 4 to form a contact portion 22 including a metal silicide. The epitaxial layer 4 that has not reacted with the metal layer 5 is used as the epitaxial portion 21. Subsequently, the metal layer 5 that has not reacted with the epitaxial layer 4 can be removed, and then an insulating layer 3 is formed between each contact portion 22. In this embodiment, the structure after the contact portion 22 is formed is as shown. Figure 1-Figure 3 As shown, the structure after forming the insulating layer 3 is as follows Figure 7-Figure 9 shown.
[0133] In an exemplary embodiment of the present disclosure, a plurality of active pillars 111 may form a plurality of active pillar groups 110 spaced apart along the second direction y, and each active pillar group 110 may include a plurality of active pillars 111 spaced apart along the first direction x. The active pillar 111 may include a first source and drain region, a channel region, and a second source and drain region sequentially distributed from bottom to top along its length. Before forming the contact structure 2, a word line may be formed corresponding to each active pillar group 110. The word line may extend along the first direction x and may be wrapped around the periphery of the channel region of all active pillars 111 in the same active pillar group 110. An insulating dielectric layer 9 may be formed under the word line 6. The insulating dielectric layer 9 may be used to insulate and isolate the word line 6 from the bit line (not shown) provided at the bottom of the active pillar 111, thereby helping to improve device reliability.
[0134] In an exemplary embodiment of the present disclosure, after forming the contact structure 2, a first supporting layer 81 and a second supporting layer 82 may be sequentially formed on the structure formed by the contact structure 2 and the insulating layer 3. The second supporting layer 82 and the first supporting layer 81 may be etched to form a plurality of capacitor holes that respectively expose the contact portions 22, and capacitors 7 may be formed in the capacitor holes. It should be noted that due to the relatively large area of the top surface of the contact portion 22, the process window for forming the capacitor 7 is larger. At the same time, the contact area between the capacitor 7 and the contact portion 22 is larger, and the contact resistance is smaller.
[0135] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.
[0136] The present disclosure further provides a semiconductor device, which is obtained by bonding the semiconductor structure of any of the above embodiments to a target wafer. The specific details, formation process, and beneficial effects of the semiconductor device have been described in detail in the corresponding semiconductor structure and semiconductor structure formation method, and will not be repeated here.
[0137] For example, the semiconductor device can be a memory device or a non-memory device. The memory device can include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change random access memory (PRAM) or a magnetoresistive random access memory (MRAM). The non-memory device can be a logic device (such as a microprocessor, a digital signal processor or a microcontroller) or a device similar thereto. The target wafer has CMOS transistors, etc., for example, the target wafer contains semiconductor devices such as peripheral region transistors in a DRAM, etc. The bonding method between the semiconductor structure and the target wafer can be bump bonding, fusion bonding, hybrid bonding, etc. The bonding method between the semiconductor structure and the target wafer can also be chip-to-chip bonding or wafer-on-wafer bonding.
[0138] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.
Claims
1. A semiconductor structure, characterized in that include: A substrate comprising a base and an isolation layer, wherein the base has a plurality of active pillars distributed at intervals; The isolation layer is located between the active pillars, the top surface of the active pillar is lower than the top surface of the isolation layer, and the active pillars and the isolation layer together form a plurality of recesses; A contact structure includes a connected epitaxial portion and a contact portion, wherein the epitaxial portion is located on the active pillar and at least partially located within the recess; the contact portion is located on a side of the epitaxial portion away from the active pillar, and the area of the orthographic projection of the top surface of the contact portion on the surface of the substrate is greater than the area of the orthographic projection of the active pillar on the surface of the substrate; the contact portion is used to connect a capacitor.
2. The semiconductor structure according to claim 1, wherein: In a direction parallel to the surface of the substrate, a ratio of an area of an orthographic projection of the active pillar on the surface of the substrate to an area of an orthographic projection of a top surface of the contact portion on the surface of the substrate is 1:1.5 to 1:
3.
3. The semiconductor structure according to claim 1, wherein: The top of the contact portion is higher than the top surface of the isolation layer; in the length direction of the active pillar, the distance between the top of the contact portion and the top surface of the isolation layer is less than or equal to 30 nm.
4. The semiconductor structure according to claim 1, wherein: The contact portion and the epitaxial portion both include doping ions, wherein the doping ions include at least one of P, B, As, C and Ge; and / or The doping concentration of the doping ions is greater than 0 and less than or equal to 2×e 22 atom / cm3.
5. The semiconductor structure according to claim 1, wherein: In the length direction of the active pillar, the depth of the recess is 5 nm to 30 nm. The semiconductor structure according to claim 1 , wherein: In a direction parallel to the surface of the substrate, a bottom surface of the recess is a plane.
7. The semiconductor structure according to claim 1, wherein: In a direction parallel to the surface of the substrate, the bottom surface of the recess is a concave surface, wherein a distance between a top end of the concave surface and a bottom end of the concave surface is greater than 0 nm and less than or equal to 30 nm; and / or The bottom surface of the recess is a V-shaped surface, and an opening angle of the V-shaped surface is greater than 0° and less than or equal to 75°.
8. The semiconductor structure according to any one of claims 1 to 7, wherein: The semiconductor structure further comprises: The insulating layer is located between the contact structures.
9. A method for forming a semiconductor structure, characterized in that: include: forming a substrate comprising a base and an isolation layer, wherein the base has a plurality of active pillars distributed at intervals; The isolation layer is located between the active pillars, the top surface of the active pillar is lower than the top surface of the isolation layer, and the active pillars and the isolation layer together form a plurality of recesses; A contact structure is formed, the contact structure comprising a connected epitaxial portion and a contact portion, the epitaxial portion being located on the active pillar and at least partially located within the recess; the contact portion being located on a side of the epitaxial portion away from the active pillar, and an orthographic projection area of a top surface of the contact portion on the surface of the substrate being larger than an orthographic projection area of the active pillar on the surface of the substrate; and the contact portion being used to connect a capacitor.
10. The forming method according to claim 9, wherein: The substrate is formed, the substrate comprising a base and an isolation layer, the base having a plurality of active pillars distributed at intervals; the isolation layer is located between the active pillars, the top surface of the active pillars is lower than the top surface of the isolation layer, and the active pillars and the isolation layer together form a plurality of recesses, including: Etching the substrate to form a plurality of initial active pillars spaced apart in the substrate; forming the isolation layer to fill the gaps between the initial active pillars, wherein the top surface of the isolation layer is flush with the top surface of the initial active pillars; The initial active pillars are etched so that the top surfaces of the remaining initial active pillars are lower than the top surface of the isolation layer; the remaining initial active pillars are used as the active pillars, and the space enclosed by the active pillars and the isolation layer is used as the recessed portion.
11. The forming method according to claim 9, wherein: An insulating layer is formed between the contact structures, and the method of forming the contact structures and the insulating layer includes: forming an epitaxial layer on top of the active pillar using an epitaxial growth process, wherein the top of the epitaxial layer is higher than the top surface of the isolation layer, and the area of the orthographic projection of the top surface of the epitaxial layer on the surface of the substrate is larger than the area of the orthographic projection of the active pillar on the surface of the substrate; forming the insulating layer between the epitaxial layers; forming a metal layer on the epitaxial layer; The metal layer is heat-treated so that the metal layer reacts with the epitaxial layer to form the contact portion, wherein the top of the contact portion is higher than the top surface of the isolation layer, and the area of the orthographic projection of the top surface of the contact portion on the surface of the substrate is larger than the area of the orthographic projection of the active pillar on the surface of the substrate; the epitaxial layer that has not reacted with the metal layer is used as the epitaxial portion, and the epitaxial portion is at least partially located in the recess; removing the unreacted metal layer; Alternatively, the method of forming the contact structure and forming the insulating layer includes: forming an epitaxial layer on top of the active pillar using an epitaxial growth process, wherein the top of the epitaxial layer is higher than the top surface of the isolation layer, and the area of the orthographic projection of the top surface of the epitaxial layer on the surface of the substrate is larger than the area of the orthographic projection of the active pillar on the surface of the substrate; forming a metal layer on a surface of a structure formed by the epitaxial layer and the isolation layer; performing heat treatment on the metal layer so that the metal layer reacts with the epitaxial layer to form the contact portion; using the epitaxial layer that has not reacted with the metal layer as the epitaxial portion, wherein the epitaxial portion is at least partially located in the concave portion; removing the unreacted metal layer; The insulating layer is formed between the contact portions.
12. The forming method according to claim 11, wherein: The precursor of the epitaxial growth process includes a doping gas, so that the epitaxial layer includes doping ions, wherein the doping ions include at least one of P, B, As, C and Ge; and / or The doping concentration of the doping ions is greater than 0 and less than or equal to 2×e 22 atom / cm3.
13. The forming method according to claim 9, wherein: In the length direction of the active pillar, a distance between the top of the contact portion and the top surface of the isolation layer is less than or equal to 30 nm.
14. The forming method according to claim 9, wherein: In a direction parallel to the surface of the substrate, a bottom surface of the recess is a flat surface or a concave surface.
15. A semiconductor device, characterized in that: The semiconductor structure according to any one of claims 1 to 8 is bonded to a target wafer.