Semiconductor device and preparation method thereof, and memory system

Abstract

The invention provides a semiconductor device, a preparation method thereof and a memory system, the semiconductor device comprises a semiconductor structure, and the first semiconductor structure comprises a first stacking structure and a spacing structure; the first stack structure comprises a first insulating layer; the first electrode layers and the first insulating layers are alternately arranged in the first direction; the energy storage structure is located in a first stacking structure formed by the first insulating layer and the first electrode layer; the energy storage structure comprises an energy storage layer and a second electrode layer, and the first electrode layer is arranged around the energy storage layer; the energy storage layers are arranged around the second electrode layers, the energy storage layers are located between the first electrode layers and the second electrode layers, and each second electrode layer comprises at least two electrode parts; the energy storage structure and the first electrode layer form a capacitor structure of the first semiconductor structure, and the spacing structure is located between two adjacent electrode parts. The semiconductor device, the preparation method thereof and the memory system provided by the invention are relatively high in memory density.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a semiconductor device, a manufacturing method thereof, and a memory system. Background Art

[0002] Ferroelectric Random Access Memory (FeRAM) requires flipping the polarization state of a capacitor to determine stored information during reading. Planar FeRAM architectures have low storage density, and this density needs to be further improved. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor device and a manufacturing method thereof, as well as a memory system that can effectively improve storage density.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The present application provides a semiconductor device, including a semiconductor structure, wherein the first semiconductor structure includes a first stacking structure and a spacing structure; the first stacking structure includes: a first insulating layer; a first electrode layer, which is arranged alternately with the first insulating layer in a first direction; and an energy storage structure, which is located in the first stacking structure formed by the first insulating layer and the first electrode layer; the energy storage structure includes an energy storage layer and a second electrode layer, wherein the first electrode layer is arranged around the energy storage layer; the energy storage layer is arranged around the second electrode layer, and the energy storage layer is located between the first electrode layer and the second electrode layer, and a second electrode layer includes at least two electrode portions; the energy storage structure and the first electrode layer constitute a capacitor structure of the first semiconductor structure, and the spacing structure is located between two adjacent electrode portions.

[0006] In some embodiments, the first spacing structure includes multiple first sub-spacer structures, and the first sub-spacer structures extend along a second direction perpendicular to the first direction; wherein the first sub-spacer structures are located between two adjacent electrode portions arranged in a third direction, and the third direction is perpendicular to the first direction and intersects with the second direction.

[0007] In some embodiments, in an energy storage structure, two of the multiple electrode portions are first sub-electrode portions, and the rest are second sub-electrode portions, and the two first sub-electrode portions are located on both sides of at least one second sub-electrode portion in the third direction; wherein, one end of the first sub-electrode portion in the third direction is connected to the energy storage layer, and the other end is connected to the first sub-spacer structure; the two ends of the second sub-electrode portion in the third direction are respectively connected to the first sub-spacer structure.

[0008] In some embodiments, in an energy storage structure, the first sub-spacer structure and two ends of the electrode portion in the second direction are in contact with the energy storage layer respectively.

[0009] In some embodiments, the spacing structure also includes a second sub-spacer structure, which extends along a third direction, and at least one end of the second sub-spacer structure is connected to the first sub-spacer structure; wherein the second sub-spacer structure is located between two adjacent first sub-electrode portions and two adjacent second sub-electrode portions arranged in the second direction.

[0010] In some embodiments, one end of the second sub-spacer structure located between two adjacent first sub-electrode portions is connected to the first sub-spacer structure, and the other end is connected to the energy storage layer; the two ends of the second sub-spacer structure located between two adjacent second sub-electrode portions are respectively connected to the two first sub-spacer structures.

[0011] In some embodiments, multiple energy storage structures are arranged in multiple rows and columns, and the energy storage structures in two adjacent rows are staggered; the energy storage structures in each row are arranged at intervals along a second direction perpendicular to the first direction, and the energy storage structures in each column are arranged at intervals along a third direction perpendicular to the first direction and intersecting the second direction; wherein the spacing structure extends along the second direction or the third direction, and a spacing structure is located between two adjacent electrode portions of the energy storage structures in the same row or column.

[0012] In some embodiments, the spacer structure is further located within the first stacked structure and contacts the first insulating layer and the first electrode layer.

[0013] In some embodiments, at least one cross-section of the energy storage structure perpendicular to the first direction is square or circular.

[0014] In some embodiments, the semiconductor device also includes a first transistor and a second transistor, the first transistor is located on one side of the first semiconductor structure and is connected to the electrode portion of the first semiconductor structure, the first transistor and the second transistor are located on the same side of the first stacked structure in the first direction, and the second transistor is connected to the first transistor.

[0015] In some embodiments, the second transistor is located on a side of the first transistor away from the electrode portion.

[0016] In some embodiments, the second transistor is disposed in the same layer as the first transistor.

[0017] In some embodiments, the semiconductor device also includes a first transistor and a second transistor, which are located on both sides of the first stack structure in the first direction, and the two ends of an electrode portion are respectively connected to a first transistor and a second transistor; wherein, one of the first transistor and the second transistor is configured to be conductive or non-conductive according to the storage content of the capacitor structure of the semiconductor device and allow the storage content of the capacitor structure to be read, and the other is configured to be conductive or non-conductive according to the written content and allow the write voltage to flow into the capacitor structure.

[0018] In some embodiments, the gate of the transistor in the first transistor and the second transistor that allows the storage content of the capacitor structure to be read is connected to the second electrode layer, and the channel layer of the transistor in the first transistor and the second transistor that allows the write voltage to flow into the capacitor structure is connected to the second electrode layer.

[0019] In some embodiments, the semiconductor device further includes a second semiconductor structure bonded to the first semiconductor structure in the first direction. The second semiconductor structure includes a peripheral driving circuit connected to the first transistor or the second transistor.

[0020] The present application also provides a method for preparing a semiconductor device, comprising: forming a first stacking structure, the first stacking structure comprising a first insulating layer and a first electrode layer alternately stacked in a first direction; forming a plurality of energy storage structures in the first stacking structure and connecting the energy storage structures to a first transistor; the energy storage structure comprising an energy storage layer and a second electrode layer, the first electrode layer being arranged around the energy storage layer, the energy storage layer being arranged around the second electrode layer, the energy storage layer being located between the first electrode layer and the second electrode layer, and the second electrode layer being connected to the first transistor; removing a portion of the second electrode layer to form at least one spacing groove in the second electrode layer, the second electrode layers located on both sides of the spacing groove being electrode portions, and one second electrode layer comprising a plurality of electrode portions; and filling the spacing groove with insulating material to form a spacing structure, the spacing structure being located between two adjacent electrode portions; the energy storage structure and the first electrode layer constitute a capacitor structure.

[0021] In some embodiments, during the process of removing a portion of the second electrode layer to form the spacing groove in the second electrode layer, the spacing groove penetrates the second electrode layer in the first direction.

[0022] In some embodiments, the spacing groove further penetrates the first insulating layer and the first electrode layer between two adjacent energy storage structures.

[0023] In some embodiments, the method for preparing the spacing groove includes: removing a portion of the second electrode layer to form a first sub-spacer groove in the second electrode layer; the first sub-spacer groove extends along a second direction perpendicular to the first direction, and the first sub-spacer groove divides the second electrode layer into a plurality of electrode portions arranged in a third direction perpendicular to the first direction and intersecting the second direction; the step of filling the spacing groove with insulating material to form a spacing structure includes: filling the first sub-spacer groove with insulating material to form a first sub-spacer structure.

[0024] In some embodiments, the method for preparing the spacing groove also includes: removing part of the second electrode layer to form a second sub-spacer groove in the second electrode layer that is connected to the first sub-spacer groove; the second sub-spacer groove extends along a third direction, and the second sub-spacer groove divides the second electrode layer into a plurality of electrode portions arranged at intervals in the third direction; the step of filling the spacing groove with insulating material to form a spacing structure also includes: filling the second sub-spacer groove with insulating material to form a second sub-spacer structure; the second sub-spacer structure extends along the third direction and is located between the electrode portions arranged at intervals in the second direction.

[0025] In some embodiments, before the step of forming the first stacking structure, it also includes: forming a second stacking structure including a first transistor and a second transistor connected to the first transistor; in the process of forming the first stacking structure, the second electrode layer of the energy storage structure is connected to the second transistor.

[0026] In some embodiments, during the process of forming the second stack structure including the first transistor, the second stack structure further includes a second transistor, and the second transistor is connected to the first transistor.

[0027] In some embodiments, before the step of forming a first stacking structure, it also includes: forming a second stacking structure including a first transistor; in the process of forming multiple energy storage structures in the first stacking structure, the second electrode layer of the energy storage structure is connected to the first transistor; after the step of filling the spacing groove with insulating material to form a spacing structure, it also includes the step of: forming a third stacking structure including a second transistor on the side of the first stacking structure away from the second stacking structure; wherein the second transistor is connected to the second electrode layer of the energy storage structure, one of the first transistor and the second transistor is configured to be conductive or non-conductive according to the storage content of the capacitor structure and allow the storage content of the capacitor structure to be read, and the other is configured to be conductive or non-conductive according to the written content and allow the write voltage to flow into the capacitor structure.

[0028] The present application also provides a storage system, which includes at least one semiconductor device as described above and a controller, wherein the controller is coupled to the semiconductor device and configured to control the semiconductor device.

[0029] The present application provides a semiconductor device, a preparation method thereof, and a memory system. The semiconductor device includes a semiconductor structure, wherein the first semiconductor structure includes a first stacking structure and a spacing structure; the first stacking structure includes: a first insulating layer; a first electrode layer, which is arranged alternately with the first insulating layer in a first direction; and an energy storage structure, which is located in the first stacking structure formed by the first insulating layer and the first electrode layer; the energy storage structure includes an energy storage layer and a second electrode layer, wherein the first electrode layer is arranged around the energy storage layer; the energy storage layer is arranged around the second electrode layer, and the energy storage layer is located between the first electrode layer and the second electrode layer, and a second electrode layer includes at least two electrode portions; the energy storage structure and the first electrode layer constitute a capacitor structure of the first semiconductor structure, and the spacing structure is located between two adjacent electrode portions. The present application divides the second electrode layer of the capacitor structure into multiple electrode portions through the spacing structure, and the electrode portions, the energy storage layer, and the first electrode layer cooperate to form multiple small sidewall capacitor structures, thereby increasing the storage density of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in some embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1A A top view of a semiconductor device provided in some embodiments of the present application.

[0032] Figure 1B Schematic diagram of a semiconductor device including a second semiconductor structure provided for some embodiments of the present application.

[0033] Figure 2 For the Figure 1A A cross-sectional view of the semiconductor device is shown along the section line AA.

[0034] Figure 3 For the Figure 1A A cross-sectional view of the semiconductor device taken along section line BB is shown.

[0035] Figure 4 For the Figure 1A A cross-sectional view of the semiconductor device is shown along section line CC.

[0036] Figure 5 for Figure 2 A schematic diagram of the connection between the first transistor, the second transistor and the capacitor structure in the semiconductor device shown.

[0037] Figure 6 A flow chart of a method for preparing a semiconductor device provided in some embodiments of the present application.

[0038] Figure 7 This is a cross-sectional view of the second stacking structure provided in this application.

[0039] Figure 8 For Figure 7 A cross-sectional view of a second stacking structure after the first stacking structure is formed is shown.

[0040] Figure 9 For Figure 8 A cross-sectional view of the first stacking structure after a through groove is formed therein is shown.

[0041] Figure 10 For Figure 9 A cross-sectional view of the through-groove after an initial energy storage layer is formed on the inner wall thereof.

[0042] Figure 11 For the general Figure 9 Cross-sectional view of the initial energy storage layer after being prepared as the energy storage layer.

[0043] Figure 12 It is a cross-sectional view after an initial electrode layer is formed on the surface of the first stacking structure away from the second stacking structure and in the through-groove.

[0044] Figure 13 For the general Figure 12 The cross-sectional view of the initial electrode layer after being prepared as the second electrode layer is shown.

[0045] Figure 14 for Figure 13 Top view of .

[0046] Figure 15 It is a cross-sectional view after forming a spacing groove in the first stacking structure.

[0047] Figure 16 for Figure 15 Top view of .

[0048] Figure 17 A cross-sectional view of a semiconductor device provided in accordance with another embodiment of the present application.

[0049] Figure 18 for Figure 17 A schematic diagram of the connection between the first transistor, the second transistor and the capacitor structure in the semiconductor device shown.

[0050] Figure 19 for Figure 18 Flowchart of a method for manufacturing a semiconductor device shown.

[0051] Figure 20 A cross-sectional view of a semiconductor device provided in yet another embodiment of the present application.

[0052] Figure 21 For the Figure 20A cross-sectional view of the semiconductor device along section line EE is shown.

[0053] Figure 22 for Figure 20 Flowchart of a method for manufacturing a semiconductor device shown.

[0054] Figure 23 A cross-sectional view of a semiconductor device provided in yet another embodiment of the present application.

[0055] Figure 24 For the Figure 23 A cross-sectional view of the semiconductor device is shown along section line MM.

[0056] Figure 25 for Figure 23 Flowchart of a method for manufacturing a semiconductor device shown.

[0057] Figure 26 A cross-sectional view of a second stacking structure provided in yet another embodiment of the present application.

[0058] Figure 27 For Figure 26 A cross-sectional view of a second stacking structure after the first stacking structure is formed is shown.

[0059] Figure 28 For Figure 27 A cross-sectional view of the first stacked structure after a through groove is formed therein is shown.

[0060] Figure 29 For Figure 28 The cross-sectional view of the inner wall of the through groove after the energy storage layer is formed is shown.

[0061] Figure 30 For Figure 29 A cross-sectional view after the second electrode layer is formed in the through-groove is shown.

[0062] Figure 31 For Figure 30 A cross-sectional view of the second electrode layer after forming a second sub-spacing groove is shown.

[0063] Figure 32 A module diagram of a memory system provided for some embodiments of the present application. DETAILED DESCRIPTION

[0064] The following will be combined with the accompanying drawings of some embodiments of the present application to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0065] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0066] In the description of the present application, it is to be understood that the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0067] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0068] This application addresses the technical problem of low storage density in a planar FeRAM architecture. The application provides a semiconductor device, a method for manufacturing the same, and a memory system. The semiconductor device includes a first semiconductor structure, the first semiconductor structure including a first stacked structure and a spacing structure. The first stacked structure includes: a first insulating layer; a first electrode layer arranged alternately with the first insulating layer in a first direction; and an energy storage structure located within the first stacked structure formed by the first insulating layer and the first electrode layer. The energy storage structure includes an energy storage layer and a second electrode layer, the first electrode layer being arranged around the energy storage layer; the energy storage layer being arranged around the second electrode layer, the energy storage layer being located between the first electrode layer and the second electrode layer, each second electrode layer including at least two electrode portions. The energy storage structure and the first electrode layer constitute a capacitor structure of the first semiconductor structure, and the spacing structure is located between two adjacent electrode portions. This application divides the second electrode layer of the capacitor structure into multiple electrode portions through the spacing structure, thereby forming multiple small capacitors, thereby increasing the storage density of the semiconductor device. Furthermore, the arrangement density is higher than that of individual square or circular capacitors.

[0069] The following will be combined Figures 1A to 31, specifically describe the specific structure and preparation method of the semiconductor device.

[0070] See also Figures 1A to 5 The present application provides a semiconductor device 100, which includes a first semiconductor structure 110. The first semiconductor structure 110 includes a first stacked structure 20, a spacer structure 29, and an energy storage structure 30. The first stacked structure 20 includes a first electrode layer 21 and a first insulating layer 22. The first electrode layer 21 and the first insulating layer 22 are alternately stacked in a first direction Z. The energy storage structure 30 is located in the stack formed by the first insulating layer 22 and the first electrode layer 21. The energy storage structure 30 includes an energy storage layer 25 and a second electrode layer 27. The first electrode layer 21 is arranged around the energy storage layer 25, and the energy storage layer 25 is arranged around the second electrode layer 27. The energy storage layer 25 is located between the first electrode layer 21 and the second electrode layer 27. One second electrode layer 27 includes at least two electrode portions 271. The energy storage structure 30 and the first electrode layer 21 constitute a capacitor structure 40 of the first semiconductor structure 110. The spacer structure 29 is located between two adjacent electrode portions 271.

[0071] Please refer again Figure 1A and Figure 2 In some embodiments, the spacing structure 29 includes a plurality of first sub-spacing structures 291 , each of which extends along a second direction X perpendicular to the first direction Z. The first sub-spacing structures 291 are located between two adjacent electrode portions 271 arranged in a third direction Y perpendicular to the first direction Z and intersecting the second direction X.

[0072] Please refer again Figure 1A 、 Figure 3 and Figure 4 In some embodiments, the electrode portion 271 extends along the first direction Z and penetrates the stack formed by the first insulating layer 22 and the first electrode layer 21 .

[0073] Please refer again Figure 1A and Figures 2 to 4 In some embodiments, in an energy storage structure 30, the energy storage layer 25 extends along the first direction Z and the third direction Y respectively, and multiple electrode portions 271 and multiple first sub-spacer structures 291 are alternately arranged in the third direction Y. One energy storage layer 25 corresponds to multiple electrode portions 271 and multiple first sub-spacer structures 291.

[0074] Please refer again Figure 1AIn some embodiments, in an energy storage structure 30, two of the multiple electrode portions 271 are first sub-electrode portions 2711, and the remaining are second sub-electrode portions 2712. The two first sub-electrode portions 2711 are located on both sides of at least one second sub-electrode portion 2712 in the third direction X. One end of the first sub-electrode portion 2711 in the third direction Y is connected to the energy storage layer 25, and the other end is connected to the first sub-spacer structure 291. Both ends of the second sub-electrode portion 2712 in the third direction Y are respectively connected to the first sub-spacer structure 291.

[0075] In some embodiments, in an energy storage structure 30 , both ends of the first sub-spacer structure 291 and the electrode portion 271 in the second direction X are in contact with the energy storage layer 25 .

[0076] In some embodiments, multiple energy storage structures 30 are spaced apart along the second direction, the electrode portions 271 of two adjacent energy storage structures 30 are opposite to each other, and the first sub-spacer structures 291 of two adjacent energy storage structures 30 are opposite to each other.

[0077] In some embodiments, at least one cross section of the energy storage structure 30 perpendicular to the first direction Z is square. Of course, the shape of the cross section of the energy storage structure 30 of the present application.

[0078] In some embodiments, the first insulating layer 22 and the first sub-spacer structure 291 are both made of insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the first insulating layer 22 and the first sub-spacer structure 291 are both made of silicon oxide.

[0079] In some embodiments, the materials of the first electrode layer 21 and the second electrode layer 27 include conductive materials, such as single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), titanium (Ti), ruthenium (Ru) or titanium nitride (TiN).

[0080] In some embodiments, the material of the energy storage layer 25 includes a ferroelectric material or an antiferroelectric material. Among them, the ferroelectric material has two or more possible orientations of spontaneous polarization at a finite temperature, and the orientation of this spontaneous polarization can be changed under the action of an electric field. The ions inside the lattice of the antiferroelectric material will undergo spontaneous polarization similar to that of the ferroelectric material, but unlike the ferroelectric material, the adjacent lattices inside the antiferroelectric material have spontaneous polarizations in opposite directions. For example, the material of the energy storage layer 25 can be selected from hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si a (HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a(HfO2) b ) or zirconium oxide (ZrO), etc. Here, a and b are positive numbers. The energy storage layer 25 can be formed by a thin film deposition process, etc.

[0081] See also Figures 2 to 4 The first semiconductor structure 110 further includes a second stacked structure 10 , which is located on one side of the first stacked structure 20 in the first direction Z. The second stacked structure 10 includes a first transistor 11 , which is located on one side of the first semiconductor structure 110 and connected to the second electrode layer 27 of the first semiconductor structure 110 .

[0082] See also Figures 2 to 4 In some embodiments, the second stacking structure 10 further includes a second transistor 13, the first transistor 11 and the second transistor 13 are located on the same side of the first stacking structure 20 in the first direction Z, an electrode portion 271 is connected to the second transistor 13, and the second transistor 13 is connected to the first transistor 11.

[0083] In some embodiments, the first transistor 11 is located on a side of the second transistor 13 away from the electrode portion 271 .

[0084] In some embodiments, the second transistor 13 and the first transistor 11 are in the same layer and spaced apart.

[0085] See also Figure 5 The capacitor structure 40 includes a plurality of sub-capacitors 41, each of which includes a first electrode layer 21 and a portion of an energy storage layer 25 and a second electrode layer 27 corresponding to the first electrode layer 21. The first electrode layer 21 of the plurality of sub-capacitors 41 inputs voltage signals PL1, PL2, PL3, ..., PLn, where n is a positive integer greater than or equal to 1. The second transistor 13 is a storage transistor, the gate of the second transistor 13 is connected to the second electrode layer 27, the source of the second transistor 13 is connected to the source line SL, and the drain of the second transistor 13 is connected to the first transistor 11. The first transistor 11 is a selection transistor, the gate of the first transistor 11 is connected to the word line WL, the source of the first transistor 11 is connected to the bit line BL, and the drain of the first transistor 11 is connected to the drain of the second transistor 13.

[0086] Among them, the first transistor 11 and the second transistor 13 induce different voltages on the first transistor 11 through the capacitive coupling effect of the capacitor structure 40, which can directly determine the storage information on the first electrode layer 21 of the sub-capacitor 41, thereby achieving non-destructive reading. Among them, the first transistor 11 selects the second transistor 13 corresponding to the storage unit (including the capacitor structure 40 and the second transistor 13), and a corresponding voltage of the voltage signals PL1, PL2, PL3, ..., PLn is applied to the gate of the second transistor 13 through the corresponding sub-capacitor structure 41. The source line SL senses the output current generated by the voltage applied to the second transistor 13 to directly determine the storage information on one of the voltage signals PL1, PL2, PL3, ..., PLn, thereby achieving non-destructive reading and improving the storage period life.

[0087] Please refer again Figure 1B In some embodiments, the semiconductor device 100 further includes a second semiconductor structure 120 bonded to the first semiconductor structure 110 in the first direction Z. The second semiconductor structure 120 includes a peripheral driving circuit 1201 connected to the first transistor 11 or the second transistor 13.

[0088] See also Figures 7 to 17 as well as Figure 1A , the present application also provides a method for preparing a semiconductor device 100, comprising:

[0089] Step S2, see Figure 7 and Figure 9 A first stacked structure 20 is formed on one side of the second stacked structure 10 . The first stacked structure 20 includes first insulating layers 22 and first electrode layers 21 alternately stacked in a first direction Z.

[0090] In some embodiments, the first electrode layer 21 is located on one side of the second stacked structure 10 , and the first insulating layer 22 is located on a side of the first electrode layer 21 away from the second stacked structure 10 .

[0091] In some embodiments, before step S2, the following steps are further included: step S1, see Figure 7 and Figure 8 , forming a second stack structure 10 including a first transistor 11 and a second transistor 13 connected to the first transistor 11.

[0092] Accordingly, step S2 includes: forming a first stack structure 20 on one side of the second stack structure 10 , wherein the first stack structure 20 includes first insulating layers 22 and first electrode layers 21 alternately stacked in a first direction Z.

[0093] In this embodiment, the first transistor 11 is located on a side of the second transistor 13 away from the first stacked structure 20 and is connected to the second transistor 13. In other embodiments, the second transistor 13 and the first transistor 11 can also be arranged in the same layer and spaced apart. Among them, the first transistor 11 is located on the side of the second transistor 13 away from the first stacked structure 20, compared with the second transistor 13 and the first transistor 11 being arranged in the same layer and spaced apart, and the density of the capacitor structure formed subsequently is greater.

[0094] Step S3, see Figure 6 and Figures 9 to 14 , multiple energy storage structures 30 are formed in the first stacked structure 20 and the energy storage structures 30 are connected to the first transistor 11; the energy storage structure 30 includes an energy storage layer 25 and a second electrode layer 27, the first electrode layer 21 is arranged around the energy storage layer 25, the energy storage layer 25 is arranged around the second electrode layer 27, and the energy storage layer 25 is located between the first electrode layer 21 and the second electrode layer 27.

[0095] The second electrode layer 27 is connected to the first transistor 11 .

[0096] Step S3 includes: first, refer to Figure 10 , a plurality of through slots 23 are formed in the first stacked structure 20, and the through slots 23 extend along the first direction Z and the third direction Y; secondly, refer to Figure 11 , an initial energy storage layer 24 is formed on the inner wall of the through groove 23 and the surface of the first stacking structure 20 away from the second stacking structure 10; again, refer to Figure 12 , remove the portion of the initial energy storage layer 24 located on the surface of the first stacking structure 20 away from the second stacking structure 10 and the portion of the initial energy storage layer 24 located on the bottom wall of the through groove 23 to obtain the energy storage layer 25 formed on the side wall of the through groove 23; then, refer to Figure 13 , forming an initial electrode layer 26 connected to the first transistor 11 in the through groove 23 and on the surface of the first stacked structure 20 away from the second stacked structure 10; finally, refer to Figure 14 and Figure 15 , a portion of the initial electrode layer 26 located on the surface of the first stacked structure 20 away from the second stacked structure 10 is removed to obtain a second electrode layer 27 , which is located on a side of the energy storage layer 25 away from the first electrode layer 21 .

[0097] In some embodiments, Figure 13 For the Figure 14 In some embodiments, please refer to Figure 15 , the through groove 23 is square.

[0098] Step S4, see Figure 6 、 Figure 15 and Figure 16 , part of the second electrode layer 27 is removed to form at least one spacing groove 28 in the second electrode layer 27 , and the second electrode layer 27 located on both sides of the spacing groove 28 is an electrode portion 271 , and one second electrode layer 27 includes multiple electrode portions 271 .

[0099] The spacing groove 28 penetrates the first stacking structure 20 along the first direction Z, and the second stacking structure 10 is exposed from the spacing groove 28 .

[0100] In some embodiments, the plurality of electrode portions 271 and the plurality of spacing grooves 28 are alternately arranged in the third direction Y, and one energy storage layer 25 corresponds to the plurality of electrode portions 271 and the plurality of spacing grooves 28 .

[0101] In some embodiments, the electrode portion 271 extends along the first direction Z and penetrates the stack formed by the first insulating layer 22 and the first electrode layer 21. Both ends of the electrode portion 271 in the second direction X are respectively connected to the energy storage layer 25. In an energy storage structure 30, two of the multiple electrode portions 271 are first sub-electrode portions 2711, and the rest are second sub-electrode portions 2712. The two first sub-electrode portions 2711 are located on both sides of at least one second sub-electrode portion 2712 in the third direction X. Among them, one end of the first sub-electrode portion 2711 in the third direction Y is connected to the energy storage layer 25, and the other end is connected to the spacing groove 28. The second sub-electrode portion 2712 in the third direction Y is respectively connected to the spacing groove 28 at both ends.

[0102] In some embodiments, multiple energy storage structures 30 are spaced apart along the second direction X, the electrode portions 271 of two adjacent energy storage structures 30 are opposite to each other, and the first sub-spacer structures 291 of two adjacent energy storage structures 30 are opposite to each other.

[0103] In some embodiments, the preparation method of the spacing groove 28 includes: removing a portion of the second electrode layer 27 to form a first sub-spacer groove 281 in the second electrode layer 27; the first sub-spacer groove 281 extends along a second direction X perpendicular to the first direction Z, and the first sub-spacer groove 281 divides the second electrode layer 27 into a plurality of electrode portions 271 arranged in a third direction Y perpendicular to the first direction Z and intersecting the second direction X.

[0104] Step S5, see Figure 6 and Figures 1A to 4 , an insulating material is filled in the spacing groove 28 to form a spacing structure 29 , and the spacing structure 29 is located between two adjacent electrode portions 271 .

[0105] The spacing groove 28 may also be referred to as a first sub-spacing groove 281 .

[0106] Step S5 includes: filling the first sub-spacer groove 281 with an insulating material to form a first sub-spacer structure 291 . The first sub-spacer structure 291 is located between two adjacent electrode portions 271 .

[0107] In some embodiments, in an energy storage structure 30 , multiple electrode portions 271 and multiple first sub-spacer structures 291 are alternately arranged in the third direction Y, and one energy storage layer 25 corresponds to multiple electrode portions 271 and multiple first sub-spacer structures 291 .

[0108] In some embodiments, the other end of the first sub-electrode portion 2711 in the third direction Y is connected to the first sub-spacer structure 291 , and both ends of the second sub-electrode portion 2712 in the third direction Y are respectively connected to the first sub-spacer structure 291 .

[0109] In some embodiments, in an energy storage structure 30 , both ends of the first sub-spacer structure 291 in the second direction X are in contact with the energy storage layer 25 .

[0110] In some embodiments, after step S5 , the method further includes bonding the first semiconductor device 110 to the second semiconductor device 120 including the peripheral driving circuit 1201 .

[0111] See also Figure 17 and Figure 18 The present application also provides a semiconductor device 200. The structure of the semiconductor device 200 is substantially the same as that of the semiconductor device 100. The only difference is that the second stack structure 10 of the semiconductor device 200 includes only the first transistor 11. The semiconductor device 200 also includes a third stack structure 50 located away from the second stack structure 10 and located in the first stack structure 20. The third stack structure 50 includes a second transistor 13. The two ends of the same electrode portion 271 in the first direction Z are respectively connected to the first transistor 11 and the second transistor 13. Figure 18 The connection relationship between the first transistor 11, the second transistor 13 and the capacitor structure 40 is only described. Figure 18 The number of the first electrode layers 21 in FIG. 1 is not drawn equal to the number of the first electrode layers 21 in the second stacked structure 10 .

[0112] In some embodiments, one of the first transistor 11 and the second transistor 13 of the semiconductor device 200 is configured to be conductive or non-conductive based on the storage content of the capacitor structure 40 of the semiconductor device 200 and allow the storage content of the capacitor structure 40 to be read, and the other is configured to be conductive or non-conductive based on the write content and allow a write voltage to flow into the capacitor structure 40. The gate of the transistor that allows the storage content of the capacitor structure 40 to be read out of the first transistor 11 and the second transistor 13 of the semiconductor device 200 is connected to the electrode portion 271, and the channel layer of the transistor that allows the write voltage to flow into the capacitor structure 40 of the first transistor 11 and the second transistor 13 is connected to the electrode portion 271.

[0113] See also Figure 18 In this embodiment, the first transistor 11 of the semiconductor device 200 is a write transistor and allows a write voltage to flow into the capacitor structure 40. The channel layer of the first transistor 11 is connected to the electrode portion 271. The second transistor 13 is a read transistor and allows the storage content of the capacitor structure 40 to be read. The gate of the second transistor 13 is connected to the electrode portion 271.

[0114] In this embodiment, the second stacked structure 10 of the semiconductor device 200 includes a first dielectric layer 121, a word line 122, a second dielectric layer 123, a first gate insulating layer 14, and a first channel layer 15. The first dielectric layer 121 is located on one side of the first stacked structure 20. The word line 122 is located on a side of the first dielectric layer 121 away from the first stacked structure 20 and extends along the second direction X. The second dielectric layer 123 is located on a side of the word line 122 away from the first dielectric layer 121. The first channel layer 15 extends along the first direction Z and is located within the stack formed by the first dielectric layer 121, the word line 122, and the second dielectric layer 123. The first channel layer 15 is provided in a one-to-one correspondence with the electrode portion 271. The first transistor 11 includes the first channel layer 15, the first gate insulating layer 14, and the word line 122. Each first channel layer 15 includes a first drain 151, a first channel 152, and a first source 153. The first drain 151 and the first source 153 are located on opposite sides of the first channel 152 in the first direction Z. The first source 153 is connected to the second electrode layer 27. The word lines 122 are located opposite the first channels 152, that is, the word lines 122 face the first channels 152 from all directions.

[0115] Please continue reading Figure 18In this embodiment, the third stacked structure 50 includes a source line 124, a second gate layer 116, a second gate insulating layer 117, a second channel 118, and a second drain 119. The second gate layer 116 is connected to the electrode portion 271. The second gate insulating layer 117 covers the second gate layer 116. The second channel 118 is arranged around the second gate insulating layer 117. The second drain 119 is located on a side of the second gate insulating layer 117 away from the electrode portion 271 and is connected to the second channel 118. The source line 124 is arranged around the second channel 118. The second transistor 13 includes the source line 124, the second channel 118, the second drain 119, and the second gate insulating layer 117. The third stacked structure 50 also includes a bit line (not shown), and the second drain 119 is connected to the bit line. The second transistor 13 of the semiconductor device 200 has different current states depending on its gate voltage: a "0" state and a "1" state. When the gate voltage of the second transistor 13 of the semiconductor device 200 is low, the state read out by the bit line is “0”; when the gate voltage of the second transistor 13 of the semiconductor device 200 is high, the state read out by the bit line is “1”.

[0116] Accordingly, see Figures 17 to 19 The present application also provides a method for preparing a semiconductor device 200. The method for preparing the semiconductor device 200 is substantially the same as the method for preparing the semiconductor device 100. The method for preparing the semiconductor device 200 includes:

[0117] Step S10 , forming a second stack structure 10 including a first transistor 11 .

[0118] In step S2 , a first stacked structure 20 is formed on one side of the second stacked structure 10 . The first stacked structure 20 includes first insulating layers 22 and first electrode layers 21 alternately stacked in a first direction Z.

[0119] In step S30 , a plurality of energy storage structures 30 are formed in the first stacked structure 20 and the energy storage structures 30 are connected to the first transistor 11 .

[0120] In step S4 , a portion of the second electrode layer 27 is removed to form at least one spacing groove 28 in the second electrode layer 27 . The second electrode layer 27 on both sides of the spacing groove 28 is an electrode portion 271 . One second electrode layer 27 includes a plurality of electrode portions 271 .

[0121] In step S5 , insulating material is filled into the spacing groove 28 to form a spacing structure 29 . The spacing structure 29 is located between two adjacent electrode portions 271 .

[0122] In step S6, a third stacking structure 50 including a second transistor 13 is formed on a side of the first stacking structure 20 away from the second stacking structure 10; wherein, one of the first transistor 11 and the second transistor 13 is configured to be turned on or off according to the storage content of the capacitor structure 40 and allow the storage content of the capacitor structure 40 to be read, and the other is configured to be turned on or off according to the written content and allow the written voltage to flow into the capacitor structure 40.

[0123] The channel layer of the first transistor 11 is connected to the electrode portion 271 , and the gate layer of the second transistor 13 is connected to the electrode portion 271 .

[0124] See also Figures 20 to 21 The present application also provides a semiconductor device 300. The structure of semiconductor device 300 is substantially the same as that of semiconductor device 100, with the only difference being that the spacer structure 29 further includes a second sub-spacer structure 292. The second sub-spacer structure 292 extends along the third direction Y, and at least one end of the second sub-spacer structure 292 is connected to the first sub-spacer structure 291. The second sub-spacer structure 292 is located between two adjacent first sub-electrode portions 2711 and two adjacent second sub-electrode portions 2712 arranged in the second direction X. One end of the second sub-spacer structure 292 located between two adjacent first sub-electrode portions 2711 is connected to the first sub-spacer structure 291, and the other end is connected to the energy storage layer 25. The two ends of the second sub-spacer structure 292 located between two adjacent second sub-electrode portions 2712 are respectively connected to the two first sub-spacer structures 291.

[0125] In some embodiments, the second sub-spacer structure 292 penetrates the first stack structure 20 and is connected to the first transistor 11 or the second transistor 13 .

[0126] See also Figure 21 In some embodiments, the two electrode portions 27 located on adjacent sides of the same second sub-spacer structure 292 are respectively connected to the first transistor 11 and the second transistor 13. In this case, the semiconductor device 300 does not include the third stacked structure 50, and the second stacked structure 10 includes the first transistor 11 and the second transistor 13.

[0127] In some embodiments, two electrode portions 27 located on adjacent sides of the same second sub-spacer structure 292 are respectively connected to two first transistors 11. In this case, the semiconductor device 300 includes a third stacked structure (not shown), which may include the second transistors 13, and the second stacked structure 10 includes only the first transistors 11.

[0128] Accordingly, see Figures 20 to 22The present application also provides a method for preparing a semiconductor device 300. Steps S1, S2, and S3 in the method for preparing the semiconductor device 300 are exactly the same as steps S1, S2, and S3 in the method for preparing the semiconductor device 100. The difference is that steps S41 and S51 in the method for preparing the semiconductor device 300 are not exactly the same as steps S4 and S5 in the method for preparing the semiconductor device 100.

[0129] The method for preparing the semiconductor device 300 includes:

[0130] Step S1 : forming a second stack structure 10 including a first transistor 11 and a second transistor 13 connected to the first transistor 11 .

[0131] In step S2 , a first stacked structure 20 is formed on one side of the second stacked structure 10 . The first stacked structure 20 includes first insulating layers 22 and first electrode layers 21 alternately stacked in a first direction Z.

[0132] In step S3, a plurality of energy storage structures are formed in the first stacked structure 20 and the energy storage structures are connected to the second transistor 13; the energy storage structure includes an energy storage layer 25 and a second electrode layer 27, the first electrode layer 21 is arranged around the energy storage layer 25, and the energy storage layer 25 is arranged around the second electrode layer 27, and the energy storage layer 25 is located between the first electrode layer 21 and the second electrode layer 27.

[0133] Step S41, remove part of the second electrode layer 27 to form a first sub-spacer groove 281 in the second electrode layer 27; remove part of the second electrode layer 27 to form a second sub-spacer groove 282 in the second electrode layer 27 that is connected to the first sub-spacer groove 281; the second sub-spacer groove 282 extends along the third direction Y, and the second sub-spacer groove 282 divides the second electrode layer 27 into a plurality of electrode portions 271 arranged at intervals in the third direction Y.

[0134] In step S51 , an insulating material is filled into the first sub-spacing groove 281 to form a first sub-spacing structure 291 , and an insulating material is filled into the second sub-spacing groove 282 to form a second sub-spacing structure 292 .

[0135] See also Figures 23 to 24The present application also provides a semiconductor device 400. The structure of semiconductor device 400 is substantially the same as that of semiconductor device 100, except that the multiple energy storage structures 30 of semiconductor device 400 are arranged in multiple rows and columns, with the energy storage structures 30 in two adjacent rows being staggered. The energy storage structures 30 in each row are spaced apart along a second direction X perpendicular to the first direction Z, and the energy storage structures 30 in each column are spaced apart along a third direction Y perpendicular to the first direction Z and intersecting the second direction X. The spacing structures 29 extend along the second direction X or the third direction Y, with each spacing structure 29 being located between two adjacent electrode portions 271 of the energy storage structures 30 in the same row or column. A spacing structure 29 extends through multiple energy storage structures 30 in the same row or column in the first direction Z. Each energy storage structure 30 includes two electrode portions 271, and the two electrode portions 271 in each energy storage structure 30 are respectively connected to two first transistors 11, two second transistors 13, or one first transistor 11 and one second transistor 13.

[0136] In this embodiment, the two electrode portions 271 in one energy storage structure 30 are connected to the two second transistors 13 respectively.

[0137] In some embodiments, the spacer structure 29 is further located in the first stacked structure 20 and contacts the first insulating layer 22 and the first electrode layer 21 .

[0138] In this embodiment, the spacing structure 29 extends along the second direction X. In other embodiments, the spacing structure 29 may also extend along the third direction Y.

[0139] In some embodiments, the cross-section of the energy storage structure 30 perpendicular to the first direction Z is circular.

[0140] Accordingly, see Figures 23 to 31 The present application further provides a method for manufacturing a semiconductor device 400. The method for manufacturing the semiconductor device 400 is substantially the same as the method for manufacturing the semiconductor device 100. The method for manufacturing the semiconductor device 400 includes:

[0141] Step S1, see Figure 25 and Figure 26 , forming a second stack structure 10 including a first transistor 11 and a second transistor 13 connected to the first transistor.

[0142] Step S2, see Figure 25 and Figure 27 A first stacked structure 20 is formed on one side of the second stacked structure 10 . The first stacked structure 20 includes first insulating layers 22 and first electrode layers 21 alternately stacked in a first direction Z.

[0143] Step S31, see Figure 25and Figures 28 to 30 A plurality of energy storage structures 30 are formed in the first stack structure 20 , and one energy storage structure 30 is connected to one first transistor 11 and one second transistor 13 or to two first transistors 11 or to two second transistors 13 .

[0144] In step S31 , one through-trench 23 corresponds to one first transistor 11 and one second transistor 13 or corresponds to two first transistors 11 or corresponds to two second transistors 13 . One second electrode layer 27 is connected to one first transistor 11 or one second transistor 13 .

[0145] In this embodiment, one second electrode layer 27 is connected to one second transistor 13 .

[0146] Multiple energy storage structures 30 are arranged in multiple rows and columns, and the energy storage structures 30 in two adjacent rows are staggered; the energy storage structures 30 in each row are arranged at intervals along a second direction X perpendicular to the first direction Z, and the energy storage structures 30 in each column are arranged at intervals along a third direction Y perpendicular to the first direction Z and intersecting the second direction X.

[0147] Step S41, please refer to Figures 23 to 25 and Figure 31 , part of the second electrode layer 27 is removed to form at least one spacing groove 28 in the second electrode layer 27, and the second electrode layer 27 located on both sides of the spacing groove 28 is an electrode portion 271. A second electrode layer 27 includes multiple electrode portions 271, and a spacing groove 28 penetrates multiple energy storage structures 30 located in the same row or column and the first insulating layer 22 and the first electrode layer 21 located between two adjacent energy storage structures 30 in the first direction Z.

[0148] Step S5, see Figures 23 to 25 , an insulating material is filled in the spacing groove 28 to form a spacing structure 29 , and the spacing structure 29 is located between two adjacent electrode portions 271 .

[0149] The spacing structure 29 extends along the second direction X or the third direction Y. One spacing structure 29 is located between two adjacent electrode portions 271 of the energy storage structures 30 in the same row or column. One spacing structure 29 runs through multiple energy storage structures 30 in the same row or column in the first direction Z.

[0150] In step S5 , the spacer structure 29 is still located in the first stacked structure 20 and is in contact with the first insulating layer 22 and the first electrode layer 21 .

[0151] See also Figure 32The present application also provides a memory system 1000 , which includes one or more semiconductor devices 100 / 200 / 300 / 400 as described above and a controller 500 , wherein the controller 500 is connected to the semiconductor device 100 / 200 / 300 / 400 and is configured to control the semiconductor device 100 .

[0152] The memory system 1000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. The controller may be configured to control operations of the semiconductor device, such as read, erase, and program operations.

[0153] In some embodiments, the controller is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0154] In some embodiments, the controller is designed to operate in a high duty cycle environment Solid State Disk (SSD) or Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0155] The semiconductor device, preparation method thereof, and memory system provided in the present application divide the second electrode layer of the capacitor structure into multiple electrode parts through a spacing structure. The multiple electrode parts, together with a storage layer and multiple first electrode layers, form multiple small sidewall capacitor structures, thereby increasing the storage density of the semiconductor device.

[0156] In addition, the semiconductor device of the present application utilizes the first transistor in the 2TXC architecture (a first transistor, a second transistor, and multiple capacitor structures) as a selection tube, the second transistor as a storage tube, and the first transistor and the second transistor are arranged on the same side of the capacitor structure and the first transistor and the second transistor are connected. Different voltages are induced on the first transistor through the capacitive coupling effect of the capacitor structure, and the storage information on the first electrode layer of the sub-capacitor can be directly judged to achieve non-destructive reading.

[0157] The semiconductor device of the present application utilizes the first transistor in the 2TXC architecture (a first transistor, a second transistor, and a plurality of capacitor structures) as a selection transistor, and the second transistor as a storage transistor. Through 3D stacking and combining with square or circular hole-shaped sidewall capacitors, the first transistor and the second transistor respectively perform write operations and read operations. Therefore, the second transistor (read transistor) of the semiconductor device provided by the present application does not require a write-back operation and can implement a non-destructive read operation, thereby enabling non-destructive reading of stored information and improving the storage life.

[0158] Furthermore, this invention utilizes the shape of the spacer structure, for example, with only the first sub-spacer structure or with both the first sub-spacer structure and the second sub-spacer structure, to adapt to different storage density scenarios. Compared to semiconductor devices with only the first sub-spacer structure, semiconductor devices with both the first sub-spacer structure and the second sub-spacer structure have higher storage density.

[0159] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A semiconductor device comprising a first semiconductor structure, characterized in that: The first semiconductor structure includes a first stacked structure and a spacer structure; The first stacking structure includes: a first insulating layer; The first electrode layer and the first insulating layer are alternately stacked in a first direction; and an energy storage structure located within a stack formed by the first insulating layer and the first electrode layer; the energy storage structure comprising an energy storage layer and a second electrode layer, the first electrode layer being disposed around the energy storage layer; the energy storage layer being disposed around the second electrode layer, the energy storage layer being located between the first electrode layer and the second electrode layer, and the second electrode layer comprising at least two electrode portions; The energy storage structure and the first electrode layer constitute a capacitor structure of the first semiconductor structure, and the spacing structure is located between two adjacent electrode portions.

2. The semiconductor device according to claim 1, wherein The spacing structure includes a plurality of first sub-spacing structures, wherein the first sub-spacing structures extend along a second direction perpendicular to the first direction; The first sub-spacer structure is located between two adjacent electrode portions arranged in a third direction, and the third direction is perpendicular to the first direction and intersects with the second direction.

3. The semiconductor device according to claim 2, wherein In one of the energy storage structures, two of the plurality of electrode portions are first sub-electrode portions, and the remaining are second sub-electrode portions, and the two first sub-electrode portions are located on both sides of at least one second sub-electrode portion in the third direction; Among them, one end of the first sub-electrode portion in the third direction is connected to the energy storage layer, and the other end is connected to the first sub-spacer structure; the two ends of the second sub-electrode portion in the third direction are respectively connected to the first sub-spacer structure.

4. The semiconductor device according to claim 3, wherein In one of the energy storage structures, the first sub-spacer structure and two ends of the electrode portion in the second direction are in contact with the energy storage layer respectively.

5. The semiconductor device according to claim 3, wherein The spacing structure further includes a second sub-spacing structure, the second sub-spacing structure extends along the third direction, and at least one end of the second sub-spacing structure is connected to the first sub-spacing structure; The second sub-spacer structure is located between two adjacent first sub-electrode portions and two adjacent second sub-electrode portions arranged in the second direction.

6. The semiconductor device according to claim 5, wherein One end of the second sub-spacer structure located between two adjacent first sub-electrode portions is connected to the first sub-spacer structure, and the other end is connected to the energy storage layer; Two ends of the second sub-spacer structure located between two adjacent second sub-electrode portions are respectively connected to two first sub-spacer structures.

7. The semiconductor device according to claim 1, wherein The plurality of energy storage structures are arranged in multiple rows and columns, and the energy storage structures in two adjacent rows are staggered; the energy storage structures in each row are arranged at intervals along a second direction perpendicular to the first direction, and the energy storage structures in each column are arranged at intervals along a third direction perpendicular to the first direction and intersecting the second direction; The spacing structure extends along the second direction or the third direction, and one spacing structure is located between two adjacent electrode portions of the energy storage structure in the same row or column.

8. The semiconductor device according to claim 7, wherein The spacer structure is also located in the first stacked structure and contacts the first insulating layer and the first electrode layer.

9. The semiconductor device according to claim 1, wherein At least one cross-section of the energy storage structure perpendicular to the first direction is square or circular.

10. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes a first transistor and a second transistor, wherein the second transistor is located on one side of the first stacked structure and connected to the electrode portion of the first stacked structure; The first transistor and the second transistor are located on the same side of the first stack structure in a first direction, and the second transistor is connected to the first transistor.

11. The semiconductor device according to claim 10, wherein The second transistor is located on a side of the first transistor away from the electrode portion.

12. The semiconductor device according to claim 10, wherein The second transistor and the first transistor are in the same layer and are spaced apart from each other.

13. The semiconductor device according to claim 1, wherein The semiconductor device further includes a first transistor and a second transistor, the first transistor and the second transistor being located on both sides of the first stacked structure in the first direction, and two ends of one electrode portion being connected to one first transistor and one second transistor respectively; Among them, one of the first transistor and the second transistor is configured to be turned on or off according to the storage content of the capacitor structure of the semiconductor device and allow the storage content of the capacitor structure to be read, and the other is configured to be turned on or off according to the written content and allow the write voltage to flow into the capacitor structure.

14. The semiconductor device according to claim 13, wherein The gate of the transistor in the first transistor and the second transistor that allows the storage content of the capacitor structure to be read is connected to the second electrode layer, and the channel layer of the transistor in the first transistor and the second transistor that allows the write voltage to flow into the capacitor structure is connected to the second electrode layer.

15. The semiconductor device according to any one of claims 11 to 14, wherein: The semiconductor device further includes a second semiconductor structure bonded to the first semiconductor structure in the first direction. The second semiconductor structure includes a peripheral driving circuit connected to the first transistor or the second transistor.

16. A method for preparing a semiconductor device, characterized in that: include: forming a first stacked structure comprising first insulating layers and first electrode layers alternately stacked in a first direction; forming a plurality of energy storage structures in the first stacked structure, the energy storage structures comprising an energy storage layer and a second electrode layer, the first electrode layer being arranged around the energy storage layer, the energy storage layer being arranged around the second electrode layer, and the energy storage layer being located between the first electrode layer and the second electrode layer; removing a portion of the second electrode layer to form at least one spacing groove in the second electrode layer, wherein the second electrode layer located on both sides of the spacing groove is an electrode portion, and one second electrode layer includes a plurality of the electrode portions; and An insulating material is filled in the spacing groove to form a spacing structure, and the spacing structure is located between two adjacent electrode parts; the energy storage structure and the first electrode layer constitute a capacitor structure.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: In the process of removing a portion of the second electrode layer to form a spacing groove in the second electrode layer, the spacing groove penetrates the second electrode layer in the first direction.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The spacing groove also penetrates the first insulating layer and the first electrode layer between two adjacent energy storage structures.

19. The method for manufacturing a semiconductor device according to claim 17, wherein: The method for preparing the spacing groove comprises: removing a portion of the second electrode layer to form a first sub-spacing groove in the second electrode layer; the first sub-spacing groove extends along a second direction perpendicular to the first direction, and the first sub-spacing groove divides the second electrode layer into a plurality of electrode portions arranged in a third direction perpendicular to the first direction and intersecting the second direction; The step of filling the spacing groove with an insulating material to form a spacing structure includes: filling the first sub-spacing groove with the insulating material to form a first sub-spacing structure.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The method for preparing the spacer groove further includes: Removing a portion of the second electrode layer to form a second sub-spacing groove in the second electrode layer that is connected to the first sub-spacing groove; the second sub-spacing groove extends along the third direction, and the second sub-spacing groove divides the second electrode layer into a plurality of electrode portions arranged at intervals in the third direction; The step of filling the spacing groove with insulating material to form a spacing structure also includes: filling the second sub-spacing groove with the insulating material to form a second sub-spacing structure; the second sub-spacing structure extends along the third direction and is located between the electrode parts spaced apart in the second direction.

21. The method for manufacturing a semiconductor device according to claim 16, wherein: Before the step of forming the first stacking structure, the method further includes: forming a second stack structure including a first transistor and a second transistor connected to the first transistor; During the process of forming a plurality of energy storage structures in the first stacked structure, the second electrode layer of the energy storage structure is connected to the second transistor.

22. The method for manufacturing a semiconductor device according to claim 16, wherein: Before forming the first stack structure, the method further includes: forming a second stack structure including a first transistor; in the process of forming a plurality of energy storage structures in the first stack structure, the second electrode layer of the energy storage structure is connected to the first transistor; After the step of filling the spacing groove with insulating material to form a spacing structure, the method further includes the following steps: forming a third stack structure including a second transistor on a side of the first stack structure away from the second stack structure; In which, the second transistor is connected to the second electrode layer of the energy storage structure, one of the first transistor and the second transistor is configured to be conductive or non-conductive according to the storage content of the capacitor structure and allow the storage content of the capacitor structure to be read, and the other is configured to be conductive or non-conductive according to the written content and allow the written voltage to flow into the capacitor structure.

23. A storage system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 15; and A controller is coupled to the semiconductor device and configured to control the semiconductor device.

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