Semiconductor device

Abstract

Provided is a semiconductor device capable of reducing on-voltage and off-switching loss. The first surface-side region of the semiconductor section has: a second semiconductor layer facing the first gate electrode via a first insulating film; and a third semiconductor layer in contact with the first electrode. The second surface-side region of the semiconductor section has: a fourth semiconductor layer facing the second gate electrode via a second insulating film; a fifth semiconductor layer of the second conductivity type in contact with the second electrode; a sixth semiconductor layer of the first conductivity type in contact with the second electrode; and a seventh semiconductor layer of the second conductivity type, the second conductivity type impurity concentration being lower than the fourth semiconductor layer and the fifth semiconductor layer, and the seventh semiconductor layer being in contact with the second electrode. In the second direction X, the seventh semiconductor layer is located between the plurality of second gate electrodes.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] An IGBT (Insulated Gate Bipolar Transistor) having a double-gate structure in which gate electrodes are provided on the front side and the back side of a semiconductor layer has been proposed.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-49610 Summary of the Invention

[0006] An object of an embodiment of the present invention is to provide a semiconductor device capable of reducing turn-off switching loss.

[0007] According to an embodiment of the present invention, a semiconductor device includes: a first electrode; a second electrode; a semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion including: a first semiconductor layer of a first conductivity type; a first surface side region located between the first electrode and the first semiconductor layer in the first direction; and a second surface side region located between the second electrode and the first semiconductor layer in the first direction; a plurality of first gate electrodes opposing the first surface side region; a plurality of first insulating films provided between the first surface side region and the plurality of first gate electrodes; a plurality of second gate electrodes opposing the second surface side region in the first direction; and a plurality of second insulating films provided between the second surface side region and the plurality of second gate electrodes. The first surface side region includes: a second semiconductor layer of a second conductivity type opposing the first gate electrode via the first insulating film; and a third semiconductor layer of a first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the first electrode. The second surface side region includes: a fourth semiconductor layer of the second conductivity type, which is opposed to the second gate electrode via the second insulating film; a fifth semiconductor layer of the second conductivity type, which has a higher second conductivity type impurity concentration than the second semiconductor layer and the fourth semiconductor layer, and is in contact with the second electrode; a sixth semiconductor layer of the first conductivity type, which has a higher first conductivity type impurity concentration than the first semiconductor layer, and is in contact with the second electrode; and a seventh semiconductor layer of the second conductivity type, which has a lower second conductivity type impurity concentration than the fourth semiconductor layer and the fifth semiconductor layer, and is in contact with the second electrode. The seventh semiconductor layer is located between the plurality of second gate electrodes in a second direction orthogonal to the first direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a schematic plan view of the second surface side of the semiconductor device according to the first embodiment.

[0010] Figure 3 This is a schematic plan view of the second surface side of the semiconductor device according to the first embodiment.

[0011] Figure 4 This is a schematic plan view of the second surface side of the semiconductor device according to the first embodiment.

[0012] Figure 5 This is a schematic plan view of the second surface side of the semiconductor device according to the first embodiment.

[0013] Figure 6 This is a schematic cross-sectional view of a semiconductor device according to a modified example of the first embodiment.

[0014] Figure 7 It is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

[0015] Figure 8 It is a schematic cross-sectional view of a semiconductor device according to a modified example of the second embodiment.

[0016] Figure 9 is a graph showing simulation results.

[0017] (Explanation of Reference Numerals)

[0018] 1-2: semiconductor device; 10: semiconductor portion; 11: first surface side region; 12: second surface side region; 21: first semiconductor layer; 22: second semiconductor layer; 23: third semiconductor layer; 24: fourth semiconductor layer; 24A: first portion; 24B: second portion; 25: fifth semiconductor layer; 26: sixth semiconductor layer; 27: seventh semiconductor layer; 28: eighth semiconductor layer; 29: ninth semiconductor layer; 30: tenth semiconductor layer; 51: first electrode, 52: second electrode; 61: first gate electrode; 62: second gate electrode; 71: first insulating film; 72: second insulating film; 73: insulating layer. DETAILED DESCRIPTION

[0019] Hereinafter, each embodiment will be described with reference to the drawings.

[0020] The drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as in reality. Even if the same part is shown, the relative sizes and ratios may be shown differently depending on the drawing.

[0021] In addition, the same reference numerals are given to the same or similar elements.

[0022] [First embodiment]

[0023] Figure 1 This is a schematic cross-sectional view of a semiconductor device 1 according to the first embodiment. The semiconductor device 1 includes a first electrode 51, a second electrode 52, a semiconductor portion 10, a plurality of first gate electrodes 61, a plurality of first insulating films 71, a plurality of second gate electrodes 62, and a plurality of second insulating films 72. The semiconductor device 1 is an IGBT, in which the first electrode 51 is an emitter electrode and the second electrode 52 is a collector electrode.

[0024] The semiconductor portion 10 is located between the first electrode 51 and the second electrode 52 in the first direction Z. Two directions perpendicular to the first direction Z are referred to as the second direction X and the third direction Y. The second direction X and the third direction Y are perpendicular to each other.

[0025] The material of semiconductor portion 10 is, for example, silicon. Alternatively, materials such as silicon carbide and gallium nitride may be used as the material of semiconductor portion 10. In this specification, the first conductivity type of semiconductor portion 10 is described as n-type and the second conductivity type as p-type. Alternatively, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0026] The semiconductor portion 10 has a first surface 10A and a second surface 10B located opposite to the first surface 10A in the first direction Z. The first electrode 51 faces the first surface 10A in the first direction Z, and the second electrode 52 faces the second surface 10B in the first direction Z.

[0027] The semiconductor portion 10 includes an n-type first semiconductor layer 21; a first-surface region 11 located between the first electrode 51 and the first semiconductor layer 21 in the first direction Z; and a second-surface region 12 located between the second electrode 52 and the first semiconductor layer 21 in the first direction Z. The first semiconductor layer 21 serves as the drift layer in the IGBT. The first-surface region 11 includes the first surface 10A of the semiconductor portion 10 and the portion between the first surface 10A and the first semiconductor layer 21. The second-surface region 12 includes the second surface 10B of the semiconductor portion 10 and the portion between the second surface 10B and the first semiconductor layer 21.

[0028] The first gate electrode 61 is opposed to the first surface-side region 11 of the semiconductor portion 10 via the first insulating film 71. The first insulating film 71 is provided between the first surface-side region 11 and the first gate electrode 61, and between the first semiconductor layer 21 and the first gate electrode 61. The first gate electrode 61 is provided within a trench extending from the first surface 10A in the first direction Z and penetrating the first surface-side region 11 via the first insulating film 71. A plurality of first gate electrodes 61 extending in the third direction Y are arranged in the second direction X. The insulating layer 73 is provided between the first gate electrode 61 and the first electrode 51 in the first direction Z, and the first gate electrode 61 does not contact the first electrode 51.

[0029] The first surface side region 11 includes a p-type second semiconductor layer 22 and an n-type third semiconductor layer 23. The second semiconductor layer 22 is a base layer in the IGBT, and the third semiconductor layer 23 is an emitter layer in the IGBT.

[0030] The second semiconductor layer 22 is located on the first semiconductor layer 21 in the first direction Z and is in contact with the first semiconductor layer 21. The second semiconductor layer 22 is located between adjacent first gate electrodes 61 in the second direction X. The side surfaces of the second semiconductor layer 22 are opposed to the first gate electrodes 61 via the first insulating film 71. In other words, the first gate electrode 61 is opposed to the second semiconductor layer 22 via the first insulating film 71 in the second direction X. The second semiconductor layer 22 is in contact with the first insulating film 71.

[0031] The n-type impurity concentration of the third semiconductor layer 23 is higher than the n-type impurity concentration of the first semiconductor layer 21. The third semiconductor layer 23 is located on the second semiconductor layer 22 in the first direction Z and is in contact with the second semiconductor layer 22. The third semiconductor layer 23 is in contact with the first electrode 51 and is electrically connected to the first electrode 51. Two third semiconductor layers 23 are provided between the first gate electrodes 61 adjacent in the second direction X, separated from each other in the second direction X. A portion 22A of the second semiconductor layer 22 is located between these two third semiconductor layers 23, and the portion 22A of the second semiconductor layer 22 is in contact with the first electrode 51. The p-type impurity concentration of the portion 22A of the second semiconductor layer 22 is higher than the p-type impurity concentration of the portion of the second semiconductor layer 22 other than the portion 22A. The third semiconductor layer 23 is in contact with the first insulating film 71.

[0032] The first surface side region 11 may further include a p-type ninth semiconductor layer 29. The ninth semiconductor layer 29 is located between adjacent first gate electrodes 61 in the second direction X. The depth of the ninth semiconductor layer 29 from the first surface 10A is deeper than the depth of the second semiconductor layer 22 from the first surface 10A. The insulating layer 73 is provided between the ninth semiconductor layer 29 and the first electrode 51 in the first direction Z, and the ninth semiconductor layer 29 is not in contact with the first electrode 51. The third semiconductor layer 23 is not arranged on the ninth semiconductor layer 29. Of the two side surfaces of the first gate electrode 61 in the second direction X, one side surface is adjacent to the third semiconductor layer 23 and the second semiconductor layer 22 via the first insulating film 71, and the other side surface is adjacent to the ninth semiconductor layer 29 via the first insulating film 71.

[0033] The second gate electrode 62 has a planar gate structure and is opposed to the second surface region 12 in the first direction Z. A second insulating film 72 is provided between the second surface region 12 and the second gate electrode 62. The second gate electrode 62 is located within the second electrode 52, with the second insulating film 72 provided between the second gate electrode 62 and the second electrode 52. The second insulating film 72 surrounds the upper surface, lower surface, and side surfaces of the second gate electrode 62. The second gate electrode 62 does not contact the second electrode 52.

[0034] The second-surface-side region 12 includes a p-type fourth semiconductor layer 24 , a p-type fifth semiconductor layer 25 , an n-type sixth semiconductor layer 26 , and a p-type seventh semiconductor layer 27 .

[0035] The fourth semiconductor layer 24 includes a first portion 24A that faces the second gate electrode 62 via the second insulating film 72 in the first direction Z. As will be described later, the first portion 24A functions as a channel portion. The fourth semiconductor layer 24 is in contact with the second insulating film 72, the fifth semiconductor layer 25, the sixth semiconductor layer 26, the seventh semiconductor layer 27, and the eighth semiconductor layer 28.

[0036] The p-type impurity concentration of the fifth semiconductor layer 25 is higher than the p-type impurity concentration of the second semiconductor layer 22 and the p-type impurity concentration of the fourth semiconductor layer 24. The fifth semiconductor layer 25 is in contact with the second electrode 52 and is electrically connected to the second electrode 52. The fifth semiconductor layer 25 serves as the collector layer in the IGBT. The fifth semiconductor layer 25 is located between the second electrode 52 and the fourth semiconductor layer 24 in the first direction Z. The fifth semiconductor layer 25 is in contact with the fourth semiconductor layer 24, the sixth semiconductor layer 26, and the seventh semiconductor layer 27.

[0037] The n-type impurity concentration of the sixth semiconductor layer 26 is higher than the n-type impurity concentration of the first semiconductor layer 21. The sixth semiconductor layer 26 is in contact with the second electrode 52 and is electrically connected to the second electrode 52. The sixth semiconductor layer 26 is located between the second electrode 52 and the fourth semiconductor layer 24 in the first direction Z. The sixth semiconductor layer 26 is in contact with the second insulating film 72, the fourth semiconductor layer 24, and the fifth semiconductor layer 25.

[0038] The p-type impurity concentration of the seventh semiconductor layer 27 is lower than the p-type impurity concentration of the fourth semiconductor layer 24 and the p-type impurity concentration of the fifth semiconductor layer 25. The seventh semiconductor layer 27 is in contact with the second electrode 52 and is electrically connected to the second electrode 52. The seventh semiconductor layer 27 is located between the second electrode 52 and the eighth semiconductor layer 28 (described later) in the first direction Z. The seventh semiconductor layer 27 is in contact with the fourth semiconductor layer 24, the fifth semiconductor layer 25, and the eighth semiconductor layer 28. Within a plane defined by the second direction X and the third direction Y, the fifth semiconductor layer 25 is located between the adjacent seventh semiconductor layer 27 and the adjacent first portion 24A of the fourth semiconductor layer 24. In a comparison between the fifth semiconductor layer 25 and the seventh semiconductor layer 27, both of which are in contact with the same fourth semiconductor layer 24, the distance between the fifth semiconductor layer 25 and the second gate electrode 62 within the plane defined by the second direction X and the third direction Y is smaller than the distance between the seventh semiconductor layer 27 and the second gate electrode 62. The seventh semiconductor layer 27 is located between two adjacent second gate electrodes 62 in the plane formed by the second direction X and the third direction Y. The seventh semiconductor layer 27 does not overlap with the second gate electrode 62 in the first direction Z.

[0039] For example, Figure 1 The structure shown in the cross section is repeated in the second direction X. The first surface side region 11 and the second surface side region 12 are configured independently of each other. For example, the shape and configuration interval of the first gate electrode 61 and the shape and configuration interval of the second gate electrode 62 are configured independently of each other. In addition, Figure 2-Figure 5 The second direction X and the third direction Y can be rotated and arranged at any angle within the plane formed by the second direction X and the third direction Y. The second direction X and the third direction Y with respect to the second surface side region 12 and the second gate electrode 62 can be replaced with any fourth direction and fifth direction, respectively, that are orthogonal to each other within the plane formed by the second direction X and the third direction Y. The fourth direction and the fifth direction are not shown.

[0040] Figure 2 1 is a schematic plan view showing an example of the arrangement of the layers and the second gate electrode 62 in the second surface side region 12 of the semiconductor device 1. The plurality of second gate electrodes 62 are arranged in the second direction X. Figure 2 , each layer of the second-surface-side region 12 between two second gate electrodes 62 adjacent to each other in the second direction X is shown.

[0041] For example, the first portion 24A (channel portion) of the fourth semiconductor layer 24 , the fifth semiconductor layer 25 , the sixth semiconductor layer 26 , and the seventh semiconductor layer 28 extend in the third direction Y.

[0042] In the second direction X, the first portion 24A (channel portion) is adjacent to the sixth semiconductor layer 26. In the second direction X, the seventh semiconductor layer 27 is located between the plurality of second gate electrodes 62. In the second direction X, the seventh semiconductor layer 27 is located farther from the second gate electrode 62 than the first portion 24A (channel portion). In the second direction X, the sixth semiconductor layer 26 is located between the first portion 24A (channel portion) and the fifth semiconductor layer 25. In the second direction X, the fifth semiconductor layer 25 is located between the sixth semiconductor layer 26 and the seventh semiconductor layer 27.

[0043] like Figure 1 As shown, the second surface side region 12 may further include an eighth semiconductor layer 28. The eighth semiconductor layer 28 is located between the first semiconductor layer 21 and the fourth semiconductor layer 24, and between the first semiconductor layer 21 and the seventh semiconductor layer 27 in the first direction Z. The eighth semiconductor layer 28 is in contact with the fourth semiconductor layer 24 and the seventh semiconductor layer 27. The n-type impurity concentration of the eighth semiconductor layer 28 is higher than the n-type impurity concentration of the first semiconductor layer 21. The eighth semiconductor layer 28 is a buffer layer in the IGBT. By providing the eighth semiconductor layer 28, the extension of the depletion layer can be stopped by the eighth semiconductor layer 28 in the off state of the semiconductor device 1, and the thickness of the first semiconductor layer 21 (the thickness in the first direction Z) can be made thinner than when the eighth semiconductor layer 28 is not provided.

[0044] A portion 28A of the eighth semiconductor layer 28 penetrates the fourth semiconductor layer 24 in the first direction Z and is adjacent to the first portion 24A (channel portion) of the fourth semiconductor layer 24 in the first direction X.

[0045] By applying a positive voltage to the second electrode 52 and a gate voltage higher than the first threshold voltage to the first gate electrode 61 while the first electrode 51 is at ground potential, a first channel (inversion layer) is formed in the portion of the second semiconductor layer 22 that faces the first gate electrode 61, and the semiconductor device 1 enters the on-state. In the on-state, an electron current flows between the first electrode 51 and the second electrode 52 via the third semiconductor layer 23 (emitter layer), the first channel, the first semiconductor layer 21 (drift layer), and the fifth semiconductor layer 25 (collector layer). In the on-state, holes are supplied from the fifth semiconductor layer 25 and the seventh semiconductor layer 27 to the first semiconductor layer 21, creating a high-density state of electrons and holes in the first semiconductor layer 21, resulting in low on-resistance. The seventh semiconductor layer 27 also functions as a collector layer, but since the p-type impurity concentration of the seventh semiconductor layer 27 is lower than that of the fifth semiconductor layer 25 , the seventh semiconductor layer 27 functions as a low injection region that reduces hole injection more than the fifth semiconductor layer 25 .

[0046] The semiconductor device 1 is turned off by applying a gate voltage lower than the threshold voltage to the first gate electrode 61. At the timing of the turn-off, when the gate voltage of the first gate electrode 61 is lower than the first threshold voltage, the gate voltage of the second gate electrode 62 is turned on at a voltage higher than the second threshold voltage. The gate voltage of the second gate electrode 62 is turned on immediately before, immediately after, or simultaneously with the turn-off of the gate voltage of the first gate electrode 61.

[0047] When the gate voltage of the second gate electrode 62 is turned on, a second channel (inversion layer) is formed in the first portion 24A of the fourth semiconductor layer 24, and electrons in the first semiconductor layer 21 are discharged to the second electrode 52 via a portion 28A of the eighth semiconductor layer 28, the second channel, and the sixth semiconductor layer 26. Electrons in the first semiconductor layer 21 are discharged to the second electrode 52 via a path that does not pass through the p-type semiconductor layer. This suppresses the injection of holes into the first semiconductor layer 21, reducing the turn-off switching loss of the semiconductor device 1. Before the gate voltage of the first gate electrode 61 is turned on, the gate voltage of the second gate electrode 62 is turned off.

[0048] In the first semiconductor layer 21, electrons in a region relatively far from the second gate electrode 62 are less likely to be discharged to the second electrode 52 through the above-described path. According to this embodiment, the seventh semiconductor layer 27 is provided as a low hole injection region as described above, at a position farther from the second gate electrode 62 than the first portion 24A (channel portion) in the second direction X. This reduces the amount of holes injected into the region of the first semiconductor layer 21 far from the second gate electrode 62, thereby enhancing the effect of reducing the turn-off switching loss of the semiconductor device 1 by turning on the second gate electrode 62.

[0049] Figure 9 The following table shows the results of simulations of the relationship between turn-off switching loss Eoff and on-state voltage Vce (collector-emitter voltage). The results for model a of the semiconductor device 1 according to the first embodiment and the results for comparative example b are shown. Comparative example b differs from model a of the embodiment in that the seventh semiconductor layer 27 is not included.

[0050] In IGBT, the reduction of turn-off switching loss Eoff and the reduction of on-state voltage Vce are in a trade-off relationship. Figure 9 The simulation results show that according to this embodiment, by enhancing the effect of reducing the turn-off switching loss Eoff, the trade-off between Eoff and Vce can be improved compared to the comparative example.

[0051] In order to suppress the operation of a parasitic element (npn transistor) including the eighth semiconductor layer 28 (or the first semiconductor layer 21), the fourth semiconductor layer 24, and the sixth semiconductor layer 26, there are sometimes restrictions on reducing the p-type impurity concentration of the fourth semiconductor layer 24. According to the first embodiment, the seventh semiconductor layer 27, which is different from the fourth semiconductor layer 24 and has a lower p-type impurity concentration than the fourth semiconductor layer 24, is provided as a low hole injection region, thereby increasing the degree of design freedom.

[0052] like Figure 3-Figure 5 As shown, a plurality of seventh semiconductor layers 27 may be arranged in the third direction Y between the second gate electrodes 62 adjacent to each other in the second direction X. The sixth semiconductor layer 26 is located between the seventh semiconductor layers 27 adjacent to each other in the third direction Y.

[0053] exist Figure 3 as well as Figure 4 In the example shown, the sixth semiconductor layer 26 is located between the first portion 24A (channel portion) of the fourth semiconductor layer 24 and the seventh semiconductor layer 27 in the second direction X. In the second direction X, the fifth semiconductor layer 25 is located between the sixth semiconductor layer 26 and the seventh semiconductor layer 27. Figure 4 In the example shown, the fourth semiconductor layer 24 is also located between the sixth semiconductor layer 26 and the seventh semiconductor layer 27 that are adjacent to each other in the third direction Y.

[0054] exist Figure 5 In the example shown, the fifth semiconductor layer 25 is located between the first portion 24A (channel portion) of the fourth semiconductor layer 24 and the seventh semiconductor layer 27 in the second direction X. The sixth semiconductor layer 26 is adjacent to the fifth semiconductor layer 25 and the seventh semiconductor layer 27 in the third direction Y. The sixth semiconductor layer 26 is located between the first portion 24A (channel portion) in the second direction X.

[0055] As a modification of the semiconductor device of the first embodiment, Figure 6 As shown, the p-type tenth semiconductor layer 30 may be provided between the fourth semiconductor layer 24 and the eighth semiconductor layer 28. The p-type impurity concentration of the tenth semiconductor layer 30 is higher than that of the fourth semiconductor layer 24 and lower than that of the fifth semiconductor layer 25.

[0056] [Second embodiment]

[0057] Figure 7 2 is a schematic cross-sectional view of a semiconductor device 2 according to a second embodiment. The semiconductor device 2 according to the second embodiment will be described mainly with respect to the structure that is different from the semiconductor device 1 according to the first embodiment.

[0058] In the semiconductor device 2 of the second embodiment, the fourth semiconductor layer 24 includes a first portion (channel portion) 24A that faces the second gate electrode 62 via the second insulating film 72 in the first direction Z; and a second portion 24B that is located between the plurality of second gate electrodes 62 in the second direction X and in contact with the second electrode 52. The second portion 24B is located between the second electrode 52 and the eighth semiconductor layer 28 in the first direction Z.

[0059] The p-type impurity concentration of the second portion 24B is lower than the p-type impurity concentration of the fifth semiconductor layer 25. The second portion 24B functions as a low-injection region that reduces hole injection more than the fifth semiconductor layer 25. Therefore, the amount of holes injected into a region of the first semiconductor layer 21 that is distant from the second gate electrode 62 can be reduced, thereby enhancing the effect of reducing the turn-off switching loss of the semiconductor device 2 by turning on the second gate electrode 62.

[0060] The layout of each layer of the second surface side region 12 and the second gate electrode 62 of the semiconductor device 2 according to the second embodiment can be set as follows: Figure 2-Figure 5 The seventh semiconductor layer 27 is replaced by the second portion 24B.

[0061] As a modification of the semiconductor device of the second embodiment, Figure 8 As shown, the fifth semiconductor layer 25 may be partially provided in the second portion 24B.

[0062] Although several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the scope of the invention. These embodiments and their variations are included within the scope and spirit of the invention and are included within the scope of the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: 1st electrode; 2nd electrode; a semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion comprising: a first semiconductor layer of a first conductivity type; and a first surface side region located between the first electrode and the first semiconductor layer in the first direction; and a second surface side region located between the second electrode and the first semiconductor layer in the first direction; a plurality of first gate electrodes facing the first surface side region; a plurality of first insulating films provided between the first surface side region and the plurality of first gate electrodes; a plurality of second gate electrodes facing the second surface side region in the first direction; as well as a plurality of second insulating films provided between the second surface side region and the plurality of second gate electrodes; The first surface side area has: a second semiconductor layer of a second conductivity type, facing the first gate electrode via the first insulating film; as well as a third semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the first electrode; The second surface side area has: a fourth semiconductor layer of the second conductivity type, facing the second gate electrode via the second insulating film; a fifth semiconductor layer of the second conductivity type, having a second conductivity type impurity concentration higher than that of the second semiconductor layer and the fourth semiconductor layer, and being in contact with the second electrode; a sixth semiconductor layer of the first conductivity type, having a higher first conductivity type impurity concentration than the first semiconductor layer, and being in contact with the second electrode; as well as The seventh semiconductor layer of the second conductivity type has a lower second conductivity type impurity concentration than the fourth semiconductor layer and the fifth semiconductor layer, and is in contact with the second electrode. In a second direction perpendicular to the first direction, the seventh semiconductor layer is located between the plurality of second gate electrodes.

2. The semiconductor device according to claim 1, wherein The second-surface region further includes an eighth semiconductor layer of the first conductivity type. The eighth semiconductor layer of the first conductivity type is located between the first semiconductor layer and the fourth semiconductor layer and has a higher first conductivity type impurity concentration than the first semiconductor layer.

3. The semiconductor device according to claim 1, wherein In the second direction, the fifth semiconductor layer is located between the sixth semiconductor layer and the seventh semiconductor layer.

4. A semiconductor device comprising: 1st electrode; 2nd electrode; a semiconductor portion located between the first electrode and the second electrode in a first direction, the semiconductor portion comprising: a first semiconductor layer of a first conductivity type; and a first surface side region located between the first electrode and the first semiconductor layer in the first direction; and a second surface side region located between the second electrode and the first semiconductor layer in the first direction; a plurality of first gate electrodes facing the first surface side region; a plurality of first insulating films provided between the first surface side region and the plurality of first gate electrodes; a plurality of second gate electrodes facing the second surface side region in the first direction; as well as a plurality of second insulating films provided between the second surface side region and the plurality of second gate electrodes; The first surface side area has: a second semiconductor layer of a second conductivity type, facing the first gate electrode via the first insulating film; as well as a third semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the first electrode; The second surface side area has: a fourth semiconductor layer of the second conductivity type; a fifth semiconductor layer of the second conductivity type, having a second conductivity type impurity concentration higher than that of the second semiconductor layer and the fourth semiconductor layer, and being in contact with the second electrode; as well as a sixth semiconductor layer of the first conductivity type having a higher first conductivity type impurity concentration than the first semiconductor layer and in contact with the second electrode; The fourth semiconductor layer has: a first portion facing the second gate electrode via the second insulating film; and The second portion is located between the plurality of second gate electrodes in a second direction perpendicular to the first direction and is in contact with the second electrode.

5. The semiconductor device according to claim 4, wherein The second-surface region further includes an eighth semiconductor layer of the first conductivity type. The eighth semiconductor layer of the first conductivity type is located between the first semiconductor layer and the fourth semiconductor layer and has a higher first conductivity type impurity concentration than the first semiconductor layer. The semiconductor device according to claim 4 , wherein: In the second direction, the fifth semiconductor layer is located between the sixth semiconductor layer and the second portion of the fourth semiconductor layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein The first gate electrode is provided in a trench formed in the first surface side region via the first insulating film. In the second direction, the first gate electrode faces the second semiconductor layer via the first insulating film.

8. The semiconductor device according to any one of claims 1 to 6, wherein The first-surface-side region further includes a ninth semiconductor layer of the second conductivity type. The ninth semiconductor layer of the second conductivity type is located between the first gate electrodes adjacent to each other in the second direction and is deeper than the second semiconductor layer.

Images