Semiconductor device

Abstract

Provided is a semiconductor device capable of reducing loss. According to one embodiment, a semiconductor device includes first and second elements, first to sixth terminals, and a circuit portion. Each of the first and second elements includes first to fourth electrodes and a semiconductor component. The circuit unit sets the second terminal to a first potential during a first period. The circuit unit sets the second terminal to a third potential during a second period after the first period. The circuit unit sets the second terminal to a second potential during a third period after the second period. The second potential is lower than the first potential. The third potential is between the first potential and the second potential. The circuit unit sets the third terminal to a first potential during the first and second periods. The circuit unit sets the third terminal to a second potential during a third period. The circuit unit sets the fifth and sixth terminals to the fourth potential during the first and second periods. The circuit unit sets the fifth and sixth terminals to the fifth potential during the third period. The fourth potential is lower than the fifth potential.

Description

[0001] This application is based on and claims the benefit of priority from Japanese Patent Application No. 2024-039149 (filing date: March 13, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device. Background Art

[0003] For example, semiconductor devices such as IGBTs (insulated gate bipolar transistors) are used in power conversion circuits, etc., and reduction in loss is desired. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device capable of reducing loss.

[0005] According to an embodiment of the present invention, a semiconductor device includes a first element, a second element, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, a sixth terminal, and a circuit unit. The first element and the second element each include a first electrode, a second electrode, a third electrode, a fourth electrode, and a semiconductor component. The semiconductor component is disposed between the first electrode and the second electrode. A second direction from the third electrode toward the fourth electrode intersects a first direction from the first electrode toward the second electrode. The semiconductor component includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a sixth semiconductor region of the second conductivity type. The first semiconductor region includes a first partial region, a second partial region, a third partial region, and a fourth partial region. The direction from the first partial region toward the third electrode is along the first direction. The direction from the second partial region toward the fourth electrode is along the first direction. The second semiconductor region is connected to the second electrode. A direction from a portion of the third electrode toward the second semiconductor region follows the second direction. A portion of the third semiconductor region is located between the third partial region and the second semiconductor region in the first direction. A direction from the portion of the third electrode toward the portion of the third semiconductor region follows the second direction. Another portion of the third semiconductor region is located between the fourth partial region and the fourth semiconductor region in the first direction. A direction from the other portion of the third semiconductor region toward a portion of the fourth electrode follows the second direction. The fifth semiconductor region is located between the first electrode and the first semiconductor region in the first direction. The sixth semiconductor region is located between the first electrode and the first semiconductor region in the first direction. A direction from the fifth semiconductor region toward the sixth semiconductor region follows the fourth direction. The fourth direction follows a plane including the third direction and the second direction, and the third direction intersects the plane including the first direction and the second direction. The first terminal is electrically connected to the second electrode of the first element. The second terminal is electrically connected to the third electrode of the first element. The third terminal is electrically connected to the fourth electrode of the first element. The fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element. The fifth terminal is electrically connected to the third electrode of the second element. The sixth terminal is electrically connected to the fourth electrode of the second element. The circuit portion is configured to set the second terminal to a first potential based on the potential of the first terminal during a first period.The circuit portion is configured to set the second terminal to a third potential based on the potential of the first terminal during a second period following the first period. The circuit portion is configured to set the second terminal to a second potential based on the potential of the first terminal during a third period following the second period. The second potential is lower than the first potential. The third potential is between the first and second potentials. The circuit portion is configured to set the third terminal to the first potential during the first and second periods. The circuit portion is configured to set the third terminal to the second potential during the third period. The circuit portion is configured to set the fifth and sixth terminals to a fourth potential based on the potential of the fourth terminal during the first and second periods. The circuit portion is configured to set the fifth and sixth terminals to a fifth potential based on the potential of the fourth terminal during the third period. The fourth potential is lower than the fifth potential.

[0006] According to the semiconductor device having the above structure, a semiconductor device capable of reducing loss can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 (a)- Figure 1 (d) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0008] Figure 2 This is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0009] Figure 3 This is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0010] Figure 4 This is an equivalent circuit illustrating the semiconductor device according to the first embodiment.

[0011] Figure 5 (a)- Figure 5 (d) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0012] (Explanation of Reference Numerals)

[0013] 10A, 10B: 1st and 2nd elements; 10M: semiconductor component; 11-16: 1st to 6th semiconductor regions; 11a-11d: 1st to 4th partial regions; 13p, 13q: a part; 41, 42: 1st and 2nd insulating components; 51-54: 1st to 4th electrodes; 70: circuit portion; 110: semiconductor device; D1-D4: 1st to 4th directions; PL1: plane; T1-T7: 1st to 7th terminals; TP1-TP3: 1st to 3rd periods; V1-V3: 1st to 3rd potentials; Vc1, Vc2, Vg1, Vg2: potentials; Vcc: controlled voltage; t0: moment; t1, t2: 1st moment; ta2: moment; tm: time; Δt, Δt1-Δt3: time. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0015] The drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as in reality. Even if the same part is shown, the relative sizes and ratios may be shown differently depending on the drawing.

[0016] In the present specification and each drawing, the same elements as those described with respect to the already mentioned drawings are denoted by the same reference numerals, and detailed description thereof will be appropriately omitted.

[0017] (First embodiment)

[0018] Figure 1 (a)- Figure 1 (d) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0019] Figure 2 as well as Figure 3 This is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.

[0020] Figure 4 This is an equivalent circuit illustrating the semiconductor device according to the first embodiment.

[0021] like Figure 2 as well as Figure 3 As shown, the semiconductor device 110 of the embodiment includes a first element 10A, a second element 10B, a first terminal T1 , a second terminal T2 , a third terminal T3 , a fourth terminal T4 , a fifth terminal T5 , a sixth terminal T6 , and a circuit portion 70 .

[0022] The first element 10A and the second element 10B each include a first electrode 51 , a second electrode 52 , a third electrode 53 , a fourth electrode 54 , and a semiconductor component 10M. The semiconductor component 10M is provided between the first electrode 51 and the second electrode 52 .

[0023] The second direction D2 from the third electrode 53 toward the fourth electrode 54 intersects the first direction D1 from the first electrode 51 toward the second electrode 52. The first direction D1 is referred to as the Z-axis direction. A direction perpendicular to the Z-axis direction is referred to as the X-axis direction. A direction perpendicular to both the Z-axis direction and the X-axis direction is referred to as the Y-axis direction. The second direction D2 may be, for example, the X-axis direction.

[0024] For example, the third electrode 53 and the fourth electrode 54 may extend along a third direction D3 that intersects a plane including the first direction D1 and the second direction D2. The third direction D3 may be, for example, the Y-axis direction.

[0025] The semiconductor component 10M includes a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, a fourth semiconductor region 14, a fifth semiconductor region 15, and a sixth semiconductor region 16. The semiconductor component 10M may include, for example, silicon. The semiconductor component 10M may include, for example, a compound semiconductor. For example, the compound semiconductor may include Ga and N. For example, the compound semiconductor may include silicon carbide. The semiconductor component 10M extends along the second direction D2 and the third direction D3.

[0026] The first semiconductor region 11 is of a first conductivity type. The first conductivity type is one of an n-type and a p-type. Hereinafter, the first conductivity type is assumed to be an n-type.

[0027] The first semiconductor region 11 includes a first partial region 11a, a second partial region 11b, a third partial region 11c, and a fourth partial region 11d. The direction from the first partial region 11a to the third electrode 53 is along the first direction D1. The direction from the second partial region 11b to the fourth electrode 54 is along the first direction D1.

[0028] The region overlapping with the third electrode 53 in the Z-axis direction corresponds to the first partial region 11a. The first partial region 11a is located between the third electrode 53 and the first electrode 51. The region overlapping with the fourth electrode 54 in the Z-axis direction corresponds to the second partial region 11b. The second partial region 11b is located between the third electrode 53 and the first electrode 51. The boundaries between the first partial region 11a, the second partial region 11b, the third partial region 11c, and the fourth partial region 11d may be clear or unclear.

[0029] The direction from a portion of the third electrode 53 to a portion of the first semiconductor region 11 follows the second direction D2. The direction from a portion of the fourth electrode 54 to a portion of the first semiconductor region 11 follows the second direction D2. The direction from a portion of the first insulating member 41 to a portion of the third partial region 11 c follows the second direction D2. The portion of the first insulating member 41 in contact with the third electrode 53 is in contact with a portion of the third partial region 11 c. The direction from a portion of the first insulating member 41 to a portion of the fourth partial region 11 d follows the second direction D2. The portion of the first insulating member 41 in contact with the fourth electrode 54 is in contact with a portion of the fourth partial region 11 d.

[0030] The second semiconductor region 12 is of the first conductivity type. The direction from a portion of the third electrode 53 toward the second semiconductor region 12 is along the second direction D2. For example, the second semiconductor region 12 is provided between the first electrode 51 and the second electrode 52 in the first direction D1. The second semiconductor region 12 is in contact with a portion of the first insulating member 41 that is in contact with the third electrode 53. The second semiconductor region 12 is in contact with the second electrode 52.

[0031] The third semiconductor region 13 has the second conductivity type. The second conductivity type is the other of n-type and p-type. Hereinafter, the second conductivity type is assumed to be p-type. The third semiconductor region 13 can be connected to the second electrode 52. The boundary between the third semiconductor region 13 and the first semiconductor region 11 is in contact with the first insulating component 41. A portion 13p of the third semiconductor region 13 is located between the third partial region 11c and the second semiconductor region 12 in the first direction D1. The direction from a portion of the third electrode 53 to the portion 13p of the third semiconductor region 13 is along the second direction D2. In the first semiconductor region 11, the region that overlaps with the second semiconductor region 12 in the first direction D1 corresponds to the third partial region 11c. A portion 13p of the third semiconductor region 13 is in contact with a portion of the first insulating component 41 that is in contact with the third electrode 53.

[0032] The fourth semiconductor region 14 is of the second conductivity type. Another portion 13q of the third semiconductor region 13 is located between the fourth partial region 11d and the fourth semiconductor region 14 in the first direction D1. The direction from the other portion 13q of the third semiconductor region 13 toward a portion of the fourth electrode 54 is along the second direction D2. In the first semiconductor region 11, the region that overlaps with the fourth semiconductor region 14 in the first direction D1 corresponds to the fourth partial region 11d. For example, the fourth semiconductor region 14 is provided between the first semiconductor region 11 and the second electrode 52 in the first direction D1. Another portion 13q of the third semiconductor region 13 is in contact with a portion of the first insulating member 41 that is in contact with the fourth electrode 54. The fourth semiconductor region 14 is in contact with a portion of the first insulating member 41 that is in contact with the fourth electrode 54. The fourth semiconductor region 14 is in contact with the second electrode 52.

[0033] The fifth semiconductor region 15 is provided in the first direction D1 between the first electrode 51 and the first semiconductor region 11. The fifth semiconductor region 15 is of the first conductivity type.

[0034] The sixth semiconductor region 16 is provided between the first electrode 51 and the first semiconductor region 11 in the first direction D1. The sixth semiconductor region 16 is of the second conductivity type. The direction from the fifth semiconductor region 15 to the sixth semiconductor region 16 is along the fourth direction D4. The fourth direction D4 is along the plane PL1 including the second direction D2 and the third direction D3. For example, the fourth direction D4 is along the second direction D2.

[0035] A plurality of fifth semiconductor regions 15 and a plurality of sixth semiconductor regions 16 may be provided. The fifth semiconductor regions 15 and the sixth semiconductor regions 16 may be provided alternately. The fifth semiconductor region 15 and the sixth semiconductor region 16 are in contact with the first electrode 51 .

[0036] like Figure 2 As shown, the first terminal T1 is electrically connected to the second electrode 52 of the first element 10A. The second terminal T2 is electrically connected to the third electrode 53 of the first element 10A. The third terminal T3 is electrically connected to the fourth electrode 54 of the first element 10A.

[0037] like Figure 2 as well as Figure 3 As shown, the fourth terminal T4 is electrically connected to the second electrode 52 of the second element 10B and the first electrode 51 of the first element 10A. The second electrode 52 of the second element 10B is electrically connected to the first electrode 51 of the first element 10A.

[0038] like Figure 3 As shown, the fifth terminal T5 is electrically connected to the third electrode 53 of the second element 10B. The sixth terminal T6 is electrically connected to the fourth electrode 54 of the second element 10B.

[0039] In the first element 10A and the second element 10B, the current flowing between the first electrode 51 and the second electrode 52 is controlled by the potential of the third electrode 53 and the potential of the fourth electrode 54. The first electrode 51 functions as, for example, a collector electrode. The second electrode 52 functions as, for example, an emitter electrode. The third electrode 53 functions as, for example, a first gate electrode. The fourth electrode 54 functions as, for example, a second gate electrode. The third electrode 53 functions as, for example, a main gate. The fourth electrode 54 functions as, for example, a control gate electrode.

[0040] The semiconductor device 110 is, for example, a dual-gate RC-IEGT (Reverse-Conducting Injection Enhanced Gate Transistor).

[0041] The circuit unit 70 is electrically connected to the first terminal T1, the second terminal T2, the third terminal T3, the fourth terminal T4, the fifth terminal T5, and the sixth terminal T6, and is configured to control the potential of each of these terminals.

[0042] Figure 1 (a) illustrates the potential Vg2 of the fifth terminal T5 of the second element 10B. Figure 1 (b) shows an example of the potential Vc2 of the sixth terminal T6 of the second element 10B. Figure 1 (c) shows an example of the potential Vg1 of the second terminal T2 of the first element 10A. Figure 1 (d) shows an example of the potential Vc1 of the third terminal T3 of the first element 10A. The horizontal axis of these graphs represents time tm.

[0043] like Figure 1 As shown in (c), the circuit portion 70 is configured such that the second terminal T2 is set to a first potential V1 during the first period TP1. The first potential V1 is a potential with respect to the potential of the first terminal T1. The circuit portion 70 is configured such that the second terminal T2 is set to a third potential V3 during the second period TP2 following the first period TP1. The third potential V3 is a potential with respect to the potential of the first terminal T1.

[0044] The circuit portion 70 is configured such that, during a third period TP3 following the second period TP2, the second terminal T2 is set to a second potential V2. The second potential V2 is a potential based on the potential of the first terminal T1. The second potential V2 is lower than the first potential V1. The third potential V3 is between the first potential V1 and the second potential V2.

[0045] In one example, the first potential V1 is +15 V. In one example, the second potential V2 is −15 V. In one example, the third potential V3 may be 0 V, for example.

[0046] like Figure 1 As shown in (d), the circuit portion 70 is configured so that the third terminal T3 is at the first potential V1 during the first period TP1 and the second period TP2. The circuit portion 70 is configured so that the third terminal T3 is at the second potential V2 during the third period TP3.

[0047] like Figure 1 (a) and Figure 1 As shown in (b), the circuit portion 70 is configured to set the fifth terminal T5 and the sixth terminal T6 to the fourth potential V4 during the first period TP1 and the second period TP2. The fourth potential V4 is a potential based on the potential of the fourth terminal T4. The circuit portion 70 is configured to set the fifth terminal T5 and the sixth terminal T6 to the fifth potential V5 during the third period TP3. The fifth potential V5 is a potential based on the potential of the fourth terminal T4. The fourth potential V4 is lower than the fifth potential V5. The value of the fourth potential V4 can be the same as the value of the second potential V2. The value of the fifth potential V5 can be the same as the value of the first potential V1. For example, the fifth potential V5 is positive and the fourth potential V4 is negative.

[0048] For example, before the first period TP1, the first element 10A is in a steady-state on state. During the first period TP1, the first element 10A operates in diode mode. The first period TP1 corresponds to, for example, the electron extraction period. The second period TP2 corresponds to the transition period (dead time) between modes. During the third period TP3, the first element 10A operates in reverse recovery mode. Meanwhile, during the first period TP1 and the second period TP2, the second element 10B is in an off state. For example, during the third period TP3, the second element 10B operates in IEGT mode. At the second time t2, the second element 10B begins to conduct.

[0049] In the embodiment, during the second period TP2, the potential Vg1 of the second terminal T2 of the first element 10A is set to an intermediate third potential V3. Thus, the first element 10A functions as a low-injection diode. This suppresses high-injection diode operation during the transition period (dead time) between modes. For example, reverse recovery occurs in a state of reduced carriers. This reduces reverse recovery loss Err. According to the embodiment, a semiconductor device capable of reducing losses can be provided.

[0050] As described above, the fourth electrode 54 is provided with the first conductivity type fourth semiconductor region 14 instead of the first conductivity type second semiconductor region 12. Thus, during the second period TP2, even when the potential Vc1 of the third terminal T3 (fourth electrode 54) is the first potential V1, electrons can be suppressed from moving toward the second electrode 52 near the fourth electrode 54.

[0051] In the embodiment, after the potential Vg1 of the second terminal T2 (third electrode 53) drops from the first potential V1, the potential Vg2 of the fifth terminal T5 and the potential Vc2 of the sixth terminal T6 change from the fourth potential V4 to the fifth potential V5. This substantially prevents a short circuit between the first terminal T1 and the seventh terminal T7, thus suppressing component damage caused by a short circuit.

[0052] For example, in the first reference example, during the first period TP1, the potential Vg1 of the second terminal T2 (third electrode 53) and the potential Vc1 of the third terminal T3 (fourth electrode 54) are the first potential V1. During the second period TP2 and the third period TP3, these potentials become the second potential V2. On the other hand, during the first period TP1 and the second period TP2, the potential Vg2 of the fifth terminal T5 (third electrode 53) and the potential Vc2 of the sixth terminal T6 (fourth electrode 54) are the fourth potential V4. During the third period TP3, these potentials become the fifth potential V5. In this first reference example, reverse recovery occurs in a state with a large number of carriers. Therefore, the reverse recovery loss Err is large.

[0053] For example, in the second reference example, a first-conductivity-type second semiconductor region 12 is provided on the side of the fourth electrode 54, rather than a second-conductivity-type fourth semiconductor region 14. Furthermore, in the second reference example, during the second period TP2, the potential Vc1 of the third terminal T3 (fourth electrode 54) becomes the second potential V2. Otherwise, the potential changes in the second reference example are the same as those in the semiconductor device 110. In this second reference example, reverse recovery occurs near the fourth electrode 54 of the first element 10A in a state with a high number of carriers. Therefore, there is a limit to reducing the reverse recovery loss Err.

[0054] When the reverse recovery loss Err in the first reference example is set to 1, the reverse recovery loss Err in the second reference example is 0.947. When the reverse recovery loss Err in the first reference example is set to 1, the reverse recovery loss Err in the semiconductor device 110 of the embodiment is 0.918. Thus, according to the embodiment, the loss can be suppressed.

[0055] like Figure 3 As shown, the semiconductor device 110 may further include a seventh terminal T7. The seventh terminal T7 is electrically connected to the first electrode 51 of the second element 10B.

[0056] like Figure 4 As shown, the circuit unit 70 is configured to apply a controlled voltage Vcc between the first terminal T1 and the seventh terminal T7.

[0057] In an embodiment, for example, the third potential V3 may be lower than the threshold voltage of the first element 10A. In an embodiment, the third potential V3 may be a value substantially intermediate between the first potential V1 and the second potential V2. For example, the first absolute value of the first difference between the third potential V3 and the first potential V1 may be greater than or equal to 0.8 times and less than or equal to 1.2 times the second absolute value of the second difference between the third potential V3 and the second potential V2. In an embodiment, for example, the first potential V1 is positive, and the second potential V2 is negative.

[0058] In an embodiment, the second length of the second period TP2 is shorter than the first length of the first period TP1. For example, the second length may be 10 to 100 times the first length. For example, the first length may be 10 to 200 μs. For example, the second length may be 1 to 10 μs.

[0059] like Figure 1 (c) and Figure 1 As shown in (d), the first period TP1 is the period from time t0 to the first time t1. The second period TP2 is the period from the first time t1 to the second time t2. The third period TP3 is the period after the second time t2.

[0060] like Figure 1 As shown in (c), the circuit portion 70 can be configured to change the potential Vg1 of the second terminal T2 from the first potential V1 to the second potential V2 at the first time t1. As already described, the first potential V1 is a potential with the potential of the first terminal T1 as a reference. The second potential V2 is a potential with the potential of the first terminal T1 as a reference. The second potential V2 is lower than the first potential V1. The circuit portion 70 is configured to set the potential Vg1 of the second terminal T2 to the second potential V2 at the second time t2 after the first time t1.

[0061] like Figure 1 As shown in (d), the circuit unit 70 is configured so that the potential Vc1 of the third terminal T3 changes from the first potential V1 to the second potential V2 at the second time t2.

[0062] like Figure 1 (a) and Figure 1 As shown in (b), the circuit portion 70 is configured to change the potential Vg2 of the fifth terminal T5 and the potential Vc2 of the sixth terminal T6 from the fourth potential V4 to the fifth potential V5 at the second time t2.

[0063] The time between the first time t1 and the second time t2 (the second period TP2) is longer than the time Δt1 during which the potential Vc1 of the third terminal T3 changes from the first potential V1 to the second potential V2. The time between the first time t1 and the second time t2 (the second period TP2) is longer than the time Δt2 and time Δt3 during which the potential Vg2 of the fifth terminal T5 and the potential Vc2 of the sixth terminal T6 change from the fourth potential V4 to the fifth potential V5. For example, the first period TP1 is longer than the second period TP2. The slope (dV / dt) of the change in the potential Vg1 of the second terminal T2 between the time t0 and the first time t1 is smaller than the slope of the change in the potential Vg1 of the second terminal T2 at the first time t1. The slope (dV / dt) of the change in the potential Vg1 of the second terminal T2 between the first time t1 and the second time t2 is smaller than the slope of the change in the potential Vg1 of the second terminal T2 at the first time t1. The slope of the change in the potential Vg1 of the second terminal T2 between the first time t1 and the second time t2 is smaller than the slope of the change in the potential Vg1 of the second terminal T2 at the second time t2.

[0064] exist Figure 1 (a)- Figure 1 In the example shown in (d), the timing at which the fifth terminal T5 and the sixth terminal T6 reach the fifth potential V5 is the same as the timing at which the third terminal T3 reaches the second potential V2.

[0065] Figure 5 (a)- Figure 5 (d) is a schematic diagram illustrating the operation of the semiconductor device according to the first embodiment.

[0066] These figures show other examples of the operation in the semiconductor device 110. Figure 5 (a)- Figure 5 In example (d), after the time (second time t2) at which the fifth terminal T5 and the sixth terminal T6 reach the fifth potential V5, the third terminal T3 reaches the second potential V2. The time Δt between the time (second time t2) at which the fifth terminal T5 and the sixth terminal T6 reach the fifth potential V5 and the time ta2 at which the third terminal T3 reaches the second potential V2 is less than 1 μs. Thus, the time ta2 can be after the second time t2. By reducing the difference in these times to, for example, less than 1 μs, it is possible to suppress losses.

[0067] like Figure 2 as well as Figure 3As shown, for example, each of the first element 10A and the second element 10B may further include a first insulating member 41. The first insulating member 41 of the first element 10A is provided between the third electrode 53 of the first element 10A and the semiconductor component 10M of the first element 10A, and between the fourth electrode 54 of the first element 10A and the semiconductor component 10M of the first element 10A.

[0068] The first insulating member 41 of the second element 10B is provided between the third electrode 53 of the second element 10B and the semiconductor component 10M of the second element 10B and between the fourth electrode 54 of the second element 10B and the semiconductor component 10M of the second element 10B.

[0069] For example, a portion of the first insulating member 41 contacts a portion of the third electrode 53 and the second semiconductor region 12 in the second direction D2. Another portion of the first insulating member 41 contacts a portion of the fourth electrode 54 and the fourth semiconductor region 14 in the second direction D2.

[0070] like Figure 2 as well as Figure 3 As shown, each of the first element 10A and the second element 10B may further include a second insulating member 42. The second insulating member 42 of the first element 10A is provided between the third electrode 53 of the first element 10A and the second electrode 52 of the first element 10A, and between the fourth electrode 54 of the first element 10A and the second electrode 52 of the first element 10A.

[0071] The second insulating member 42 of the second element 10B is provided between the third electrode 53 of the second element 10B and the second electrode 52 of the second element 10B and between the fourth electrode 54 of the second element 10B and the second electrode 52 of the second element 10B.

[0072] In the embodiment, for example, the second impurity concentration of the first conductivity type in the second semiconductor region 12 is higher than the first impurity concentration of the first conductivity type in the first semiconductor region 11. For example, the fifth impurity concentration of the first conductivity type in the fifth semiconductor region 15 is higher than the first impurity concentration.

[0073] For example, the concentration of the second conductivity type fourth impurity in the fourth semiconductor region 14 is higher than the concentration of the second conductivity type third impurity in the third semiconductor region 13. For example, the concentration of the second conductivity type sixth impurity in the sixth semiconductor region 16 is higher than the concentration of the third impurity.

[0074] like Figure 2 as well as Figure 3As shown, each of the first element 10A and the second element 10B may further include a fifth electrode 55. The fifth electrode 55 is electrically connected to the second electrode 52. The direction from a portion of the fifth electrode 55 toward a portion of the first semiconductor region 11 is along the second direction D2. The direction from a portion of the fifth electrode 55 toward a portion of the third semiconductor region 13 is along the second direction D2. The direction from a portion of the fifth electrode 55 toward a portion of the fourth semiconductor region 14 is along the second direction D2. Providing the fifth electrode 55 facilitates, for example, achieving a high withstand voltage.

[0075] In an embodiment, information related to the shape of the semiconductor region, etc. is obtained by electron microscopy, etc. For example, information related to the impurity concentration in the semiconductor region can be obtained by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). For example, information related to the carrier concentration in the semiconductor region can be obtained by SCM (Scanning Capacitance Microscopy), etc.

[0076] Implementation methods may include the following technical solutions.

[0077] (Technical Solution 1)

[0078] A semiconductor device comprising:

[0079] 1st element;

[0080] 2nd element;

[0081] Terminal 1;

[0082] Terminal 2;

[0083] Terminal 3;

[0084] Terminal 4;

[0085] Terminal 5;

[0086] Terminal 6; and

[0087] Circuit Department,

[0088] The first element and the second element respectively include:

[0089] 1st electrode;

[0090] 2nd electrode;

[0091] 3rd electrode;

[0092] a fourth electrode; and

[0093] a semiconductor component disposed between the first electrode and the second electrode,

[0094] The second direction from the third electrode to the fourth electrode intersects the first direction from the first electrode to the second electrode.

[0095] The semiconductor component comprises:

[0096] a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, and a fourth partial region, a direction from the first partial region toward the third electrode being along the first direction, and a direction from the second partial region toward the fourth electrode being along the first direction;

[0097] The second semiconductor region of the first conductivity type is arranged along the second direction from a portion of the third electrode toward the second semiconductor region, and the second semiconductor region is connected to the second electrode;

[0098] a third semiconductor region of the second conductivity type, a portion of the third semiconductor region being located between the third partial region and the second semiconductor region in the first direction, and a direction from the portion of the third electrode to the portion of the third semiconductor region being along the second direction;

[0099] the fourth semiconductor region of the second conductivity type, the other portion of the third semiconductor region being located between the fourth partial region and the fourth semiconductor region in the first direction, and the direction from the other portion of the third semiconductor region to the portion of the fourth electrode being along the second direction;

[0100] The fifth semiconductor region of the first conductivity type is provided between the first electrode and the first semiconductor region in the first direction; and

[0101] The sixth semiconductor region of the second conductivity type is provided between the first electrode and the first semiconductor region in the first direction, and a direction from the fifth semiconductor region to the sixth semiconductor region is along a fourth direction, the fourth direction is along a plane including a third direction and the second direction, and the third direction intersects the plane including the first direction and the second direction.

[0102] The first terminal is electrically connected to the second electrode of the first element,

[0103] The second terminal is electrically connected to the third electrode of the first element.

[0104] The third terminal is electrically connected to the fourth electrode of the first element.

[0105] The fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element.

[0106] The fifth terminal is electrically connected to the third electrode of the second element.

[0107] The sixth terminal is electrically connected to the fourth electrode of the second element.

[0108] The circuit unit is configured to set the second terminal to a first potential based on the potential of the first terminal during a first period.

[0109] The circuit unit is configured to set the second terminal to a third potential based on the potential of the first terminal during a second period following the first period.

[0110] The circuit portion is configured to set the second terminal to a second potential based on the potential of the first terminal during a third period following the second period, wherein the second potential is lower than the first potential, and the third potential is between the first potential and the second potential.

[0111] The circuit unit is configured to set the third terminal to the first potential during the first period and the second period.

[0112] The circuit unit is configured to set the third terminal to the second potential during the third period.

[0113] The circuit unit is configured to set the fifth terminal and the sixth terminal to a fourth potential based on the potential of the fourth terminal during the first period and the second period.

[0114] The circuit unit is configured to set the fifth terminal and the sixth terminal to a fifth potential based on the potential of the fourth terminal during the third period, and the fourth potential is lower than the fifth potential.

[0115] (Technical Solution 2)

[0116] The semiconductor device according to claim 1 further comprises a seventh terminal electrically connected to the first electrode of the second element.

[0117] The circuit unit is configured to apply a controlled voltage between the first terminal and the seventh terminal.

[0118] (Technical Solution 3)

[0119] The semiconductor device according to claim 1 or 2, wherein the third potential is lower than a threshold voltage of the first element.

[0120] (Technical Solution 4)

[0121] The semiconductor device according to any one of technical solutions 1 to 3, wherein a first absolute value of a first difference between the third potential and the first potential is greater than or equal to 0.8 times and less than or equal to 1.2 times a second absolute value of a second difference between the third potential and the second potential.

[0122] (Technical Solution 5)

[0123] The semiconductor device according to any one of technical solutions 1 to 4, wherein the first potential is positive,

[0124] The second potential is negative.

[0125] (Technical Solution 6)

[0126] The semiconductor device according to any one of claims 1 to 5, wherein a second length of the second period is shorter than a first length of the first period.

[0127] (Technical Solution 7)

[0128] The semiconductor device according to claim 6, wherein the second length is not less than 10 times and not more than 100 times the first length.

[0129] (Technical Solution 8)

[0130] The semiconductor device according to claim 6 or 7, wherein the first length is not less than 10 μs and not more than 200 μs,

[0131] The second length is greater than or equal to 1 μs and less than 10 μs.

[0132] (Technical Solution 9)

[0133] The semiconductor device according to any one of claims 1 to 8, wherein the timing at which the fifth terminal and the sixth terminal attain the fifth potential is the same as the timing at which the third terminal attains the second potential.

[0134] (Technical Solution 10)

[0135] The semiconductor device according to any one of claims 1 to 8, wherein the third terminal becomes the second potential after the fifth terminal and the sixth terminal become the fifth potential.

[0136] A time period between the time when the fifth terminal and the sixth terminal are at the fifth potential and the time when the third terminal is at the second potential is 1 μs or less.

[0137] (Technical Solution 11)

[0138] The semiconductor device according to any one of technical solutions 1 to 10, wherein each of the first element and the second element further includes a first insulating member.

[0139] The first insulating member of the first element is provided between the third electrode of the first element and the semiconductor member of the first element and between the fourth electrode of the first element and the semiconductor member of the first element.

[0140] The first insulating member of the second element is provided between the third electrode of the second element and the semiconductor component of the second element and between the fourth electrode of the second element and the semiconductor component of the second element.

[0141] (Technical Solution 12)

[0142] The semiconductor device according to claim 11, wherein a portion of the first insulating member is in contact with a portion of the third electrode and the second semiconductor region in the second direction.

[0143] (Technical Solution 13)

[0144] In the semiconductor device according to claim 12, another portion of the first insulating member is in contact with a portion of the fourth electrode and the fourth semiconductor region in the second direction.

[0145] (Technical Solution 14)

[0146] The semiconductor device according to any one of technical solutions 1 to 13, wherein the first element and the second element each further include a second insulating member.

[0147] The second insulating member of the first element is provided between the third electrode of the first element and the second electrode of the first element and between the fourth electrode of the first element and the second electrode of the first element.

[0148] The second insulating member of the second element is provided between the third electrode of the second element and the second electrode of the second element and between the fourth electrode of the second element and the second electrode of the second element.

[0149] (Technical Solution 15)

[0150] The semiconductor device according to any one of claims 1 to 14, wherein the second impurity concentration of the first conductivity type in the second semiconductor region is higher than the first impurity concentration of the first conductivity type in the first semiconductor region.

[0151] (Technical Solution 16)

[0152] The semiconductor device according to claim 15, wherein the concentration of the fifth impurity of the first conductivity type in the fifth semiconductor region is higher than the first impurity concentration.

[0153] (Technical Solution 17)

[0154] The semiconductor device according to any one of technical solutions 1 to 16, wherein the concentration of the fourth impurity of the second conductivity type in the fourth semiconductor region is higher than the concentration of the third impurity of the second conductivity type in the third semiconductor region.

[0155] (Technical Solution 18)

[0156] The semiconductor device according to claim 17, wherein the concentration of the sixth impurity of the second conductivity type in the sixth semiconductor region is higher than the third impurity concentration.

[0157] (Technical Solution 19)

[0158] The semiconductor device according to any one of technical solutions 1 to 18, wherein the third electrode and the fourth electrode extend along a third direction that intersects a plane including the first direction and the second direction.

[0159] (Technical Solution 20)

[0160] A semiconductor device comprising:

[0161] 1st element;

[0162] 2nd element;

[0163] Terminal 1;

[0164] Terminal 2;

[0165] Terminal 3;

[0166] Terminal 4;

[0167] Terminal 5;

[0168] Terminal 6; and

[0169] Circuit Department,

[0170] The first element and the second element respectively include:

[0171] 1st electrode;

[0172] 2nd electrode;

[0173] 3rd electrode;

[0174] a fourth electrode; and

[0175] a semiconductor component disposed between the first electrode and the second electrode,

[0176] The second direction from the third electrode to the fourth electrode intersects the first direction from the first electrode to the second electrode.

[0177] The semiconductor component comprises:

[0178] a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, and a fourth partial region, a direction from the first partial region toward the third electrode being along the first direction, and a direction from the second partial region toward the fourth electrode being along the first direction;

[0179] The second semiconductor region of the first conductivity type is arranged along the second direction from a portion of the third electrode to the second semiconductor region;

[0180] a third semiconductor region of the second conductivity type, a portion of the third semiconductor region being located between the third partial region and the second semiconductor region in the second direction, and a direction from the portion of the third electrode to the portion of the third semiconductor region being along the second direction;

[0181] the fourth semiconductor region of the second conductivity type, the other portion of the third semiconductor region being located between the fourth partial region and the fourth semiconductor region in the second direction, and the direction from the other portion of the third semiconductor region to the portion of the fourth electrode being along the second direction;

[0182] The fifth semiconductor region of the first conductivity type is provided between the first electrode and the first semiconductor region in the first direction; and

[0183] The sixth semiconductor region of the second conductivity type is provided between the first electrode and the first semiconductor region in the first direction, and a direction from the fifth semiconductor region to the sixth semiconductor region is along a fourth direction, the fourth direction is along a plane including a third direction and the second direction, and the third direction intersects the plane including the first direction and the second direction.

[0184] The first terminal is electrically connected to the second electrode of the first element,

[0185] The second terminal is electrically connected to the third electrode of the first element.

[0186] The third terminal is electrically connected to the fourth electrode of the first element.

[0187] The fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element.

[0188] The fifth terminal is electrically connected to the third electrode of the second element.

[0189] The sixth terminal is electrically connected to the fourth electrode of the second element.

[0190] The circuit unit is configured to change the potential of the second terminal from a first potential to a second potential at a first moment.

[0191] The first potential is a potential based on the potential of the first terminal.

[0192] The second potential is a potential based on the potential of the first terminal.

[0193] The second potential is lower than the first potential,

[0194] The circuit portion is configured to set the potential of the second terminal to the second potential at a second time after the first time.

[0195] The circuit unit is configured to change the potential of the third terminal from the first potential to the second potential at the second time.

[0196] The circuit portion is configured to change the potential of the fifth terminal and the potential of the sixth terminal from a fourth potential to a fifth potential at the second time.

[0197] The fourth potential is a potential based on the potential of the fourth terminal.

[0198] The fifth potential is a potential based on the potential of the fourth terminal.

[0199] The fourth potential is lower than the fifth potential,

[0200] The time between the first moment and the second moment is longer than the time it takes for the potential of the third terminal to change from the first potential to the second potential.

[0201] The time between the first time and the second time is longer than the time it takes for the potential at the fifth terminal and the potential at the sixth terminal to change from the fourth potential to the fifth potential.

[0202] According to the embodiment, a semiconductor device capable of reducing loss can be provided.

[0203] In the present specification, “perpendicular” and “parallel” are not only strictly perpendicular and strictly parallel but also include, for example, fluctuations in the manufacturing process, as long as they are substantially perpendicular and substantially parallel.

[0204] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of various elements included in a semiconductor device, such as components, terminals, circuit portions, electrodes, semiconductor components, and insulating components, are encompassed by the present invention as long as those skilled in the art can achieve the same effects by appropriately selecting from known configurations and implementing the present invention in the same manner.

[0205] Furthermore, any combination of two or more elements of each specific example within a technically feasible range is also included in the scope of the present invention as long as it includes the gist of the present invention.

[0206] Furthermore, based on the semiconductor devices described above as embodiments of the present invention, any semiconductor devices that can be implemented by a person skilled in the art by appropriately changing the design fall within the scope of the present invention as long as they include the gist of the present invention.

[0207] It is considered that those skilled in the art can conceive of various changes and modifications within the scope of the concept of the present invention, and these changes and modifications also fall within the scope of the present invention.

[0208] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in various other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

Claims

1. A semiconductor device comprising: 1st element; 2nd element; Terminal 1; Terminal 2; Terminal 3; Terminal 4; Terminal 5; Terminal 6; as well as Circuit Department, The first element and the second element respectively include: 1st electrode; 2nd electrode; 3rd electrode; a fourth electrode; and a semiconductor component disposed between the first electrode and the second electrode, The second direction from the third electrode to the fourth electrode intersects the first direction from the first electrode to the second electrode. The semiconductor component comprises: a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, and a fourth partial region, a direction from the first partial region toward the third electrode being along the first direction, and a direction from the second partial region toward the fourth electrode being along the first direction; The second semiconductor region of the first conductivity type is arranged along the second direction from a portion of the third electrode toward the second semiconductor region, and the second semiconductor region is connected to the second electrode; a third semiconductor region of the second conductivity type, a portion of the third semiconductor region being located between the third partial region and the second semiconductor region in the first direction, and a direction from the portion of the third electrode to the portion of the third semiconductor region being along the second direction; the fourth semiconductor region of the second conductivity type, the other portion of the third semiconductor region being located between the fourth partial region and the fourth semiconductor region in the first direction, and the direction from the other portion of the third semiconductor region to the portion of the fourth electrode being along the second direction; The fifth semiconductor region of the first conductivity type is provided between the first electrode and the first semiconductor region in the first direction; and The sixth semiconductor region of the second conductivity type is provided between the first electrode and the first semiconductor region in the first direction, and a direction from the fifth semiconductor region to the sixth semiconductor region is along a fourth direction, the fourth direction is along a plane including a third direction and the second direction, and the third direction intersects the plane including the first direction and the second direction. The first terminal is electrically connected to the second electrode of the first element, The second terminal is electrically connected to the third electrode of the first element. The third terminal is electrically connected to the fourth electrode of the first element. The fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element. The fifth terminal is electrically connected to the third electrode of the second element. The sixth terminal is electrically connected to the fourth electrode of the second element. The circuit unit is configured to set the second terminal to a first potential based on the potential of the first terminal during a first period. The circuit unit is configured to set the second terminal to a third potential based on the potential of the first terminal during a second period following the first period. The circuit portion is configured to set the second terminal to a second potential based on the potential of the first terminal during a third period following the second period, wherein the second potential is lower than the first potential, and the third potential is between the first potential and the second potential. The circuit unit is configured to set the third terminal to the first potential during the first period and the second period. The circuit unit is configured to set the third terminal to the second potential during the third period. The circuit unit is configured to set the fifth terminal and the sixth terminal to a fourth potential based on the potential of the fourth terminal during the first period and the second period. The circuit unit is configured to set the fifth terminal and the sixth terminal to a fifth potential based on the potential of the fourth terminal during the third period, and the fourth potential is lower than the fifth potential.

2. The semiconductor device according to claim 1, wherein further comprising a seventh terminal electrically connected to the first electrode of the second element, The circuit unit is configured to apply a controlled voltage between the first terminal and the seventh terminal.

3. The semiconductor device according to claim 1 or 2, wherein The third potential is lower than a threshold voltage of the first element.

4. The semiconductor device according to any one of claims 1 to 3, wherein A first absolute value of a first difference between the third potential and the first potential is greater than or equal to 0.8 times and less than or equal to 1.2 times a second absolute value of a second difference between the third potential and the second potential.

5. The semiconductor device according to any one of claims 1 to 4, wherein The first potential is positive, The second potential is negative.

6. The semiconductor device according to any one of claims 1 to 5, wherein The second length of the second period is shorter than the first length of the first period.

7. The semiconductor device according to claim 6, wherein The second length is not less than 10 times and not more than 100 times the first length.

8. The semiconductor device according to claim 6 or 7, wherein The first length is greater than or equal to 10 μs and less than or equal to 200 μs. The second length is greater than or equal to 1 μs and less than 10 μs.

9. The semiconductor device according to any one of claims 1 to 8, wherein The timing at which the fifth terminal and the sixth terminal attain the fifth potential is the same as the timing at which the third terminal attains the second potential.

10. The semiconductor device according to any one of claims 1 to 8, wherein After the fifth terminal and the sixth terminal are at the fifth potential, the third terminal is at the second potential. A time period between the time when the fifth terminal and the sixth terminal are at the fifth potential and the time when the third terminal is at the second potential is 1 μs or less.

11. The semiconductor device according to any one of claims 1 to 10, wherein: The first element and the second element each further include a first insulating component, The first insulating member of the first element is provided between the third electrode of the first element and the semiconductor member of the first element and between the fourth electrode of the first element and the semiconductor member of the first element. The first insulating member of the second element is provided between the third electrode of the second element and the semiconductor component of the second element and between the fourth electrode of the second element and the semiconductor component of the second element.

12. The semiconductor device according to claim 11, wherein A portion of the first insulating member is in contact with a portion of the third electrode and the second semiconductor region in the second direction.

13. The semiconductor device according to claim 12, wherein Another portion of the first insulating member is in contact with a portion of the fourth electrode and the fourth semiconductor region in the second direction.

14. The semiconductor device according to any one of claims 1 to 13, wherein The first element and the second element each further include a second insulating member. The second insulating member of the first element is provided between the third electrode of the first element and the second electrode of the first element and between the fourth electrode of the first element and the second electrode of the first element. The second insulating member of the second element is provided between the third electrode of the second element and the second electrode of the second element and between the fourth electrode of the second element and the second electrode of the second element.

15. The semiconductor device according to any one of claims 1 to 14, wherein The second impurity concentration of the first conductivity type in the second semiconductor region is higher than the first impurity concentration of the first conductivity type in the first semiconductor region.

16. The semiconductor device according to claim 15, wherein The concentration of the first conductivity type fifth impurity in the fifth semiconductor region is higher than the first impurity concentration.

17. The semiconductor device according to any one of claims 1 to 16, wherein: The concentration of the second conductivity type fourth impurity in the fourth semiconductor region is higher than the concentration of the second conductivity type third impurity in the third semiconductor region.

18. The semiconductor device according to claim 17, wherein The concentration of the sixth impurity of the second conductivity type in the sixth semiconductor region is higher than the third impurity concentration.

19. The semiconductor device according to any one of claims 1 to 18, wherein The third electrode and the fourth electrode extend along a third direction intersecting a plane including the first direction and the second direction.

20. A semiconductor device comprising: 1st element; 2nd element; Terminal 1; Terminal 2; Terminal 3; Terminal 4; Terminal 5; Terminal 6; as well as Circuit Department, The first element and the second element respectively include: 1st electrode; 2nd electrode; 3rd electrode; a fourth electrode; and a semiconductor component disposed between the first electrode and the second electrode, The second direction from the third electrode to the fourth electrode intersects the first direction from the first electrode to the second electrode. The semiconductor component comprises: a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, and a fourth partial region, a direction from the first partial region toward the third electrode being along the first direction, and a direction from the second partial region toward the fourth electrode being along the first direction; The second semiconductor region of the first conductivity type is arranged along the second direction from a portion of the third electrode to the second semiconductor region; a third semiconductor region of the second conductivity type, a portion of the third semiconductor region being located between the third partial region and the second semiconductor region in the second direction, and a direction from the portion of the third electrode to the portion of the third semiconductor region being along the second direction; the fourth semiconductor region of the second conductivity type, the other portion of the third semiconductor region being located between the fourth partial region and the fourth semiconductor region in the second direction, and the direction from the other portion of the third semiconductor region to the portion of the fourth electrode being along the second direction; The fifth semiconductor region of the first conductivity type is provided between the first electrode and the first semiconductor region in the first direction; and The sixth semiconductor region of the second conductivity type is provided between the first electrode and the first semiconductor region in the first direction, and a direction from the fifth semiconductor region to the sixth semiconductor region is along a fourth direction, the fourth direction is along a plane including a third direction and the second direction, and the third direction intersects the plane including the first direction and the second direction. The first terminal is electrically connected to the second electrode of the first element, The second terminal is electrically connected to the third electrode of the first element. The third terminal is electrically connected to the fourth electrode of the first element. The fourth terminal is electrically connected to the second electrode of the second element and the first electrode of the first element. The fifth terminal is electrically connected to the third electrode of the second element. The sixth terminal is electrically connected to the fourth electrode of the second element. The circuit unit is configured to change the potential of the second terminal from a first potential to a second potential at a first moment. The first potential is a potential based on the potential of the first terminal. The second potential is a potential based on the potential of the first terminal. The second potential is lower than the first potential, The circuit portion is configured to set the potential of the second terminal to the second potential at a second time after the first time. The circuit unit is configured to change the potential of the third terminal from the first potential to the second potential at the second time. The circuit portion is configured to change the potential of the fifth terminal and the potential of the sixth terminal from a fourth potential to a fifth potential at the second time. The fourth potential is a potential based on the potential of the fourth terminal. The fifth potential is a potential based on the potential of the fourth terminal. The fourth potential is lower than the fifth potential, The time between the first moment and the second moment is longer than the time it takes for the potential of the third terminal to change from the first potential to the second potential. The time between the first time and the second time is longer than the time it takes for the potential at the fifth terminal and the potential at the sixth terminal to change from the fourth potential to the fifth potential.

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