Semiconductor device

Abstract

The invention provides a semiconductor device. The turn-on voltage can be reduced. According to one embodiment, a semiconductor device includes first and second electrodes, a semiconductor layer, first and second gate electrodes, and first and second insulating regions. The direction from the second electrode to the first electrode is along the first direction. The semiconductor layer is provided between the first and second electrodes. The semiconductor layer includes first, second, and sixth semiconductor regions of a first conductivity type and third, fourth, and fifth semiconductor regions of a second conductivity type. The second semiconductor region is provided between the first semiconductor region and the first electrode, and is electrically connected to the first electrode. A portion of the third semiconductor region is provided between the first and second semiconductor regions and faces the first gate electrode. The fourth semiconductor region is provided between the first semiconductor region and the second electrode, and is electrically connected to the second electrode. The sixth semiconductor region includes the first region. The first region is provided between the fourth semiconductor region and the fifth semiconductor region and faces the second gate electrode.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] For example, there are semiconductor devices such as IGBT (Insulated Gate Bipolar Transistor).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-049610 Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor device capable of reducing on-voltage.

[0007] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a semiconductor layer, a first gate electrode, a second gate electrode, a first insulating region, and a second insulating region. The direction from the second electrode toward the first electrode is along a first direction. The semiconductor layer is disposed between the first electrode and the second electrode. The semiconductor layer has a first surface on the first electrode side and a second surface on the side opposite to the first surface. The first surface and the second surface extend along a second direction perpendicular to the first direction. The first gate electrode is disposed on the first electrode side of the semiconductor layer. The second gate electrode is disposed on the second electrode side of the semiconductor layer. The second surface is located between the first surface and the second electrode. The first insulating region is disposed between the first gate electrode and the semiconductor layer. The second insulating region is disposed between the second gate electrode and the second surface of the semiconductor layer. The semiconductor layer includes a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of the first conductivity type. The second semiconductor region is disposed between the first semiconductor region and the first electrode and is electrically connected to the first electrode. The third semiconductor region is electrically connected to the first electrode. A portion of the third semiconductor region is disposed between the first semiconductor region and the second semiconductor region, in contact with the first insulating region, and opposite to the first gate electrode. The fourth semiconductor region is disposed between the first semiconductor region and the second electrode and is electrically connected to the second electrode. The fifth semiconductor region is spaced apart from the fourth semiconductor region in the second direction. The sixth semiconductor region includes a first region. The first region is disposed between the fourth semiconductor region and the fifth semiconductor region, in contact with the second insulating region, and opposite to the second gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0009] Figure 2 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0010] Figure 3 (a) and Figure 3 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the embodiment.

[0011] Figure 4 It is a schematic cross-sectional view illustrating a semiconductor device according to a reference example.

[0012] Figure 5 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0013] Figure 6 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0014] Figure 7 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0015] Figure 8 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0016] Figure 9 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0017] Figure 10 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0019] The drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the size ratio between parts, etc. may not necessarily be the same as in reality. Even when showing the same part, the mutual dimensions and ratios may be expressed differently depending on the drawings.

[0020] In the present specification and the drawings, the same elements as those described above are denoted by the same reference numerals as in the drawings shown above, and detailed description thereof will be appropriately omitted.

[0021] In the following description and drawings, n + 、n、n - 、p + ,p,p - Such expressions indicate the relative highs and lows of the concentrations of each impurity. That is, expressions with a "+" appended have a relatively higher impurity concentration than expressions without any of the "+" and "-" signs, and expressions with a "-" appended have a relatively lower impurity concentration than expressions without any of the "+" and "-" signs. In the case where each region contains both p-type impurities and n-type impurities, these expressions indicate the relative highs and lows of the net impurity concentration after these impurities compensate for each other. With respect to each embodiment described below, each embodiment can also be implemented by reversing the p-type (second conductivity type) and n-type (first conductivity type) of each semiconductor region.

[0022] Figure 1 as well as Figure 2 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0023] Figure 2 Example edge Figure 1 The cross section of line A1-A2 is shown. Figure 2 In FIG. 3 , the positions of the semiconductor regions on the back side of the semiconductor layer 30 are indicated by dotted lines. In addition, the impurity concentrations (n, p) of these semiconductor regions are exemplified. + 、p - wait).

[0024] like Figure 1 As shown, the semiconductor device 101 according to the embodiment includes a first electrode 11 (eg, an emitter electrode), a second electrode 12 (eg, a collector electrode), and a semiconductor layer 30. The semiconductor layer 30 is provided between the first electrode 11 and the second electrode 12.

[0025] The direction from the second electrode 12 toward the first electrode 11 is along the first direction. In the description of the embodiment, the first direction is referred to as the Z direction. The direction intersecting the first direction is referred to as the second direction (X direction). The X direction may be a direction perpendicular to the Z direction. The direction intersecting the first and second directions is referred to as the third direction (Y direction). The Y direction may be a direction perpendicular to the Z direction and the X direction.

[0026] The semiconductor layer 30 has a first surface F1 (e.g., the front surface) and a second surface F2 (e.g., the back surface). The first surface F1 is the surface of the semiconductor layer 30 facing the first electrode 11. The second surface F2 is the surface of the semiconductor layer 30 facing the second electrode 12 and is opposite to the first surface F1 of the semiconductor layer 30. The first surface F1 and the second surface F2 each extend along an XY plane perpendicular to the Z direction.

[0027] In the description of the embodiments, for convenience, the first electrode 11 side of the semiconductor layer 30 is sometimes referred to as the "front" (front side) or "upper", and the second electrode 12 side of the semiconductor layer 30 is sometimes referred to as the "back" (back side) or "lower". "Front", "back", "upper", and "lower" are based on the relative positional relationship between the first electrode 11 and the second electrode 12, and do not limit the direction of gravity or the manufacturing process.

[0028] Semiconductor device 101 includes a plurality of first gate electrodes 21 (surface gate electrodes) and a plurality of first insulating regions 41 (surface gate insulating films) provided on the surface side of semiconductor layer 30. First insulating region 41 is a portion of first insulating portion 40A that insulates semiconductor layer 30 from first gate electrodes 21.

[0029] The plurality of first gate electrodes 21 are arranged in the X direction. Each first gate electrode 21 extends in the Y direction. The first gate electrodes 21 extend from the first surface F1 toward the second surface F2. Each of the plurality of first insulating regions (first insulating portions 40A) is provided between each of the plurality of first gate electrodes 21 and the semiconductor layer 30.

[0030] That is, in this example, the first gate electrode 21 is a trench gate. A trench T1 extending toward the second surface F2 is provided on the first surface F1 of the semiconductor layer 30. A first insulating portion 40A is provided within the trench T1. The first gate electrode 21 is provided within the first insulating portion 40A. The first gate electrode 21 is insulated from the semiconductor layer 30.

[0031] The semiconductor layer 30 includes a first semiconductor region 31 (drift region) of a first conductivity type. In this example, the first conductivity type is n-type. The lower portion 31b of the first semiconductor region 31 is located below the first gate electrode 21 and is in contact with the first insulating portion 40A. That is, the direction from the lower portion 31b to the first gate electrode 21 is along the Z direction. The upper portion 31a of the first semiconductor region 31 is opposite the first gate electrode 21 with the first insulating region 41 interposed therebetween. The direction from the upper portion 31a to the first gate electrode 21 is along the X direction. The upper portion 31a is in contact with the first insulating region 41. The first insulating region 41 is between the upper portion 31a and the first gate electrode 21.

[0032] Furthermore, the semiconductor layer 30 includes a plurality of second semiconductor regions 32 (emitter regions), a plurality of third semiconductor regions 33 (base regions), and a plurality of semiconductor regions 39 provided on the front side. The second semiconductor regions 32, the third semiconductor regions 33, and the semiconductor regions 39 are adjacent to the first insulating portion 40A and extend in the Y direction along the first insulating portion 40A (the first gate electrode 21).

[0033] The second semiconductor region 32 is of the first conductivity type. The second semiconductor region 32 is provided between the first semiconductor region 31 and the first electrode 11. The second semiconductor region 32 is in contact with the first electrode 11 and is electrically connected to the first electrode 11. The second semiconductor region 32 is opposite the first gate electrode 21 via the first insulating region 41. The direction from the second semiconductor region 32 to the first gate electrode 21 is along the X direction. The second semiconductor region 32 is in contact with the first insulating region 41. The first insulating region 41 is between the second semiconductor region 32 and the first gate electrode 21. The second semiconductor region 32 is provided on a portion of the third semiconductor region 33, away from the first semiconductor region 31. The direction from the first semiconductor region 31 (upper portion 31a) to the second semiconductor region 32 is along the Z direction.

[0034] The third semiconductor region 33 is of the second conductivity type. In this example, the second conductivity type is p-type. The third semiconductor region 33 is in contact with the first electrode 11 and is electrically connected to the first electrode 11. The third semiconductor region 33 is provided above the upper portion 31a of the first semiconductor region 31. A portion 33a of the third semiconductor region 33 is located between the first semiconductor region 31 (upper portion 31a) and the second semiconductor region 32. The third semiconductor region 33 is in contact with the first semiconductor region 31 and the second semiconductor region 32 (forming a pn junction). A portion 33a of the third semiconductor region 33 is opposed to the first gate electrode 21 across the first insulating region 41. The direction from the portion 33a toward the first gate electrode 21 is along the X direction. The portion 33a is in contact with the first insulating region 41. The first insulating region 41 is between the portion 33a and the first gate electrode 21.

[0035] The semiconductor region 39 is of the second conductivity type and is provided on the first semiconductor region 31. A first gate electrode 21 is disposed between the semiconductor region 39 and the third semiconductor region 33. A third semiconductor region 33 is disposed between two adjacent first gate electrodes 21 among the plurality of first gate electrodes 21. Two second semiconductor regions 32 are disposed on the third semiconductor region 33.

[0036] The insulating portion 48 is provided between the first electrode 11 and the first gate electrode 21, between the first electrode 11 and the first insulating portion 40A, and between the first electrode 11 and the semiconductor region 39. The first electrode 11 and the first gate electrode 21 are insulated from each other.

[0037] The semiconductor device 101 further includes a plurality of second gate electrodes 22 (back gate electrodes) and a plurality of second insulating regions 42 (back gate insulating films) provided on the back side of the semiconductor layer 30. The second insulating region 42 is a portion of a second insulating portion 40B that covers the second gate electrodes 22. The second insulating portion 40B (second insulating region 42) is provided between the semiconductor layer 30 and the second gate electrode 22 to insulate the semiconductor layer 30 from the second gate electrode 22. Furthermore, the second insulating portion 40B is provided between the second electrode 12 and the second gate electrode 22 to insulate the second electrode 12 from the second gate electrode 22.

[0038] The second surface F2 is located between the first surface F1 and the second gate electrode 22. The second insulating region 42 is located between the second surface F2 and the second gate electrode 22. The plurality of second gate electrodes 22 are arranged in the X direction. Each second gate electrode 22 extends in the Y direction.

[0039] Furthermore, the semiconductor layer 30 includes a plurality of fourth semiconductor regions 34 (collector regions), a plurality of fifth semiconductor regions 35 (backside regions), and a sixth semiconductor region 36 provided on the back side. The sixth semiconductor region 36 includes a plurality of first regions 36p (channel regions) and a second region 36q (buffer region). The fourth semiconductor regions 34, the fifth semiconductor regions 35, and the sixth semiconductor region 36 (first regions 36p) extend in the Y direction along the second insulating portion 40B (second gate electrode 22).

[0040] The fourth semiconductor region 34 is of the second conductivity type and is provided between the first semiconductor region 31 and the second electrode 12 . The fourth semiconductor region 34 is in contact with the second electrode 12 and is electrically connected to the second electrode 12 .

[0041] An end 34p of the fourth semiconductor region 34 in the X direction is in contact with the second insulating region 42. The end 34p of the fourth semiconductor region 34 may overlap with the second gate electrode 22 and the second insulating region 42 in the Z direction. In other words, the direction from a portion of the second gate electrode 22 toward the end 34p of the fourth semiconductor region 34 is along the Z direction. A portion of the second insulating region 42 is between this portion of the second gate electrode 22 and the end 34p of the fourth semiconductor region 34.

[0042] The fifth semiconductor region 35 is of the second conductivity type. The fifth semiconductor region 35 is spaced apart from the fourth semiconductor region 34 in the X direction. That is, the direction from the fifth semiconductor region 35 toward the fourth semiconductor region 34 is along the X direction. The fifth semiconductor region 35 is located between the first semiconductor region 31 and the second insulating portion 40B (second insulating region 42) in the Z direction. The fifth semiconductor region 35 is spaced apart from the second electrode 12.

[0043] The fifth semiconductor region 35 is in contact with the second insulating portion 40B (second insulating region 42). The end 35p of the fifth semiconductor region 35 in the X direction can overlap with the second gate electrode 22 and the second insulating region 42 in the Z direction. In other words, the direction from a portion of the second gate electrode 22 toward the end 35p of the fifth semiconductor region 35 is along the Z direction. A portion of the second insulating region 42 is between the portion of the second gate electrode 22 and the end 35p of the fifth semiconductor region 35. The entire lower surface of the fifth semiconductor region 35 (the surface on the second electrode 12 side) is in contact with the second insulating portion 40B. For example, both ends of the fifth semiconductor region 35 in the X direction (end 35p and end 35q) are in contact with the second insulating portion 40B and overlap with the second gate electrode 22 in the Z direction.

[0044] The sixth semiconductor region 36 (the first region 36p and the second region 36q) is of the first conductivity type. The concentration of the first conductivity type impurities in the sixth semiconductor region 36 is higher than the concentration of the first conductivity type impurities in the first semiconductor region 31. The concentration of the first conductivity type impurities in the sixth semiconductor region 36 is, for example, 1×10 16 atoms / cm 3 Above and 1×10 18 atoms / cm 3 The concentration of the first conductivity type impurity in the sixth semiconductor region 36 is 10 times the concentration of the first conductivity type impurity in the first semiconductor region 31. 3 times or more and 10 5 times or less.

[0045] The first region 36p is provided between the fourth semiconductor region 34 and the fifth semiconductor region 35. The first region 36p is in contact with the fourth semiconductor region 34 (forming a pn junction) and in contact with the fifth semiconductor region 35 (forming a pn junction). The first region 36p is in contact with the second insulating region 42. The first region 36p faces the second gate electrode 22 with the second insulating region 42 interposed therebetween. The first region 36p overlaps the second gate electrode 22 and the second insulating region 42 in the Z direction. In other words, the direction from the second gate electrode 22 toward the first region 36p is along the Z direction. The second insulating region 42 is between the sixth semiconductor region 36 and the second gate electrode 22. The fifth semiconductor region 35 is located between two first regions 36p that are adjacent in the X direction and face the same second gate electrode 22 in the Z direction. The fifth semiconductor region 35 is located between two first regions 36p that are in contact with the same second insulating region 42.

[0046] The second region 36q is provided on the first region 36p, on the fourth semiconductor region 34, and on the fifth semiconductor region 35. Specifically, the second region 36q is provided between the first region 36p and the first semiconductor region 31, between the fourth semiconductor region 34 and the first semiconductor region 31, and between the fifth semiconductor region 35 and the first semiconductor region 31. The second region 36q is in contact with the fourth semiconductor region 34 (forming a pn junction) and in contact with the fifth semiconductor region 35 (forming a pn junction). The fourth semiconductor region 34 and the fifth semiconductor region 35 can be surrounded by the sixth semiconductor region 36 and are separated from the first semiconductor region 31.

[0047] An example of materials for each element of the semiconductor device 101 will be described.

[0048] Each semiconductor region of semiconductor layer 30 (such as the first to sixth semiconductor regions) includes silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. Semiconductor layer 30 is, for example, a silicon substrate. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity.

[0049] The first gate electrode 21 and the second gate electrode 22 are made of a conductive material such as polysilicon.

[0050] The first insulating portion 40A (the first insulating region 41 and the like), the second insulating portion 40B (the second insulating region 42 and the like), and the insulating portion 48 include an insulating material such as silicon oxide.

[0051] The first electrode 11 and the second electrode 12 are made of metal such as aluminum.

[0052] The semiconductor device 101 according to the embodiment operates as an IGBT (Insulated Gate Bipolar Transistor), for example. For example, when a positive voltage is applied to the second electrode 12 relative to the first electrode 11, the first gate electrode 21 is set to an on-state. That is, for example, a voltage greater than a threshold value (on-state voltage) is applied to the first gate electrode 21, and the potential of the first gate electrode 21 is set to a state greater than the first threshold value. As a result, an inversion layer is formed in the third semiconductor region 33 (base region). For example, electrons are injected from the first electrode 11 into the first semiconductor region 31 (drift region) via the second semiconductor region 32 (source region) and the channel. For example, holes are injected from the second electrode 12 into the first semiconductor region 31 via the fourth semiconductor region 34 (collector region). Thereafter, the first gate electrode 21 is set to an off-state. That is, for example, the voltage applied to the first gate electrode 21 is lower than the threshold value, and the potential of the first gate electrode 21 is set to a state less than the first threshold value. As a result, the inversion layer in the first semiconductor region 31 disappears.

[0053] The second gate electrode 22, fourth semiconductor region 34, fifth semiconductor region 35, and first region 36p, provided on the back side of the semiconductor layer 30, operate as, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor). In this example, a p-channel MOSFET is formed. The injection efficiency of carriers injected from the back side of the semiconductor layer 30 can be controlled by turning the MOSFET on and off. By controlling the carrier concentration in the semiconductor layer 30, the on-state voltage of the semiconductor device 101 can be reduced. Furthermore, the off-state loss of the semiconductor device 101 can be reduced.

[0054] For example, when a positive voltage is applied to the second electrode 12 relative to the first electrode 11, the second gate electrode 22 is placed in an on state. Specifically, for example, a voltage below the threshold is applied to the second gate electrode 22, setting the potential of the second gate electrode 22 to below the second threshold. This forms an inversion layer in the first region 36p. For example, holes flow from the second electrode 12 into the first semiconductor region 31 via the fourth semiconductor region 34, the first region 36p, and the fifth semiconductor region 35. Thus, the on state of the second gate electrode 22 achieves a high carrier injection efficiency.

[0055] Alternatively, for example, the second gate electrode 22 is set to an off state. That is, for example, a voltage greater than a threshold voltage is applied to the second gate electrode 22, setting the potential of the second gate electrode 22 to a state higher than the second threshold voltage. This eliminates the inversion layer in the first region 36p. For example, holes do not flow from the fourth semiconductor region 34 into the fifth semiconductor region 35. Hole injection via the fifth semiconductor region 35 is suppressed. Holes flow from the second electrode 12 to the first semiconductor region 31 via the fourth semiconductor region 34. Thus, the off state of the second gate electrode 22 achieves a low carrier injection efficiency.

[0056] Figure 3 (a) and Figure 3 (b) is a schematic diagram illustrating the operation of the semiconductor device according to the embodiment.

[0057] Figure 3 (a) and Figure 3 The horizontal axis of (b) is time tm. Figure 3 (a) shows an example of the voltage V1 of the first gate electrode 21 . Figure 3 (b) shows an example of the voltage V2 of the second gate electrode 22. For example, before time tm1, the voltage V1 is the threshold voltage V t 1, the first gate electrode 21 is in the on state. For example, before time tm1, the voltage V1 is lower than the threshold voltage V t 1 High voltage V on 1. Voltage V on 1 is positive based on the potential of the first electrode 11. Before time tm1, the voltage V2 is the threshold voltage V t 2 or less, the second gate electrode 22 is in the on state. For example, the voltage V2 is higher than the threshold voltage V t 2 Low voltage V on 2. Voltage V on 2 is negative with respect to the potential of the first electrode 11. Before time tm1, for example, the second gate electrode 22 is in the on state, the efficiency of carrier injection from the back surface is high, and the hole density in the first semiconductor region 31 is high.

[0058] At time tm1, the voltage V2 is higher than the threshold voltage V t 2, the second gate electrode 22 is turned off. For example, at time tm1, the voltage V2 is increased from the voltage V on 2 becomes the voltage V off 2. Voltage V off 2 is positive based on the potential of the first electrode 11. The second gate electrode 22 is in the off state, and the efficiency of carrier injection from the back surface is reduced. Moreover, at time tm2 after time tm1, the voltage V1 is lower than the threshold voltage V t 1, the first gate electrode 21 is in the off state. For example, at time tm2, the voltage V1 changes from voltage V on 1 becomes the voltage V off 1. Voltage V off 1 is negative based on the potential of the first electrode 11 .

[0059] In this way, when the first gate electrode 21 is in the on state, the second gate electrode 22 switches from the on state to the off state, and when the second gate electrode 22 is in the off state, the first gate electrode 21 switches from the on state to the off state. By switching the second gate electrode 22 off before the first gate electrode 21 switches off, for example, the carrier density in the first semiconductor region 31 can be controlled, thereby shortening the turn-off time. For example, turn-off losses can be reduced. As an example, the time between time tm1 and time tm2 can be set to be 0.1 microseconds or more and 100 microseconds or less.

[0060] At time tm3 after time tm2, voltage V2 becomes threshold voltage V t 2, the second gate electrode 22 becomes conductive. For example, at time tm3, the voltage V2 changes from voltage V off 2 becomes the voltage V on 2. At time tm4 after time tm3, voltage V1 becomes the threshold voltage V t 1, the first gate electrode 21 becomes conductive. For example, at time tm4, the voltage V1 changes from voltage V off 1 becomes the voltage V on 1. As a result, the efficiency of carrier injection from the back surface becomes higher and the hole density becomes higher.

[0061] Thus, when the first gate electrode 21 is in the off state, the second gate electrode 22 changes from the off state to the on state, and when the second gate electrode 22 is in the on state, the first gate electrode 21 changes from the off state to the on state. The on state of the second gate electrode 22 controls the carrier density in the first semiconductor region 31, for example, and can reduce the on-state voltage when the first gate electrode 21 is in the on state.

[0062] For example, using Figure 1 The control unit 70 (control circuit), shown schematically, controls the voltages of the first gate electrode 21 and the second gate electrode 22. The control unit 70 controls the voltage V1 to switch the first gate electrode 21 between the on and off states. The control unit 70 controls the voltage V2 to switch the second gate electrode 22 between the on and off states. The semiconductor device 101 may also include the control unit 70.

[0063] Figure 4 It is a schematic cross-sectional view illustrating a semiconductor device according to a reference example.

[0064] exist Figure 4 In the semiconductor device 190 shown, an n-channel MOSFET is provided instead of a p-channel MOSFET on the back side of the semiconductor layer 30. That is, the semiconductor layer 30 includes a p-channel MOSFET. + Shaped area 91, n + A p-type region 92, a p-type region 93, and an n-type region 94. + Shaped area 91, n + The p-type region 92 is provided on the second surface F2 and is in contact with the second electrode 12. The p-type region 93 is provided between the n-type region 94 and the n-type region 95. + between the n-type region 92 and between the n-type region 94 and the p-type region 94. + Between the shaped areas 91. n + Part of each of the p-type region 92 , the p-type region 93 , and the n-type region 94 faces the second gate electrode 22 via the second insulating region 42 .

[0065] n + The p-type region 92, the p-type region 93, the n-type region 94, the second insulating region 42, and the second gate electrode 22 function as an n-channel MOSFET. By controlling the voltage of the second gate electrode 22, the on / off state of the n-channel MOSFET can be controlled. For example, when a positive voltage is applied to the second electrode 12 relative to the first electrode 11, when the first gate electrode 21 is in the on state and the second gate electrode 22 is in the off state, electrons are injected from the surface side and electrons are injected from the p-type region 92. + Here, when the second gate electrode 22 changes from the off state to the on state, an inversion layer is formed in the p-type region 93, and electrons are injected from the n-type region 94 through the p-type region 93 and the n-type region 93. + The shaped region 92 is discharged to the second electrode 12. Therefore, the + Holes are injected into the p-type region 91 and the p-type region 93. In this way, the second gate electrode 22 can control the injection efficiency of holes.

[0066] Here, n is provided on the second surface F2. +In a semiconductor device having a shaped region 92, a parasitic element may be formed. For example, Figure 4 In the Z direction, n + The n-type region 92, the p-type region 93, and the n-type region 94 form a parasitic element (npn bipolar transistor). When the parasitic element is turned on, an electron current EC flows from the n-type region 94 to the n-type region 94. + The hole injection efficiency will be reduced in the n-shaped region 92. + When the length Ln of the X direction of the shape region 92 becomes longer, the electrons + The path through which current flows in p-type region 93 above p-type region 92 becomes longer, increasing the resistance component formed by p-type region 93. Consequently, the potential of p-type region 93 increases, potentially facilitating the operation of parasitic elements. In contrast, in semiconductor device 101 according to the embodiment, an n-channel MOSFET need not be formed on the back side. According to the embodiment, the operation of parasitic elements can be suppressed.

[0067] As described above, the sixth semiconductor region 36 includes the first region 36p and the second region 36q. For example, the threshold voltage of the p-channel MOSFET on the back side can be adjusted by adjusting the impurity concentration of the sixth semiconductor region 36.

[0068] The concentration of the second conductivity type impurity in the fifth semiconductor region 35 can be higher than the concentration of the second conductivity type impurity in the fourth semiconductor region 34. The high concentration of the second conductivity type impurity in the fifth semiconductor region 35 can improve the efficiency of hole injection through the fifth semiconductor region 35, for example, when the second gate electrode 22 is in the on state. The low concentration of the second conductivity type impurity in the fourth semiconductor region 34 can reduce the efficiency of hole injection through the fourth semiconductor region 34, for example, when the second gate electrode 22 is in the off state. This can increase the change in hole injection efficiency caused by the second gate electrode 22.

[0069] The second conductivity type impurity concentration in the fifth semiconductor region 35 is, for example, 5×10 17 atoms / cm 3 Above and 1×10 19 atoms / cm 3 The second conductivity type impurity concentration in the fourth semiconductor region 34 is, for example, 5×10 16 atoms / cm 3 Above and 5×10 17 atoms / cm 3 The second conductivity type impurity concentration in the fifth semiconductor region 35 is, for example, 2 times or more and 100 times or less of the second conductivity type impurity concentration in the fourth semiconductor region 34 .

[0070] like Figure 1 As shown, the sixth semiconductor region 36 includes a plurality of first regions 36p. The plurality of first regions 36p are arranged in the X direction. The plurality of fourth semiconductor regions 34 are arranged in the X direction. The plurality of fifth semiconductor regions 35 are arranged in the X direction. Each first region 36p is located between the fourth semiconductor region 34 and the fifth semiconductor region 35. In other words, one first region 36p is provided between one fourth semiconductor region 34 and one fifth semiconductor region 35.

[0071] More specifically, if Figure 1 As shown, two first regions 36p (region 36pa and region 36pb) are provided between two fourth semiconductor regions 34 (between region 34a and region 34b). One fifth semiconductor region (region 35a) is provided between the two first regions 36p (between region 36pa and region 36pb). Regions 34a and 34b are two fourth semiconductor regions 34 adjacent to each other in the X direction among the plurality of fourth semiconductor regions 34. Regions 36pa and 36pb are two first regions 36p adjacent to each other in the X direction among the plurality of first regions 36p.

[0072] In this example, the two first regions 36 p and the one fifth semiconductor region 35 face the one second gate electrode 22 in the Z direction. Thus, the current in the two first regions 36 p can be controlled by the one second gate electrode 22 .

[0073] More specifically, if Figure 1 As shown, the direction from a portion of the second gate electrode 22 (first gate portion 22p) toward the region 36pa is along the Z direction. The direction from a portion of the second gate electrode 22 (second gate portion 22q) toward the region 36pb is along the Z direction. The direction from a portion of the second gate electrode 22 (third gate portion 22r) toward the region 35a is along the Z direction. Furthermore, the third gate portion 22r is located between the first gate portion 22p and the second gate portion 22q, and the first gate portion 22p, the second gate portion 22q, and the third gate portion 22r are arranged in the X direction.

[0074] Furthermore, two first regions 36p (region 36pa and region 36pc) are provided between the two fifth semiconductor regions 35 (between region 35a and region 35b). One fourth semiconductor region 34 (region 34a) is provided between the two first regions 36p (between region 36pa and region 36pc). Regions 35a and 35b are two of the plurality of fifth semiconductor regions 35 that are adjacent to each other in the X direction. Regions 36pa and 36pc are two of the plurality of first regions 36p that are adjacent to each other in the X direction.

[0075] The plurality of second insulating regions 42 are arranged in the X direction corresponding to the plurality of first regions 36 p , and each second insulating region 42 is in contact with each first region 36 p .

[0076] Between two second gate electrodes 22 (electrode 22a and electrode 22b) adjacent to each other in the X direction among the plurality of second gate electrodes 22, the second electrode 12 need not be in contact with the first conductivity type semiconductor region. Consequently, the parasitic element described with respect to the semiconductor device 190 of the reference example is not formed. The semiconductor layer 30 need not include a first conductivity type region in contact with the second electrode 12.

[0077] More specifically, if Figure 1 As shown, one fourth semiconductor region 34 (region 34a) is in contact with each of the two second insulating regions 42 (insulating region 42a and insulating region 42b). Furthermore, insulating region 42a and insulating region 42b are two second insulating regions 42 adjacent to each other in the X direction among the plurality of second insulating regions 42. Insulating region 42a is located between region 36pa and electrode 22a and is in contact with region 36pa. Insulating region 42b is located between region 36pc and electrode 22b and is in contact with region 36pc. Between the X-direction positions of insulating region 42a and insulating region 42b, a semiconductor region of the first conductivity type need not be provided on second surface F2 of semiconductor layer 30.

[0078] Figure 5 as well as Figure 6 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0079] Figure 6 Example edge Figure 5 The cross section of line A3-A4 is shown. Figure 6 In FIG. 3 , the positions of the semiconductor regions on the back side of the semiconductor layer 30 are indicated by dotted lines. In addition, the impurity concentrations (n, p) of these semiconductor regions are exemplified. + 、p - wait).

[0080] Figure 5 as well as Figure 6 The semiconductor device 102 shown in FIG. 1 is similar to the semiconductor device 102 in terms of the size relationship between the width of the fourth semiconductor region 34 and the width of the fifth semiconductor region 35. Figure 1 The semiconductor device 102 is different from the semiconductor device 101 shown in FIG.

[0081] like Figure 6 As shown, in the semiconductor device 102 , the length W35 of the fifth semiconductor region 35 along the X direction is longer than the length W34 of the fourth semiconductor region 34 along the X direction.

[0082] The length W35 of the fifth semiconductor region 35 is long, and thus, for example, when the second gate electrode 22 is in the on state, the efficiency of hole injection through the fifth semiconductor region 35 can be improved. The length W34 of the fourth semiconductor region 34 is short, and thus, for example, when the second gate electrode 22 is in the off state, the efficiency of hole injection through the fourth semiconductor region 34 can be reduced. This can increase the change in hole injection efficiency caused by the second gate electrode 22.

[0083] In addition, you can also Figure 2 In the semiconductor device 101 shown, the length W34 of the fourth semiconductor region 34 is longer than the length W35 of the fifth semiconductor region 35. When the length W34 of the fourth semiconductor region 34 is longer, for example, the semiconductor layer 30 and the second electrode 12 are in contact over a larger area, which facilitates better contact.

[0084] Figure 7 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0085] Figure 7 The semiconductor device 103 shown in FIG. 1 is similar to the arrangement of the second gate electrode 22 and the second insulating portion 40B. Figure 1 The semiconductor device 103 is different from the semiconductor device 101 or the semiconductor device 102 shown in FIG.

[0086] The plurality of second gate electrodes 22 are arranged in the X direction. Two second gate electrodes 22 (electrode 22c and electrode 22d) adjacent to each other in the X direction among the plurality of second gate electrodes 22 are each opposed to each of the two first regions 36p (region 36pa and region 36pb) in the Z direction. Specifically, the direction from electrode 22c toward region 36pa is along the Z direction. The direction from electrode 22d toward region 36pb is along the Z direction.

[0087] The two second gate electrodes 22 (electrode 22c and electrode 22d) are covered by a second insulating portion 40B. The second insulating portion 40B includes a third insulating region 43 provided between the two second gate electrodes 22. The fifth semiconductor region 35 is opposed to the third insulating region 43 in the Z direction. Specifically, for example, the fifth semiconductor region 35 extends from the third insulating region 43 between electrodes 22c and 22d toward region 35a along the Z direction. This reduces the gate capacitance of the second gate electrode 22, for example, and thus reduces gate drive losses.

[0088] Figure 8 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0089] Figure 8 The semiconductor device 104 shown is different from the semiconductor device 104 in that the semiconductor layer 30 includes a plurality of seventh semiconductor regions 37 (contact regions). Figure 1 The semiconductor device 104 is different from the semiconductor device 101 shown in FIG.

[0090] The seventh semiconductor region 37 is continuous with the fourth semiconductor region 34. The seventh semiconductor region 37 is of the second conductivity type. The concentration of the second conductivity type impurities in the seventh semiconductor region 37 is higher than the concentration of the second conductivity type impurities in the fourth semiconductor region 34. The seventh semiconductor region 37 is in contact with the second electrode 12 and is electrically connected to the second electrode 12. The provision of the seventh semiconductor region 37 can, for example, reduce the resistance between the semiconductor layer 30 and the second electrode 12.

[0091] exist Figure 8 In the example shown in FIG, the seventh semiconductor region 37 (region 37a) is located between the fourth semiconductor region 34 (region 34a) and the second electrode 12. For example, the X-direction center position p37 of the seventh semiconductor region 37 is between the X-direction center position p34 of the fourth semiconductor region 34 and the X-direction position of the second gate electrode 22 (the second gate electrode 22 closest to the seventh semiconductor region 37). The X-direction position of region 37a is between the X-direction center position of region 34a and the X-direction position of electrode 22a.

[0092] In this manner, the seventh semiconductor region 37 is arranged near the second gate electrode 22 relative to the center of the fourth semiconductor region 34. This makes it possible, for example, to shorten the distance between the fifth semiconductor region 35 and the seventh semiconductor region 37. For example, the resistance to current flowing between the fifth semiconductor region 35 and the second electrode 12 via the seventh semiconductor region 37 can be reduced.

[0093] exist Figure 8In the example shown in FIG. 3 , the semiconductor layer 30 includes two seventh semiconductor regions 37 (region 37a and region 37b) that are in contact with one fourth semiconductor region 34 (region 34a). The position p34 of the center in the X direction of the fourth semiconductor region 34 is between the positions in the X direction of the two seventh semiconductor regions 37 (between the position in the X direction of region 37a and the position in the X direction of region 37b).

[0094] The concentration of the second conductivity type impurity in the seventh semiconductor region 37 is, for example, 5×10 17 atoms / cm 3 Above and 5×10 19 atoms / cm 3 In one example, the concentration of the second conductivity type impurities in the second conductivity type semiconductor region in contact with the second electrode 12 is 5×10 17 atoms / cm 3 The above region is the seventh semiconductor region 37 (in other words, the concentration of the second conductivity type impurity is less than 5×10 17 atoms / cm 3 The region is the fourth semiconductor region 34. For example, the area of ​​the seventh semiconductor region 37 in contact with the second electrode 12 is smaller than the area of ​​the fourth semiconductor region 34 in contact with the second electrode 12. For example, the length W37 of the seventh semiconductor region 37 along the X direction is shorter than the length W34 of the fourth semiconductor region 34 along the X direction. Thus, the seventh semiconductor region 37, which has a higher impurity concentration than the fourth semiconductor region 34, is narrower, thereby reducing the efficiency of hole injection through the fourth semiconductor region 34 and the seventh semiconductor region 37.

[0095] When a semiconductor region with a high impurity concentration contacts the second insulating region 42, the properties of the second insulating region 42, such as the defect density, may change. For example, during the manufacturing process, impurities may diffuse at an accelerated rate within the second insulating region 42. In contrast, the seventh semiconductor region 37 may be spaced apart from the second insulating region 42 (second insulating portion 40B). This can minimize the impact of the semiconductor region with a high impurity concentration on the second insulating region 42.

[0096] Figure 9 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0097] Figure 9 The semiconductor device 105 shown is similar to the semiconductor device 105 in that the fifth semiconductor region 35 includes a first partial region 35t and a second partial region 35u. Figure 1 The semiconductor device 105 is different from the semiconductor device 101 shown in FIG.

[0098] The second insulating region 42 is located between the second partial region 35u and the second gate electrode 22. The second insulating region 42 is in contact with the second partial region 35u. The first partial region 35t may be separated from the second insulating region 42.

[0099] exist Figure 9 In the example shown in FIG, the second gate electrode 22, the second insulating region 42, the second partial region 35u, and the first partial region 35t overlap in the Z direction. That is, the direction from the second gate electrode 22 to the first partial region 35t is along the Z direction. The direction from the second gate electrode 22 to the second partial region 35u is along the Z direction. The second partial region 35u is located between the first partial region 35t and the second gate electrode 22.

[0100] The first partial region 35t and the second partial region 35u are of the second conductivity type. The concentration of the second conductivity type impurities in the first partial region 35t is higher than the concentration of the second conductivity type impurities in the second partial region 35u. The concentration of the second conductivity type impurities in the first partial region 35t may be higher than the concentration of the second conductivity type impurities in the fourth semiconductor region 34. The concentration of the second conductivity type impurities in the second partial region 35u may be higher or lower than the concentration of the second conductivity type impurities in the fourth semiconductor region 34.

[0101] In this manner, by providing the second partial region 35 u having a lower impurity concentration than the first partial region 35 t , it is possible to suppress the influence of the semiconductor region having a high impurity concentration on the second insulating region 42 .

[0102] The second conductivity type impurity concentration in the first partial region 35t is, for example, 5×10 17 atoms / cm 3 Above and 1×10 19 atoms / cm 3 The second conductivity type impurity concentration in the second partial region 35u is, for example, 5×10 16 atoms / cm 3 Above and 5×10 17 atoms / cm 3 the following.

[0103] Figure 10 It is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment.

[0104] Figure 10 The semiconductor device 106 shown is similar to the semiconductor device 106 in that the fifth semiconductor region 35 includes a first partial region 35t and a second partial region 35u. Figure 7The semiconductor device 103 shown is different. Except for this, the semiconductor device 106 can be the same as the semiconductor device 103.

[0105] Even in Figure 10 In the example shown in FIG, the second insulating region 42 is located between the second partial region 35u and the second gate electrode 22. The second insulating region 42 is in contact with the second partial region 35u. The concentration of the second conductivity type impurity in the first partial region 35t is higher than the concentration of the second conductivity type impurity in the second partial region 35u.

[0106] exist Figure 10 In the example shown in FIG. 1 , one fifth semiconductor region 35 includes two second partial regions 35u and one first partial region 35t. Each of the two second partial regions 35u is located at either end of the fifth semiconductor region 35 in the X direction. The first partial region 35t is located between the two second partial regions 35u. That is, the direction from the first partial region 35t to the second partial region 35u is along the X direction.

[0107] The direction from the third insulating region 43 to the first partial region 35 t is along the Z direction. The direction from the second gate electrode 22 to the second partial region 35 u is along the Z direction.

[0108] Even in the semiconductor device 106 , by providing the second partial region 35 u having a relatively low impurity concentration, it is possible to suppress the influence of the semiconductor region having a high impurity concentration on the second insulating region 42 .

[0109] The implementation method may also include the following structures (eg, technical solutions).

[0110] (Structure 1)

[0111] A semiconductor device comprising:

[0112] 1st electrode;

[0113] a second electrode, wherein a direction from the second electrode to the first electrode is along a first direction;

[0114] a semiconductor layer provided between the first electrode and the second electrode, having a first surface on the first electrode side and a second surface opposite to the first surface, wherein the first surface and the second surface extend along a second direction perpendicular to the first direction;

[0115] a first gate electrode disposed on the first electrode side of the semiconductor layer;

[0116] a second gate electrode provided on the second electrode side of the semiconductor layer, with the second surface being located between the first surface and the second electrode;

[0117] a first insulating region disposed between the first gate electrode and the semiconductor layer; and

[0118] a second insulating region provided between the second gate electrode and the second surface of the semiconductor layer;

[0119] The semiconductor layer includes:

[0120] a first semiconductor region of a first conductivity type;

[0121] a second semiconductor region of the first conductivity type, disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode;

[0122] a third semiconductor region of the second conductivity type, electrically connected to the first electrode, wherein a portion of the third semiconductor region is disposed between the first semiconductor region and the second semiconductor region, in contact with the first insulating region, and opposite to the first gate electrode;

[0123] a fourth semiconductor region of the second conductivity type, provided between the first semiconductor region and the second electrode and electrically connected to the second electrode;

[0124] a fifth semiconductor region of the second conductivity type, spaced apart from the fourth semiconductor region in the second direction; and

[0125] The sixth semiconductor region of the first conductivity type includes a first region provided between the fourth semiconductor region and the fifth semiconductor region, in contact with the second insulating region, and facing the second gate electrode.

[0126] (Structure 2)

[0127] The semiconductor device according to Structure 1, wherein:

[0128] The sixth semiconductor region includes a second region provided between the first semiconductor region and the fifth semiconductor region.

[0129] The concentration of the first conductivity type impurities in the sixth semiconductor region is higher than the concentration of the first conductivity type impurities in the first semiconductor region.

[0130] (Structure 3)

[0131] A semiconductor device comprising:

[0132] 1st electrode;

[0133] a second electrode, wherein a direction from the second electrode to the first electrode is along a first direction;

[0134] a semiconductor layer disposed between the first electrode and the second electrode;

[0135] a first gate electrode disposed on the first electrode side of the semiconductor layer;

[0136] a second gate electrode disposed on the second electrode side of the semiconductor layer;

[0137] a first insulating region disposed between the first gate electrode and the semiconductor layer; and

[0138] a second insulating region provided between the second gate electrode and the semiconductor layer;

[0139] The semiconductor layer includes:

[0140] a first semiconductor region of a first conductivity type;

[0141] a second semiconductor region of the first conductivity type, disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode;

[0142] a third semiconductor region of the second conductivity type, electrically connected to the first electrode, wherein a portion of the third semiconductor region is disposed between the first semiconductor region and the second semiconductor region, in contact with the first insulating region, and opposite to the first gate electrode;

[0143] a fourth semiconductor region of the second conductivity type, provided between the first semiconductor region and the second electrode and electrically connected to the second electrode;

[0144] a fifth semiconductor region of the second conductivity type, spaced apart from the fourth semiconductor region; and

[0145] The sixth semiconductor region of the first conductive type includes a first region arranged between the fourth semiconductor region and the fifth semiconductor region, connected to the second insulating region and opposite to the second gate electrode, and a second region arranged between the first semiconductor region and the fifth semiconductor region, and the impurity concentration of the first conductive type in the sixth semiconductor region is higher than the impurity concentration of the first conductive type in the first semiconductor region.

[0146] (Structure 4)

[0147] The semiconductor device according to any one of Structures 1 to 3, wherein:

[0148] The concentration of the second conductivity type impurities in the fifth semiconductor region is higher than the concentration of the second conductivity type impurities in the fourth semiconductor region.

[0149] (Structure 5)

[0150] The semiconductor device according to any one of Structures 1 to 4, wherein:

[0151] A length of the fifth semiconductor region along a second direction perpendicular to the first direction is shorter than a length of the fourth semiconductor region along the second direction.

[0152] (Structure 6)

[0153] The semiconductor device according to any one of Structures 1 to 4, wherein:

[0154] A length of the fifth semiconductor region along a second direction perpendicular to the first direction is longer than a length of the fourth semiconductor region along the second direction.

[0155] (Structure 7)

[0156] The semiconductor device according to any one of Structures 1 to 6, wherein:

[0157] The fourth semiconductor region is arranged in a plurality in a second direction perpendicular to the first direction.

[0158] The first area is arranged in a plurality in the second direction.

[0159] Two of the plurality of first regions adjacent to each other in the second direction are provided between two of the plurality of fourth semiconductor regions adjacent to each other in the second direction.

[0160] One of the fifth semiconductor regions is provided between the two first regions.

[0161] The two first regions and the one fifth semiconductor region face the one second gate electrode in the first direction.

[0162] (Structure 8)

[0163] The semiconductor device according to any one of Structures 1 to 6, wherein:

[0164] The fourth semiconductor region is arranged in a plurality in a second direction perpendicular to the first direction.

[0165] The first area is arranged in a plurality in the second direction.

[0166] A plurality of second gate electrodes are arranged in the second direction.

[0167] Two of the plurality of first regions adjacent to each other in the second direction are provided between two of the plurality of fourth semiconductor regions adjacent to each other in the second direction.

[0168] One of the fifth semiconductor regions is provided between the two first regions.

[0169] Each of the two first regions is opposed in the first direction to each of two second gate electrodes adjacent to each other in the second direction among the plurality of second gate electrodes.

[0170] One of the fifth semiconductor regions faces the third insulating region provided between the two second gate electrodes in the first direction.

[0171] (Structure 9)

[0172] The semiconductor device according to any one of Structures 1 to 7, wherein:

[0173] The fifth semiconductor region includes a first partial region and a second partial region,

[0174] The second conductivity type impurity concentration in the first partial region is higher than the second conductivity type impurity concentration in the second partial region.

[0175] The second insulating region is located between the second partial region and the second gate electrode and is in contact with the second partial region.

[0176] (Structure 10)

[0177] The semiconductor device according to structure 9, wherein

[0178] A direction from the second gate electrode to the first partial region is along the first direction,

[0179] A direction from the second gate electrode to the second partial region is along the first direction,

[0180] The second partial region is located between the first partial region and the second gate electrode.

[0181] (Structure 11)

[0182] The semiconductor device according to Structure 8, wherein:

[0183] The fifth semiconductor region includes a first partial region and a second partial region,

[0184] The second conductivity type impurity concentration in the first partial region is higher than the second conductivity type impurity concentration in the second partial region.

[0185] A direction from the third insulating region to the first partial region is along the first direction,

[0186] The direction from the first partial area to the second partial area is along the second direction,

[0187] The second partial region is in contact with the second insulating region.

[0188] (Structure 12)

[0189] The semiconductor device according to any one of structures 1 to 11, wherein

[0190] The semiconductor layer further includes a seventh semiconductor region of the second conductivity type that is continuous with the fourth semiconductor region and in contact with the second electrode.

[0191] The concentration of the second conductivity type impurities in the seventh semiconductor region is higher than the concentration of the second conductivity type impurities in the fourth semiconductor region.

[0192] (Structure 13)

[0193] The semiconductor device according to structure 12, wherein:

[0194] The seventh semiconductor region is located between the fourth semiconductor region and the second electrode.

[0195] (Structure 14)

[0196] The semiconductor device according to structure 12 or 13, wherein:

[0197] The position of the center of the seventh semiconductor region in the second direction perpendicular to the first direction is between the position of the center of the fourth semiconductor region in the second direction and the position of the second gate electrode in the second direction.

[0198] (Structure 15)

[0199] The semiconductor device according to any one of structures 12 to 14, wherein:

[0200] The seventh semiconductor region has a second conductivity type impurity concentration of 5×10 17 atoms / cm 3 The above areas,

[0201] An area where the seventh semiconductor region is in contact with the second electrode is smaller than an area where the fourth semiconductor region is in contact with the second electrode.

[0202] (Structure 16)

[0203] The semiconductor device according to any one of Structures 1 to 15, wherein:

[0204] A plurality of second gate electrodes are arranged in a second direction perpendicular to the first direction.

[0205] The first area is arranged in a plurality in the second direction.

[0206] The second insulating region is arranged in a plurality in the second direction.

[0207] A plurality of the fifth semiconductor regions are arranged in the second direction and are in contact with the second insulating region.

[0208] A plurality of the fourth semiconductor regions are arranged in the second direction and are in contact with the second insulating region.

[0209] The fifth semiconductor region is located between the two first regions that are in contact with the same second insulating region.

[0210] (Structure 17)

[0211] The semiconductor device according to any one of structures 1 to 16, wherein

[0212] A plurality of second gate electrodes are arranged in a second direction perpendicular to the first direction.

[0213] The first area is arranged in a plurality in the second direction.

[0214] The second insulating region is arranged in a plurality in the second direction.

[0215] A plurality of the fifth semiconductor regions are arranged in the second direction.

[0216] Two of the plurality of first regions that are adjacent to each other in the second direction are provided between two of the plurality of fifth semiconductor regions that are adjacent to each other in the second direction.

[0217] One of the fourth semiconductor regions is provided between the two first regions.

[0218] Each of the plurality of second insulating regions is in contact with each of the plurality of first regions.

[0219] One of the fourth semiconductor regions is in contact with each of two of the second insulating regions that are adjacent to each other in the second direction among the plurality of second insulating regions.

[0220] (Structure 18)

[0221] The semiconductor device according to structure 17, wherein

[0222] The semiconductor layer further includes two seventh semiconductor regions of the second conductivity type that are continuous with the fourth semiconductor region and in contact with the second electrode.

[0223] The concentration of the second conductivity type impurity in the seventh semiconductor region is higher than the concentration of the second conductivity type impurity in the fourth semiconductor region.

[0224] The two seventh semiconductor regions are between the one fourth semiconductor region and the second electrode,

[0225] The position of the center of the fourth semiconductor region in the second direction is between the positions of the two seventh semiconductor regions in the second direction.

[0226] (Structure 19)

[0227] The semiconductor device according to any one of structures 1 to 18, wherein

[0228] When the first gate electrode is in the on state, the second gate electrode changes from the on state to the off state.

[0229] When the second gate electrode is in the off state, the first gate electrode changes from the on state to the off state.

[0230] (Structure 20)

[0231] The semiconductor device according to any one of structures 1 to 19, wherein

[0232] When the first gate electrode is in an off state, the second gate electrode changes from an off state to an on state.

[0233] When the second gate electrode is in the on state, the first gate electrode is switched from the off state to the on state.

[0234] In an embodiment, information related to the shape of a semiconductor region, etc. can be obtained, for example, by electron microscopy. For example, information related to the impurity concentration in a semiconductor region can be obtained by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). For example, information related to the carrier concentration in a semiconductor region can be obtained by SCM (Scanning Capacitance Microscopy).

[0235] According to the embodiment, a semiconductor device capable of reducing on-voltage can be provided.

[0236] In this specification, the term "electrical connection" includes not only direct contact connection but also connection via other conductive members.

[0237] In the present specification, “perpendicular” and “parallel” mean not only strictly perpendicular and strictly parallel but also include variations in the manufacturing process, for example, and may be substantially perpendicular and substantially parallel.

[0238] One direction along another direction may also mean that the one direction and the other direction are parallel.

[0239] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, as long as a person skilled in the art can achieve the same effect by appropriately selecting the specific structure of each element included in the semiconductor device from the known range and implementing the present invention in the same manner, the specific structure is included in the scope of the present invention.

[0240] Examples obtained by combining any two or more elements of each specific example within a technically possible range are also included in the scope of the present invention as long as they include the gist of the present invention.

[0241] Furthermore, any semiconductor devices obtained by appropriately changing the design and implementing the semiconductor devices described above as the embodiments of the present invention by those skilled in the art also fall within the scope of the present invention as long as they include the gist of the present invention.

[0242] Furthermore, within the scope of the concept of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also fall within the scope of the present invention.

[0243] While several embodiments of the present invention have been described, these embodiments are illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their variations are included within the scope and gist of the invention, and are included in the invention described in the claims and their equivalents.

[0244] (Explanation of Symbols)

[0245] 11: First electrode; 12: Second electrode; 21: First gate electrode; 22: Second gate electrode; 22a, 22b, 22c, 22d: Electrodes; 22p: First gate portion; 22q: Second gate portion; 22r: Third gate portion; 30: Semiconductor layer; 31: First semiconductor region; 31a: Upper portion; 31b: Lower portion; 32: Second semiconductor region; 33: Third semiconductor region; 33a: Part; 34: Fourth semiconductor region; 34a, 34b: Region; 34p: End portion; 35: Fifth semiconductor region; 35a, 35b: Region; b: region; 35p, 35q: end portions; 35t: first partial region; 35u: second partial region; 36: sixth semiconductor region; 36p: first region; 36pa, 36pb, 36pc: region; 36q: second region; 37: seventh semiconductor region; 37a, 37b: region; 39: semiconductor region; 40A: first insulating portion; 40B: second insulating portion; 41: first insulating region; 42: second insulating region; 42a, 42b: insulating region; 43: third insulating region; 48: insulating portion; 70: control portion; 91: p + Shape area; 92:n + shaped region; 93: p-shaped region; 94: n-shaped region; 101-106, 190: semiconductor device; EC: electron current; F1, F2: first surface; Ln: length; T1: trench; V1, V2, V off 1. V off 2. V on 1. V on 2: Voltage; V t 1. V t 2: threshold voltage; W34, W35, W37: length; p34, p37: position; tm: time; tm1~tm4: moment.

Claims

1. A semiconductor device comprising: 1st electrode; a second electrode, wherein a direction from the second electrode to the first electrode is along a first direction; a semiconductor layer provided between the first electrode and the second electrode, having a first surface on the first electrode side and a second surface opposite to the first surface, wherein the first surface and the second surface extend along a second direction perpendicular to the first direction; a first gate electrode disposed on the first electrode side of the semiconductor layer; a second gate electrode provided on the second electrode side of the semiconductor layer, with the second surface being located between the first surface and the second electrode; a first insulating region disposed between the first gate electrode and the semiconductor layer; as well as a second insulating region provided between the second gate electrode and the second surface of the semiconductor layer; The semiconductor layer includes: a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type, disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode; a third semiconductor region of the second conductivity type, electrically connected to the first electrode, wherein a portion of the third semiconductor region is disposed between the first semiconductor region and the second semiconductor region, in contact with the first insulating region, and opposite to the first gate electrode; a fourth semiconductor region of the second conductivity type, provided between the first semiconductor region and the second electrode and electrically connected to the second electrode; a fifth semiconductor region of the second conductivity type, spaced apart from the fourth semiconductor region in the second direction; and The sixth semiconductor region of the first conductivity type includes a first region provided between the fourth semiconductor region and the fifth semiconductor region, in contact with the second insulating region, and facing the second gate electrode.

2. The semiconductor device according to claim 1, wherein The sixth semiconductor region includes a second region provided between the first semiconductor region and the fifth semiconductor region. The concentration of the first conductivity type impurities in the sixth semiconductor region is higher than the concentration of the first conductivity type impurities in the first semiconductor region.

3. A semiconductor device comprising: 1st electrode; a second electrode, wherein a direction from the second electrode to the first electrode is along a first direction; a semiconductor layer disposed between the first electrode and the second electrode; a first gate electrode disposed on the first electrode side of the semiconductor layer; a second gate electrode disposed on the second electrode side of the semiconductor layer; a first insulating region disposed between the first gate electrode and the semiconductor layer; as well as a second insulating region provided between the second gate electrode and the semiconductor layer; The semiconductor layer includes: a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type, disposed between the first semiconductor region and the first electrode and electrically connected to the first electrode; a third semiconductor region of the second conductivity type, electrically connected to the first electrode, wherein a portion of the third semiconductor region is disposed between the first semiconductor region and the second semiconductor region, in contact with the first insulating region, and opposite to the first gate electrode; a fourth semiconductor region of the second conductivity type, provided between the first semiconductor region and the second electrode and electrically connected to the second electrode; a fifth semiconductor region of the second conductivity type, spaced apart from the fourth semiconductor region; and The sixth semiconductor region of the first conductive type includes a first region arranged between the fourth semiconductor region and the fifth semiconductor region, connected to the second insulating region and opposite to the second gate electrode, and a second region arranged between the first semiconductor region and the fifth semiconductor region, and the impurity concentration of the first conductive type in the sixth semiconductor region is higher than the impurity concentration of the first conductive type in the first semiconductor region.

4. The semiconductor device according to any one of claims 1 to 3, wherein The concentration of the second conductivity type impurities in the fifth semiconductor region is higher than the concentration of the second conductivity type impurities in the fourth semiconductor region.

5. The semiconductor device according to any one of claims 1 to 3, wherein A length of the fifth semiconductor region along a second direction perpendicular to the first direction is shorter than a length of the fourth semiconductor region along the second direction.

6. The semiconductor device according to any one of claims 1 to 3, wherein A length of the fifth semiconductor region along a second direction perpendicular to the first direction is longer than a length of the fourth semiconductor region along the second direction.

7. The semiconductor device according to any one of claims 1 to 3, wherein The fourth semiconductor region is arranged in a plurality in a second direction perpendicular to the first direction. The first area is arranged in a plurality in the second direction. Two of the plurality of first regions adjacent to each other in the second direction are provided between two of the plurality of fourth semiconductor regions adjacent to each other in the second direction. One of the fifth semiconductor regions is provided between the two first regions. The two first regions and the one fifth semiconductor region face the one second gate electrode in the first direction.

8. The semiconductor device according to any one of claims 1 to 3, wherein The fourth semiconductor region is arranged in a plurality in a second direction perpendicular to the first direction. The first area is arranged in a plurality in the second direction. A plurality of second gate electrodes are arranged in the second direction. Two of the plurality of first regions adjacent to each other in the second direction are provided between two of the plurality of fourth semiconductor regions adjacent to each other in the second direction. One of the fifth semiconductor regions is provided between the two first regions. Each of the two first regions is opposed in the first direction to each of two second gate electrodes adjacent to each other in the second direction among the plurality of second gate electrodes. One of the fifth semiconductor regions faces the third insulating region provided between the two second gate electrodes in the first direction.

9. The semiconductor device according to any one of claims 1 to 3, wherein The fifth semiconductor region includes a first partial region and a second partial region, The second conductivity type impurity concentration in the first partial region is higher than the second conductivity type impurity concentration in the second partial region. The second insulating region is located between the second partial region and the second gate electrode and is in contact with the second partial region.

10. The semiconductor device according to claim 9, wherein A direction from the second gate electrode to the first partial region is along the first direction, A direction from the second gate electrode to the second partial region is along the first direction, The second partial region is located between the first partial region and the second gate electrode.

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