Semiconductor device
By providing an insulating film and a field plate electrode between the channel and the electrode, the problem of insufficient design margin in the vertical MOSFET is solved, a balance between high withstand voltage and low threshold voltage is achieved, and the performance of the semiconductor device is improved.
Patent Information
- Application Number
- CN202510162101.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-13
- Filing Date
- 2025-02-14
- Publication Date
- 2025-09-16
AI Technical Summary
In the prior art, the lack of a p-type base layer in a vertical MOSFET results in insufficient design margin, making it difficult to achieve a balance between high withstand voltage and low threshold voltage.
A single-layer insulating film is used to cover the side of the channel part and the area between the electrode. The insulating film reduces the Fermi level pinning effect, increases the barrier height between the electrode and the semiconductor layer, and sets a field plate electrode between the channel part and the electrode to relax the electric field and enhance the voltage resistance.
The design margin is expanded, the voltage resistance and threshold voltage control capability of the semiconductor device are improved, and the leakage current in the off state is reduced.
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Figure CN120659358A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a semiconductor device. Background Art
[0002] A Schottky-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) has been proposed in which a p-type base layer is not provided in a vertical MOSFET and an off state is achieved by a depletion layer extending from the Schottky junction of a source electrode and a semiconductor layer in a trench contact portion.
[0003] Prior art literature
[0004] Non-patent literature
[0005] Non-patent literature 1: Yee-Chia Yeo, Pushkar Ranade, Tsu-Jae King, Chenming Hu "Effects of High-k Gate Dielectric Materials on Metal and Silicon GateWorkfunctions" IEEE ELECTRON DEVICE LETTERS, VOL.23, NO.6, JUNE 2002 Summary of the Invention
[0006] An object of an embodiment of the present invention is to provide a semiconductor device capable of increasing a design margin.
[0007] According to an embodiment of the present invention, a semiconductor device comprises: a first electrode; a semiconductor layer of a first conductive type, arranged on the first electrode and having a plurality of mesa portions arranged away from each other in a first direction; a second electrode, located in a recess extending from the upper surface of the mesa portion in a second direction perpendicular to the first direction; a gate electrode, located between mesa portions adjacent to each other in the first direction among the plurality of mesa portions; and a single-layer insulating film, located in the recess, the mesa portion having: a channel portion, located between the recess and the gate electrode in the first direction; and a contact portion, arranged on the channel portion and having a higher first conductive type impurity concentration than the channel portion, the channel portion having: a first side surface, opposite to the gate electrode in the first direction; and a second side surface, located on the opposite side of the first side surface in the first direction, the insulating film being arranged on the second side surface, the second electrode being in contact with the contact portion and the insulating film in the recess. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1It is a schematic cross-sectional view of a semiconductor device according to an embodiment.
[0009] Figure 2 It is a schematic cross-sectional view of a semiconductor device according to an embodiment.
[0010] Figure 3 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.
[0011] Figure 4 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.
[0012] Figure 5 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.
[0013] Figure 6 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment.
[0014] Figure 7 (a) and (b) are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION
[0015] Hereinafter, each embodiment will be described with reference to the drawings.
[0016] The drawings are schematic or conceptual diagrams, and the relationship between the thickness and width of each part, the size ratio between parts, etc. may not necessarily be the same as in reality. Even when showing the same part, the mutual dimensions and ratios may be expressed differently depending on the drawings.
[0017] In addition, the same or similar elements are denoted by the same reference numerals.
[0018] like Figure 1 As shown, the semiconductor device 1 of the embodiment includes a first electrode 41, a semiconductor layer 100 provided on the first electrode 41, and a second electrode 42 provided on the semiconductor layer 100. The semiconductor device 1 has a vertical MOSFET structure in which current flows in the thickness direction of the semiconductor layer 100 provided between the first electrode 41 and the second electrode 42. The first electrode 41 functions as a drain electrode, and the second electrode 42 functions as a source electrode. The first electrode 41 and the second electrode 42 are made of metal.
[0019] The thickness direction of the semiconductor layer 100 is along the second direction Z. Two directions perpendicular to the second direction Z are referred to as the first direction X and the third direction Y. Figure 1 In the figure, the first direction X is the horizontal direction, the second direction Z is the vertical direction, and the third direction Y is the direction passing through the paper.
[0020] Semiconductor layer 100 is of a first conductivity type. While n-type is used as the first conductivity type in this specification, p-type is also acceptable. Semiconductor layer 100 is, for example, a silicon layer. Alternatively, semiconductor layer 100 may be a silicon carbide layer, a gallium nitride layer, or the like.
[0021] The semiconductor layer 100 includes an n-type first semiconductor layer 10 provided on a first electrode 41, an n-type second semiconductor layer 20 provided on the first semiconductor layer 10, and an n-type third semiconductor layer 30 provided on the second semiconductor layer 20. The n-type impurity concentration of the first semiconductor layer 10 is higher than the n-type impurity concentration of the second semiconductor layer 20. The first semiconductor layer 10 is electrically connected to the first electrode 41 and functions as a drain layer in the MOSFET. The n-type impurity concentration of the second semiconductor layer 20 is lower than the n-type impurity concentration of the first semiconductor layer 10 and the n-type impurity concentration of the third semiconductor layer 30. The second semiconductor layer 20 functions as a drift layer in the MOSFET. The n-type impurity concentration of the third semiconductor layer 30 is higher than the n-type impurity concentration of the second semiconductor layer 20. The third semiconductor layer 30 is electrically connected to the second electrode 42 and functions as a source layer in the MOSFET. In semiconductor layer 100, no p-type base layer is provided between second semiconductor layer 20 (drift layer) and third semiconductor layer 30 (source layer). Semiconductor device 1 has a Schottky-type MOSFET structure. Unless otherwise specified, the relationship between impurity concentrations can be rewritten as the relationship between carrier concentrations.
[0022] The semiconductor layer 100 includes a root portion extending in the first direction X and the third direction Y, and a plurality of mesa portions 100A spaced apart from one another in the first direction X. The mesa portion 100A is located on the upper surface side of the semiconductor layer 100 where the second electrode 42 is located. The root portion is located between the first electrode 41 and the gate electrode 50 in the second direction Z. The mesa portion 100A includes a portion of the second semiconductor layer 20 and the third semiconductor layer 30.
[0023] The semiconductor device 1 includes a gate electrode 50 located between adjacent mesa portions 100A in a first direction X. The semiconductor device 1 includes, for example, a plurality of gate electrodes 50. The mesa portions 100A and the gate electrodes 50 are alternately arranged in the first direction X. The mesa portions 100A and the gate electrodes 50 extend in a third direction Y. For example, polycrystalline silicon can be used as a material for the gate electrode 50.
[0024] The mesa portion 100A has a recessed portion 100B that opens on the top surface. The recessed portion 100B extends from the top surface of the mesa portion 100A in the second direction Z. Furthermore, the recessed portion 100B extends in the third direction Y. Each mesa portion 100A has two sidewall portions 100C separated in the first direction X by the recessed portion 100B. The recessed portion 100B is located between the two sidewall portions 100C spaced apart from each other in the first direction X. The bottom of the recessed portion 100B is located between two gate electrodes 50 adjacent to each other in the first direction X.
[0025] The sidewall portion 100C includes a channel portion 21 and a contact portion 31. The channel portion 21 is included in the second semiconductor layer 20. The channel portion 21 is located between the recess 100B and the gate electrode 50 in the first direction X. The contact portion 31 is provided on the channel portion 21 and is included in the third semiconductor layer 30. The n-type impurity concentration of the contact portion 31 is higher than the n-type impurity concentration of the channel portion 21. The n-type carrier concentration of the contact portion 31 is higher than the n-type carrier concentration of the channel portion 21. For example, the p-type impurity concentration of the contact portion 31 is lower than the p-type impurity concentration of the channel portion 21. In this case, the n-type impurity concentration of the contact portion 31 and the n-type impurity concentration of the channel portion 21 may be the same, for example.
[0026] The channel portion 21 has a first side surface 21A facing the side surface of the gate electrode 50 in the first direction X, and a second side surface 21B located on the opposite side of the first side surface 21A in the first direction X.
[0027] Semiconductor device 1 includes insulating film 70 located in recess 100B. Insulating film 70 is provided on second side surface 21B of channel 21. Insulating film 70 is a single layer film, such as a silicon oxide film. Alternatively, a silicon nitride film may be used as insulating film 70.
[0028] The semiconductor device 1 includes a gate insulating film 81 provided between the first side surface 21A of the channel portion 21 and the side surface of the gate electrode 50. Furthermore, the semiconductor device 1 includes a first interlayer insulating film 82 provided between the gate electrode 50 and the second electrode 42. For example, a silicon oxide film can be used as the gate insulating film 81 and the first interlayer insulating film 82.
[0029] The second electrode 42 has a root portion extending in the first direction X and the third direction Y, and a plurality of protrusions spaced apart from one another in the first direction X. The protrusions are located between the root portion of the second electrode 42 and the first electrode 41 in the second direction Z. In this example, one protrusion contacts one mesa portion 100A. The second electrode 42 is located in the recess 100B. Furthermore, the second electrode 42 is located on the contact portion 31 and on the first interlayer insulating film 82. The second electrode 42 contacts the top surface of the contact portion 31. The contact portion 31 is located in the recess 100B and has an inner side surface 31B that is continuous with the second side surface 21B of the channel portion 21. At least a portion of the inner side surface 31B of the contact portion 31 is exposed from the insulating film 70, and the second electrode 42 contacts the inner side surface 31B of the contact portion 31. The second electrode 42 is electrically connected to the contact portion 31 at both the top surface and the inner side surface 31B of the contact portion 31. The second electrode 42 covers the insulating film 70 in the recess 100B and is in contact with the insulating film 70. Figure 1 The second electrode 42 and the contact portion 31 are shown facing each other in contact with each other in the first direction X and the second direction Z. However, they may be faced with each other in contact with each other in the first direction X and not in contact with each other in the second direction Z.
[0030] In the first direction X, the insulating film 70 is located between the second electrode 42 and the channel portion 21 within the recess 100B. The channel portion 21 is located between the insulating film 70 and the gate insulating film 81. The gate insulating film 81 is located between the channel portion 21 and the gate electrode 50. The channel portion 21 is in contact with the insulating film 70 and the gate insulating film 81. In the first direction X, only one channel portion 21 is provided between adjacent gate electrodes 50 and protrusions of the second electrode 42. Between two adjacent channel portions 21 in the first direction X, exactly one gate electrode 50 or exactly one protrusion of the second electrode 42 is provided. The contact portion 31 is located between the channel portion 21 and the second electrode 42 in the second direction Z. In this example, two channel portions 21 are provided in a single mesa portion 100A.
[0031] For example, a positive potential (e.g., 20V to 50V) is applied to the first electrode 41, and a ground potential is applied to the second electrode 42. In this state, when the potential of the gate electrode 50 is lower than the threshold voltage, the channel portion 21 is depleted by the depletion layer extending from the interface between the second side surface 21B of the channel portion 21 and the insulating film 70, and the semiconductor device 1 enters the off state. When the potential of the gate electrode 50 reaches or exceeds the threshold voltage, the depletion layer in the channel portion 21 disappears or narrows, and the semiconductor device 1 enters the on state. In the on state, current flows from the first electrode 41 to the second electrode 42 via the first semiconductor layer 10, the channel portion 21 of the second semiconductor layer 20, and the contact portion 31 (third semiconductor layer 30).
[0032] The channel portion 21 is depleted, thereby achieving a high breakdown voltage in the off state. In order to facilitate the depletion of the channel portion 21, the width of the channel portion 21 in the first direction X is preferably small. In this embodiment, the width of the channel portion 21 in the first direction X is smaller than the width of the recess 100B in the first direction X. The width of the channel portion 21 in the first direction X is, for example, greater than 20 nm and less than 80 nm. The threshold voltage of the semiconductor device 1 also depends on the width of the channel portion 21 in the first direction X. The width of the channel portion 21 in the first direction X is very thin, and from the perspective of process difficulty, it is difficult to adjust the breakdown voltage and threshold voltage of the semiconductor device 1 by the width of the channel portion 21 in the first direction X.
[0033] Furthermore, the breakdown voltage and threshold voltage of the semiconductor device 1 also depend on the barrier height between the metal of the second electrode 42 and the semiconductor layer 100. By using a metal with a high work function, such as Pt, Ni, or Co, as the second electrode 42, the barrier height between the second electrode 42 and the semiconductor layer 100 can be increased, thereby improving the breakdown voltage.
[0034] In the comparative example where the second electrode 42 and the second side surface 21B of the channel portion 21 are directly in contact, there is a problem with the barrier height derived from the work function of the metal of the second electrode 42 not being achieved due to the influence of Fermi level pinning. For example, when Pt is used as the metal of the second electrode 42 and Si is used as the semiconductor layer 100, the ideal barrier height is calculated to be 5.6 eV (Pt work function) - 4.05 eV (Si electron affinity) - 0.05 eV (mirror effect) = 1.5 eV. However, in actual samples, the barrier height is reduced from 0.8 eV to 0.85 eV. This may reduce the design margin.
[0035] According to this embodiment, by providing the insulating film 70 between the second side surface 21B of the channel portion 21 and the second electrode 42, the influence of Fermi level pinning can be reduced, and a barrier height reflecting the work function of the metal of the second electrode 42 can be achieved. This increases the selection of metals for the second electrode 42, and can expand the design margin of the semiconductor device 1.
[0036] The electric field tends to concentrate on the corner portion on the bottom surface side of the recessed portion 100B. The presence of the insulating film 70 at the corner portion can suppress the leakage current generated at the corner portion during the off state.
[0037] A simulation was conducted to determine whether the insulating film 70 provided on the second side surface 21B of the channel portion 21 affects the current-voltage characteristics (IV characteristics) of the semiconductor device 1. The calculations were performed with Si as the material of the channel portion 21, a silicon oxide film (SiO2 film) as the insulating film 70, the work function of the metal of the second electrode 42 as 5.3 eV, and the barrier height between the second electrode 42 and Si as 1.2 eV. The IV characteristics were calculated while maintaining the thickness of the insulating film 70 (thickness in the first direction X) at 10 nm and varying the height of the insulating film 70 from the bottom of the recess 100B (thickness in the second direction Z) to 100 nm, 200 nm, and 280 nm. Furthermore, the IV characteristics were calculated while maintaining the height of the insulating film 70 at 100 nm and varying the thickness to 10 nm, 50 nm, and 100 nm. The IV characteristics remained substantially the same regardless of the thickness and height, confirming that the insulating film 70 did not affect the withstand voltage of the semiconductor device 1.
[0038] The film thickness of the insulating film 70 can be set to, for example, 1 nm or more and 10 nm or less.
[0039] The semiconductor device 1 can be used as a switching element in applications such as inverters and motor drives. In this case, the semiconductor device 1 is required to function as a freewheeling diode that allows the reverse current generated during switching to flow. Therefore, it is preferable that the insulating film 70 is not provided at the bottom of the recess 100B, and the second electrode 42 is in contact with the second semiconductor layer 20 at the bottom of the recess 100B. This ensures a current path (a current path that does not pass through the channel portion) when the freewheeling diode is in operation.
[0040] The semiconductor device 1 can further include a field plate electrode 60 located below the gate electrode 50 between adjacent mesa portions 100A in the first direction X. For example, polycrystalline silicon can be used as the material of the field plate electrode 60. A second interlayer insulating film 83 is provided between the gate electrode 50 and the field plate electrode 60, and between the field plate electrode 60 and the second semiconductor layer 20. For example, a silicon oxide film can be used as the second interlayer insulating film 83.
[0041] The field plate electrode 60 is provided with the same potential as the second electrode 42. This can mitigate the electric field (longitudinal electric field) applied in the second direction Z in the second semiconductor layer 20, thereby improving the withstand voltage. The field plate electrode 60 is not limited to having the same potential as the second electrode 42 and can provide a potential lower than that of the first electrode 41.
[0042] according to Figure 2In the semiconductor device 2 of another embodiment shown, the second electrode 42 includes: a first metal portion 42A, which is opposite to the second side surface 21B of the channel portion 21 via the insulating film 70; and a second metal portion 42B, which is in contact with the inner side surface 31B of the contact portion 31. The protruding portion of the second electrode 42 includes the first metal portion 42A and the second metal portion 42B. The work function of the first metal portion 42A is higher than the work function of the second metal portion 42B. As a result, the barrier height between the first metal portion 42A and the semiconductor layer 100 can be increased and the contact resistance between the second metal portion 42B and the contact portion 31 can be reduced. For example, the first metal portion 42A mainly includes at least one selected from Pt, Ni, and Co, and the second metal portion 42B mainly includes Ti.
[0043] Reference Figure 3 (a)~ Figure 4 (b) An example of a method for forming the insulating film 70 is described.
[0044] By forming the recessed portion 100B on the upper surface side of the mesa portion 100A, the sidewall portion 100C is formed on the upper surface side of the mesa portion 100A. The recessed portion 100B can be formed by, for example, RIE (Reactive Ion Etching).
[0045] After forming the recess 100B, as shown in FIG. Figure 3 As shown in (a), a barrier film 91 is formed on the side surface of the recess 100B (the inner side surface of the side wall portion 100C). The barrier film 91 is formed on the side surface of the opening of the recess 100B. For example, a resist film can be used as the barrier film 91.
[0046] After forming the barrier film 91, as shown in FIG. Figure 3 As shown in (b), an insulating film 70 is formed on the side and bottom surfaces of the recess 100B where the barrier film 91 is not formed. As the insulating film 70, for example, a silicon oxide film can be formed by ALD (Atomic Layer Deposition).
[0047] After forming the insulating film 70, the barrier film 91 is removed. Figure 4 As shown in (a), the side surface of the opening side of the recess 100B is exposed. The barrier film 91 can be removed by, for example, cleaning or etching.
[0048] After removing the barrier film 91, the insulating film 70 is etched by RIE. Figure 4As shown in (b), the insulating film 70 formed on the bottom surface of the recess 100B is removed, exposing the bottom surface of the recess 100B. The portion of the sidewall 100C adjacent to the insulating film 70 becomes the channel portion. In addition, a contact portion having a higher n-type impurity concentration than the channel portion is formed on the upper portion of the sidewall 100C, for example, by ion implantation. The contact portion is in contact with the second electrode formed in the recess 100B at the upper portion of the side surface of the recess 100B where the insulating film 70 is not formed. As the second electrode, Pt can be formed in the recess 100B by sputtering, for example.
[0049] Reference Figure 5 (a)~ Figure 7 (b) Another example of the method of forming the insulating film 70 will be described.
[0050] After the recess 100B is formed in the mesa portion 100A, Figure 5 As shown in (a), a precursor 92 is continuously formed on the upper surface of the sidewall portion 100C and the side and bottom surfaces of the recessed portion 100B. As the precursor 92, for example, a TDMAS (trimethylsilane) precursor can be formed by the ALD method.
[0051] After forming the precursor 92, as Figure 5 As shown in (b), a portion of the precursor 92 is removed. The precursor 92 on the upper surface of the sidewall portion 100C and the side surface of the opening in the recess 100B are removed. The precursor 92 on the side surface and the bottom surface of the bottom of the recess 100B remain. For example, a reduced pressure atmosphere or O2 plasma gas can be used to remove a portion of the precursor 92.
[0052] After removing a portion of the precursor 92, for example, O2 plasma or O3 gas is supplied to convert the remaining precursor 92 into SiO2. Figure 6 As shown in (a), a SiO 2 film 71 is formed on the side surface and the bottom surface of the bottom surface side of the recess 100B.
[0053] After the precursor 92 is converted into SiO2, the precursor 93 is formed again on the upper surface of the side wall portion 100C and the side and bottom surfaces of the recessed portion 100B. Figure 6 As shown in (b), the precursor 93 covers the SiO2 film 71 formed in the previous step.
[0054] After forming the precursor 93, as Figure 7 As shown in (a), a portion of the precursor 93 is removed. The precursor 93 on the upper surface of the sidewall portion 100C and the side surface of the opening in the recess 100B are removed. The precursor 93 laminated on the SiO2 film 71 remains.
[0055] After removing a portion of the precursor 93, the remaining precursor 93 is SiO2-converted. Figure 7 As shown in (b), a SiO2 film 72 is formed on the side surfaces and bottom surface of the bottom side of the recess 100B. The SiO2 film 72 is a film formed by integrating the film formed by SiO2-transforming the precursor 92 and the film formed by SiO2-transforming the precursor 93. Subsequently, the steps of re-forming the precursor, removing a portion of the precursor, and SiO2-transforming the precursor are repeated until the SiO2 film formed on the side surfaces and bottom surface of the bottom side of the recess 100B reaches a desired thickness.
[0056] Thereafter, the SiO 2 film is etched by RIE to remove the SiO 2 film formed on the bottom surface of the recess 100B. Thus, an insulating film 70 having a desired thickness is formed on the side surface of the bottom surface of the recess 100B.
[0057] The insulating film 70 is a single-layer film. The manufacturing process of the single-layer insulating film 70 is simple. The single-layer insulating film 70 has no thickness variations, and the influence of crystal quality at the interface of the stacked films is minimal, resulting in stable quality.
[0058] While several embodiments of the present invention have been described, these embodiments are illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the gist of the invention. These embodiments and their variations are included within the scope and gist of the invention, and are included in the invention described in the claims and their equivalents.
[0059] (Explanation of Symbols)
[0060] 1, 2: semiconductor device; 10: first semiconductor layer; 20: second semiconductor layer; 21: channel portion; 21A: first side surface; 21B: second side surface; 30: third semiconductor layer; 31: contact portion; 31B: inner side surface; 41: first electrode; 42: second electrode; 42A: first metal portion; 42B: second metal portion; 50: gate electrode; 60: field plate electrode; 70: insulating film; 81: gate insulating film; 82: first interlayer insulating film; 83: second interlayer insulating film; 100: semiconductor layer; 100A: mesa portion; 100B: recessed portion; 100C: sidewall portion.
Claims
1. A semiconductor device comprising: 1st electrode; a first conductive type semiconductor layer provided on the first electrode and having a plurality of mesa portions provided spaced apart from each other in a first direction; a second electrode located in a recessed portion extending from the upper surface of the mesa portion in a second direction perpendicular to the first direction; a gate electrode located between adjacent mesa portions in the first direction among the plurality of mesa portions; and a single-layer insulating film located in the recessed portion, The mesa portion includes: a channel portion located between the recess and the gate electrode in the first direction; and a contact portion provided on the channel portion and having a higher first conductivity type impurity concentration than the channel portion. The channel portion includes: a first side surface facing the gate electrode in the first direction; and a second side surface located on the opposite side of the first side surface in the first direction. The insulating film is provided on the second side surface, The second electrode is in contact with the contact portion and the insulating film in the recessed portion.
2. The semiconductor device according to claim 1, wherein The second electrode is in contact with the semiconductor layer at the bottom of the recess.
3. The semiconductor device according to claim 1 or 2, wherein: The second electrode includes a first metal portion facing the channel portion with the insulating film interposed therebetween and a second metal portion in contact with the contact portion. A work function of the first metal portion is higher than a work function of the second metal portion.
4. The semiconductor device according to claim 3, wherein The first metal portion includes Pt, Ni or Co, The second metal portion includes Ti.
5. The semiconductor device according to claim 1 or 2, wherein The width of the channel portion in the first direction is smaller than the width of the recessed portion in the first direction.
6. The semiconductor device according to claim 1 or 2, wherein: The semiconductor layer has: a first semiconductor layer disposed on the first electrode; a second semiconductor layer, disposed on the first semiconductor layer, having a lower first conductivity type impurity concentration than the first semiconductor layer, and including the channel portion; as well as The third semiconductor layer is provided on the second semiconductor layer, has a higher first conductivity type impurity concentration than the second semiconductor layer, and includes the contact portion.
7. The semiconductor device according to claim 1 or 2, wherein: The insulating film is a silicon oxide film.
8. The semiconductor device according to claim 1 or 2, wherein: The insulating film has a thickness of 1 nm to 10 nm.
9. The semiconductor device according to claim 1 or 2, wherein: A field plate electrode is further provided between the mesa portions adjacent to each other in the first direction and located below the gate electrode.
10. The semiconductor device according to claim 9, wherein The field plate electrode is provided with the same potential as that of the second electrode.
11. A semiconductor device comprising: 1st electrode; a first conductive type semiconductor layer provided on the first electrode and having a plurality of mesa portions provided spaced apart from each other in a first direction; a second electrode located in a recessed portion extending from the upper surface of the mesa portion in a second direction perpendicular to the first direction; a gate electrode located between adjacent mesa portions in the first direction among the plurality of mesa portions; and a single-layer insulating film located in the recessed portion, The mesa portion includes: a channel portion located between the recess and the gate electrode in the first direction; and a contact portion provided on the channel portion and having a lower second conductivity type carrier concentration than the channel portion. The channel portion includes: a first side surface facing the gate electrode in the first direction; and a second side surface located on the opposite side of the first side surface in the first direction. The insulating film is provided on the second side surface, The second electrode is in contact with the contact portion and the insulating film in the recessed portion.
12. A semiconductor device comprising: 1st electrode; a first conductive type semiconductor layer provided on the first electrode and having a plurality of mesa portions provided spaced apart from each other in a first direction; a second electrode located in a recessed portion extending from the upper surface of the mesa portion in a second direction perpendicular to the first direction; a gate electrode located between adjacent mesa portions in the first direction among the plurality of mesa portions; and a single-layer insulating film located in the recessed portion, The mesa portion includes: a channel portion located between the recess and the gate electrode in the first direction; and a contact portion provided on the channel portion and having a higher first conductivity type carrier concentration than the channel portion. The channel portion includes: a first side surface facing the gate electrode in the first direction; and a second side surface located on the opposite side of the first side surface in the first direction. The insulating film is provided on the second side surface, The second electrode is in contact with the contact portion and the insulating film in the recessed portion.