Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device having high reliability and high on-current is achieved. The semiconductor device includes: an oxide insulating film; a metal oxide layer having a first region and a second region provided separately from each other on the oxide insulating film; an oxide semiconductor layer provided in contact with the first region and the second region; a gate insulating film provided so as to cover the oxide semiconductor layer; and a gate electrode provided on the oxide semiconductor layer via a gate insulating film, the oxide semiconductor layer including a channel region overlapping the gate electrode, and a source region and a drain region sandwiching the channel region, the channel region being in contact with the oxide insulating film between the first region and the second region.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. In particular, one embodiment of the present invention relates to a semiconductor device using an oxide semiconductor for a channel. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] In recent years, the development of semiconductor devices using oxide semiconductors for their channels, replacing amorphous silicon, low-temperature polysilicon, and single-crystal silicon, has continued to advance (e.g., Patent Documents 1-6). Semiconductor devices using oxide semiconductors for their channels can be formed using simple structures and low-temperature processes, similar to semiconductor devices using amorphous silicon for their channels. Semiconductor devices using oxide semiconductors for their channels are known to have higher mobility than semiconductor devices using amorphous silicon for their channels.

[0003] In order to ensure stable operation of semiconductor devices using an oxide semiconductor as a channel, it is important to supply oxygen to the oxide semiconductor layer during the manufacturing process to reduce oxygen vacancies formed in the oxide semiconductor layer. For example, as one method of supplying oxygen to the oxide semiconductor layer, a technique is disclosed in which the oxide semiconductor layer is subjected to a heat treatment while being covered with an insulating film formed under conditions that contain a large amount of oxygen.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-141338

[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 2014-099601

[0008] Patent Document 3: Japanese Patent Application Laid-Open No. 2021-153196

[0009] Patent Document 4: Japanese Patent Application Publication No. 2018-006730

[0010] Patent Document 5: Japanese Patent Application Laid-Open No. 2016-184771

[0011] Patent Document 6: Japanese Patent Application Laid-Open No. 2021-108405 Summary of the Invention

[0012] Problems to be solved by the invention

[0013] If the oxide semiconductor layer is covered with an insulating film formed under conditions that contain a high amount of oxygen and then subjected to heat treatment, oxygen is uniformly supplied to the oxide semiconductor layer. This reduces oxygen vacancies in the channel region of the oxide semiconductor layer, thereby suppressing abnormal transistor characteristics or characteristic fluctuations during reliability testing caused by electrons generated by hydrogen being trapped in the defects. On the other hand, if oxygen vacancies in the source and drain regions are reduced, the resistance of the source and drain regions increases, thereby reducing the on-current of the transistor.

[0014] Therefore, one object of one embodiment of the present invention is to realize a semiconductor device with high reliability and high on-current.

[0015] Means for solving problems

[0016] A semiconductor device according to one embodiment of the present invention comprises: an oxide insulating film; a metal oxide layer having a first region and a second region separately arranged on the oxide insulating film; an oxide semiconductor layer arranged in contact with the first region and the second region; a gate insulating film arranged so as to cover the oxide semiconductor layer; and a gate electrode arranged on the oxide semiconductor layer via the gate insulating film, the oxide semiconductor layer including a channel region overlapping with the gate electrode, and a source region and a drain region sandwiching the channel region, the channel region being in contact with the oxide insulating film between the first region and the second region.

[0017] A semiconductor device according to one embodiment of the present invention comprises: an oxide insulating film; a metal oxide layer having a first region and a second region separated from each other on the oxide insulating film, and a third region between the first region and the second region; an oxide semiconductor layer arranged in contact with the metal oxide layer; a gate insulating film arranged so as to cover the oxide semiconductor layer; and a gate electrode arranged on the oxide semiconductor layer via the gate insulating film, the oxide semiconductor layer including a channel region overlapping with the gate electrode, and a source region and a drain region sandwiching the channel region, the source region being in contact with the first region, the drain region being in contact with the second region, and the channel region being in contact with the third region, and the film thickness of the metal oxide layer in the first region and the second region being greater than the film thickness of the metal oxide layer in the third region. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0019] Figure 2 It will Figure 1 An enlarged view of a portion of a semiconductor device is shown.

[0020] Figure 3It is a plan view schematically showing a semiconductor device according to one embodiment of the present invention.

[0021] Figure 4 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0022] Figure 5 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0023] Figure 6 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0024] Figure 7 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0025] Figure 8 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0026] Figure 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0027] Figure 10 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0028] Figure 11 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0029] Figure 12 It will Figure 10 An enlarged view of a portion of a semiconductor device is shown.

[0030] Figure 13 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0031] Figure 14 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0032] Figure 15 It is a plan view schematically showing a semiconductor device according to one embodiment of the present invention.

[0033] Figure 16 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0034] Figure 17 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0035] Figure 18 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0036] Figure 19 It will Figure 18 An enlarged view of a portion of a semiconductor device is shown.

[0037] Figure 20 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0038] Figure 21 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0039] Figure 22 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0040] Figure 23 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0041] Figure 24 It will Figure 23 An enlarged view of a portion of a semiconductor device is shown.

[0042] Figure 25 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0043] Figure 26 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0044] Figure 27 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0045] Figure 28 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0046] Figure 29 It is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention.

[0047] Figure 30 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0048] Figure 31 It is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0049] Description of Reference Numerals

[0050] 10: Semiconductor device, 10A to 10H: Semiconductor device, 12GE: Gate electrode, 12GL: Gate wiring, 13: Gate insulating film, 14: Gate insulating film, 14a: Nitride insulating film, 14b: Oxide insulating film, 17: Metal oxide film, 18: Metal oxide layer, 18-1: Metal oxide layer, 18-2: Metal oxide layer, 19-1: First region, 19-2: Second region, 19-3: Third region, 21: Oxide semiconductor film, 22: Oxide semiconductor layer, 23: Resist mask, 24: Oxide semiconductor layer , 24a: first region, 24b: second region, 24c: third region, 26: gate insulating film, 28: metal oxide film, 32GE: gate electrode, 32GL: gate wiring, 34: interlayer insulating film, 36DE: drain electrode, 36SE: source electrode, 36SL: source wiring, 37: metal oxide film, 38: metal oxide layer, 43: oxide semiconductor film, 44: oxide semiconductor layer, 44-1: oxide semiconductor layer, 44-2: oxide semiconductor layer, 46: oxide semiconductor layer, OP1: opening portion, OP2: opening portion DETAILED DESCRIPTION

[0051] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely an example. Of course, any configuration that a person skilled in the art can easily conceive of by appropriately changing the configuration of the embodiment while maintaining the gist of the invention is included within the scope of the present invention. With respect to the accompanying drawings, in order to make the description clearer, the width, film thickness, shape, etc. of each part are sometimes schematically indicated compared to the actual method. However, the shape shown in the drawings is merely an example and does not limit the interpretation of the present invention. In this specification and the drawings, the same reference numerals are used for the same elements as those described in the accompanying drawings, and detailed descriptions are sometimes appropriately omitted.

[0052] A "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Transistors and semiconductor circuits are one form of a semiconductor device. The semiconductor devices described in the following embodiments may also be transistors used in integrated circuits (ICs) such as display devices, microprocessors (MPUs), or memory circuits.

[0053] A “display device” refers to a structure that uses an electro-optical layer to display an image. For example, a term such as a display device sometimes refers to a display panel including an electro-optical layer, or sometimes refers to a structure that is equipped with other optical components (such as a polarization component, a backlight, a touch panel, etc.) relative to a display unit. As long as there is no technical contradiction, the “electro-optical layer” may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, with respect to the embodiments described below, as display devices, a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer are exemplified for explanation, but the structure in this embodiment can be applied to display devices including the other electro-optical layers mentioned above.

[0054] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or below. Thus, for ease of explanation, the phrases "above" or "below" are used for explanation, but for example, the up-down relationship between the substrate and the oxide semiconductor layer may be configured in a manner opposite to that shown in the figure. In the following description, for example, expressions such as the oxide semiconductor layer on the substrate are merely used to illustrate the up-down relationship between the substrate and the oxide semiconductor layer as described above, and other components may be configured between the substrate and the oxide semiconductor layer. Above or below means the stacking order in a structure in which a plurality of layers are stacked. It should be noted that viewing from above refers to observing from a direction perpendicular to the surface of the substrate.

[0055] In this specification and the like, the term "film" and the term "layer" can be used interchangeably depending on circumstances.

[0056] In this specification, etc., unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," or "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C. Furthermore, the above expressions do not exclude the case where α includes other elements.

[0057] It should be noted that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0058] <First embodiment>

[0059] use Figures 1 to 22 Semiconductor devices 10 to 10E according to an embodiment of the present invention will be described.

[0060] <Configuration of Semiconductor Device 10>

[0061] use Figures 1 to 3 Next, a configuration of a semiconductor device 10 according to an embodiment of the present invention will be described. Figure 1 It is a cross-sectional view schematically showing a semiconductor device 10 according to one embodiment of the present invention. Figure 2 It will Figure 1 An enlarged view of a portion of a semiconductor device is shown. Figure 3 1 is a top view showing an outline of a semiconductor device 10 according to an embodiment of the present invention. Figure 3 The cross section when cut by the single-dot chain line shown is the same as Figure 1 The cross-sectional views shown correspond to the following.

[0062] like Figure 1 As shown, the semiconductor device 10 is provided above the substrate 11. The semiconductor device 10 includes at least an oxide insulating film 14b, metal oxide layers 18-1 and 18-2, an oxide semiconductor layer 24, a gate insulating film 26, and a gate electrode 32GE. The oxide semiconductor layer 24, the gate insulating film 26, and the gate electrode 32GE are sometimes referred to as a transistor. The semiconductor device 10 may also include a gate electrode 12GE, a nitride insulating film 14a, an interlayer insulating film 34, a source electrode 36SE, and a drain electrode 36DE.

[0063] In this embodiment, a dual-gate transistor configuration is used as an example of the semiconductor device 10, in which gate electrodes are provided both above and below the oxide semiconductor layer. However, the present invention is not limited to this configuration. For example, a bottom-gate transistor in which the gate electrode is provided only below the oxide semiconductor layer, or a top-gate transistor in which the gate electrode is provided only above the oxide semiconductor layer, may also be used as the semiconductor device 10. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0064] The gate electrode 12GE functions as the bottom gate of the semiconductor device 10 and as a light-shielding film for the oxide semiconductor layer 24. The gate insulating film 14 functions as a gate insulating film for the bottom gate. Furthermore, the gate insulating film 14 includes a nitride insulating film 14a and an oxide insulating film 14b. The nitride insulating film 14a functions as a barrier film to block impurities diffusing from the substrate 11 toward the oxide semiconductor layer 24. Furthermore, the oxide insulating film 14b releases oxygen during heat treatment during the manufacturing process.

[0065] The metal oxide layer 18 has the function of suppressing the permeation of oxygen and hydrogen released from the adjacent insulating film. The metal oxide layer 18 is, for example, a layer including a metal oxide whose main component is aluminum. As long as the thickness of the metal oxide layer 18 is at least greater than 5 nm, the permeation of oxygen and hydrogen from the adjacent insulating film can be suppressed. The metal oxide layer 18 has a first region 19-1 and a second region 19-2 that are separated from each other. The first region 19-1 and the second region 19-2 refer to the regions of the metal oxide layer 18 that are in contact with the oxide semiconductor layer 24. Figures 1 to 3 In the embodiment, the metal oxide layer 18 includes a metal oxide layer 18 - 1 including a first region 19 - 1 and a metal oxide layer 18 - 2 including a second region 19 - 2 .

[0066] An oxide semiconductor layer 24 is provided on the oxide insulating film 14b and the metal oxide layers 18-1 and 18-2. The oxide semiconductor layer 24 is in contact with the oxide insulating film 14b, the first region 19-1, and the second region 19-2. The ends of the oxide semiconductor layer 24 are substantially aligned with the ends of the metal oxide layer 18-1 and the ends of the metal oxide layer 18-2. Figure 1 In the embodiment, the sidewalls of the metal oxide layer 18 and the sidewalls of the oxide semiconductor layer 24 are aligned in a straight line, but the present invention is not limited to this configuration. The angle of the sidewalls of the metal oxide layer 18 relative to the principal surface of the substrate 11 may be different from the angle of the sidewalls of the oxide semiconductor layer 24 relative to the principal surface of the substrate 11. The cross-sectional shape of the sidewalls of at least one of the metal oxide layer 18 and the oxide semiconductor layer 24 may be curved. The sidewalls of the metal oxide layer 18 and the sidewalls of the oxide semiconductor layer 24 may not be aligned in a straight line.

[0067] The oxide semiconductor layer 24 is light-transmissive. It has a polycrystalline structure consisting of multiple crystal grains. Poly-OS (Poly-crystalline Oxide Semiconductor) technology is used to form the oxide semiconductor layer 24, details of which will be described later. The following describes the composition of the oxide semiconductor layer 24, with the polycrystalline oxide semiconductor sometimes being referred to as Poly-OS.

[0068] The crystal grain size of the poly-OS particles observed from the top surface of the oxide semiconductor layer 24 (or in the thickness direction of the oxide semiconductor layer 24) or a cross-section of the oxide semiconductor layer 24 is 0.1 μm or larger, preferably 0.3 μm or larger, and more preferably 0.5 μm or larger. The crystal grain size can be determined, for example, using cross-sectional SEM observation, cross-sectional TEM observation, or electron backscattered diffraction (EBSD) analysis.

[0069] The oxide semiconductor layer 24 has a thickness greater than 10 nm and not greater than 30 nm. As described above, since the crystal grains contained in the Poly-OS have a grain size of 0.1 μm or greater, the oxide semiconductor layer 24 includes a region containing only one crystal grain in the thickness direction.

[0070] The oxide semiconductor layer 24 contains two or more metal elements including indium, and the ratio of indium in the two or more metal elements is 50% or more, which will be described in detail later. As metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) and lanthanides are used. As the oxide semiconductor layer 24, metal elements other than the above may also be used. Alternatively, as the oxide semiconductor layer 24, an oxide semiconductor such as indium gallium zinc oxide (IGZO) may also be used. The case of using IGZO as the oxide semiconductor layer 24 will be described in detail in the following modification examples.

[0071] The gate electrode 32GE functions as the top gate of the semiconductor device 10 and as a light shielding film for the oxide semiconductor layer 24. The gate insulating film 26 functions as a gate insulating film for the top gate and has the function of releasing oxygen through heat treatment during the manufacturing process. The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 32GE. An auxiliary voltage is supplied to the gate electrode 12GE. However, when the gate electrode 12GE is used only as a light shielding film, it is also possible to place the gate electrode 12GE in a floating state without supplying a specific voltage to the gate electrode 12GE. In this case, the gate electrode 12GE can also be simply referred to as a "light shielding film."

[0072] An interlayer insulating film 34 is provided over the gate insulating film 26 and the gate electrode 32GE. Contact holes CH2 and CH3 are provided in the interlayer insulating film 34, reaching the oxide semiconductor layer 24. A source electrode 36SE is provided inside the contact hole CH2, and the source electrode 36SE is in contact with the oxide semiconductor layer 24 at the bottom of the contact hole CH2. A drain electrode 36DE is provided inside the contact hole CH3, and is in contact with the oxide semiconductor layer 24 at the bottom of the contact hole CH3.

[0073] Furthermore, the gate wiring 12GL electrically connected to the gate electrode 12GE is connected to the gate wiring 32GL electrically connected to the gate electrode 32GE via the contact hole CH1 provided in the gate insulating films 14 and 26 .

[0074] In the semiconductor device 10, during the heat treatment process of the manufacturing process, the upper surface of the oxide semiconductor layer is affected by the process after the oxide semiconductor layer is formed (for example, a patterning process or an etching process). As a result, oxygen defects are generated on the surface of the oxide semiconductor layer. Electrons generated by hydrogen contained in the surrounding insulating film are easily captured by oxygen defects. Therefore, when electrons are captured by oxygen defects, the resistance of the oxide semiconductor layer becomes lower. If the resistance of the oxide semiconductor layer becomes uniformly lower, the resistance in the channel region will also decrease, and thus it will not be able to function as a transistor.

[0075] Even if oxygen vacancies are generated in the oxide semiconductor layer, as long as the oxygen vacancies can be repaired in the subsequent heat treatment, the resistance of the oxide semiconductor layer can be increased. For example, if the heat treatment is performed in a state where the oxide semiconductor layer is covered by an insulating film formed under conditions that contain more oxygen, oxygen is uniformly supplied to the oxide semiconductor layer. As a result, the oxygen vacancies in the oxide semiconductor layer are uniformly reduced. By repairing the oxygen vacancies in the channel region, the resistance can be increased. On the other hand, when the oxygen vacancies in the source and drain regions are repaired, the resistance increases in the same way as in the channel region, thereby reducing the on-current of the transistor.

[0076] Therefore, in a transistor using an oxide semiconductor layer, it is required to promote the repair of oxygen vacancies in the oxide semiconductor layer in the channel region and suppress the repair of oxygen vacancies in the oxide semiconductor in the source region and the drain region.

[0077] Therefore, in the semiconductor device 10 according to one embodiment of the present invention, a metal oxide layer 18 including a first region 19-1 and a second region 19-2 provided separately from each other is provided on the oxide insulating film 14b, and an oxide semiconductor layer 24 is provided on the oxide insulating film 14b and the metal oxide layer 18. A gate electrode 32GE is provided so as to cover a space between the first region 19-1 and the second region 19-2.

[0078] like Figure 2As shown, the oxide semiconductor layer 24 is divided into a first region 24a, a second region 24b, and a third region 24c. The first region 24a is a region of the oxide semiconductor layer 24 located vertically below the gate electrode 32GE and is a region that does not overlap with the metal oxide layer 18. The second region 24b is a region of the oxide semiconductor layer 24 that does not overlap with the gate electrode 32GE and is in contact with the metal oxide layer 18. The third region 24c is a region of the oxide semiconductor layer 24 located vertically below the gate electrode 32GE and is a region that overlaps with the metal oxide layers 18-1 and 18-2.

[0079] The thickness of the metal oxide layer 18 may be greater than 5 nm, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. By making the thickness of the metal oxide layer 18 at least greater than 5 nm, the migration of oxygen and hydrogen from the nearby insulating film can be suppressed.

[0080] The heat treatment allows oxygen to be supplied to the first region 24a from both the oxide insulating film 14b and the gate insulating film 26. This increases the resistance of the first region 24a, allowing it to function as a semiconductor. This allows the first region 24a to function as a channel region. The channel region is provided between the first region 19-1 and the second region 19-2 of the metal oxide layer 18.

[0081] The second region 24b and the third region 24c are regions that are in contact with the metal oxide layers 18-1 and 18-2. Oxygen is supplied from the gate insulating film 26 to the second region 24b and the third region 24c by heat treatment, but the movement of oxygen from the oxide insulating film 14b is suppressed by the metal oxide layers 18-1 and 18-2. Therefore, the resistance of the second region 24b and the third region 24c does not increase compared to the first region 24a. In addition, by adding impurity elements to the second region 24b after the heat treatment, oxygen vacancies are increased. By capturing electrons generated by hydrogen in the oxygen vacancies, the resistance of the second region 24b can be reduced. The second region 24b can function as a source region and a drain region. Since the third region 24c overlaps with the gate electrode 32GE, no impurity elements are added. Therefore, electrons generated by hydrogen are not easily captured by oxygen vacancies. As a result, the resistance of the third region 24c can be lower than that of the first region 24a and higher than that of the second region 24b. Therefore, the third region 24 c can function as an LDD (Lightly Doped Drain) region.

[0082] The concentration of the impurity element contained in the second region 24b is preferably 1×10 18 cm -3 Above 1×10 21 cm -3 Here, the impurity element refers to argon (Ar), phosphorus (P), or boron (B). In addition, the second region 24b contains 1×10 18 cm -3 Above 1×10 21 cm -3 In the following cases, it is presumed that the impurity element is intentionally added by ion implantation or doping. However, it is also possible to add less than 1×10 18 cm -3 The concentration of impurity elements other than argon (Ar), phosphorus (P) or boron (B) is included.

[0083] like Figure 3 As shown, when viewed from above, the gate wiring 12GL and the gate wiring 32GL extend in the D1 direction, and the gate electrode 12GE and the gate electrode 32GE extend in the D2 direction. In addition, the source wiring SL extends in the D2 direction. The top view pattern of the metal oxide layers 18-1 and 18-2 overlaps with the top view pattern of the oxide semiconductor layer 24. In the D1 direction, the width of the gate electrode 12GE is larger than the width of the gate electrode 32GE. In addition, the width of the gate electrode 12GE and the width of the gate electrode 32GE in the D1 direction are larger than the length between the metal oxide layer 18-1 and the metal oxide layer 18-2. Here, the length between the metal oxide layer 18-1 and the metal oxide layer 18-2 is consistent with the length of the first region 24a. Figure 3 , the D1 direction is the direction connecting the source electrode SE and the drain electrode DE, and is the direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of the first region 24a (channel region) where the oxide semiconductor layer 24 overlaps with the gate electrode 32GE is the channel length L, and the length in the D2 direction of the first region 24a is the channel width W.

[0084] In the semiconductor device 10, the resistance can be increased by sufficiently supplying oxygen to the first region 24a of the oxide semiconductor layer 24, which forms the channel region. Meanwhile, the resistance can be reduced by suppressing the supply of oxygen to the second region 24b of the oxide semiconductor layer 24, which forms the source and drain regions of the transistor. This allows the resistance of the channel region, as well as the resistance of the source and drain regions, in the semiconductor device 10 to be appropriately controlled. Consequently, good reliability test results for the semiconductor device 10 can be obtained, and the on-current can be increased.

[0085] Here, the reliability test refers to, for example, an NGBT (Negative Gate Bias-Temperature) stress test in which a negative voltage is applied to the gate, or a PGBT (Positive Gate Bias-Temperature) stress test in which a positive voltage is applied to the gate. It should be noted that BT stress tests such as NGBT and PGBT are a type of accelerated test that can evaluate the characteristic changes (year-on-year changes) of transistors caused by long-term use in a short period of time. In particular, the change in the threshold voltage of the transistor before and after the BT stress test has become an important indicator for studying reliability. It can be said that the smaller the change in the threshold voltage before and after the BT stress test, the more reliable the transistor.

[0086] In the semiconductor device 10 manufactured by the above-mentioned manufacturing method, a mobility of 30 cm-2 can be obtained when the channel length L of the channel region is 2 μm to 4 μm and the channel width of the channel region is 2 μm to 25 μm. 2 / Vs or above, 35cm 2 / Vs or above or 40cm 2 / Vs or above. The mobility in this specification and other documents refers to the field-effect mobility in the saturation region of the semiconductor device 10, and means the maximum value of the field-effect mobility in the region where the potential difference (Vd) between the source electrode and the drain electrode is greater than the value (Vg-Vth) obtained by subtracting the threshold voltage (Vth) of the semiconductor device 10 from the voltage (Vg) supplied to the gate electrode.

[0087] <Method of Manufacturing Semiconductor Device 10>

[0088] use Figures 4 to 10 A method for manufacturing the semiconductor device 10 according to one embodiment of the present invention will be described. Figure 4 It is a sequence diagram showing a method for manufacturing the semiconductor device 10 according to one embodiment of the present invention. Figures 5 to 10 1 is a cross-sectional view illustrating a method for manufacturing the semiconductor device 10 according to an embodiment of the present invention.

[0089] like Figure 4 and Figure 5 As shown, a gate electrode 12GE is formed on the substrate 11, and a gate insulating film 14 is formed on the gate electrode 12GE (see FIG. Figure 4 Steps S1001 "GE formation" and S1002 "GI formation" are shown).

[0090] As the substrate 11, a glass substrate, a quartz substrate, a sapphire substrate, or other light-transmitting rigid substrate can be used. When the substrate 11 is required to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, can be used as the substrate 11. When a substrate containing a resin is used as the substrate 11, impurity elements can be introduced into the resin to improve the heat resistance of the substrate 11. When the semiconductor device 10 is used as an integrated circuit, a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, which is not light-transmitting, can be used as the substrate 11.

[0091] The gate electrode 12GE is formed by processing a conductive film formed by sputtering. A common metal material is used for the gate electrode 12GE. Examples of the gate electrode 12GE include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The gate electrode 12GE can be made of any of the above materials in a single layer or in a stacked form.

[0092] The gate insulating film 14 is formed by CVD (Chemical Vapor Deposition) or sputtering. As the gate insulating film 14, a common insulating material is used. As the gate insulating film 14, for example, silicon oxide (SiO x ), silicon oxide nitride (SiO x N y ), silicon nitride (SiN x ), silicon oxide nitride (SiN x O y ) and other inorganic insulating materials are used in a single layer or in a stacked manner. x N y It is a silicon compound containing nitrogen (N) at a ratio (x>y) less than oxygen (O). SiN x O y It is a silicon compound containing oxygen at a ratio smaller than nitrogen (x>y).

[0093] In this embodiment, a nitride insulating film 14a and an oxide insulating film 14b are used as the gate insulating film 14. The nitride insulating film 14a is formed using, for example, silicon nitride. By using silicon nitride, it is possible to block impurities that diffuse from the substrate 11 side toward the oxide semiconductor layer 24. In addition, the oxide insulating film 14b is formed using, for example, silicon oxide. By using silicon oxide, oxygen can be released by heat treatment. The temperature of the heat treatment for causing the insulating material containing oxygen to release oxygen is, for example, below 500°C, below 450°C, or below 400°C. That is, silicon oxide releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 10 when, for example, a glass substrate is used as the substrate 11.

[0094] like Figure 4 and Figure 5 As shown, a metal oxide film 17 ( Figure 4 (Step S1003 “MO film formation” shown in FIG. 1 ) The metal oxide film 17 is formed by sputtering or atomic layer deposition (ALD).

[0095] As the metal oxide film 17, for example, a metal oxide containing aluminum as a main component is used. For example, as the metal oxide film 17, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum nitride (AlN x O y ), aluminum nitride (AlN x ) or other inorganic insulating films. A metal oxide film with aluminum as the main component means that the ratio of aluminum contained in the metal oxide film is more than 1% of the entire metal oxide film 17. The ratio of aluminum contained in the metal oxide film 17 may also be more than 5% and less than 70% of the entire metal oxide film 17, more than 10% and less than 60%, or more than 30% and less than 50%. The above ratios may be mass ratios or weight ratios. Alternatively, an oxide semiconductor such as indium gallium zinc oxide (IGZO) may be used as the metal oxide film 17. The case of using IGZO as the metal oxide film 17 will be described in detail in the subsequent modification examples.

[0096] The thickness of the metal oxide film 17 may be, for example, greater than 5 nm, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. In this embodiment, the case of using aluminum oxide as the metal oxide film 17 is described. Aluminum oxide has a high barrier property against gases such as oxygen and hydrogen. In other words, barrier property refers to the function of inhibiting gases such as oxygen and hydrogen from passing through aluminum oxide. As long as the thickness of the metal oxide film 17 is greater than 5 nm, it has the following effect: even if gases such as oxygen and hydrogen exist in the layer provided below the aluminum oxide film, the gases will not move to the layer provided above the aluminum oxide film. Alternatively, it has the following effect: even if gases such as oxygen and hydrogen exist in the layer provided above the aluminum oxide film, the gases will not move to the layer provided below the aluminum oxide film. On the other hand, when the thickness of the metal oxide film 17 is less than 5 nm, gases such as oxygen and hydrogen may sometimes pass through. In this embodiment, aluminum oxide used as the metal oxide film 17 blocks hydrogen and oxygen released from the oxide insulating film 14 b and prevents the released hydrogen and oxygen from reaching the oxide semiconductor layer formed thereafter.

[0097] like Figure 4 and Figure 5 As shown, an opening OP1 is formed in the metal oxide film 17 ( Figure 4 Step S1004 "MO pattern formation" is shown). The opening OP1 provided in the metal oxide film 17 is formed in a region overlapping with the gate electrode 12GE. Although not shown in the figure, the opening OP1 is formed in a manner parallel to the direction in which the gate electrode 12GE extends. The opening OP1 can be formed, for example, by wet etching using hydrofluoric acid. In the semiconductor device 10, the width W2 of the opening OP1 (the length in the D1 direction) is smaller than the width W1 of the gate electrode 12GE. In addition, the width W2 of the opening OP1 (the length in the D1 direction) is equivalent to the channel length L of the channel region to be formed later. In addition, the length of the opening OP1 (the length in the D2 direction) is preferably longer than the width (the length in the D2 direction) of the oxide semiconductor layer 24 to be formed later.

[0098] Then, if Figure 4 and Figure 5 As shown, an oxide semiconductor film 21 is formed on the metal oxide film 17 ( Figure 4 The oxide semiconductor film 21 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 21 is, for example, greater than 10 nm and less than 30 nm.

[0099] As the oxide semiconductor film 21, a metal oxide having semiconductor properties can be used. As the oxide semiconductor film 21, for example, an oxide semiconductor containing two or more metal elements including indium (In) is used. In addition, the ratio of indium in the two or more metal elements contained in the oxide semiconductor is 50% or more. As the oxide semiconductor film 21, in addition to the indium element, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) or lanthanide elements are used. As the oxide semiconductor film 21, elements other than the above may also be used. Alternatively, as the oxide semiconductor film 21 (oxide semiconductor layer 24), an oxide semiconductor such as indium gallium zinc oxide (IGZO) may also be used. The case of using IGZO as the oxide semiconductor film 21 will be described in detail in the subsequent modification examples.

[0100] When using an oxide semiconductor film 21 containing two or more metal elements with an indium ratio of 50% or more, the oxide semiconductor film 21 is preferably amorphous (a state with a low crystalline component of the oxide semiconductor) after film formation and before OS annealing. Specifically, the oxide semiconductor film 21 is preferably formed under conditions that minimize crystallization of the oxide semiconductor film 21 immediately after film formation. For example, when forming the oxide semiconductor film 21 by sputtering, the oxide semiconductor film 21 is formed while controlling the temperature of the object to be formed (the substrate 11 and the structures formed thereon).

[0101] When a film is formed on an object to be formed by sputtering, the ions generated in the plasma and the atoms ejected by the sputtering target collide with the object to be formed, so that the temperature of the object to be formed rises as the film forming process progresses. If the temperature of the object to be formed rises during the film forming process, the oxide semiconductor film 21 will contain microcrystals in the state just after the film is formed. If microcrystals are contained in the oxide semiconductor film 21, the crystal grain size cannot be increased by subsequent OS annealing. In order to control the temperature of the object to be formed as described above, for example, the film can be formed while the object to be formed is cooled. For example, the object to be formed can be cooled from the surface opposite to the film forming surface in such a manner that the temperature of the film forming surface of the object to be formed (hereinafter referred to as the "film forming temperature") is below 100°C, below 70°C, below 50°C or below 30°C. In particular, the film forming temperature of the oxide semiconductor film 21 of this embodiment is preferably below 50°C. By forming the oxide semiconductor film 21 while cooling the substrate, it is possible to obtain an oxide semiconductor film 21 with a low crystalline content immediately after film formation. In this embodiment, the oxide semiconductor film 21 is formed at a film formation temperature of 50°C or less, and the OS annealing described later is performed at a heating temperature of 400°C or higher. Thus, in this embodiment, the difference between the temperature when forming the oxide semiconductor film 21 and the temperature when performing the OS annealing on the oxide semiconductor film 21 is preferably 350°C or higher.

[0102] In the sputtering process, the amorphous oxide semiconductor film 21 is formed under an oxygen partial pressure of 10% or less. If the oxygen partial pressure is high, the oxide semiconductor film 21 immediately after formation may contain microcrystals due to the excess oxygen contained in the oxide semiconductor film 21. Therefore, it is preferable to form the oxide semiconductor film 21 under conditions of low oxygen partial pressure. The oxygen partial pressure is, for example, 3% to 5%, preferably 3% to 4%. It should be noted that when the oxide semiconductor film is formed under an oxygen partial pressure of 2%, the oxide semiconductor film will not crystallize even if an OS annealing process is subsequently performed.

[0103] like Figure 4 and Figure 6 As shown, the pattern of the oxide semiconductor layer 22 is formed ( Figure 4 (See step S1006 ("OS pattern formation") above the oxide semiconductor film 21. A resist mask 23 is formed over the oxide semiconductor film 21, and the oxide semiconductor film 21 is etched using the resist mask 23. The oxide semiconductor film 21 can be etched using either wet or dry etching. Wet etching can be performed using an acidic etchant. For example, oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid can be used as the etchant. Thus, a patterned oxide semiconductor layer 22 can be formed. The resist mask 23 is then removed.

[0104] The oxide semiconductor film 21 is preferably patterned before OS annealing. Crystallization of the oxide semiconductor film 21 by OS annealing tends to make etching difficult. Even if the patterned oxide semiconductor layer 22 is damaged by etching, this is preferable because the damage to the oxide semiconductor layer 22 can be repaired by the subsequent OS annealing in step S1007.

[0105] like Figure 4 and Figure 7 As shown, after the patterning of the oxide semiconductor layer 22, the oxide semiconductor layer 22 is subjected to heat treatment (OS annealing) ( Figure 4 (See step S1007 "OS annealing" shown in the figure.) During the OS annealing, the oxide semiconductor layer 22 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is between 300°C and 500°C, preferably between 350°C and 450°C. The hold time at the target temperature is between 15 minutes and 120 minutes, preferably between 30 minutes and 60 minutes. The OS annealing crystallizes the oxide semiconductor layer 22, forming an oxide semiconductor layer 24 having a polycrystalline structure.

[0106] In this embodiment, when the oxide semiconductor film 21 is formed by sputtering, it is formed under a low oxygen partial pressure of 3% to 5%. By forming the oxide semiconductor film 21 under low oxygen partial pressure conditions, it is possible to suppress excessive oxygen inclusion in the oxide semiconductor film 21 and to suppress the inclusion of microcrystals in the oxide semiconductor film 21 immediately after formation. This can suppress the growth of crystals from the microcrystals during the heat treatment of the oxide semiconductor layer 22. Therefore, even when the oxide semiconductor film 21 is formed with a thin film thickness of greater than 10 nm and less than 30 nm, the crystal grain size of the polycrystalline structure of the oxide semiconductor layer 22 can be increased.

[0107] like Figure 4 and Figure 8 As shown, the metal oxide film 17 is patterned to form a metal oxide layer 18-1 having a first region 19-1 and a metal oxide layer 18-2 having a second region 19-2 ( Figure 4Step S1008 "MO pattern formation" shown). The oxide semiconductor layer 24 that has been fully crystallized by heat treatment has high etching resistance. Therefore, when the metal oxide film 17 is patterned using the crystallized oxide semiconductor layer 24 as a mask, the oxide semiconductor layer 24 can be suppressed from disappearing. The metal oxide film 17 is etched using the oxide semiconductor layer 24 that has been polycrystallized in the above-mentioned process as a mask. As a result, the side walls of the metal oxide layer 18-1 and the side walls of the metal oxide layer 18-2 are arranged in a straight line with the side walls of the oxide semiconductor layer 24. As the etching of the metal oxide film 17, wet etching or dry etching can be used. As wet etching, for example, diluted hydrofluoric acid (DHF) is used. By etching the metal oxide film 17 using the oxide semiconductor layer 24 as a mask, the photolithography process can be omitted. In this embodiment, as Figure 3 As shown, the length of the opening OP1 formed in the metal oxide film 17 in the direction D2 is longer than the channel width W of the oxide semiconductor layer. By etching the metal oxide film 17 in this state, the metal oxide film 17 can be separated into the metal oxide layer 18-1 including the first region 19-1 and the metal oxide layer 18-2 including the second region 19-2.

[0108] like Figure 4 and Figure 9 As shown, a gate insulating film 26 is formed on the oxide semiconductor layer 24 ( Figure 4 The gate insulating film 26 may have a thickness of, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm.

[0109] As the gate insulating film 26, an insulating material containing oxygen is preferably used. In addition, as the gate insulating film 26, an insulating film with fewer defects is preferably used. For example, when the composition ratio of oxygen in the gate insulating film 26 is compared with the composition ratio of oxygen in an insulating film having the same composition as the gate insulating film 26 (hereinafter referred to as "other insulating film"), the composition ratio of oxygen in the gate insulating film 26 is closer to the stoichiometric ratio of the insulating film than the composition ratio of oxygen in the other insulating film. For example, silicon oxide (SiO x ), the oxygen composition ratio of the silicon oxide used as the gate insulating film 26 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio of the silicon oxide used as the interlayer insulating film 34. For example, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used as the gate insulating film 26.

[0110] To form an insulating film with few defects, the gate insulating film 26 may be formed at a film formation temperature of 350°C or higher. Alternatively, after forming the gate insulating film 26, a process of implanting oxygen into a portion of the gate insulating film 26 may be performed. In this embodiment, silicon oxide is formed at a film formation temperature of 350°C or higher to form an insulating film with few defects.

[0111] like Figure 4 and Figure 9 As shown, a metal oxide film 28 is formed on the gate insulating film 26 ( Figure 4 (See step S1010 "MO film formation" shown in the figure). Regarding the materials and film formation method of the metal oxide film 28, refer to the materials and film formation method described for the metal oxide film 17. Furthermore, the film thickness of the metal oxide film 28 may be greater than 5 nm, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm.

[0112] like Figure 4 and Figure 9 As shown, with the gate insulating film 26 and the metal oxide film 28 formed on the oxide semiconductor layer 24, a heat treatment (oxidation annealing) for supplying oxygen to the oxide semiconductor layer 24 is performed ( Figure 4 Step S1011 “oxidation annealing” shown).

[0113] In this embodiment, an oxide semiconductor containing two or more metals including indium (In), with the ratio of indium in the two or more metals being 50% or greater, is used as the oxide semiconductor layer 24. Oxide semiconductors with a high indium ratio tend to crystallize easily, but oxygen contained in the oxide semiconductor layer is easily reduced, and oxygen vacancies tend to form.

[0114] The upper surface of the oxide semiconductor layer 22 is affected by subsequent steps (e.g., patterning or etching) after the oxide semiconductor layer 22 is formed. On the other hand, the lower surface of the oxide semiconductor layer 22 (the surface of the oxide semiconductor layer 22 facing the substrate 11) is less susceptible to such influences.

[0115] Therefore, the number of oxygen vacancies formed on the upper surface of the oxide semiconductor layer 22 is greater than the number of oxygen vacancies formed on the lower surface of the oxide semiconductor layer 22. In other words, the oxygen vacancies in the oxide semiconductor layer 22 are not uniformly distributed in the thickness direction of the oxide semiconductor layer 22, but are unevenly distributed in the thickness direction of the oxide semiconductor layer 22. Specifically, the number of oxygen vacancies in the oxide semiconductor layer 22 decreases toward the lower surface of the oxide semiconductor layer 22 and increases toward the upper surface of the oxide semiconductor layer 22.

[0116] When oxygen is uniformly supplied to the oxide semiconductor layer 22 having the above-described distribution of oxygen vacancies, if oxygen is supplied in an amount necessary to repair the oxygen vacancies formed on the upper surface of the oxide semiconductor layer 22, an excessive amount of oxygen will be supplied to the lower surface of the oxide semiconductor layer 22. As a result, defect energy levels different from those of the oxygen vacancies are formed on the lower surface due to the excessive oxygen, resulting in variations in characteristics during reliability testing or a decrease in field-effect mobility. Therefore, to suppress such phenomena, it is necessary to supply oxygen to the upper surface of the oxide semiconductor layer 22 while suppressing oxygen supply to the lower surface.

[0117] Furthermore, as described above, it is more preferable to repair oxygen vacancies in the channel region of the transistor rather than in the source region and the drain region.

[0118] The oxygen released from the gate insulating film 26 and the oxide insulating film 14b by the oxidation annealing is blocked by the metal oxide film 28. As a result, the oxygen released from the gate insulating film 26 and the oxide insulating film 14b is supplied to the upper surface and side surfaces of the oxide semiconductor layer 24. As a result, the oxygen defects in the upper surface and side surfaces of the oxide semiconductor layer 24 are reduced. In addition, although the oxygen released from the oxide insulating film 14b is blocked by the metal oxide layers 18-1 and 18-2, it is supplied to the first region 24a of the oxide semiconductor layer 24 that is in contact with the oxide insulating film 14b. As a result, the oxygen defects in the first region 24a of the oxide semiconductor layer 24 that is in contact with the oxide insulating film 14b are reduced. In addition, in the lower surface of the oxide semiconductor layer 24, there are regions where the supply of oxygen is suppressed and regions where oxygen is supplied. In this way, by providing metal oxide layers 18-1 and 18-2 separated from each other under the oxide semiconductor layer 24, it is possible to control the region where the oxygen defects are repaired. After the oxidation annealing, the metal oxide film 28 ( Figure 4 (Step S1012 "MO removal" shown in the figure) When the gate wiring 32GL formed in the next step is to be connected to the gate wiring 12GL, at this point in time, a contact hole CH1 is formed in the gate insulating films 14 and 16.

[0119] Then, if Figure 4 and Figure 10 As shown, a gate electrode 32GE ( Figure 4 Step S1013 "GE formation" shown).

[0120] The gate electrode 32GE is formed by processing a conductive film formed by sputtering. As with the gate electrode 12GE, a conventional metal material is used for the gate electrode 32GE. For materials that can be used for the gate electrode 32GE, refer to the description of the materials for the gate electrode 12GE. The above-mentioned materials can be used as a single layer or as a stacked layer for the gate electrode 32GE.

[0121] Then, if Figure 4 and Figure 10 As shown, the gate electrode 32GE is used as a mask to add an impurity element ( Figure 4 In step S1014 (“Impurity Addition (SD Region Formation)”), in this embodiment, the case where the impurity element is added by ion implantation is described, but it may also be added by ion doping.

[0122] Specifically, an impurity element is added to the second region 24b of the oxide semiconductor layer 24 through the gate insulating film 26 by ion implantation. As the impurity element, argon (Ar), phosphorus (P), or boron (B) can be used, for example. When boron (B) is added by ion implantation, the acceleration energy is set to 20 keV or more and 40 keV or less, and the implantation amount of boron (B) is set to 1×10 14 cm -2 Above 1×10 16 cm -2 The following will do.

[0123] Impurity elements can be removed at a rate of 1×10 18 cm -3 Above 1×10 21 cm -3 The following concentrations are added to the second region 24b. At this point, the oxide semiconductor in the second region 24b forms oxygen vacancies due to the addition of the impurity element. These oxygen vacancies easily capture electrons. This reduces the resistance of the second region 24b, allowing it to function as a conductor.

[0124] Since the first region 24a and the third region 24c of the oxide semiconductor layer 24 overlap with the gate electrode 32GE, no impurity elements are added. In addition, the first region 24a is supplied with oxygen from both the oxide insulating film 14b and the gate insulating film 26 by oxidation annealing. As a result, the resistance of the first region 24a can be increased, so that it can function as a semiconductor. Although the third region 24c is supplied with oxygen from the gate insulating film 26 by oxidation annealing, the oxygen from the oxide insulating film 14b is blocked by the metal oxide layers 18-1 and 18-2. As a result, the resistance of the third region 24c can be lower than that of the first region 24a and higher than that of the third region 24c. Therefore, the third region 24c can function as an LDD region.

[0125] For example, when IGZO is used as the oxide semiconductor layer 24, due to the high resistance of the oxide semiconductor, the resistance of the source and drain regions cannot be sufficiently reduced without increasing the film thickness. In contrast, in the oxide semiconductor layer 24 having a polycrystalline structure, even with a small film thickness, the sheet resistance can be reduced by adding impurity elements to the second region 24b. In this embodiment, the sheet resistance of the second region 24b can be set to 1000Ω / sq. or less, preferably 500Ω / sq. or less, and more preferably 250Ω / sq. or less.

[0126] like Figure 4 As shown, an interlayer insulating film 34 ( Figure 4 Step S1015 "interlayer film formation" shown).

[0127] The film formation method and insulating material of the interlayer insulating film 34 can be referred to the description of the material of the gate insulating film 14. The film thickness of the interlayer insulating film 34 is not less than 50 nm and not more than 500 nm. The film thickness of the interlayer insulating film 34 is not less than 50 nm and not more than 500 nm. In this embodiment, the interlayer insulating film 34 is formed by stacking silicon oxide and silicon nitride, for example.

[0128] Next, contact holes CH2 and CH3 are formed in the gate insulating film 26 and the interlayer insulating film 34 ( Figure 4 (Step S1016 “Contact hole formation” shown in FIG. 1 ) The second region 24 b of the oxide semiconductor layer 24 is exposed through the contact holes CH2 and CH3 .

[0129] Finally, a source electrode 36SE and a drain electrode 36DE are formed on the oxide semiconductor layer 24 exposed through the contact hole and on the interlayer insulating film 34 ( Figure 4 Step S1017 "SD formation" shown in FIG. Figure 1 The semiconductor device 10 is shown.

[0130] The source electrode 36SE and the drain electrode 36DE are formed, for example, by processing a conductive film formed by sputtering. As with the gate electrode 12GE, a conventional metal material is used for the source electrode 36SE and the drain electrode 36DE. For materials that can be used for the source electrode 36SE and the drain electrode 36DE, refer to the description of the gate electrode 12GE. The above-mentioned materials can be used as single layers or as a stacked layer.

[0131] Through the above process, it is possible to produce Figure 1 The semiconductor device 10 is shown.

[0132] Modification

[0133] Next, refer to Figures 11 to 22 Semiconductor devices 10A to 10E are described, which have partially different structures from semiconductor device 10. Semiconductor devices 10A to 10E are described using Poly-OS as oxide semiconductor layer 24 and aluminum oxide as metal oxide film 17 and metal oxide layer 18 unless otherwise specified.

[0134] Figure 11 This is a semiconductor device 10A according to one embodiment of the present invention. Figure 12 It will Figure 11 FIG. 1 is an enlarged view showing a portion of the semiconductor device 10A. Figure 11 The semiconductor device 10A shown has a structure in which the gate electrode 32GE does not overlap with the first region 19-1 and the second region 19-2. In other words, the gate electrode 32GE is provided between the metal oxide layer 18-1 and the metal oxide layer 18-2 that are separated from each other. Figure 11 The manufacturing method of the semiconductor device 10A shown is similar to that of the semiconductor device 10 , and thus will be described with reference thereto as appropriate.

[0135] exist Figure 11 In the embodiment, the width of the gate electrode 12GE in the direction D1 is longer than the lengths of the metal oxide layer 18 - 1 and the metal oxide layer 18 - 2 , and the width of the gate electrode 32GE is shorter than the lengths of the metal oxide layer 18 - 1 and the metal oxide layer 18 - 2 .

[0136] When manufacturing the semiconductor device 10A, Figure 4In step S1011 shown in FIG. 1 , oxygen is supplied to the oxide semiconductor layer 24 in contact with the oxide insulating film 14b from both the oxide insulating film 14b and the gate insulating film 26, thereby reducing oxygen vacancies. In addition, although oxygen is supplied to the oxide semiconductor layer 24 in contact with the metal oxide layers 18-1 and 18-2 from the gate insulating film 26, oxygen supply from the oxide insulating film 14b is suppressed, thereby suppressing the repair of oxygen vacancies. Figure 4 After steps S1012 and S1013 shown in the figure, in step S1014 , an impurity element is added to the oxide semiconductor layer 24 using the gate electrode 32GE as a mask.

[0137] The region of the oxide semiconductor layer 24 that overlaps with the gate electrode 32GE is not doped with impurity elements because it overlaps with the gate electrode 32GE. Oxygen vacancies in this region are repaired through oxidation annealing, and no impurity elements are subsequently added. This allows this region to function as a semiconductor and as a channel region (first region 24a). In the region of the oxide semiconductor layer 24 that does not overlap with the gate electrode 32GE but still overlaps with the metal oxide layers 18-1 and 18-2, oxygen repair through oxidation annealing is suppressed, and impurity elements are added. This allows this region to function as a conductor and as a source and drain region (second region 24b). Furthermore, in the region of the oxide semiconductor layer 24 that does not overlap with the gate electrode 32GE and does not overlap with the metal oxide layers 18-1 and 18-2, oxygen vacancies are repaired through oxidation annealing, and impurity elements are added. Therefore, the resistance of this region can be made higher than that of the second region 24b and lower than that of the first region 24a. This allows this region to function as an LDD region. The region functioning as the LDD region is referred to as a third region 24c.

[0138] <Variant 2>

[0139] Figure 13 This is a semiconductor device 10B according to one embodiment of the present invention. The gate insulating film 26 in the semiconductor device 10B is removed except for the portion below the gate electrode 32GE and the portion below the gate wiring 32GL. That is, the second region 24b of the oxide semiconductor layer 24 is exposed. Figure 13 The manufacturing method of the semiconductor device 10B shown is similar to that of the semiconductor device 10 , and thus will be described with reference thereto as appropriate.

[0140] When manufacturing the semiconductor device 10B, Figure 4In step S1013 shown in FIG. 1 , after etching to form the gate electrode 32GE and the gate wiring 32GL, the gate insulating film 26 can be further removed by etching. The oxide semiconductor layer 24 having a crystalline structure has the characteristic of being difficult to etch, so it can be suppressed from disappearing due to etching. In addition, oxygen vacancies are formed in the surface of the oxide semiconductor layer 24 exposed by etching. Figure 4 In step S1015 shown, electrons generated from hydrogen contained in the interlayer insulating film 34 are easily captured in the oxygen vacancies. Therefore, the resistance of the second region 24b can be reduced.

[0141] <Variant 3>

[0142] Figure 14 This is a semiconductor device 10C according to one embodiment of the present invention. Figure 15 1 is a top view showing an overview of a semiconductor device 10C according to an embodiment of the present invention. The semiconductor device 10C has an opening OP1 provided in the metal oxide film 17. The metal oxide film 17 has an opening OP1 between the first region 19-1 and the second region 19-2. In addition, an opening OP2 is provided in the region of the metal oxide film 17 where the gate wiring 12GL and the gate wiring 32GL are connected. In the metal oxide film 17, the region in contact with the second region 24b of the oxide semiconductor layer 24 corresponds to the first region 19-1 and the second region 19-2. It should be noted that Figure 14 The manufacturing method of the semiconductor device 10C shown is similar to the manufacturing method of the semiconductor device 10 , and thus will be described with reference thereto as appropriate.

[0143] When manufacturing the semiconductor device 10C, Figure 4 In step S1004 shown in FIG. 1 , not only the opening OP1 is formed in the region overlapping the gate electrode 12GE, but also the opening OP2 is formed in the region overlapping the gate wiring 12GL. The openings OP1 and OP2 can be formed by, for example, wet etching using hydrofluoric acid. In the semiconductor device 10C, the metal oxide film 17 is provided in a film-like manner on the entire surface of the substrate 11. Therefore, the metal oxide film 17 is omitted. Figure 4 The metal oxide film 17 is patterned in step S1008 shown in FIG. Since the metal oxide film 17 is not easily etched, it is difficult to form a contact hole in the same process as the nitride insulating film 14a, the oxide insulating film 14b, and the gate insulating film 26. Figure 4 In step S1004 shown, the opening OP2 is formed in advance, thereby facilitating the formation of the contact hole CH1 in the nitride insulating film 14 a , the oxide insulating film 14 b , and the gate insulating film 26 in subsequent steps.

[0144] When manufacturing the semiconductor device 10C, Figure 4 In step S1011 shown, oxidation annealing is performed while the metal oxide film 17 and the gate insulating film 26 are in contact with each other. Figure 16 17 is a diagram illustrating the oxidation annealing process in manufacturing the semiconductor device 10C. As a result, oxygen released from the oxide insulating film 14b is blocked by the metal oxide film 17, but is supplied to the region of the oxide semiconductor layer 24 in contact with the oxide insulating film 14b. Figure 16 In the embodiment, since the metal oxide film 17 is provided in a film-like manner over the entire surface of the substrate 11, the oxide insulating film 14b is substantially in contact with the gate insulating film 26. Therefore, the oxygen released from the oxide insulating film 14b during the oxidation annealing can be suppressed from migrating to the gate insulating film 26. This suppresses the supply of oxygen to the second region 24b of the oxide semiconductor layer 24. Furthermore, since oxygen is concentratedly supplied to the first region 24a of the oxide semiconductor layer 24, oxygen vacancies in the first region 24a can be repaired.

[0145] <Variant 4>

[0146] Figure 17 This is a semiconductor device 10D according to an embodiment of the present invention. The semiconductor device 10D has the same structure as the semiconductor device 10C except that the gate insulating film 26 is removed except for the portion below the gate electrode 32GE and the portion below the gate wiring 32GL. That is, the second region 24b of the oxide semiconductor layer 24 is exposed. Figure 17 The manufacturing method of the semiconductor device 10D shown is similar to the manufacturing method of the semiconductor device 10C, and thus will be described with reference thereto as appropriate.

[0147] When manufacturing the semiconductor device 10D, Figure 4 In step S1013 shown in FIG. 1 , after etching to form the gate electrode 32GE and the gate wiring 32GL, the gate insulating film 26 can be further removed by etching. The oxide semiconductor layer 24 having a crystalline structure has the characteristic of being difficult to etch, so it can be suppressed from disappearing due to etching. In addition, oxygen defects are formed on the surface of the oxide semiconductor layer 24 due to etching. Figure 4 In step S1015 shown, electrons generated from hydrogen contained in the interlayer insulating film 34 are easily captured in the oxygen vacancies. Therefore, the resistance of the second region 24b can be reduced.

[0148] <Variant 5>

[0149] Figure 18 This is a semiconductor device 10E according to one embodiment of the present invention. Figure 19 It will Figure 11 FIG. 1 is an enlarged view of a portion of the semiconductor device 10E. Figure 18 In the semiconductor device 10E shown, an oxide semiconductor is used as the metal oxide layers 18-1 and 18-2 instead of aluminum oxide. In the semiconductor device 10E, oxide semiconductor layers 44-1 and 44-2 are described to distinguish them from the metal oxide layers 18-1 and 18-2 using aluminum oxide. Oxide semiconductor layers 44-1 and 44-2 are sometimes referred to as oxide semiconductor layers 44.

[0150] The oxide semiconductor layers 44-1 and 44-2 have the function of suppressing the permeation of oxygen and hydrogen released from the adjacent insulating film. As the oxide semiconductor layers 44-1 and 44-2, metal oxides having semiconductor properties can be used. As the oxide semiconductor layers 44-1 and 44-2, oxide semiconductors containing two or more metal elements including indium (In) are used. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr) or lanthanide elements are used as the oxide semiconductor layers 44-1 and 44-2. Elements other than the above may also be used as the oxide semiconductor layers 44-1 and 44-2. In this modification, the case of using indium gallium zinc oxide (IGZO) as the oxide semiconductor layers 44-1 and 44-2 and using Poly-OS as the oxide semiconductor layer 24 is described. In this case, the content of indium contained in the oxide semiconductor layer 24 is greater than the content of indium contained in the oxide semiconductor layers 44-1 and 44-2. As described above, in the semiconductor device 10E, the oxide semiconductor layer 24 and the oxide semiconductor layers 44 - 1 and 44 - 2 may be made of different oxide semiconductor materials.

[0151] The film thickness of the oxide semiconductor layers 44-1 and 44-2 is, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. If the film thickness of the oxide semiconductor layers 44-1 and 44-2 is at least greater than 5 nm, the permeation of oxygen and hydrogen from the adjacent insulating film can be suppressed. The oxide semiconductor layer 44 has a first region 19-1 and a second region 19-2 that are separated from each other. That is, the first region 19-1 and the second region 19-2 refer to the regions of the oxide semiconductor layer 44 that are in contact with the oxide semiconductor layer 24. In Figure 18 In the embodiment, the oxide semiconductor layer 44 includes an oxide semiconductor layer 44-1 including a first region 19-1 and a metal oxide layer 18-2 including a second region 19-2.

[0152] The oxide semiconductor layers 44-1 and 44-2 block oxygen released from the oxide insulating film 14b and also function as semiconductor layers of the semiconductor device 10E. Therefore, the oxide semiconductor layer 24 and the oxide semiconductor layers 44-1 and 44-2 can also be regarded as a single semiconductor layer. In this case, the film thickness t of the first region 24a (channel region) is ch The thickness of the second region 24b (source region and drain region) is only the thickness of the oxide semiconductor layer 24. SD The thickness of the oxide semiconductor layer 24 and the oxide semiconductor layer 44-1 or the thickness of the oxide semiconductor layer 24 and the oxide semiconductor layer 44-2. The film thickness t of the region where the contact hole CH3 is formed in the second region 24b is cnt The thickness of the oxide semiconductor layer 24 and the oxide semiconductor layer 44-1 or the thickness of the oxide semiconductor layer 24 and the oxide semiconductor layer 44-2. When the contact hole CH3 is formed, the second region 24b may also be thinned. Therefore, the film thickness of the oxide semiconductor layers 24 and 44 satisfies t ch <t cnt ≤t SD The thinner the oxide semiconductor layer 24 is, the less oxygen supply is needed to oxidize the oxide semiconductor layer 24. Therefore, the thinner the oxide semiconductor layer 24 is, the lower the resistance can be achieved with less oxygen supply. Therefore, by making the oxide semiconductor layers 24 and 44 satisfy the thickness of t ch <t cnt ≤t SD , thereby making it possible to reduce the resistance of the channel region and easily reduce the resistance of the source region and the drain region.

[0153] Figure 20 It is a sequence diagram showing a method for manufacturing the semiconductor device 10E according to one embodiment of the present invention. Figure 20 Since the manufacturing method of the semiconductor device 10E shown includes many of the same steps as the semiconductor device 10 , only the differences will be described.

[0154] like Figure 20 As shown, an IGZO oxide semiconductor film 43 is formed on the oxide insulating film 14b ( Figure 20 (See step S1103 "OS1 film formation" shown in the figure). The oxide semiconductor film 43 is formed by sputtering or atomic layer deposition (ALD). The thickness of the oxide semiconductor film 43 is, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm.

[0155] like Figure 20 As shown, an opening OP1 is formed in the oxide semiconductor film 43 ( Figure 4 (See step S1104 "OS1 patterning" in the figure). The opening OP1 provided in the oxide semiconductor film 43 is located in a region overlapping the gate electrode 12GE. Although not shown, the opening OP1 is provided parallel to the direction in which the gate electrode 12GE extends. It should be noted that the width of the opening OP1 corresponds to the channel length L of the channel region to be formed later.

[0156] like Figure 20 As shown, the oxide semiconductor film 21 is formed on the oxide semiconductor film 43 ( Figure 20 (See step S1105 “OS2 film formation” in the figure). Here, the content of indium contained in the oxide semiconductor film 21 is higher than the content of indium contained in the oxide semiconductor film 43 .

[0157] like Figure 20 and Figure 21 As shown, the oxide semiconductor layer 44 and the oxide semiconductor layer 24 are patterned ( Figure 20 (See step S1106 "OS1, OS2 patterning"). A resist mask is formed on the oxide semiconductor film 21, and the oxide semiconductor films 43 and 21 are etched using the resist mask 23. This forms patterned oxide semiconductor layers 22 and 44. The resist mask 23 is then removed. Figure 20 The steps S1107 to S1116 shown in FIG. Figure 4 The processes of steps S1007 and S1009 to S1017 shown are the same.

[0158] In the semiconductor device 10E, similar to the case where aluminum oxide is used for the metal oxide layers 18-1 and 18-2, the oxide semiconductor layers 44-1 and 44-2 block oxygen released from the oxide insulating film 14b. Therefore, the semiconductor device 10E can obtain good reliability test results and increase the on-current.

[0159] Although not described in detail, in semiconductor devices 10A and 10B, IGZO can be used instead of aluminum oxide as the metal oxide layer 18. When IGZO is used as the metal oxide layer 18, the description of the oxide semiconductor layer 44 of semiconductor device 10E can be referred to. In this case, the indium content contained in the oxide semiconductor layer 24 is higher than the indium content contained in the metal oxide layer 18. In semiconductor device 10F, the oxide semiconductor layer 24 and the oxide semiconductor used for the metal oxide layer 18 can also be made of different oxide semiconductor materials.

[0160] <Second embodiment>

[0161] use Figures 23 to 31 Semiconductor devices 10F to 10H according to one embodiment of the present invention will be described. Unless otherwise specified, semiconductor devices 10F to 10H are described using Poly-OS as the oxide semiconductor layer 24 and aluminum oxide as the metal oxide films 17 and 37 and the metal oxide layers 18 and 38 .

[0162] <Configuration of Semiconductor Device 10F>

[0163] use Figures 23 to 26 The configuration of a semiconductor device 10F according to an embodiment of the present invention will be described. Figure 23 It is a cross-sectional view schematically showing a semiconductor device 10F according to an embodiment of the present invention. Figure 24 It will Figure 1 FIG. 1 is an enlarged view showing a portion of the semiconductor device 10F.

[0164] like Figure 23 As shown, a semiconductor device 10F is provided above a substrate 11. The semiconductor device 10F includes at least an oxide insulating film 14b, a metal oxide layer 38, metal oxide layers 18-1 and 18-2, an oxide semiconductor layer 24, a gate insulating film 26, and a gate electrode 32GE. The oxide semiconductor layer 24, the gate insulating film 26, and the gate electrode 32GE are sometimes referred to as a transistor. The semiconductor device 10F may also include a gate electrode 12GE, a nitride insulating film 14a, an interlayer insulating film 34, a source electrode 36SE, and a drain electrode 36DE. The configuration of the semiconductor device 10F is the same as that of the semiconductor device 10, except that the metal oxide layer 38 is provided between the metal oxide layers 18-1 and 18-2 and the oxide semiconductor layer 24.

[0165] Metal oxide layers 18 and 38 are composed primarily of aluminum and function as gas barrier films, shielding against gases such as oxygen and hydrogen. Metal oxide layers 18 and 38 include a first region 19-1 and a second region 19-2, each separated from each other, and a third region 19-3 disposed between the first and second regions 19-1 and 19-2. Specifically, metal oxide layer 38 comprises a portion 1-1 corresponding to the first region, a portion 1-2 corresponding to the second region, and a portion 1-3 corresponding to the third region; metal oxide layer 18-1 disposed below portion 1-1 and corresponding to the first region; and metal oxide layer 18-2 disposed below portion 1-2 and corresponding to the second region.

[0166] The metal oxide layers 18 and 38 have a function of suppressing the permeation of oxygen supplied from the adjacent oxide insulating film 14 b . Therefore, the metal oxide layers 18 and 38 can be regarded as a single metal oxide layer.

[0167] The metal oxide layer 38 is provided on the oxide insulating film 14b and the metal oxide layers 18-1 and 18-2. The metal oxide layer 38 is aluminum oxide. The thickness of the metal oxide layers 18-1 and 18-2 is greater than that of the metal oxide layer 38. The thickness of the metal oxide layer 38 is 5 nm or less. In addition, the metal oxide layers 18-1 and 18-2 are aluminum oxide. The thickness of the metal oxide layer 18-1 and the thickness of the metal oxide layer 18-2 are, for example, greater than 5 nm and less than 50 nm, greater than 5 nm and less than 30 nm, greater than 5 nm and less than 20 nm, or greater than 5 nm and less than 10 nm. When the metal oxide layers 18 and 38 are considered as a single metal oxide layer, the thickness of the metal oxide layer in the first region 19-1 and the second region 19-2 can be greater than the thickness of the metal oxide layer in the third region 19-3. Furthermore, when the metal oxide layers 18 and 38 are regarded as one metal oxide layer, the total thickness of the metal oxide layers 18 and 38 in the first region 19 - 1 and the second region 19 - 2 may be greater than 5 nm and not greater than 50 nm.

[0168] <Method for Manufacturing Semiconductor Device 10F>

[0169] use Figures 25 to 27 A method for manufacturing the semiconductor device 10F according to one embodiment of the present invention will be described. Figure 25 FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device 10F according to an embodiment of the present invention. Figure 25 In the figure, although the steps S1213 to S1216 are omitted, Figure 4 The processes of steps S1012 to S1015 shown are the same, so reference may be made to them as appropriate. Figures 26 and 27 It is a cross-sectional view showing a method for manufacturing the semiconductor device 10F according to one embodiment of the present invention.

[0170] about Figure 25 The steps S1201 to S1204 shown in FIG. Figure 3 The steps S1001 to S1004 are the same as those shown in the figure. The opening OP1 is formed in the metal oxide film 17 by the step S1204.

[0171] like Figure 25 As shown, a metal oxide film 37 is formed on the metal oxide film 17 ( Figure 25(See step S1205 "MO2 film formation" in the figure). Metal oxide film 37 uses a metal oxide containing aluminum as a main component, similarly to metal oxide film 17. Metal oxide film 37 can be formed using the same film formation method as metal oxide film 17. The thickness of metal oxide film 37 is preferably 5 nm or less.

[0172] about Figure 25 The process of steps S1206 to S1208 shown in FIG. Figure 4 The process of step S1005 to step S1007 is the same as that of step S1208. Figure 26 As shown, an oxide semiconductor layer 24 having a polycrystalline structure is formed.

[0173] like Figure 25 As shown in step S1209 "MO1, MO2 patterning", the metal oxide films 17, 37 are patterned using the oxide semiconductor layer 24 as a mask. Figure 27 As shown, the metal oxide layer 38, the metal oxide layers 18-1 and 18-2 can be formed. Figure 27 As shown, the sidewalls of the metal oxide layer 18 - 1 , the sidewalls of the metal oxide layer 18 - 2 , the sidewalls of the metal oxide layer 38 , and the sidewalls of the oxide semiconductor layer 24 are arranged in a straight line.

[0174] about Figure 25 The process of steps S1210 to S1212 shown in FIG. Figure 4 The processes of steps S1009 to S1011 are similar. Oxygen released from the gate insulating film 26 and the oxide insulating film 14 b by the oxidation annealing shown in step S1212 is blocked by the metal oxide film 28. As a result, oxygen released from the gate insulating film 26 and the oxide insulating film 14 b is supplied to the upper surface and side surfaces of the oxide semiconductor layer 24.

[0175] As described above, the oxygen vacancies in the oxide semiconductor layer 24 are not uniformly distributed across the thickness of the oxide semiconductor layer 22. Instead, more oxygen vacancies are present on the upper surface than on the lower surface of the oxide semiconductor layer 24. When the lower surface of the oxide semiconductor layer 24 is in contact with the oxide insulating film 14b, an excessive amount of oxygen may be supplied to the lower surface of the oxide semiconductor layer 24. As a result, the excess oxygen forms defect energy levels different from those of the oxygen vacancies on the lower surface, causing variations in characteristics during reliability testing or a decrease in field-effect mobility. Therefore, to suppress such phenomena, it is necessary to supply oxygen to the upper surface of the oxide semiconductor layer 22 while suppressing the supply of oxygen to the lower surface.

[0176] In the semiconductor device 10F, a metal oxide layer 38 having a thickness of 5 nm or less is provided between the oxide semiconductor layer 24 and the oxide insulating film 14b. The thin metal oxide layer 38 allows oxygen from the oxide insulating film 14b to pass therethrough while also blocking it.

[0177] The first region 24a is supplied with oxygen from both the oxide insulating film 14b and the gate insulating film 26 by heat treatment. Although a metal oxide layer 38 is provided in the first region 24a, since the film thickness is as thin as 5 nm or less, oxygen from the oxide insulating film 14b can be transmitted. Therefore, compared with the semiconductor device 10, since it is possible to suppress the excessive supply of oxygen to the first region 24a, the generation of defect energy levels can be suppressed. Since the resistance of the first region 24a can be increased by oxidation annealing, it can function as a semiconductor. Thus, the first region 24a functions as a channel region. The resistance of the first region 24a is higher than that of the second region 24b and the third region 24c.

[0178] The second region 24b and the third region 24c are regions that overlap with the metal oxide layers 18-1, 18-2, and the metal oxide layer 38. Oxygen is supplied from the gate insulating film 26 to the second region 24b by the heat treatment, but the movement of oxygen from the oxide insulating film 14b is suppressed by the metal oxide layers 18-1, 18-2, and 38. Therefore, the second region 24b and the third region 24c can have lower resistance than the first region 24a. In addition, by adding impurity elements to the second region 24b after the oxidation annealing, the resistance of the second region 24b can be reduced compared to the third region 24c. The second region 24b can function as a source region and a drain region, and the third region 24c can function as an LDD region.

[0179] Providing the metal oxide layer 38 with a thickness of 5 nm or less in the third region 19-3 can suppress excessive oxygen supply from the oxide insulating film 14 b to the oxide semiconductor layer 24. As a result, the formation of defect levels caused by excessive oxygen vacancies supplied to the lower surface can be suppressed, thereby suppressing characteristic fluctuations during reliability testing and increasing field-effect mobility.

[0180] about Figure 25 The process of steps S1213 to S1218 is Figure 4 The steps S1011 to S1017 shown in FIG. are the same. Figure 23 The semiconductor device 10F is shown.

[0181] In the semiconductor device 10F, IGZO may be used instead of aluminum oxide as the metal oxide layer 18. When IGZO is used as the metal oxide layer 18, the description of the oxide semiconductor layer 44 of the semiconductor device 10E may be referred to. When IGZO is used as the metal oxide layer 18, aluminum oxide is preferably used as the metal oxide layer 38. In this case, the indium content of the oxide semiconductor layer 24 is higher than that of the metal oxide layer 18. In the semiconductor device 10F, the oxide semiconductor material of the oxide semiconductor layer 24 and the oxide semiconductor used for the metal oxide layer 18 may be different.

[0182] Next, refer to Figures 28 to 31 Semiconductor devices 10G to 10H having partially different structures from semiconductor device 10F will be described. In semiconductor devices 10G and 10H, unless otherwise specified, the oxide semiconductor layer 24 is made of Poly-OS and the metal oxide film 17 and metal oxide layer 18 are made of aluminum oxide.

[0183] <Variant 6>

[0184] Figure 28 This is a semiconductor device 10G according to one embodiment of the present invention. Semiconductor device 10G has an opening OP1 and an opening OP2 provided in a metal oxide film 17. A first region 19-1 and a second region 19-2 are provided in the metal oxide film 17, sandwiching the opening OP1. Specifically, the metal oxide layer includes a metal oxide layer 38 having a portion 1-1 corresponding to the first region 19-1, a portion 1-2 corresponding to the second region 19-2, and a portion 1-3 corresponding to the third region 19-3; and a metal oxide film 17 having an opening OP1 between the first region 19-1 and the second region 19-2, provided below the portions 1-1 and 1-2, and corresponding to the first region 19-1 and the second region 19-2. The method for manufacturing semiconductor device 10G is similar to that for manufacturing semiconductor device 10F, so only the differences will be described.

[0185] The method for manufacturing the semiconductor device 10G differs from the method for manufacturing the semiconductor device 10F in that Figure 25 In the method for manufacturing the semiconductor device 10G, the step S1209 may be omitted. Figure 25 In step S1209, the metal oxide film 37 is etched using the oxide semiconductor layer 24 as a mask, but the metal oxide film 17 may not be etched. This allows the side surfaces of the oxide semiconductor layer 24 and the metal oxide layer 38 to be straight.

[0186] In the semiconductor device 10G, IGZO may be used as the metal oxide film 17 instead of aluminum oxide. When IGZO is used as the metal oxide film 17, the description of the oxide semiconductor film 43 of the semiconductor device 10E may be referred to. When IGZO is used as the metal oxide film 17, aluminum oxide is preferably used as the metal oxide layer 38. When IGZO is used as the metal oxide film 17, the content of indium contained in the oxide semiconductor layer 24 is greater than the content of indium contained in the metal oxide film 17. In the semiconductor device 10G, the oxide semiconductor material may be different in the oxide semiconductor layer 24 and the oxide semiconductor used for the metal oxide film 17. In the manufacturing method of the semiconductor device 10G, when IGZO is used as the metal oxide film 17, when using Figure 25 After etching the oxide semiconductor film 21 in the process shown in step S1207 , only the metal oxide film 37 is etched in the process shown in step S1208 , and then in the process shown in step S1209 to form the metal oxide layer 38 .

[0187] <Variant 7>

[0188] Figure 29 This is a semiconductor device 10H according to one embodiment of the present invention. Semiconductor device 10H has openings OP1 and OP2 in metal oxide film 17. A first region 19-1 and a second region 19-2 are provided in metal oxide film 17, sandwiching opening OP1. The manufacturing method for semiconductor device 10H is similar to that for semiconductor device 10F, so only the differences will be described.

[0189] The method for manufacturing the semiconductor device 10H differs from the method for manufacturing the semiconductor device 10F in that Figure 25 In the method for manufacturing the semiconductor device 10, etching of the metal oxide film 17 may not be performed, and thus step S1209 may be omitted. When forming the contact hole CH1 in the gate insulating film 26, the metal oxide film 37, and the gate insulating film 14 before forming the gate electrode 32GE and the gate wiring 32GL, since these insulating films are made of different materials, the contact hole CH1 cannot be formed in a single etching step. Therefore, different etching methods are required for each process.

[0190] As a first method for forming the contact hole CH1, after the gate insulating film 26 is etched by dry etching using a fluorine-based gas, the metal oxide film 37 inside the opening OP2 is removed by wet etching, and the gate insulating film 14 is etched by dry etching using a fluorine-based gas. As a second method, after the gate insulating film 26 is etched by dry etching using a fluorine-based gas, the metal oxide film 37 inside the opening OP2 is removed by dry etching using a chlorine-based gas, and the gate insulating film 14 is etched by dry etching using a fluorine-based gas. As a third method, after the gate insulating film 26 and the metal oxide film 37 are etched by dry etching using a chlorine-based gas, the gate insulating film 14 is etched by dry etching using a fluorine-based gas. As a fourth method, after the gate insulating film 26 and the metal oxide film 37 are etched by wet etching, the gate insulating film 14 is etched by dry etching using a fluorine-based gas. As a fifth method, the gate insulating film 26, the metal oxide film 37, and the gate insulating film 14 may be etched by dry etching using a fluorine-based gas. When etching the metal oxide film 37, it is preferable to increase the bias voltage. Figure 29 As shown, the metal oxide film 37 is also provided inside the opening OP2 of the metal oxide film 37 .

[0191] In the semiconductor device 10H, IGZO may be used instead of aluminum oxide as the metal oxide film 17. When IGZO is used as the metal oxide film 17, aluminum oxide is preferably used as the metal oxide film 37.

[0192] <Variant 8>

[0193] In the semiconductor devices 10, 10A to 10E, indium gallium zinc oxide (IGZO) may be used as the oxide semiconductor layer 24 instead of Poly-OS. For the cross-sectional structure when IGZO is used as the oxide semiconductor layer 24, refer to the respective descriptions of the semiconductor devices 10, 10A to 10E. The crystallinity of IGZO may be amorphous or crystalline. Regarding the method for manufacturing a semiconductor device when IGZO is used as the oxide semiconductor layer 24, see the following. Figure 30 In Figure 30 In, with Figure 4The difference from the sequence diagram shown is the process of steps S1305, S1306, and S1308. IGZO has lower etching resistance than Poly-OS. Therefore, considering the subsequent etching process, in step S1305, it is preferred to form the IGZO film in a manner such that the film thickness is greater than 10 nm and less than 50 nm, preferably greater than 10 nm and less than 30 nm. In addition, it is difficult to etch the metal oxide film 17 using the oxide semiconductor layer 24 as a mask. Therefore, in step S1306, it is preferred to use a resist mask to etch the oxide semiconductor film 21 and then continue to etch the metal oxide film 17 to form the oxide semiconductor layer 46 and the metal oxide layer 18. Afterwards, the processes of steps S1307 to S1316 are different from those of step S1308. Figure 4 The processes of step S1007 and step S1009 to step S1017 are the same, and therefore detailed descriptions thereof are omitted.

[0194] <Variant 9>

[0195] In the semiconductor device 10F, indium gallium zinc oxide (IGZO) may be used instead of Poly-OS as the oxide semiconductor layer 24. For the cross-sectional structure when IGZO is used as the oxide semiconductor layer 24, refer to the description of the semiconductor device 10F. In the semiconductor device 10F, for the method of manufacturing the semiconductor device when IGZO is used as the oxide semiconductor layer 24, see the following. Figure 31 In Figure 31 In, with Figure 25 The difference in the sequence diagram shown is the process of step S1406 to step S1407. As explained in variant example 8, IGZO has lower etching resistance than Poly-OS. Therefore, considering the subsequent etching process, in step S1406, it is preferred to form the IGZO film in a manner such that the film thickness is greater than 10nm and less than 50nm, preferably greater than 10nm and less than 30nm. In addition, it is difficult to etch the metal oxide films 17 and 37 using the oxide semiconductor layer 24 as a mask. Therefore, in step S1407, it is preferred to use a resist mask to etch the oxide semiconductor film 21 and then continue to etch the metal oxide films 17 and 37 to form the oxide semiconductor layer 22 and the metal oxide layers 18 and 38. Afterwards, the processes of step S1408 to step S1417 are different from those of step S1417. Figure 25 The processes of step S1007 and step S1009 to step S1017 are the same, and therefore detailed descriptions thereof are omitted.

[0196] <Variant 10>

[0197] In the semiconductor device 10G, IGZO may be used instead of Poly-OS as the oxide semiconductor layer 24. When IGZO is used as the oxide semiconductor layer 24, aluminum oxide may be used as the metal oxide films 17 and 37. Alternatively, IGZO may be used as the metal oxide film 17 and aluminum oxide may be used as the metal oxide layer 38. In the method for manufacturing the semiconductor device 10G, when IGZO is used as the oxide semiconductor layer 24, aluminum oxide may be used as the metal oxide film 17 and aluminum oxide may be used as the metal oxide layer 38. Figure 25 In the process shown in step S1207 , both the oxide semiconductor film 21 and the metal oxide film 37 are etched to form the oxide semiconductor layer 22 and the metal oxide layer 38 .

[0198] <Variant 11>

[0199] In the semiconductor device 10H, IGZO may be used instead of Poly-OS as the oxide semiconductor layer 24. When IGZO is used as the oxide semiconductor layer 24, aluminum oxide may be used as the metal oxide films 17 and 37. Alternatively, IGZO may be used as the metal oxide film 17 and aluminum oxide may be used as the metal oxide layer 38. In the method for manufacturing the semiconductor device 10H, when IGZO is used as the oxide semiconductor layer 24, aluminum oxide may be used as the metal oxide film 17 and aluminum oxide may be used as the metal oxide layer 38. Figure 25 In the process shown in step S1207 , only the oxide semiconductor film 21 is etched to form the oxide semiconductor layer 22 and the metal oxide layer 38 .

[0200] <Variant 12>

[0201] In the semiconductor devices 10B to 10H, the width of the gate electrode 32GE in the direction D1 is described as being greater than the length of the first region 24a. However, the present invention is not limited to this. In the semiconductor devices 10B to 10H, the width of the gate electrode 32GE in the direction D1 may be smaller than the length of the first region 24a of the oxide semiconductor layer 24.

[0202] The various embodiments and modifications described above as embodiments of the present invention may be implemented in appropriate combinations as long as they do not contradict each other. Furthermore, solutions obtained by those skilled in the art by adding, deleting, or modifying the design of components, or by adding, omitting, or modifying conditions of processes based on the semiconductor devices and display devices of the various embodiments and modifications are also within the scope of the present invention as long as they contain the gist of the present invention.

[0203] Even if there are other effects different from the effects brought about by the schemes of the above-mentioned embodiments, if they are clearly known from the description of this specification or can be easily predicted by those skilled in the art, they are of course understood to be the effects brought about by the present invention.

Claims

1. A semiconductor device comprising: oxide insulating film; a metal oxide layer having a first region and a second region provided separately from each other on the oxide insulating film; an oxide semiconductor layer, disposed in contact with the first region and the second region; a gate insulating film provided so as to cover the oxide semiconductor layer; and a gate electrode provided on the oxide semiconductor layer via the gate insulating film, The oxide semiconductor layer includes a channel region overlapping with the gate electrode, and a source region and a drain region sandwiching the channel region. The channel region is in contact with the oxide insulating film between the first region and the second region.

2. The semiconductor device according to claim 1, wherein The metal oxide layer includes a first metal oxide layer including the first region and a second metal oxide layer including the second region.

3. The semiconductor device according to claim 1, wherein The metal oxide layer has an opening between the first region and the second region.

4. The semiconductor device according to claim 1, wherein The metal oxide layer has a thickness greater than 5 nm and less than 10 nm.

5. The semiconductor device according to claim 1, wherein The metal oxide layer is aluminum oxide or indium gallium zinc oxide. The semiconductor device according to claim 5 , wherein: In the case where the metal oxide layer is indium gallium zinc oxide, The content of indium contained in the oxide semiconductor layer is higher than the content of indium contained in the indium gallium zinc oxide.

7. The semiconductor device according to claim 1, wherein The oxide semiconductor layer contains indium and at least one metal element. The ratio of the indium to the indium and the at least one metal element is 50% or more, The oxide semiconductor layer has a polycrystalline structure.

8. A semiconductor device comprising: oxide insulating film; a metal oxide layer having, on the oxide insulating film, a first region and a second region provided separately from each other, and a third region provided between the first region and the second region; an oxide semiconductor layer, disposed in contact with the metal oxide layer; a gate insulating film provided so as to cover the oxide semiconductor layer; and a gate electrode provided on the oxide semiconductor layer via the gate insulating film, The oxide semiconductor layer includes a channel region overlapping with the gate electrode, and a source region and a drain region sandwiching the channel region. The source region is in contact with the first region, the drain region is in contact with the second region, and the channel region is in contact with the third region. The film thickness of the metal oxide layer in the first region and the second region is greater than the film thickness of the metal oxide layer in the third region.

9. The semiconductor device according to claim 8, wherein The metal oxide layer is aluminum oxide.

10. The semiconductor device according to claim 8, wherein The metal oxide layer comprises: a first metal oxide layer having a portion 1-1 corresponding to the first region, a portion 1-2 corresponding to the second region, and a portion 1-3 corresponding to the third region; a second metal oxide layer disposed below the portion 1-1, corresponding to the first region; and The third metal oxide layer is disposed below the 1-2 portion and corresponds to the second region.

11. The semiconductor device according to claim 10, wherein The thickness of the first metal oxide layer is 5 nm or less. The thickness of the second metal oxide layer and the thickness of the third metal oxide layer are greater than 5 nm and not more than 10 nm.

12. The semiconductor device according to claim 10, wherein The first metal oxide layer is aluminum oxide, The second metal oxide layer and the third metal oxide layer are aluminum oxide or indium gallium zinc oxide.

13. The semiconductor device according to claim 12, wherein When the second metal oxide layer and the third metal oxide layer are indium gallium zinc oxide, The oxide semiconductor layer contains more indium than the second metal oxide layer and the third metal oxide layer.

14. The semiconductor device according to claim 8, wherein The metal oxide layer comprises: a first metal oxide layer having a 1-1 portion corresponding to the first region, a 1-2 portion corresponding to the second region, and a 1-3 portion corresponding to the third region; and The second metal oxide layer has an opening between the first region and the second region, is provided below the 1-1 portion and the 1-2 portion, and corresponds to the first region and the second region.

15. The semiconductor device according to claim 10, wherein The thickness of the first metal oxide layer is 5 nm or less. The second metal oxide layer has a thickness greater than 5 nm and less than or equal to 10 nm.

16. The semiconductor device according to claim 15, wherein The first metal oxide layer is aluminum oxide, The second metal oxide layer is aluminum oxide or indium gallium zinc oxide.

17. The semiconductor device according to claim 16, wherein The content of indium contained in the oxide semiconductor layer is higher than the content of indium contained in the second metal oxide layer.

18. The semiconductor device according to claim 8, wherein The oxide semiconductor layer contains indium and at least one metal element. The ratio of the indium to the indium and the at least one metal element is 50% or more, The oxide semiconductor layer has a polycrystalline structure.

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