High electron mobility transistor and preparation method thereof

Abstract

The invention provides a high electron mobility transistor and a preparation method thereof, and relates to the technical field of semiconductors, a heterojunction is arranged on a substrate, and a plurality of pits with different depths are formed on a first surface of the heterojunction, so that the bottom of gate metal arranged on the first surface is filled in the plurality of pits with different depths in a gate region, and thus, the high electron mobility transistor is formed. The distances between different regions and two-dimensional electron gas under the same gate metal are different, so that the different regions under the gate have different turn-off voltages, thereby realizing the planarization of transconductance and improving the linearity of the high electron mobility transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisional application of the following application: the application date is June 17, 2022, the application number is 2022106909864, and the name of the invention is “A method for preparing a high electron mobility transistor”. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a high electron mobility transistor and a method for preparing the same. Background Art

[0003] GaN material has advantages such as a large bandgap, high breakdown electric field, high thermal conductivity, high electron saturation velocity, and high radiation resistance. It has broad application prospects in high-temperature, high-frequency, and microwave high-power semiconductor devices and is a frontier and hot topic in global semiconductor research. GaN high-electron-mobility transistor devices are planar lateral devices. The device is fabricated by evaporating source, drain, and gate metals and various passivation layers on a flat surface of GaN high-electron-mobility transistor epitaxial material to form a three-terminal device.

[0004] In practical applications, the transconductance (Gm) of traditional GaN high-electron-mobility transistor devices decreases as the gate voltage (Vgs) increases, corresponding to a decrease in device gain. The nonlinearity caused by the decrease in transconductance can lead to premature saturation of output power and signal distortion, affecting system characteristics and increasing the complexity of system design. Summary of the Invention

[0005] The purpose of this application is to provide a high electron mobility transistor and a method for manufacturing the same, in order to achieve flattening of the transconductance and improve the linearity of the high electron mobility transistor, in order to address the deficiencies in the above-mentioned prior art.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows: In one aspect of an embodiment of the present application, a high electron mobility transistor is provided, comprising: substrate; A heterojunction is provided on the substrate, and a plurality of pits are provided on a first surface of the heterojunction facing away from the substrate, wherein the plurality of pits are at least partially distributed in a gate region within the first surface; A source metal, a drain metal and a gate metal are arranged on the first surface of the heterojunction, and the gate metal fills the pit in the gate area.

[0007] Optionally, the pits are formed by V-shaped pits on the first surface, and the V-shaped pits correspond to threading dislocations, and the pits are randomly distributed on the first surface of the heterojunction.

[0008] Optionally, the gate metal is filled in a plurality of pits of varying depths distributed in the gate region.

[0009] Optionally, the heterojunction includes a channel layer and a barrier layer sequentially arranged on the substrate, a side of the barrier layer facing away from the substrate is a first surface, and a depth of the pit is less than a thickness of the barrier layer.

[0010] Optionally, an insertion layer is further provided between the channel layer and the barrier layer.

[0011] Optionally, a cap layer is provided on the first surface of the barrier layer.

[0012] Optionally, the material of the channel layer is GaN; The material of the insertion layer is AlN; And / or; the material of the barrier layer is one or a combination of AlGaN, AlN or AlInN.

[0013] Optionally, a nucleation layer is further provided between the substrate and the heterojunction, and a buffer layer is further provided between the nucleation layer and the heterojunction.

[0014] Optionally, the material of the nucleation layer is AlN, and / or the material of the buffer layer is GaN.

[0015] Optionally, the depth of the pit is 10 nm to 12 nm.

[0016] Optionally, any two pits in at least some of the pits have different depths.

[0017] Another aspect of the present invention provides a method for manufacturing a high electron mobility transistor, the method comprising: preparing a prefabricated structure, the prefabricated structure comprising a substrate and a heterojunction formed on the substrate, wherein the heterojunction has a plurality of V-shaped pits corresponding to threading dislocations on a first surface facing away from the substrate; The prefabricated structure is annealed in a predetermined atmosphere to enlarge the V-shaped pits to form a plurality of pits distributed on the first surface of the heterojunction; A source metal, a drain metal and a gate metal are formed on the first surface of the heterojunction, wherein the gate metal fills a pit located in the gate region.

[0018] Optionally, the preset atmosphere is H2 atmosphere, N2 atmosphere or a mixed atmosphere of H2 and N2.

[0019] Optionally, annealing the prefabricated structure in a preset atmosphere includes: annealing the prefabricated structure in situ in a H2 atmosphere for 5 to 20 minutes, the annealing temperature is 900° C. to 1200° C., the chamber pressure is 50 mbar to 500 mbar, and the gas flow rate of the preset atmosphere is 1 SLM to 100 SLM.

[0020] Optionally, annealing the prefabricated structure in a preset atmosphere includes: annealing the prefabricated structure in situ in a N2 atmosphere for 10 min to 30 min, the annealing temperature is 900° C. to 1200° C., the chamber pressure is 50 mbar to 500 mbar, and the gas flow rate of the N2 atmosphere is 1 SLM to 100 SLM. Optionally, annealing the prefabricated structure in a preset atmosphere includes: annealing the prefabricated structure in situ in a mixed atmosphere of H2 and N2 for 10 min to 30 min, the annealing temperature is 900°C to 1200°C, the chamber pressure is 50 mbar to 500 mbar, the gas flow rate of the mixed atmosphere of H2 and N2 is 1 SLM to 100 SLM, and the mixing ratio of H2 and N2 is 0 to 1.

[0021] Optionally, the heterojunction includes a channel layer and a barrier layer sequentially formed on the substrate, a side of the barrier layer facing away from the substrate is a first surface, and a depth of the pit is less than a thickness of the barrier layer.

[0022] Optionally, the prefabricated structure further includes an insertion layer formed between the channel layer and the barrier layer. Optionally, the prefabricated structure further includes a nucleation layer and a buffer layer sequentially formed between the substrate and the heterojunction. Optionally, the depth of the pit is 10 nm to 12 nm.

[0023] Optionally, the annealing time is positively correlated with the depth of the pit.

[0024] The beneficial effects of this application include: The present application provides a high electron mobility transistor and a method for preparing the same. A heterojunction is provided on a substrate. Since multiple pits of varying depths are formed on a first surface of the heterojunction, the bottom of a gate metal provided on the first surface is filled into the multiple pits of varying depths in the gate region. This results in different regions under the same gate metal being at different distances from a two-dimensional electron gas. Consequently, different voltages are required to deplete the two-dimensional electron gas, resulting in different turn-off voltages in different regions under the gate. This achieves flattening of the transconductance and improves the linearity of the high electron mobility transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic flow chart of a method for preparing a high electron mobility transistor provided in an embodiment of the present application; Figure 2 This is one of the state diagrams of a method for manufacturing a high electron mobility transistor provided in an embodiment of the present application; Figure 3 A second schematic diagram of a method for manufacturing a high electron mobility transistor according to an embodiment of the present application; Figure 4 The third state diagram of a method for manufacturing a high electron mobility transistor provided in an embodiment of the present application; Figure 5 This is one of the structural schematic diagrams of a high electron mobility transistor provided in an embodiment of the present application; Figure 6 The second structural diagram of a high electron mobility transistor provided in an embodiment of the present application; Figure 7 A schematic diagram of transconductance and gate voltage of a high electron mobility transistor provided in an embodiment of the present application; Figure 8 This is a third structural schematic diagram of a high electron mobility transistor provided in an embodiment of the present application.

[0027] Icons: 100-heterojunction; 110-first surface; 111-V-shaped pit; 112-pit; 120-source metal; 130-drain metal; 140-gate metal; 150-barrier layer; 160-channel layer; 170-substrate; 180-nucleation layer; 190-buffer layer; 200-insertion layer. DETAILED DESCRIPTION

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0029] It should be understood that although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to regionally distinguish one element from another element. For example, without departing from the scope of this disclosure, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be understood that when an element (such as a layer, region or substrate) is referred to as being "on another element" or "extending onto another element", it may be directly on the other element or directly extending onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on another element" or "extending directly onto another element", there are no intervening elements. Similarly, it should be understood that when an element (such as a layer, region or substrate) is referred to as being "above another element" or "extending over another element", it may be directly on the other element or directly extending over the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on another element" or "extending directly over another element", there are no intervening elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. It should also be understood that the terms used herein should be interpreted as having the same meaning as they have in the context of this specification and the relevant art, and should not be interpreted in an idealized or overly formal sense unless otherwise explicitly defined herein.

[0032] In one aspect of the present invention, a method for preparing a high electron mobility transistor is provided. Figure 1 As shown, the method includes: S010: preparing a prefabricated structure, the prefabricated structure including a substrate and a heterojunction formed on the substrate, wherein the heterojunction has a plurality of V-shaped pits corresponding to threading dislocations on a first surface facing away from the substrate.

[0033] A substrate 170 is provided. The substrate 170 may be a SiC, sapphire or Si substrate 170 , which is not limited in the present application.

[0034] like Figure 2 As shown, a heterojunction 100 is then epitaxially grown on the substrate 170 to obtain a prefabricated structure, wherein the heterojunction 100 has a two-dimensional electron gas located at the heterojunction interface. Figure 5As shown, the heterojunction 100 may include a channel layer 160 and a barrier layer 150. During the epitaxial growth process of the heterojunction 100, a large number of threading dislocations may exist within the heterojunction 100. For the first surface 110 of the heterojunction 100 facing away from the substrate 170, some threading dislocations may be exposed on the first surface 110, thereby forming a plurality of tiny V-shaped pits 111 on the first surface 110. The plurality of V-shaped pits 111 are randomly distributed on the first surface 110 of the heterojunction 100.

[0035] S020: The prefabricated structure is annealed in a preset atmosphere to enlarge the V-shaped pit to form a plurality of pits distributed on the first surface of the heterojunction.

[0036] like Figure 3 As shown, after the prefabricated structure is obtained by S010 epitaxial growth, the prefabricated structure is annealed in a preset atmosphere. Since there are multiple tiny V-shaped pits 111 on the first surface 110 of the heterojunction 100, the semi-polar surface of the heterojunction 100 material will be exposed. During the annealing process, the semi-polar surface will be decomposed and etched in the high-temperature preset atmosphere, so the multiple V-shaped pits 111 where the dislocations are exposed on the first surface 110 will be enlarged after annealing, and then a plurality of pits 112 of varying depths will be formed on the first surface 110 of the heterojunction 100.

[0037] S030: forming a source metal, a drain metal, and a gate metal on the first surface of the heterojunction, wherein the gate metal fills a pit located in the gate region.

[0038] The first surface 110 of the heterojunction 100 may have a source region, a drain region, and a gate region, wherein the gate region is located between the source region and the drain region. Figure 4 and Figure 5 As shown, a source metal 120 located in the source region, a drain metal 130 located in the drain region, and a gate metal 140 located in the gate region are formed on the first surface 110 of the heterojunction 100 by processes such as photolithography, evaporation, and lift-off.

[0039] Since a plurality of pits 112 of varying depths are formed on the first surface 110 of the heterojunction 100 by SO20, at least a portion of the plurality of pits 112 is distributed in the gate region. Figure 6As shown, when the gate metal 140 is evaporated on the first surface 110, the bottom of the gate metal 140 is filled in a plurality of pits 112 of varying depths distributed in the gate region. As a result, different regions under the same gate metal 140 are at different distances from the two-dimensional electron gas. Therefore, different voltages are required to deplete the two-dimensional electron gas, resulting in different turn-off voltages in different regions under the gate. This achieves flattening of the transconductance, improves the linearity of the high electron mobility transistor, and reduces adverse effects such as premature output power saturation and signal distortion caused by device nonlinearity.

[0040] Please refer to the figure Figure 6 (Only some of the pits 112 are shown in the figure). After the gate metal 140 is formed by evaporation on the first surface 110 of the heterojunction 100, the bottom of the gate metal 140 will be filled with a portion of pits 112 of varying depths. For example, in the gate width direction, there are multiple pits 112 of varying depths filled by the bottom of the gate metal 140. As a result, different areas under the same gate metal 140 are at different distances from the two-dimensional electron gas. Figure 7 As shown, the voltage required to deplete the two-dimensional electron gas is different, so that different regions under the gate have different turn-off voltages, thereby achieving flattening of the transconductance and improving the linearity of the high electron mobility transistor.

[0041] In some embodiments, the high electron mobility transistor may be a GaN device, and the corresponding heterojunction 100 may be a GaN heterojunction 100, such as AlGaN / GaN. Figure 5 As shown, the heterojunction 100 can be epitaxially grown on the substrate 170 using MOCVD equipment (metal organic chemical vapor deposition equipment) with H2 or N2 as carrier gas and TMAl, TMGa, and NH3 as Al source, Ga source, and N source, respectively.

[0042] In some embodiments, after the heterojunction 100 is epitaxially grown on the substrate 170 , S020 may be performed in an MOCVD device by in-situ annealing or cooling.

[0043] It should be noted that the depth of the pit 112 can be adjusted by controlling the annealing or cooling time. For example, the annealing time is positively correlated with the depth of the pit 112. In other words, the longer the annealing time, the deeper the pit 112, and vice versa. When the heterojunction 100 includes the channel layer 160 and the barrier layer 150, the side of the barrier layer 150 facing away from the substrate 170 is the first surface 110. The depth of the pit 112 should be less than the thickness of the barrier layer 150 to avoid affecting the device function.

[0044] When the prefabricated structure is subjected to in-situ annealing or cooling by SO20, the preset atmosphere can be one of an H2 atmosphere, an N2 atmosphere, or a mixed atmosphere of H2 and N2. For example, when the preset atmosphere is an N2 atmosphere, the small V-shaped pit 111 can be enlarged by utilizing the high-temperature decomposition of the nitride; for example, when the atmosphere is an H2 atmosphere, the high-temperature decomposition of the nitride and the etching effect of H2 on the nitride can be utilized to effectively enlarge the size of the V-shaped pit 111. This will be described below through an embodiment: In one embodiment, when the prefabricated structure is annealed in a preset atmosphere, the prefabricated structure is annealed in situ in an H2 atmosphere in the chamber of an MOCVD device. The annealing time is 5 to 20 minutes, the annealing temperature is 900°C to 1200°C, the chamber pressure is maintained at 50 mbar to 500 mbar, and the H2 flow rate is 1 SLM to 100 SLM. By controlling the annealing time, randomly distributed pits 112 of varying depths and less than the thickness of the barrier layer 150 can be formed on the first surface 110. For example, if the barrier layer 150 is 25 nm thick and the prefabricated structure is annealed in an H2 atmosphere at a temperature of 1050°C for 10 minutes, the depth of the pits 112 formed on the first surface 110 is approximately 10 nm.

[0045] In one embodiment, when the prefabricated structure is annealed in a predetermined atmosphere, the prefabricated structure is annealed in situ in an N2 atmosphere within a chamber of an MOCVD device. The annealing time is 10 to 30 minutes, the annealing temperature is 900°C to 1200°C, the chamber pressure is maintained at 50 mbar to 500 mbar, and the N2 flow rate is 1 SLM to 100 SLM. For example, if the barrier layer 150 has a thickness of 25 nm, the prefabricated structure is annealed in an N2 atmosphere at a temperature of 1050°C for 20 minutes. As a result, the depth of the pit 112 formed on the first surface 110 is approximately 12 nm.

[0046] In one embodiment, when the prefabricated structure is annealed in a predetermined atmosphere, the prefabricated structure is annealed in situ in a mixed atmosphere of H2 and N2 in a chamber of an MOCVD device. The annealing time is 10 to 30 minutes, the annealing temperature is 900° C. to 1200° C., the chamber pressure is maintained at 50 mbar to 500 mbar, the flow rate of the H2 and N2 mixed gas is 1 SLM to 100 SLM, and the H2 to N2 mixing ratio is between 0 and 1. For example, if the barrier layer 150 has a thickness of 25 nm, the prefabricated structure is annealed in a mixed atmosphere of H2 and N2 at a temperature of 1050° C. for 14 minutes. As a result, the depth of the pit 112 formed on the first surface 110 is approximately 10 nm.

[0047] See also Figure 8The prefabricated structure also includes an insertion layer 200 formed between the channel layer 160 and the barrier layer 150, a nucleation layer 180 and a buffer layer 190 formed in sequence between the substrate 170 and the heterojunction 100, and a cap layer formed on the barrier layer 150, so that the device has better performance.

[0048] like Figure 8 As shown, MOCVD equipment can be used with H2 or N2 as carrier gas, TMAl, TMGa, and NH3 as Al source, Ga source, and N source, respectively, to epitaxially grow a nucleation layer 180, a buffer layer 190, a channel layer 160, an insertion layer 200, a barrier layer 150, and a cap layer on a substrate 170 in sequence. Specifically: In one embodiment, the nucleation layer 180 is made of AlN, and its growth temperature is between 1000° C. and 1200° C., and its growth pressure is between 50 mbar and 150 mbar, for example, a growth temperature of 1150° C. and a growth pressure of 100 mbar.

[0049] In one embodiment, the buffer layer 190 is made of GaN, grown at a temperature between 1000°C and 1100°C, and at a pressure between 100 mbar and 500 mbar. For example, a growth temperature of 1080°C and a pressure of 300 mbar are employed. The GaN buffer layer 190 is a high-resistance buffer layer 190, achieved by introducing a C source or an Fe source as a doping source.

[0050] In one embodiment, the channel layer 160 is made of GaN, and its growth temperature is between 1000°C and 1100°C, and the growth pressure is between 100mbar and 500mbar. For example, a growth temperature of 1080°C and a growth pressure of 500mbar are used. The channel layer 160 is an unintentionally doped GaN layer, and the C impurity concentration is <1E16 atoms / cm 3 .

[0051] In one embodiment, the insertion layer 200 is made of AlN, and its growth temperature is between 1000° C. and 1100° C., and its growth pressure is between 50 mbar and 200 mbar, for example, a growth temperature of 1080° C. and a growth pressure of 100 mbar.

[0052] In one embodiment, the barrier layer 150 is made of one or a combination of AlGaN, AlN, or AlInN. When the barrier layer 150 is made of AlGaN, its thickness is 10 nm to 30 nm, the growth temperature is between 1000°C and 1100°C, and the growth pressure is between 50 mbar and 200 mbar. For example, a growth temperature of 1080°C and a growth pressure of 100 mbar are used.

[0053] In one embodiment, the cap layer is made of GaN and is grown to a thickness of 1 nm to 10 nm at a growth temperature of 1000° C. to 1100° C. and a growth pressure of 50 mbar to 200 mbar. For example, to achieve a growth thickness of 2 nm, a growth temperature of 1080° C. and a growth pressure of 100 mbar are used.

[0054] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A high electron mobility transistor, characterized in that include: substrate; A heterojunction is provided on the substrate, a plurality of pits are provided on a first surface of the heterojunction facing away from the substrate, and the plurality of pits are at least partially distributed in a gate region within the first surface; A source metal, a drain metal and a gate metal are provided on the first surface of the heterojunction, and the gate metal fills the pit in the gate region.

2. The high electron mobility transistor according to claim 1, wherein The heterojunction includes a channel layer and a barrier layer sequentially arranged on the substrate, a side of the barrier layer facing away from the substrate is the first surface, and a depth of the pit is smaller than a thickness of the barrier layer.

3. The high electron mobility transistor according to claim 2, wherein An insertion layer is further provided between the channel layer and the barrier layer.

4. The high electron mobility transistor according to claim 2, wherein A cap layer is disposed on the first surface of the barrier layer.

5. The high electron mobility transistor according to claim 3, wherein The material of the channel layer is GaN; The material of the insertion layer is AlN; And / or; the material of the barrier layer is one or a combination of AlGaN, AlN or AlInN.

6. The high electron mobility transistor according to any one of claims 1 to 5, wherein: A nucleation layer is further provided between the substrate and the heterojunction, and a buffer layer is further provided between the nucleation layer and the heterojunction; The material of the nucleation layer is AlN, and / or the material of the buffer layer is GaN.

7. The high electron mobility transistor according to claim 1, wherein The pits are formed by V-shaped pits on the first surface, and the V-shaped pits correspond to threading dislocations. The pits are randomly distributed on the first surface of the heterojunction.

8. The high electron mobility transistor according to any one of claims 1 to 5, wherein: The depth of the pit is 10 nm to 12 nm; the gate metal is filled in a plurality of pits of different depths distributed in the gate area.

9. The high electron mobility transistor according to any one of claims 1 to 5, wherein: Any two of the at least some of the recesses have different depths.

10. A method for preparing a high electron mobility transistor, characterized in that: The method comprises: preparing a prefabricated structure, the prefabricated structure comprising a substrate and a heterojunction formed on the substrate, the heterojunction having a plurality of V-shaped pits corresponding to threading dislocations on a first surface facing away from the substrate; Annealing the prefabricated structure in a preset atmosphere to enlarge the V-shaped pit to form a plurality of pits distributed on the first surface of the heterojunction; A source metal, a drain metal and a gate metal are formed on the first surface of the heterojunction, wherein the gate metal fills the pit located in the gate region.

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