Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a semiconductor substrate; an interlayer insulating film; a first electrode pad and a second electrode pad; and a first coating film and a second coating film. The semiconductor substrate has a first main surface and a second main surface opposite the first main surface. The semiconductor substrate acts as an n-type drain region. The semiconductor substrate includes: an n-type source region; a p-type channel region adjacent to a side surface of the source region, the side surface being closer to the first main surface, and the p-type channel region being pn-bonded to the source region and the drain region; and a p-type well region, the p-type well region being pn-bonded to the drain region. An interlayer insulating film is formed on the second main surface. First and second electrode pads are formed on the interlayer insulating film, and are electrically connected to the source region and the well region, respectively.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2024-038804 filed on March 13, 2024 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to semiconductor devices and methods of manufacturing semiconductor devices. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2020-120133.

[0006] The semiconductor device described in Patent Document 1 includes a semiconductor substrate, a trench gate electrode, a gate insulating film, an interlayer insulating film, an electrode pad, and a plating film. The semiconductor substrate has a first main surface and a second main surface, the second main surface being opposite the first main surface. The semiconductor substrate has an n-type conductivity. The semiconductor substrate serves as a drain region. An n-type source region located on the first main surface and a p-type region located between the source region and the drain region are formed in the semiconductor substrate. The p-type region is pn-bonded to the source region and the drain region.

[0007] A plurality of gate trenches and a plurality of trenches are formed on the second main surface. The gate trenches are arranged to be spaced apart from each other. The gate trenches extend toward the first main surface, penetrate the source region and the p-type region, and reach the drain region. Each trench is formed between two adjacent gate trenches. The trenches extend toward the first main surface, penetrate the source region, and reach the p-type region.

[0008] The trench gate electrode is embedded in the gate trench. A gate insulating film is formed between the side surface and bottom surface of the gate trench and the trench gate electrode. An interlayer insulating film is formed on the second main surface. A contact hole is formed in the interlayer insulating film. The contact hole penetrates the interlayer insulating film and is connected to the trench. An electrode pad is formed on the interlayer insulating film. The electrode pad is also embedded in the contact hole and the trench and is therefore electrically connected to the source region. A plating film is formed on the electrode pad. The plating film is formed by an electroless plating method. Summary of the Invention

[0009] In the semiconductor device described in Patent Document 1, nodules are formed on the surface of the plating film. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] A semiconductor device according to the present disclosure includes a semiconductor substrate, an interlayer insulating film, a first electrode pad and a second electrode pad, and a first plated film and a second plated film. The semiconductor substrate has a first main surface and a second main surface, the second main surface being opposite the first main surface. The second main surface includes a first region and a second region, the second region being adjacent to the first region. The semiconductor substrate serves as an n-type drain region. The semiconductor substrate includes: an n-type source region positioned in the first region; a p-type channel region adjacent to a side of the source region, the side being closer to the first main surface, and the p-type channel region being pn-bonded to the source region and the drain region; and a p-type well region, the p-type well region being located in the second region and being pn-bonded to the drain region. The interlayer insulating film is formed on the second main surface. The first electrode pad and the second electrode pad are formed on the interlayer insulating film and are electrically connected to the source region and the well region, respectively. The first plated film and the second plated film are formed to cover the first electrode pad and the second electrode pad, respectively.

[0011] According to the semiconductor device of the present disclosure, it is possible to prevent nodules from being formed on the surface of the first plating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a plan view illustrating the semiconductor device DEV1.

[0013] Figure 2 It is along Figure 1 A cross-sectional view taken along line II-II.

[0014] Figure 3A is a first cross-sectional view illustrating the semiconductor device DEV1 connected to the connection member CM.

[0015] Figure 3B is a second cross-sectional view illustrating the semiconductor device DEV1 connected to the connection member CM.

[0016] Figure 4 are diagrams illustrating steps of manufacturing the semiconductor device DEV1 .

[0017] Figure 5 is a cross-sectional view for explaining the trench forming step S2.

[0018] Figure 6 It is a cross-sectional view for explaining the insulating film forming step S3.

[0019] Figure 7 It is a cross-sectional view for explaining the gate forming step S4.

[0020] Figure 8 It is a cross-sectional view for explaining the insulating film forming step S5.

[0021] Figure 9It is a cross-sectional view for explaining the gate forming step S6.

[0022] Figure 10 It is a cross-sectional view for explaining the ion implantation step S7.

[0023] Figure 11 It is a cross-sectional view for explaining the interlayer insulating film forming step S8.

[0024] Figure 12 It is a cross-sectional view for explaining the contact hole forming step S9.

[0025] Figure 13 is a cross-sectional view for explaining the trench forming step S10.

[0026] Figure 14 It is a cross-sectional view for explaining the contact hole forming step S11.

[0027] Figure 15 is a cross-sectional view for explaining the trench forming step S12.

[0028] Figure 16 It is a cross-sectional view for explaining the ion implantation step S13.

[0029] Figure 17 It is a cross-sectional view for explaining the contact member forming step S14.

[0030] Figure 18 is a cross-sectional view for explaining the electrode pad forming step S15.

[0031] Figure 19 It is a cross-sectional view for explaining the passivation film forming step S16.

[0032] Figure 20 It is a cross-sectional view for explaining the plated film forming step S17.

[0033] Figure 21 It is a cross-sectional view for explaining the polishing step S18.

[0034] Figure 22 It is a cross-sectional view for explaining the electrode forming step S19.

[0035] Figure 23 is a cross-sectional view illustrating the semiconductor device DEV2.

[0036] Figure 24 is a cross-sectional view illustrating the semiconductor device DEV3.

[0037] Figure 25 is a cross-sectional view illustrating the semiconductor device DEV4.

[0038] Figure 26is a cross-sectional view illustrating a semiconductor device DEV4 according to a modified example. DETAILED DESCRIPTION

[0039] The embodiments of the present disclosure will be described in detail. In the following drawings, the same or corresponding components are denoted by the same reference numerals, and repeated descriptions will not be repeated.

[0040] (First embodiment)

[0041] A semiconductor device according to a first embodiment will be described. The semiconductor device according to the first embodiment will be described as a semiconductor device DEV1.

[0042] <Configuration of Semiconductor Device DEV1>

[0043] The configuration of the semiconductor device DEV1 will be described below.

[0044] Figure 1 is a plan view illustrating the semiconductor device DEV1. Figure 2 It is along Figure 1 The cross-sectional view taken along line II-II is shown. Figure 1 and Figure 2 As shown, the semiconductor device DEV1 includes a semiconductor substrate SUB.

[0045] The semiconductor substrate SUB has a main surface F1 and a main surface F2. The main surface F2 is an opposite surface to the main surface F1. The main surface F1 and the main surface F2 are end surfaces of the semiconductor substrate SUB in the thickness direction. The main surface F2 includes a chip region CHP and a scribe region SCR. The scribe region SCR is along the periphery of the main surface F2 in a plan view and defines the chip region CHP. The main surface F2 includes a region R1 and a region R2. The region R1 and the region R2 are, for example, located in the chip region CHP and the scribe region SCR, respectively.

[0046] The constituent material of the semiconductor substrate SUB is, for example, single crystal silicon. However, the constituent material of the semiconductor substrate SUB is not limited thereto. The conductivity type of the semiconductor substrate SUB is n-type, and the semiconductor substrate SUB serves as the drain region DR. The drain region DR serves as the main surface F1. A source region SR, a channel region CHR, and a well region WR are formed in the semiconductor substrate SUB. The conductivity type of the source region SR is n-type. The conductivity type of each of the channel region CHR and the well region WR is p-type.

[0047] Source region SR is located in region R1. Channel region CHR is adjacent to a side surface of source region SR, with the side surface being closer to main surface F1. Well region WR is located in region R2. Channel region CHR is pn-bonded to source region SR and drain region DR. Well region WR is pn-bonded to drain region DR. Well region WR is formed deeper than channel region CHR relative to main surface F2. That is, the bottom surface of well region WR is farther from main surface F2 than the bottom surface of channel region CHR.

[0048] A plurality of gate trenches GTR1 are formed in the region R1. The gate trenches GTR1 are spaced apart from each other. The gate trenches GTR1 extend toward the main surface F1. The gate trenches GTR1 penetrate the source region SR and the channel region CHR and reach the drain region DR. In other words, the bottom surface of the gate trenches GTR1 is located in the drain region DR.

[0049] A plurality of trenches TR1 are formed in region R1. Each trench TR1 is arranged between two adjacent gate trenches GTR1. The trenches TR1 extend toward the main surface F1. The trenches TR1 penetrate the source region SR and reach the channel region CHR. That is, the bottom surfaces of the trenches TR1 are located in the channel region CHR. A back gate region BGR is also formed in the semiconductor substrate SUB. The back gate region BGR is located at the bottom surface of the trenches TR1. The conductivity type of the back gate region BGR is p-type.

[0050] A plurality of trenches TR2 are formed in the region R2. The trenches TR2 are arranged to be spaced apart from each other. The trenches TR2 extend toward the main surface F1. The trenches TR2 do not penetrate the well region WR. That is, the bottom surface of the trenches TR2 is located in the well region WR. The trenches TR2 are formed deeper than the trenches TR1 relative to the main surface F2. That is, the bottom surface of the trenches TR2 is farther from the main surface F2 than the bottom surface of the trenches TR1. The trenches TR2 are formed deeper than the channel region CHR relative to the main surface F2. That is, the bottom surface of the trenches TR2 is farther from the main surface F2 than the bottom surface of the channel region CHR. The trenches TR2 are used for optical critical dimensions (OCD) using light. The trenches TR2 are used, for example, to measure dimensions when the trenches TR1 are formed.

[0051] The semiconductor device DEV1 further includes a split gate SPG1 and a trench gate electrode TGE1. The split gate SPG1 and the trench gate electrode TGE1 are arranged in a gate trench GTR1. The trench gate electrode TGE1 is further away from the bottom surface of the gate trench GTR1 than the split gate SPG1. The constituent materials of the split gate SPG1 and the trench gate electrode TGE1 are each, for example, polysilicon containing a dopant.

[0052] The semiconductor device DEV1 further includes a gate insulating film GI1. The gate insulating film GI1 is arranged in the gate trench GTR1 and individually surrounds each of the split gate SPG1 and the trench gate electrode TGE1. The trench gate electrode TGE1 faces the channel region CHR through the gate insulating film GI1. The constituent material of the gate insulating film GI1 is, for example, silicon oxide.

[0053] The semiconductor device DEV1 further includes an interlayer insulating film ILD. The interlayer insulating film ILD is formed on the main surface F2. Contact holes CH1 and CH2 are formed in the interlayer insulating film ILD. The contact holes CH1 and CH2 penetrate the interlayer insulating film ILD. The contact holes CH1 and CH2 are arranged so as to overlap with the trenches TR1 and TR2, respectively, in a plan view. That is, the contact hole CH1 is connected to the trench TR1, and the contact hole CH2 is connected to the trench TR2. The constituent material of the interlayer insulating film ILD is, for example, silicon oxide.

[0054] The semiconductor device DEV1 further includes a contact member CNT1 and a contact member CNT2. The contact member CNT1 is embedded in the trench TR1 and the contact hole CH1. The contact member CNT1 is electrically connected to the source region SR and the back gate region BGR. The contact member CNT2 is embedded in the trench TR2 and the contact hole CH2. The contact member CNT2 is electrically connected to the well region WR.

[0055] Each of the constituent materials of the contact member CNT1 and the contact member CNT2 is a conductor containing tungsten as a main component. The state that a certain component is a main component means that the content of the component in the constituent material is 50% by mass or more.

[0056] The semiconductor device DEV1 further includes an electrode pad PD1 and an electrode pad PD2. The electrode pad PD1 and the electrode pad PD2 are arranged on the interlayer insulating film ILD. More specifically, the electrode pad PD1 and the electrode pad PD2 are arranged on the region R1 and the region R2, respectively.

[0057] Electrode pad PD1 functions as a source electrode SE. Electrode pad PD1 is electrically connected to contact member CNT1. That is, electrode pad PD1 is electrically connected to source region SR and channel region CHR (back gate region BGR) via contact member CNT1. Electrode pad PD2 is electrically connected to contact member CNT2. That is, electrode pad PD2 is electrically connected to well region WR via contact member CNT2. Each of the constituent materials of electrode pad PD1 and electrode pad PD2 is, for example, a conductor containing aluminum as a main component.

[0058] The semiconductor device DEV1 further includes a gate electrode GE. The gate electrode GE is disposed on the interlayer insulating film ILD. Although not shown, the gate electrode GE is electrically connected to the trench gate electrode TGE1 via a contact member embedded in a contact hole formed in the interlayer insulating film ILD.

[0059] The semiconductor device DEV1 further includes a passivation film PV. The passivation film PV is formed on the interlayer insulating film ILD to cover the electrode pads PD1 and PD2 and the gate electrode GE. Openings OP1 and OP2 are formed in the passivation film PV. The openings OP1 and OP2 penetrate the passivation film PV. The electrode pads PD1 and PD2 are exposed through the openings OP1 and OP2. Although not shown, an opening for exposing the gate electrode GE is formed in the passivation film PV. The passivation film PV is made of silicon nitride.

[0060] Semiconductor device DEV1 further includes a plating film PL1 and a plating film PL2. Plating film PL1 is formed on electrode pad PD1 exposed from opening OP1. Plating film PL2 is formed on electrode pad PD2 exposed from opening OP2. Plating film PL1 and plating film PL2 are plating films (electroless plating films) formed by, for example, electroless plating.

[0061] Each of the plating films PL1 and PL2 includes, for example, a first film, a second film, and a third film. The second film is formed on the first film. The third film is formed on the second film. The first film is composed of, for example, a conductor containing nickel as a main component. The second film is composed of, for example, a conductor containing palladium as a main component. The third film is composed of, for example, a conductor containing gold as a main component. Although not shown, the semiconductor device DEV1 also includes a plating film similar to the plating films PL1 and PL2, which is formed on the gate electrode GE exposed through the opening of the passivation film PV.

[0062] The semiconductor device DEV1 further includes a drain electrode DE. The drain electrode DE is formed on the main surface F2. The drain electrode DE is electrically connected to the drain region DR. The drain electrode DE is a film (sputtered film) formed by, for example, a sputtering method. The drain electrode DE includes, for example, a first film, a second film, and a third film. The second film is formed on the first film. The third film is formed on the second film. The constituent material of the first film is, for example, a conductor containing titanium as a main component. The constituent material of the second film is, for example, a conductor containing nickel as a main component. The constituent material of the third film is, for example, a conductor containing silver as a main component.

[0063] When voltage is applied to the gate electrode GE, an inversion layer is formed in the channel region CHR facing the trench gate electrode TGE1 via the gate insulating film GI1, and the source region SR and the drain region DR are electrically connected. In this way, the source electrode SE (electrode pad PD1), the drain electrode DE, and the gate electrode GE configure a metal oxide semiconductor field effect transistor (MOSFET).

[0064] Figure 3A is a first cross-sectional view illustrating the semiconductor device DEV1 connected to the connection member CM. Figure 3B 2 is a second cross-sectional view illustrating the semiconductor device DEV1 connected to the connection member CM. Figure 3A and Figure 3B As shown, the connection member CM is connected to the plating film PL1. The connection member CM is made of, for example, a clip CL and solder SRD, which connects the clip CL to the plating film PL1. The connection member CM may be a bonding wire BW.

[0065] <Method of Manufacturing Semiconductor Device DEV1>

[0066] A method of manufacturing the semiconductor device DEV1 will be described below.

[0067] Figure 4 1 is a diagram illustrating steps of manufacturing the semiconductor device DEV1. Figure 4 As shown, the method for manufacturing a semiconductor device DEV1 includes a preparation step S1, a trench forming step S2, an insulating film forming step S3, a gate forming step S4, an insulating film forming step S5, a gate forming step S6, an ion implantation step S7, an interlayer insulating film forming step S8, a contact hole forming step S9, a trench forming step S10, a contact hole forming step S11, and a trench forming step S12. The method for manufacturing a semiconductor device DEV1 also includes an ion implantation step S13, a contact member forming step S14, an electrode pad forming step S15, a passivation film forming step S16, a plating film forming step S17, a polishing step S18, an electrode forming step S19, and a cutting step S20.

[0068] In the preparation step S1 , a semiconductor substrate SUB is prepared. The source region SR, the channel region CHR, the well region WR, and the back gate region BGR are not formed in the semiconductor substrate SUB prepared in the preparation step S1 .

[0069] Figure 5 : is a cross-sectional view for explaining the groove forming step S2. Figure 5 As shown, in the trench forming step S2 , the main surface F2 is etched to form a gate trench GTR1 in the main surface F2 . Figure 6 : is a cross-sectional view for explaining the insulating film forming step S3. Figure 6 As shown, in the insulating film forming step S3 , the gate insulating film GI1 is formed on the side surfaces and the bottom surface of the gate trench GTR1 by, for example, thermal oxidation.

[0070] Figure 7 : is a cross-sectional view for explaining the gate forming step S4. Figure 7 As shown, in the gate forming step S4, the split gate SPG1 is embedded in the gate trench GTR1. The split gate SPG1 is formed by forming the constituent material of the split gate SPG1 by, for example, a chemical vapor deposition (CVD) method, and then partially removing the constituent material of the formed split gate SPG1 by a chemical mechanical polishing (CMP) method or an etch-back method.

[0071] Figure 8 : is a cross-sectional view for explaining the insulating film forming step S5. Figure 8 As shown, in the insulating film forming step S5 , the gate insulating film GI1 is also formed by, for example, a CVD method to cover the split gate SPG1 . Figure 9 : is a cross-sectional view for explaining the gate forming step S6. Figure 9 As shown, in the gate forming step S6, the trench gate electrode TGE1 is embedded in the gate trench GTR1. The trench gate electrode TGE1 is formed by forming the constituent material of the trench gate electrode TGE1 by, for example, a CVD method and then partially removing the constituent material of the formed trench gate electrode TGE1 by a CMP method or an etch-back method. Figure 10 : is a cross-sectional view for explaining the ion implantation step S7. Figure 10 As shown, in the ion implantation step S7 , ions are implanted to form the source region SR, the channel region CHR, and the well region WR.

[0072] Figure 11 1 is a cross-sectional view for explaining the interlayer insulating film forming step S8. Figure 11 As shown, in the interlayer insulating film forming step S8 , the interlayer insulating film ILD is formed by, for example, a CVD method. Figure 12 1 is a cross-sectional view for explaining the contact hole forming step S9. Figure 12 As shown, in the contact hole forming step S9, the interlayer insulating film ILD is etched to form the contact hole CH2. Figure 13 : is a cross-sectional view for explaining the trench forming step S10. Figure 13 As shown, in the trench forming step S10 , main surface F2 is etched while using interlayer insulating film ILD as a mask to form trench TR2 .

[0073] Figure 14 1 is a cross-sectional view for explaining the contact hole forming step S11. Figure 14 As shown, in the contact hole forming step S11 , the interlayer insulating film ILD is etched to form a contact hole CH1 . Figure 15 : is a cross-sectional view for explaining the groove forming step S12. Figure 15 As shown, in the trench forming step S12, the main surface F2 is etched while using the interlayer insulating film ILD as a mask to form the trench TR1. The trench TR2 is made deeper by the etching at this time, and thus the trench TR2 is formed deeper than the trench TR1.

[0074] Figure 16 : is a cross-sectional view for explaining the ion implantation step S13. Figure 16 As shown, in the ion implantation step S13 , the back gate region BGR is formed through the contact hole CH1 by ion implantation. Figure 17 1 is a cross-sectional view for explaining the contact member forming step S14. Figure 17 As shown, in the contact member forming step S14, the contact member CNT1 is embedded in the contact hole CH1 and the trench TR1, and the contact member CNT2 is embedded in the contact hole CH2 and the trench TR2. Each of the contact member CNT1 and the contact member CNT2 is formed by forming its constituent material by, for example, a CVD method and then partially removing the formed constituent material by a CMP method or the like.

[0075] Figure 18 : is a cross-sectional view for explaining the electrode pad forming step S15. Figure 18 As shown, in the electrode pad forming step S15, the electrode pad PD1 (source electrode SE) and the electrode pad PD2 are formed on the interlayer insulating film ILD. Each of the electrode pad PD1 and the electrode pad PD2 is formed by forming its constituent material on the interlayer insulating film ILD by sputtering or the like, and then etching and patterning the formed constituent material while using a mask formed by photolithography. Although not shown, the gate electrode GE is also formed in this step.

[0076] Figure 19 : is a cross-sectional view for explaining the passivation film forming step S16. Figure 19 As shown, in the passivation film forming step S16, a passivation film PV is formed on the interlayer insulating film ILD to cover the electrode pads PD1 and PD2 and the gate electrode GE. The passivation film PV is formed by forming a constituent material of the passivation film PV and then etching and patterning the formed constituent material while using a mask formed by photolithography.

[0077] Figure 20 1 is a cross-sectional view for explaining the plating film forming step S17. Figure 20 As shown, in the plating film forming step S17, plating films PL1 and PL2 are formed. Plating films PL1 and PL2 are formed by, for example, performing a zinc plating process on the surfaces of electrode pads PD1 and PD2, and then performing electroless plating. The zinc plating process may be performed, for example, multiple times. At this time, although not shown, a plating film is also formed on gate electrode GE.

[0078] Figure 21 1 is a cross-sectional view for explaining the polishing step S18. Figure 21 As shown, in the polishing step S18, the main surface F1 is polished. As a result, the thickness of the semiconductor substrate SUB is reduced.

[0079] Figure 22 : is a cross-sectional view for explaining the electrode forming step S19. Figure 22 As shown, in electrode forming step S19 , drain electrode DE is formed on main surface F1 by, for example, a sputtering method.

[0080] In the cutting step S20 , the semiconductor wafer is cut into a plurality of semiconductor devices DEV1 by cutting along scribe line regions SCR. Figure 1 and Figure 2 The structure of the semiconductor device DEV1 shown in FIG. 1 is formed by the above-described steps.

[0081] <Effects of semiconductor device DEV1>

[0082] The effects of the semiconductor device DEV1 will be described below.

[0083] A semiconductor device according to a comparative example is assumed to be a semiconductor device DEV2. Figure 23 FIG is a cross-sectional view illustrating the semiconductor device DEV2. Figure 23 As shown, in the semiconductor device DEV2, the p-type region PR is formed in the region R2 rather than the well region WR. The p-type region PR is formed no deeper than the channel region CHR. Since the trench TR2 is formed deeper than the channel region CHR, the trench TR2 in the semiconductor device DEV2 penetrates the p-type region PR and reaches the drain region DR. Therefore, in the semiconductor device DEV2, the electrode pad PD2 is electrically connected to the drain region DR via the contact member CNT2.

[0084] The zinc plating treatment in the plating film forming step S17 causes the reaction "Al+3OH - →Al(OH)3+3e - " and reaction "Zn 2+ +2e -→Zn". Since the electrode pad PD2 in the semiconductor device DEV2 is electrically connected to the semiconductor substrate SUB, the reaction easily proceeds on the surface of the electrode pad PD2, and aluminum is excessively dissolved on the surface of the electrode pad PD2. Such excessive aluminum dissolution causes nodules to appear in the flow direction of the plating solution on the plating film PL1 formed on the electrode pad PD1 at the downstream side of the electrode pad PD2. The nodules cause appearance failures or failures related to the connecting member CM.

[0085] In contrast, in the semiconductor device DEV1, the well region WR is pn-bonded to the drain region DR, and the trench TR2 does not penetrate the well region WR. Therefore, the electrode pad PD2 is not electrically connected to the semiconductor substrate SUB (drain region DR). Therefore, electron exchange between the electrode pad DP2 and the semiconductor substrate SUB is limited, and dissolution of transition aluminum during the zinc plating process is prevented. As described above, according to the semiconductor device DEV1, the formation of nodules on the plating film PL1 can be prevented.

[0086] (Second embodiment)

[0087] A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment is assumed to be a semiconductor device DEV3. Differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions thereof will not be repeated.

[0088] <Configuration of Semiconductor Device DEV3>

[0089] The configuration of the semiconductor device DEV3 will be described below.

[0090] Figure 24 FIG is a cross-sectional view illustrating the semiconductor device DEV3. Figure 24 As shown, in the semiconductor device DEV3, the p-type region PR is formed in the region R2 instead of the well region WR, and the trench TR2 penetrates the channel region CHR. That is, in the semiconductor device DEV3, the electrode pad PD2 is electrically connected to the semiconductor substrate SUB (drain region DR) via the contact member CNT2.

[0091] In the semiconductor device DEV3, the opening OP2 is not formed in the passivation film PV, and the electrode pad PD2 is not exposed from the passivation film PV. That is, the semiconductor device DEV3 does not include the plating film PL2. The configuration of the semiconductor device DEV3 differs from that of the semiconductor device DEV1 in these points.

[0092] <Method of Manufacturing Semiconductor Device DEV3>

[0093] A method of manufacturing the semiconductor device DEV3 will be described below.

[0094] In the method of manufacturing the semiconductor device DEV3, in the ion implantation step S7, ions are implanted into the region R2, similarly to the region R1, and the p-type region PR is formed in the region R2 instead of the well region WR. In addition, in the method of manufacturing the semiconductor device DEV3, the opening OP2 is not formed in the passivation film formation step S16, and the plating film PL2 is not formed in the plating film formation step S17. The method of manufacturing the semiconductor device DEV3 differs from the method of manufacturing the semiconductor device DEV1 in these points.

[0095] <Effects of semiconductor device DEV3>

[0096] The effects of the semiconductor device DEV3 will be described below.

[0097] In the semiconductor device DEV3, the opening OP2 is not formed in the passivation film forming step S16, and the surface of the electrode pad PD2 is covered with the passivation film PV during the zinc plating process performed in the plating film forming step S17. Therefore, according to the semiconductor device DEV3, it is difficult to cause excessive aluminum dissolution on the surface of the electrode pad PD2, and therefore it is difficult for nodules to appear on the surface of the plating film PL1.

[0098] (Third embodiment)

[0099] A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment is assumed to be a semiconductor device DEV4. Differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions thereof will not be repeated.

[0100] <Configuration of semiconductor device DEV4>

[0101] The configuration of the semiconductor device DEV4 will be described below.

[0102] Figure 25 FIG is a cross-sectional view illustrating the semiconductor device DEV4. Figure 25 As shown, in the semiconductor device DEV4, the region R2 in which the well region WR is formed is located in the chip region CHP. In the semiconductor device DEV4, a plurality of gate trenches GTR2 are formed in the region R2. A split gate SPG2 and a trench gate electrode TGE2 are embedded in the gate trenches GTR2. Each of the split gate SPG2 and the trench gate electrode TGE2 is surrounded by a gate insulating film GI2 in the gate trenches GTR2. The trench gate electrode TGE2 is positioned higher than the split gate SPG2 and faces the well region WR through the gate insulating film GI2.

[0103] In semiconductor device DEV4, electrode pad PD2 serves as an electrode pad for inspection. Specifically, in semiconductor device DEV4, voltage is applied to trench gate electrode TGE1 and trench gate electrode TGE2 to electrically connect channel region CHR and drain region DR, and also to electrically connect well region WR and drain region DR. Consequently, current flows between electrode pad PD1 and electrode pad PD2 via drain region DR. Consequently, the properties of the MOSFET can be evaluated. The configuration of semiconductor device DEV4 differs from that of semiconductor device DEV1 in these respects.

[0104] <Method of Manufacturing Semiconductor Device DEV4>

[0105] A method of manufacturing the semiconductor device DEV4 will be described below.

[0106] In the method for manufacturing the semiconductor device DEV4, in addition to forming the gate trench GTR1, the gate trench GTR2 is also formed in the trench forming step S2. In the method for manufacturing the semiconductor device DEV4, in addition to forming the gate insulating film GI1, the split gate SPG1, and the trench gate electrode TGE1, the gate insulating film GI2, the split gate SPG2, and the trench gate electrode TGE2 are also formed in the insulating film forming step S3, the gate forming step S4, the insulating film forming step S5, and the gate forming step S6. The method for manufacturing the semiconductor device DEV4 differs from the method for manufacturing the semiconductor device DEV1 in these respects.

[0107] <Effects of semiconductor device DEV4>

[0108] The effects of the semiconductor device DEV4 will be described below.

[0109] Since voltage is not applied to the trench gate electrode TGE2 during the plating film forming step S17, the electrode pad PD2 is not electrically connected to the semiconductor substrate SUB due to the pn junction between the well region WR and the drain region DR, and the electron exchange between the electrode pad PD2 and the semiconductor substrate SUB is restricted, thereby preventing excessive aluminum dissolution on the surface of the electrode pad PD2 during the zinc plating process, and thus preventing nodules from appearing on the surface of the plating film PL1.

[0110] In contrast, voltage is applied to trench gate electrode TGE2 when inspecting semiconductor device DEV4, and thus, current flows between electrode pad PD2 and electrode pad PD1 via drain region DR, and thus electrode pad PD2 functions as an electrode pad for inspection. As described above, according to semiconductor device DEV4, it is possible to prevent nodules from occurring on the surface of plating film PL1, and electrode pad PD2 can achieve electrical functionality.

[0111] <Modification example>

[0112] Figure 26 1 is a cross-sectional view illustrating a semiconductor device DEV4 according to a modified example. Figure 26 As shown, in the semiconductor device DEV4, a p-type region PR is formed instead of the well region WR, and the trench TR2 can penetrate the p-type region PR and reach the drain region DR. In this case, the electrode pad PD1 is electrically connected to the semiconductor substrate SUB (drain region DR) via the contact member CNT2.

[0113] Furthermore, in this case, gate trench GTR2 is not formed in region R2, and semiconductor device DEV4 does not include gate insulating film GI2, split gate SPG2, trench gate electrode TGE2, and plating film PL2. In this case, opening OP2 is not formed in passivation film PV by passivation film formation step S16. Therefore, the surface of electrode pad PD2 is covered with passivation film PV during the zinc plating process, and excessive aluminum dissolution on electrode pad PD2 is prevented. However, in this case, in order to use electrode pad PD2 as an electrode pad for inspection, etching for forming opening OP2 in passivation film PV is additionally performed after plating film formation step S17.

[0114] In the above, the invention made by the inventors of this application has been specifically described based on the embodiment. However, it is obvious that the present invention is not limited to the foregoing embodiment, and various modifications can be made within the scope of the present invention.

Claims

1. A semiconductor device comprising: semiconductor substrates; interlayer insulating film; a first electrode pad and a second electrode pad; as well as First coating and second coating, The semiconductor substrate has a first main surface and a second main surface, the second main surface being opposite to the first main surface, wherein the second major surface includes a first region and a second region, the second region being adjacent to the first region, wherein the semiconductor substrate acts as an n-type drain region, The semiconductor substrate comprises: an n-type source region, wherein the n-type source region is located in the first region; a p-type channel region adjacent to a side surface of the source region, the side surface being closer to the first main surface, and pn-bonded to the source region and the drain region; and a p-type well region located in the second region and pn-bonded to the drain region, wherein the interlayer insulating film is formed on the second main surface, wherein the first electrode pad and the second electrode pad are formed on the interlayer insulating film and are electrically connected to the source region and the well region, respectively, and The first plating film and the second plating film are formed to cover the first electrode pad and the second electrode pad respectively.

2. The semiconductor device according to claim 1, further comprising: a first contact member and a second contact member, wherein a first trench is formed in the first region to reach the channel region, wherein a second trench is formed in the second region to reach the well region, wherein the first contact member and the second contact member are embedded in the first groove and the second groove, respectively, wherein the first electrode pad is electrically connected to the source region via the first contact member, and The second electrode pad is electrically connected to the well region via the second contact member.

3. The semiconductor device according to claim 2, wherein the well region is formed deeper than the channel region with reference to the second main surface, and A bottom surface of the second trench is located in the well region.

4. The semiconductor device according to claim 1, The second electrode pad is an electrode pad for inspection configured to generate a current flow between the second electrode pad and the first electrode pad via the drain region.

5. The semiconductor device according to claim 2, The plurality of second grooves are formed to be spaced apart from each other and are a pattern for measuring a dimension while using light.

6. The semiconductor device according to claim 5, The second main surface includes a chip area and a scribe line area, the scribe line area defines the chip area, and The first region and the second region are located in the chip region and the scribe line region respectively.

7. The semiconductor device according to claim 2, wherein each of the first electrode pad and the second electrode pad is made of a conductor containing aluminum as a main component, wherein each of the first contact member and the second contact member is made of a conductor containing tungsten as a main component, Each of the first plating film and the second plating film includes a first film, a second film and a third film, the first film is made of a conductor containing nickel as a main component, the second film is made of a conductor containing palladium as a main component, and the third film is made of a conductor containing gold as a main component.

8. The semiconductor device according to claim 1, The first plating film and the second plating film are formed by an electroless plating method.

9. The semiconductor device according to claim 1, further comprising: connecting components, The connecting member is made of a bonding wire or a clip-shaped member and solder, the bonding wire or the clip-shaped member is connected to the first plating film, and the solder connects the clip-shaped member to the first plating film.

10. The semiconductor device according to claim 1, further comprising: Trench gate electrode; gate electrode; as well as drain electrode, wherein a gate trench penetrating the source region and the channel region and reaching the drain region is formed in the first region, wherein the trench gate electrode is embedded in the gate trench, wherein the gate electrode is formed on the interlayer insulating film, wherein the first electrode pad serves as a source electrode, wherein the drain electrode is formed on the first main surface, and The source electrode, the gate electrode, and the drain electrode configure a MOSFET.

11. A semiconductor device comprising: semiconductor substrates; interlayer insulating film; a first electrode pad and a second electrode pad; Passivation film; as well as First coating, The semiconductor substrate has a first main surface and a second main surface, the second main surface being opposite to the first main surface, wherein the second major surface includes a first region and a second region, the second region being adjacent to the first region, wherein the semiconductor substrate acts as an n-type drain region, The semiconductor substrate comprises: an n-type source region, wherein the n-type source region is located in the first region; as well as a p-type channel region adjacent to a side surface of the source region, the side surface being closer to the first main surface, and the p-type channel region being pn-bonded to the source region and the drain region, wherein the interlayer insulating film is formed on the second main surface, wherein the first electrode pad and the second electrode pad are formed on the interlayer insulating film and are electrically connected to the source region and the drain region, respectively, wherein the passivation film is formed to cover the first electrode pad and the second electrode pad, and includes an opening formed in the passivation film, the opening being configured to expose a portion of the first electrode pad, wherein the first plating film is formed on the first electrode pad exposed from the opening, and The first plating film is not formed on the first electrode pad.

12. The semiconductor device according to claim 11, further comprising: a first contact member and a second contact member, wherein a first trench is formed in the first region to reach the channel region, wherein a second trench is formed in the second region to reach the drain region, wherein the first contact member and the second contact member are embedded in the first groove and the second groove, respectively, wherein the first electrode pad is electrically connected to the source region via the first contact member, and The second electrode pad is electrically connected to the drain region via the second contact member.

13. The semiconductor device according to claim 12, The plurality of second grooves are formed to be spaced apart from each other and are a pattern for measuring a dimension while using light.

14. The semiconductor device according to claim 11, The second main surface includes a chip area and a scribe line area, the scribe line area defines the chip area, and The first region and the second region are located in the chip region and the scribe line region respectively.

15. The semiconductor device according to claim 12, wherein each of the first electrode pad and the second electrode pad is made of a conductor containing aluminum as a main component, wherein each of the first contact member and the second contact member is made of a conductor containing tungsten as a main component, and The first plating film includes a first film, a second film and a third film, the first film is made of a conductor containing nickel as a main component, the second film is made of a conductor containing palladium as a main component, and the third film is made of a conductor containing gold as a main component.

16. The semiconductor device according to claim 11, The first plating film is formed by an electroless plating method.

17. The semiconductor device according to claim 11, further comprising: connecting components, The connecting member is made of a bonding wire or a clip-shaped member and solder, the bonding wire or the clip-shaped member is connected to the first plating film, and the solder connects the clip-shaped member to the first plating film.

18. The semiconductor device according to claim 11, further comprising: Trench gate electrode; gate electrode; as well as drain electrode, wherein a gate trench penetrating the source region and the channel region and reaching the drain region is formed in the first region, wherein the trench gate electrode is embedded in the gate trench, wherein the gate electrode is formed on the interlayer insulating film, wherein the first electrode pad serves as a source electrode, wherein the drain electrode is formed on the first main surface, and The source electrode, the gate electrode, and the drain electrode configure a MOSFET.

19. A method for manufacturing a semiconductor device, comprising the steps of: preparing semiconductor substrates; The semiconductor substrate has a first main surface and a second main surface, the second main surface being opposite to the first main surface, wherein the second major surface includes a first region and a second region, the second region being adjacent to the first region, wherein the semiconductor substrate acts as an n-type drain region, and The semiconductor substrate comprises: an n-type source region, wherein the n-type source region is located in the first region; a p-type channel region adjacent to a side surface of the source region, the side surface being closer to the first main surface, and pn-bonded to the source region and the drain region; and a p-type well region located in the second region and pn-bonded to the drain region, The method further comprises the following steps: forming an interlayer insulating film on the second main surface; forming a first electrode pad and a second electrode pad on the interlayer insulating film, the first electrode pad and the second electrode pad being electrically connected to the source region and the well region, respectively; and A first plating film and a second plating film are formed to cover the first electrode pad and the second electrode pad, respectively.

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