Display device

Abstract

The present disclosure relates to a display device including: a substrate including a display area and a non-display area; an external common voltage line and an external driving voltage line disposed in the non-display area; a plurality of pixels and a common voltage line disposed in the display area; and a driving voltage line connected to each of the plurality of pixels, in which a subset of the plurality of pixels overlaps the common voltage line in the display area in a plan view, and each of the external driving voltage line and the external common voltage line includes a plurality of portions separated from each other.

Description

[0001] This application is a divisional application of the invention patent application with application date of April 17, 2020, application number 202010305109.1, and invention name “Display Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0045420 filed on April 18, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0004] The present disclosure relates to a display device, and in particular, to a display device in which a common voltage line is connected to a non-display area within a display area. Background Art

[0005] A display device displays an image. Recently, an emissive display device has attracted attention as a self-emissive display.

[0006] Emissive display devices have self-luminous properties and, unlike liquid crystal displays, do not require a separate light source, thus reducing their thickness and weight. Furthermore, emissive display devices offer high-quality features such as low power consumption, high brightness, and high response speed.

[0007] Typically, an emissive display device may include: a substrate; a plurality of thin film transistors disposed on the substrate; a plurality of insulating layers disposed between wirings constituting the thin film transistors; and a light emitting element connected to the thin film transistors. An organic light emitting element may be an example of a light emitting element.

[0008] On the other hand, as the frame of the display device becomes thinner, the user's line of sight is fixed or focused on the image (or the screen of the display device). In recent years, a full-surface display technology has been developed to eliminate the frame on the front surface of the display device and display the image on the entire front surface of the display device.

[0009] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the Invention

[0010] The present disclosure provides a display device for preventing a common voltage drop and minimizing right / left bezels.

[0011] A display device according to an exemplary embodiment of the present disclosure includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a plurality of pixels and a common voltage line disposed in the display area; and a driving voltage line connected to each of the plurality of pixels, wherein, in a plan view, a subset of the plurality of pixels overlaps with the common voltage line in the display area, and the external common voltage line and the common voltage line are connected to each other.

[0012] The driving voltage line may be indirectly connected to the subset of the plurality of pixels via a driving voltage connection line.

[0013] The external common voltage lines may be disposed to surround four edges of the display area.

[0014] The common voltage lines may further include a transverse common voltage line and a longitudinal common voltage line.

[0015] The external common voltage line may be divided through the display area.

[0016] The display device may further include an external initialization voltage line and an external driving voltage line disposed in the non-display area, and each of the external initialization voltage line, the external driving voltage line, and the external common voltage line may have a multi-layer structure.

[0017] Each of the external initialization voltage line, the external driving voltage line, and the external common voltage line may include a plurality of portions separated from each other, and each of the plurality of portions may be connected to each other by a connection member.

[0018] The connection member may be provided on the same layer as the gate line, the data line or the pixel electrode in the display area.

[0019] The connection member may include a first connection member disposed on the same layer as the gate line and a second connection member disposed on the same layer as the pixel electrode, and the first and second connection members may overlap each other in a plan view.

[0020] The display area may further include a driving voltage connection line disposed in the display area and crossing the driving voltage line, and a width of the driving voltage connection line may be reduced where the common voltage line and the driving voltage connection line overlap.

[0021] The driving voltage link line, the driving voltage line, and the common voltage line may be disposed on different layers from each other, and the driving voltage link line may be disposed closer to the substrate than the driving voltage line and the common voltage line.

[0022] The display device may further include a common electrode contacting the external common voltage line in the non-display area.

[0023] A display device according to another exemplary embodiment of the present disclosure includes: a substrate including a display area and a non-display area; an external common voltage line disposed in the non-display area; a plurality of pixels disposed in the display area; a driving voltage line connected to each of the plurality of pixels; and a plurality of common voltage lines disposed in the display area, wherein the external common voltage line and the plurality of common voltage lines are connected to each other.

[0024] The external common voltage lines may be disposed to surround four edges of the display area.

[0025] The plurality of common voltage lines and the driving voltage lines may be disposed on the same layer.

[0026] Each of the plurality of common voltage lines may further include a transverse common voltage line and a longitudinal common voltage line.

[0027] The plurality of common voltage lines may be disposed farther from the substrate than the driving voltage lines, and an insulating layer may be disposed between the plurality of common voltage lines and the driving voltage lines.

[0028] The external common voltage line may be disposed to be divided through the display area.

[0029] The display device may further include an external initialization voltage line and an external driving voltage line disposed in the non-display area, and each of the external initialization voltage line, the external driving voltage line, and the external common voltage line may have a multi-layer structure.

[0030] Each of the external initialization voltage line, the external driving voltage line, and the external common voltage line may include a plurality of portions separated from each other, and each of the plurality of portions may be connected to each other by a connection member.

[0031] The connection member may be provided on the same layer as the gate line, the data line or the pixel electrode in the display area.

[0032] The display device may further include a driving voltage connection line disposed in the display area and crossing the driving voltage line, and a width of the driving voltage connection line may be reduced where the common voltage line and the driving voltage connection line overlap.

[0033] According to exemplary embodiments, by connecting the external common voltage line in the non-display area to the common voltage line in the display area, a common voltage drop may be prevented, and right and left side bezels of the display device may be minimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0035] Figure 2 is a view illustrating a display device according to another exemplary embodiment.

[0036] Figure 3 is a view illustrating a display device according to another exemplary embodiment.

[0037] Figure 4 is a view illustrating a display device according to another exemplary embodiment.

[0038] Figure 5 is a view illustrating a display device according to another exemplary embodiment.

[0039] Figure 6 is a view illustrating a display device according to another exemplary embodiment.

[0040] Figure 7 is a view schematically illustrating arrangement shapes of driving voltage connection lines, driving voltage lines, and common voltage lines in a display area of ​​a display device according to an exemplary embodiment.

[0041] Figures 8 to 10 are views schematically illustrating arrangement shapes of a driving voltage connection line, a driving voltage line, and a common voltage line within a display area in a display device according to another exemplary embodiment.

[0042] Figure 11 is a view illustrating a wiring connection structure of a display area and a non-display area in a display device according to an exemplary embodiment of the present disclosure.

[0043] Figure 12 and Figure 13 is a view illustrating a wiring connection structure of a display area and a non-display area in a display device according to another exemplary embodiment.

[0044] Figure 14 is a view of an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment.

[0045] Figure 15 is a layout diagram of a pixel region of a display device according to an exemplary embodiment.

[0046] Figure 16 It is along Figure 15 A cross-sectional view taken along line XVI-XVI'.

[0047] Figure 17 is a layout diagram of a pixel region of a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0048] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present disclosure are shown. As those skilled in the art will recognize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0049] The drawings and accompanying description are to be regarded as illustrative in nature and not restrictive.Throughout the specification, like reference numerals refer to like elements.

[0050] In addition, in the drawings, for better understanding and ease of description, the size and thickness of each element are arbitrarily represented, and the present disclosure is not limited thereto. In the drawings, for clarity, better understanding and ease of description, the thickness of layers, films, panels, regions, locations, etc. are exaggerated.

[0051] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or one or more intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, no intervening elements are present. Furthermore, in the specification, the terms "on" or "above" mean being on or below a target portion, and do not necessarily mean being on the upper side of the target portion based on the direction of gravity.

[0052] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0053] Furthermore, throughout the specification, the phrase “on a plane” means observing a target portion from the top, and the phrase “on a cross section” means a cross section formed by vertically cutting the target portion from the side.

[0054] Now, a display device according to exemplary embodiments of the present disclosure is described with reference to the accompanying drawings.

[0055] Figure 1 is a view showing a display device according to an exemplary embodiment of the present disclosure. Figure 1 , the display device includes a display area DA and a non-display area NDA.

[0056] A plurality of pixels PX1, PX2, and PX3 are arranged in the display area, and a driving voltage line 172 is connected to each pixel and applies a driving voltage VDD to the pixel. A driving voltage connection line 172c that intersects the driving voltage line 172 is arranged in the display area DA. The driving voltage connection line 172c intersects the driving voltage line 172 and connects to the driving voltage line 172 at the intersection. Therefore, the driving voltage transmitted to the driving voltage line 172 can be transmitted to adjacent pixels via the driving voltage connection line 172c. The driving voltage connection line 172c can be arranged on a layer different from the layer of the driving voltage line 172.

[0057] For convenience, Figure 1 Only a partial view of the pixels PX1 , PX2 , and PX3 , the driving voltage line 172 , and the driving voltage connection line 172 c is shown.

[0058] The external driving voltage line 1720 is disposed in the non-display area NDA. The external driving voltage line 1720 may include a first driving voltage line 1720a and a second driving voltage line 1720b separated from each other by the display area DA. The first driving voltage line 1720a and the second driving voltage line 1720b may be disconnected from each other in the non-display area NDA and may be connected to the driving voltage line 172 in the display area DA.

[0059] The external common voltage line 7410 is disposed in the non-display area NDA. The external common voltage line 7410 may include a first common voltage line 7410a and a second common voltage line 7410b separated from each other. The first common voltage line 7410a and the second common voltage line 7410b may be separated from each other via the display area DA and may be connected to each other via the common voltage line 741 disposed in the display area DA.

[0060] Reference Figure 1 , one of the driving voltage lines 172 connected to the plurality of pixels PX1, PX2, and PX3 may be replaced with the common voltage line 741. Thus, the first and second common voltage lines 7410a and 7410b spaced apart from each other via the display area DA may be connected to each other via the common voltage line 741.

[0061] Therefore, when the first common voltage line 7410a and the second common voltage line 7410b are connected through the common voltage line 741 in the display area DA, the problem of voltage drop during the transmission period of the common voltage VSS can be solved. In addition, because the first common voltage line 7410a and the second common voltage line 7410b are not provided at the edge of the display area DA, the left non-display area NDA and the right non-display area NDA can be minimized.

[0062] In other words, when the external common voltage line 7410 is disposed around all four edges of the display area DA, a voltage drop may occur during the transmission of the common voltage VSS. In addition, because the external common voltage line 7410 should be disposed on the left and right non-display areas NDA located outside the left and right edges of the display area DA, the left and right non-display areas NDA may not be removed.

[0063] However, if Figure 1 As shown in the figure, when the external common voltage lines 7410 are set to be separated from each other via the display area DA and connected to each other through the common voltage line 741 set in the display area DA, the problem of common voltage reduction can be prevented, and the left non-display area NDA and the right non-display area NDA can be removed, thereby minimizing the border, or even completely removing the border at least on the right and left sides of the display device.

[0064] The common electrode 270 (herein, also referred to as the second electrode) contacts the external common voltage line 7410, thereby receiving the common voltage VSS. Figure 1 As shown in the figure, the driving voltage line 172 connected to the pixel PX3 among the driving voltage lines 172 connected to the multiple pixels PX1, PX2 and PX3 is replaced by the common voltage line 741, however, the driving voltage line 172 is connected through the driving voltage connection line 172c in the display area DA, so that all pixels PX1, PX2 and PX3 can receive the driving voltage VDD.

[0065] Table 1 below shows the Figure 1 Table 2 shows the LRU, voltage drop, and panel power reduction of a comparative display device in which the common voltage line 741 is not provided in the display area DA and the external common voltage line 7410 surrounds all four edges of the display area DA.

[0066] (Table 1)

[0067] project result LRU (%) 81.25 VDD drop (V) 0.22 VSS drop (V) 2.16 Reduction in panel power consumption 19.2％

[0068] (Table 2)

[0069] project result LRU (%) 79.24 VDD drop (V) 0.18 VSS drop (V) 4.09

[0070] Comparing Table 1 and Table 2, when the external common voltage line 7410 is not provided on the right and left sides of the display area DA and the external common voltage line 7410 is connected via the common voltage line 741 inside the display area DA, the common voltage drop is low. By connecting the external common voltage line 7410 via the common voltage line 741 in the display area DA, the common voltage drop can be reduced and the LRU can be improved.

[0071] Figure 2 is a view showing a display device according to another exemplary embodiment. Figure 2 , except for the shape of the external common voltage line 7410 and the point that the external common voltage line 7410 surrounds the four edges of the display area DA, the display device is similar to Figure 1 The detailed description of the same components is omitted. Figure 2 In the case of Figure 1 Likewise, the common voltage line 741 provided in the display area DA is connected to the external common voltage line 7410. Therefore, a voltage drop during a transmission process of the common voltage VSS can be prevented.

[0072] Figure 3 is a view showing a display device according to another exemplary embodiment. Figure 3 In addition to the common voltage line 741 provided in the display area DA including a horizontal common voltage line 741b and a vertical common voltage line 741a, the display device is similar to Figure 2 Detailed descriptions of the same components are omitted. Specifically, the display device has a grid structure, and the common voltage lines 741 of the grid structure include a horizontal common voltage line 741b and a vertical common voltage line 741a. In this case, a reduction in the common voltage VSS can be effectively prevented, and the common voltage VSS can be uniformly transmitted through the common voltage lines 741 having the grid structure.

[0073] Figures 4 to 6 are views respectively showing a display device according to another exemplary embodiment. Figure 4 , the common voltage line 741 is provided in the display area DA, however, Figure 1 Unlike the display device shown in FIG, the common voltage line 741 is provided separately from the driving voltage lines 172 connected to the pixels PX1, PX2, and PX3. Figure 1 That is, if there is enough space in the display area DA for separately setting the common voltage line 741, the common voltage line 741 can be separately formed without removing the existing driving voltage line 172.

[0074] In addition to forming a common voltage line 741 without removing the driving voltage line 172 in the display area DA, Figure 5 also with Figure 2 Detailed description of the same constituent elements is omitted.

[0075] In addition to forming a common voltage line 741 without removing the driving voltage line 172 in the display area DA, Figure 6 and Figure 3 Detailed description of the same constituent elements is omitted.

[0076] exist Figures 1 to 6 In the embodiment, the driving voltage connection line 172c, the driving voltage line 172, and the common voltage line 741 can be respectively provided in different layers, thereby being separated from each other. Although the driving voltage connection line 172c and the driving voltage line 172 can be provided in different layers, the driving voltage connection line 172c and the driving voltage line 172 are connected through the contact hole, thereby uniformly transmitting the driving voltage VDD.

[0077] Figure 7 The arrangement shape of the driving voltage connection line 172c, the driving voltage line 172 and the common voltage line 741 in the display area DA is schematically shown. Figure 7 , PX1, PX2, and PX3 denote pixels connected to respective connection wirings among one or more connection wirings.

[0078] Reference Figure 7 , the driving voltage connection line 172c, the driving voltage line 172, and the common voltage line 741 are respectively arranged on different layers. For example, the driving voltage connection line 172c can be arranged on the bottom layer so that the driving voltage connection line 172c is closest to the substrate of the display device, followed by the driving voltage line 172 and the common voltage line 741. However, the present disclosure is not limited to this, and they can be arranged in a different stacking order. In some embodiments, the driving voltage line 172 and the common voltage line 741 can be arranged on the same layer.

[0079] Reference Figure 7 , the width of the driving voltage connection line 172c overlapping the common voltage line 741 can be narrower than the width of the driving voltage connection line 172c overlapping the driving voltage line 172. Therefore, the risk of the common voltage line 741 and the driving voltage connection line 172c short-circuiting each other can be reduced. The driving voltage connection line 172c and the driving voltage line 172 are connected to each other through the contact hole 28.

[0080] Figure 8Schematically shows the arrangement shapes of the driving voltage connection line 172c, the driving voltage line 172 and the common voltage line 741 in the display area DA of the display device according to another exemplary embodiment. Figure 8 , the common voltage line 741 includes a horizontal common voltage line 741b and a vertical common voltage line 741a. In addition to the common voltage line 741 including the horizontal common voltage line 741b and the vertical common voltage line 741a, the display device is similar to the display device according to Figure 7 Detailed description of the same constituent elements is omitted.

[0081] The horizontal common voltage line 741a and the vertical common voltage line 741b can be arranged on the same layer and connected to each other. That is, the common voltage line 741 can have a grid shape including the horizontal common voltage line 741b and the vertical common voltage line 741a. In this case, the common voltage line 741 can be arranged on a layer different from the layer of the driving voltage line 172, and an insulating layer can be provided between the common voltage line 741 and the driving voltage line 172. In one embodiment, the driving voltage line 172 can be arranged closer to the substrate than the common voltage line 741.

[0082] Figure 9 Schematically shows the arrangement shapes of the driving voltage connection line 172c, the driving voltage line 172 and the common voltage line 741 in the display area DA of the display device according to another exemplary embodiment. Figure 9 , except that the common voltage line 741 is provided outside the pixels PX1, PX2 and PX3, the display device is similar to Figure 7 Detailed description of the same components is omitted. Because the common drive voltage line 741 is provided outside the pixels PX1, PX2, and PX3, the common voltage line 741 is provided without removing the existing drive voltage line 172. That is, each drive voltage line 172 is connected to a respective pixel in the pixels PX1, PX2, and PX3, and the common voltage line 741 is separately provided in each empty area between the pixels. The common voltage line 741 can be provided on the same layer as the drive voltage line 172.

[0083] Figure 10 Schematically shows the arrangement shapes of the driving voltage connection line 172c, the driving voltage line 172 and the common voltage line 741 in the display area DA of the display device according to another exemplary embodiment. Figure 10 , the common voltage line 741 includes a horizontal common voltage line 741b and a vertical common voltage line 741a. In addition to the common voltage line 741 including the horizontal common voltage line 741b and the vertical common voltage line 741a, the display device is similar to the display device according to Figure 9Detailed description of the same constituent elements is omitted.

[0084] The transverse common voltage line 741b and the longitudinal common voltage line 741a may be disposed on the same layer and connected to each other. That is, the common voltage line 741 may have a mesh shape including the transverse common voltage line 741a and the longitudinal common voltage line 741b.

[0085] The common voltage line 741 may be disposed on the driving voltage line 172. The common voltage line 741 may be disposed farther from the substrate than the driving voltage line 172, and an insulating layer may be disposed between the driving voltage line 172 and the common voltage line 741.

[0086] Next, various methods of connecting wirings of the display area DA and the non-display area NDA are described with reference to the accompanying drawings.

[0087] Figure 11 FIG. 1 shows a wiring connection structure of a display area DA and a non-display area NDA in a display device according to an exemplary embodiment of the present disclosure. Figures 11 to 13 , for better understanding and ease of description, a voltage transmitted from each wiring is described with respect to the wiring.

[0088] Reference Figure 11 , the display device includes an external common voltage line 7410 , an external initialization voltage line 1270 , and an external driving voltage line 1720 provided in the non-display area NDA.

[0089] The external common voltage line 7410 includes a first common voltage line 7410a, a second common voltage line 7410b, a third common voltage line 7410c, and a fourth common voltage line 7410d that are separated from each other. The external common voltage line 7410 may be formed in a plurality of layers including at least a first layer and a second layer. Figure 11 , the first layer and the second layer are shown in different patterns. The second common voltage line 7410b, the third common voltage line 7410c, and the fourth common voltage line 7410d may include the first layer and the second layer, and the first common voltage line 7410a may include only the first layer.

[0090] In this case, the first layer may be the same layer as the first source / drain layer of the display area DA, and the second layer may be the same layer as the second source / drain layer of the display area DA.

[0091] The first common voltage line 7410a, the second common voltage line 7410b, the third common voltage line 7410c, and the fourth common voltage line 7410d are connected to each other through a first connecting member 7415, a second connecting member 7416, and contact holes 14 and 15. The first connecting member 7415 may be provided in the same layer as the layer in which the pixel electrodes in the display area DA are provided. The first connecting member 7415 may be connected to the second connecting member 7416 through the contact hole 15, and the second connecting member 7416 may be connected to the external common voltage line 7410a through the contact hole 14. The second connecting member 7416 may be provided in the same layer as the second source / drain layer of the display area DA.

[0092] In addition, the first common voltage line 7410a disposed near the display area DA is connected to the common voltage line 741 disposed in the display area DA through a connecting member 7417. The first common voltage line 7410a and the connecting member 7417 may be connected through the contact hole 18. The connecting member 7417 may be disposed in the same layer as the second source / drain layer.

[0093] The external initialization voltage line 1270 partially protrudes, and a portion of the protruding area includes a second layer. That is, the external initialization voltage line 1270 may include a first layer in the same layer as the first source / drain layer of the display area DA and a second layer in the same layer as the second source / drain layer of the display area DA.

[0094] The external initialization voltage line 1270 is connected to the initialization voltage line 127 within the display area DA through a connecting member 1275. The connecting member 1275 can be provided in the same layer as the second source / drain layer. The connecting member 1275 can be connected to the external initialization voltage line 1270 via the contact hole 27. The second layer of the connecting member 1275 can also be connected to the first layer through the contact hole 28.

[0095] The external driving voltage line 1720 may include a first layer in the same layer as the first source / drain layer of the display area DA and a second layer in the same layer as the second source / drain layer of the display area DA. A portion of the second layer extends to the display area DA to connect to the driving voltage line 172 of the display area DA.

[0096] Next, refer to Figure 12 A display device according to another exemplary embodiment of the present disclosure is described. Figure 12, the external initialization voltage line 1270 is arranged closer to the display area DA than the external common voltage line 7410. The external initialization voltage line 1270 is connected to the connection member 1275 through the contact hole 27, and is connected to the initialization voltage line 127 inside the display area DA through the connection member 1275. The connection member 1275 can be arranged in the same layer as the first source / drain layer of the display area DA. The external initialization voltage line 1270 can be connected to the outside via the connection members 1276, 1277 and 1278. The connection members 1276 and 1278 can be arranged in the same layer as the connection member 1275, and the connection member 1277 can be arranged in the same layer as the pixel electrode in the display area DA. The connection member 1277 can be connected to the connection member 1276 and the connection member 1278 respectively through the contact hole 25. The connection member 1276 is also connected to the external initialization voltage line 1270 via the contact hole 28.

[0097] The external common voltage line 7410 is connected to the connection member 7417 via the contact hole 14. The external common voltage line 7410 is connected to the common voltage line 741 of the display area DA via the connection member 7417. The external common voltage line 7410 is disposed in the same layer as the first source / drain layer of the display area DA. A portion of the external common voltage line 7410 includes a second layer, and the second layer is disposed in the same layer as the second source / drain layer of the display area DA. The first layer and the second layer may be connected to each other through the contact hole 15.

[0098] Next, the external driving voltage line 1720 is described. The external driving voltage line 1720 includes a first layer coexisting with the first source / drain layer of the display area DA and a second layer coexisting with the second source / drain layer of the display area DA. Portions of the first layer of the external driving voltage line 1720 are separated from each other but connected to each other via the second layer. A portion of the second layer extends to connect to the driving voltage line 172 of the display area DA to transmit the driving voltage VDD.

[0099] Next, refer to Figure 13 A display device according to another exemplary embodiment of the present disclosure is described. Figure 13 The external driving voltage line 1720, the external common voltage line 7410, and the external initialization voltage line 1270 are formed in a single layer. Each of the external driving voltage line 1720, the external common voltage line 7410, and the external initialization voltage line 1270 is arranged in a direction parallel to the edge of the display area DA.

[0100] In addition, the island-shaped external driving voltage line 1721, the external common voltage line 7411, and the external initialization voltage line 1271 are respectively connected to the island-shaped external driving voltage line 1720, the external common voltage line 7410, and the external initialization voltage line 1270 through a connecting member 7711. The connecting member 7711 is connected to each wiring through the contact hole 17. The connecting member 7711 may be provided in the same layer as the layer in which the pixel electrodes in the display area DA are provided.

[0101] In addition, the island-shaped external driving voltage line 1721, the external common voltage line 7411, and the external initialization voltage line 1271 are respectively connected to the island-shaped external driving voltage line 1720, the external common voltage line 7410, and the external initialization voltage line 1270 through connection members 7712. Each connection member 7712 is connected to a wiring through a contact hole 12. The connection members 7712 can be provided on the same layer as the gate conductor layer in the display area DA.

[0102] The island-shaped wiring and the line-shaped wiring can be connected by two overlapping connection members. That is, the separated wirings are connected by the connection member 7712 and the connection member 7711. The connection member 7712 is provided in the same layer as the gate conductor layer in the display area DA, and the connection member 7711 is provided in the same layer as the layer in which the pixel electrodes in the display area DA are provided.

[0103] Figures 11 to 13 are examples only, and Figures 1 to 9 The wiring connection structure of the display device shown in FIG is not limited to Figures 11 to 13 structure.

[0104] Next, refer to Figures 14 to 16 The pixel structure of the display area DA is described. Figure 14 is an equivalent circuit diagram of one pixel of a display device according to an exemplary embodiment.

[0105] Reference Figure 14 , a pixel PX of the display device includes a plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 and T7 , a storage capacitor Cst, a light emitting diode LED and a plurality of signal lines 127 , 151 , 152 , 153 , 158 , 171 , 172 and 741 .

[0106] The display device includes a display area in which an image is displayed, and pixels PX are arranged in the display area in various forms.

[0107] The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1, two switching transistors, and compensation transistors T4, T5, T6, and T7 for operating the light emitting diode LED. The two switching transistors are connected to the scan line 151 and include a second transistor T2 and a third transistor T3. The compensation transistors T4, T5, T6, and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0108] The plurality of signal lines 127, 151, 152, 153, 158, 171, 172, and 741 may include a scan line 151, a previous scan line 152, a light emitting control line 153, a bypass control line 158, a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 158 may correspond to a portion of the previous scan line 152 or may be electrically connected thereto.

[0109] The scan line 151 is connected to the gate electrode G2 of the second transistor T2 and the gate electrode G3 of the third transistor T3 and transmits a scan signal Sn. The previous scan line 152 is connected to the gate electrode G4 of the fourth transistor T4 and transmits a previous scan signal Sn-1 applied to the pixel PX arranged in the previous stage. The light emission control line 153 is connected to a light emission controller (not shown) and transmits a light emission control signal EM to the gate electrode G5 of the fifth transistor T5 and the gate electrode G6 of the sixth transistor T6, thereby controlling the emission time of the light emitting diode LED. The bypass control line 158 transmits a bypass signal GB to the gate electrode G7 of the seventh transistor T7.

[0110] The data line 171 is a wiring for transmitting a data voltage Dm generated from a data driver (not shown), and the brightness of the light emitting diode LED (also referred to as a light emitting element) varies according to the data voltage Dm. The driving voltage line 172 applies a driving voltage ELVDD (also referred to as VDD, as shown in FIG. 1 ). Figure 1 When the fourth transistor T4 is turned on, the initialization voltage line 127 transmits the initialization voltage Vint (ie, VINT, as shown in FIG. 1 ). Figure 11 、 Figure 12 and Figure 13 The initialization voltage Vint initializes the voltage applied to the gate electrode G1 of the driving transistor T1. The common voltage line 741 applies a common voltage ELVSS (also referred to as VSS, as shown in FIG. 1 ). Figure 1 ). The voltage applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741 may be a constant voltage.

[0111] The driving transistor T1 adjusts the amount of driving current Id output from the driving transistor T1 based on the data voltage Dm. The driving current Id is applied to the light-emitting diode LED to control the brightness of the light-emitting diode LED based on the data voltage Dm. To this end, the first electrode S1 of the driving transistor T1 is configured to receive the driving voltage ELVDD. The first electrode S1 is connected to the driving voltage line 172 via the fifth transistor T5. Furthermore, the first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2, so that when the second transistor T2 is turned on, the data voltage Dm is also applied to the first electrode S1. The second electrode D1 (output electrode) of the driving transistor T1 is configured to output the driving current Id to the light-emitting diode LED. The second electrode D1 of the driving transistor T1 is connected to the light-emitting diode LED via the sixth transistor T6. Meanwhile, the gate electrode G1 of the driving transistor T1 is connected to the second storage electrode E2 of the storage capacitor Cst. Therefore, the voltage applied to the gate electrode G1 of the driving transistor T1 changes according to the voltage stored in the storage capacitor Cst, and the driving current Id output from the driving transistor T1 changes accordingly.

[0112] The second transistor T2 receives the data voltage Dm into the pixel PX. The gate electrode G2 of the second transistor T2 is connected to the scan line 151, the first electrode S2 of the second transistor T2 is connected to the data line 171, and the second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. When the second transistor T2 is turned on in response to the scan signal Sn transmitted via the scan line 151, the data voltage Dm transmitted via the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0113] The third transistor T3 transmits a compensation voltage (the sum of the data voltage Dm and the threshold voltage Vth of the driving transistor T1) to the second storage electrode E2 of the storage capacitor Cst. The data voltage Dm of the compensation voltage is changed by the driving transistor T1. The gate electrode G3 of the third transistor T3 is connected to the scan line 151, the first electrode S3 of the third transistor T3 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D3 of the third transistor T3 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1. When the third transistor T3 is turned on by the scan signal Sn transmitted via the scan line 151, the gate electrode G1 and the second electrode D1 of the driving transistor T1 are diode-connected, and the second electrode D1 of the driving transistor T1 is connected to the second storage electrode E2 of the storage capacitor Cst.

[0114] The fourth transistor T4 is used to initialize the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst. The gate electrode G4 of the fourth transistor T4 is connected to the previous scan line 152, the first electrode S4 of the fourth transistor T4 is connected to the initialization voltage line 127, and the second electrode D4 of the fourth transistor T4 is connected to the second storage electrode E2 of the storage capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second storage electrode E2 of the storage capacitor Cst based on the previous scan signal Sn-1 transmitted via the previous scan line 152. As a result, the gate voltage of the gate electrode G1 of the driving transistor T1 and the storage capacitor Cst are initialized. The initialization voltage Vint has a low voltage value, thereby serving as a voltage that can turn on the driving transistor T1.

[0115] The fifth transistor T5 is used to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 of the fifth transistor T5 is connected to the light emission control line 153, the first electrode S5 of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0116] The sixth transistor T6 is used to transfer the driving current Id output from the driving transistor T1 to the light emitting diode LED. The gate electrode G6 of the sixth transistor T6 is connected to the light emitting control line 153, the first electrode S6 of the sixth transistor T6 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D6 of the sixth transistor T6 is connected to the anode of the light emitting diode LED.

[0117] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the light emitting control signal EM transmitted through the light emitting control line 153. When the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current Id according to the voltage of the gate electrode G1 of the driving transistor T1 (that is, the voltage of the second storage electrode E2 of the storage capacitor Cst). The driving current Id flows to the light emitting diode LED through the sixth transistor T6. As the current I led The current flows through the light emitting diode LED, and the light emitting diode LED emits light.

[0118] The seventh transistor T7 is responsible for initializing the anode of the light-emitting diode LED. The gate electrode G7 of the seventh transistor T7 is connected to the bypass control line 158, the first electrode S7 of the seventh transistor T7 is connected to the anode of the light-emitting diode LED, and the second electrode D7 of the seventh transistor T7 is connected to the initialization voltage line 127. According to one embodiment, the bypass control line 158 can be connected to the previous scan line 152. In this case, the bypass signal GB is applied with a signal with the same timing as the previous scan signal Sn-1. In another embodiment, the bypass control line 158 may not be connected to the previous scan line 152 and may transmit a signal different from the previous scan signal Sn-1. When the seventh transistor T7 is turned on in response to the bypass signal GB, the initialization voltage Vint is applied to the anode of the light-emitting diode LED, thereby initializing the light-emitting diode LED.

[0119] A first storage electrode E1 of the storage capacitor Cst is connected to the driving voltage line 172, and a second storage electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. Therefore, the voltage charged across the second storage electrode E2 and the first storage electrode E1 at the storage capacitor Cst determines the voltage applied to the gate electrode G1 of the driving transistor T1. The second storage electrode E2 of the storage capacitor Cst receives the data voltage Dm through the second electrode D3 of the third transistor T3 or receives the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0120] On the other hand, an anode of the light emitting diode LED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7 , and a cathode of the light emitting diode LED is connected to the common voltage line 741 transmitting the common voltage ELVSS.

[0121] exist Figure 14 In the exemplary embodiment of FIG. 5 , the pixel PX includes seven transistors T1 to T7 and one capacitor Cst, but the present disclosure is not limited thereto, and the number of transistors, the number of capacitors, and their connections may be changed without departing from the scope of the present disclosure.

[0122] Figure 15 is a layout diagram of a pixel region of a display device according to an exemplary embodiment, and Figure 16 It is along Figure 15 A cross-sectional view taken along line XVI-XVI'.

[0123] Reference Figure 15The display device according to the exemplary embodiment includes a scan line 151 extending in a first direction DR1 and transmitting a scan signal Sn, a previous scan line 152 transmitting a previous scan signal Sn-1, a light emitting control line 153 transmitting a light emitting control signal EM, and an initialization voltage line 127 transmitting an initialization voltage Vint. The bypass signal GB may be transmitted through the previous scan line 152.

[0124] The display device includes a data line 171 extending in a second direction DR2 orthogonal to the first direction DR1 and transmitting a data voltage Dm, and a common voltage line 741 transmitting a common voltage ELVSS. Figure 15 and Figure 16 The first pixel PX1 shown in FIG corresponds to a pixel in which the driving voltage line 172 is replaced by Figures 1 to 3 Pixels in the common voltage line 741. Figure 15 The driving voltage line 172 connected to the second pixel PX2 shown in FIG is not replaced with the common voltage line 741, and a conventional driving voltage line 172 is provided. Hereinafter, the first pixel PX1 is described in comparison with the second pixel PX2.

[0125] The display device includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, and a light emitting diode LED.

[0126] Each channel of the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is provided in the semiconductor layer 130. At least some of the first electrodes and the second electrodes of the plurality of transistors T1, T2, T3, T4, T5, T6, and T7 are also provided in the semiconductor layer 130. The semiconductor layer 130 ( Figure 15 The semiconductor layer 130 may include a polycrystalline semiconductor such as polysilicon or an oxide semiconductor.

[0127] The semiconductor layer 130 includes a channel doped with N-type impurities or P-type impurities and a first doped region and a second doped region located on each side of the channel and having a higher doping concentration than the channel. The first doped region and the second doped region may correspond to the first electrode and the second electrode of the plurality of transistors T1, T2, T3, T4, T5, T6 and T7, respectively. If one of the first doped region and the second doped region is a source region, the other doped region may be a drain region. In addition, in the semiconductor layer 130, the region (e.g., channel) between the first electrode and the second electrode of different transistors may be doped so that the source electrode of one transistor and the drain electrode of another transistor may be electrically connected to each other.

[0128] Each channel of the transistors T1, T2, T3, T4, T5, T6, and T7 overlaps with the gate electrode of each of the transistors T1, T2, T3, T4, T5, T6, and T7, and is disposed between the first electrode and the second electrode of each of the transistors T1, T2, T3, T4, T5, T6, and T7. The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 may have substantially the same stacked structure. Hereinafter, the driving transistor T1 will be primarily described in detail, and the remaining transistors T2 to T7 will be schematically described.

[0129] The driving transistor T1 includes a channel, a first gate electrode 155 ( Figure 14 The gate electrode G1 shown in FIG, the first electrode S1 and the second electrode D1. In a plan view, the channel of the driving transistor T1 disposed between the first electrode S1 and the second electrode D1 overlaps with the first gate electrode 155. Figure 15 As shown in FIG, the channel is curved to form a longer channel length within a limited area. As the channel length becomes longer, the driving range of the gate voltage Vg applied to the first gate electrode 155 of the driving transistor T1 widens, and the driving current Id continuously increases according to the gate voltage Vg. Therefore, by changing the magnitude of the gate voltage Vg, the grayscale of the light emitted by the light-emitting diode LED can be more accurately controlled, and the display quality of the display device can be improved. In addition, because the channel extends in several directions rather than in one direction, the effects caused by directionality are offset in the manufacturing process, thereby reducing the impact of process dispersion. Therefore, it is possible to prevent degradation of image quality such as speckle defects (for example, uneven brightness occurring from pixel to pixel even when the same data voltage Dm is applied) due to the characteristics of the driving transistor T1, which may vary depending on the area of ​​the display device due to process dispersion. The shape of the channel is not limited to the Ω shape shown, and the channel can have various shapes.

[0130] The first gate electrode 155 overlaps the channel in a plan view. The first electrode S1 and the second electrode D2 are located on opposite sides of the channel. The extended portion of the storage line 126 is isolated and located on the first gate electrode 155. The extended portion of the storage line 126 overlaps the first gate electrode 155 in a plan view, with the second gate insulating layer located therebetween to form a storage capacitor Cst. The extended portion of the storage line 126 corresponds to the first storage electrode E1 of the storage capacitor Cst, and the first gate electrode 155 may correspond to Figure 145. The second storage electrode E2 of the storage capacitor Cst is shown in FIG. The extended portion of the storage line 126 is provided with an opening 56 so that the first gate electrode 155 can be connected to the first data connection member 71. In the opening 56, the upper surface of the first gate electrode 155 and the first data connection member 71 are electrically connected through the opening 61. The first data connection member 71 is connected to the second electrode D3 of the third transistor T3 to connect the first gate electrode 155 of the driving transistor T1 and the second electrode D3 of the third transistor T3.

[0131] The gate electrode G2 of the second transistor T2 may correspond to a portion of the scan line 151. The data line 171 is connected to the first electrode S2 of the second transistor T2 through the contact hole 62. The first electrode S2 and the second electrode D2 of the second transistor T2 may be disposed on the semiconductor layer 130.

[0132] The third transistor T3 may be formed by two transistors adjacent to each other. Figure 15 In the pixel PX shown in FIG, the third transistor T3 is shown to have a first portion extending to the left side relative to the folded portion of the semiconductor layer 130 and a second portion extending to the lower side. Each of these two portions functions as the third transistor T3 and has a structure in which the first electrode S3 of one of the two transistors is connected to the second electrode D3 of the other transistor. The gate electrodes of the two transistors may correspond to a portion of the scan line 151 or a portion protruding upward from the scan line 151. Such a structure may be referred to as a dual-gate structure and serves to prevent leakage current. The first electrode S3 of the third transistor T3 is connected to the first electrode S6 of the sixth transistor T6 and the second electrode D1 of the drive transistor T1. The second electrode D3 of the third transistor T3 is connected to the first data connection member 71 through the contact hole 63.

[0133] The fourth transistor T4 includes two fourth transistors formed where the previous scan line 152 and the semiconductor layer 130 meet. The gate electrode G4 of the fourth transistor T4 may correspond to a portion of the previous scan line 152. There is a structure in which the first electrode S4 of one of the two transistors is connected to the second electrode D4 of the other transistor. Similar to the third transistor T3, the fourth transistor T4 has a dual-gate structure that can prevent leakage current. The second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65, and the first data connection member 71 is connected to the second electrode D4 of the fourth transistor T4 through the contact hole 63.

[0134] As described above, the third transistor T3 and the fourth transistor T4 have a double-gate structure, and therefore, electron movement paths of their channels are blocked in an off state, thereby effectively preventing leakage current.

[0135] The gate electrode G5 of the fifth transistor T5 may correspond to a portion of the light emission control line 153. The driving voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 77, and the second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130.

[0136] Since the driving voltage line 172 connected to the pixel is replaced with the common voltage line 741 , the first pixel PX1 receives the driving voltage ELVDD from the adjacent pixel PX2 through the driving voltage connection line 172 c connected to the driving voltage line 172 of the adjacent pixel PX2 .

[0137] However, in the second pixel PX2 , the common voltage line 172 is connected to the first electrode S5 of the fifth transistor T5 through the contact hole 67 , and the second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1 through the semiconductor layer 130 .

[0138] The gate electrode G6 of the sixth transistor T6 may correspond to a portion of the light emission control line 153. The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 through the contact hole 69, and the first electrode S6 of the sixth transistor T6 is connected to the second electrode D1 of the driving transistor T1 through the semiconductor layer 130.

[0139] A gate electrode G7 of the seventh transistor T7 may correspond to a portion of the previous scan line 152. A first electrode S7 of the seventh transistor T7 is connected to the second electrode D6 of the sixth transistor T6, and a second electrode D7 of the seventh transistor T7 is connected to the first electrode S4 of the fourth transistor T4.

[0140] The storage capacitor Cst includes a first storage electrode E1 and a second storage electrode E2 that overlap with each other via a second gate insulating layer 142. The second storage electrode E2 of the storage capacitor Cst may correspond to the first gate electrode 155 of the drive transistor T1, and the first storage electrode E1 of the storage capacitor Cst may correspond to an extension of the storage line 126. Here, the second gate insulating layer 142 may be formed of a dielectric material, and the capacitance is determined by the charge charged in the storage capacitor Cst and the voltage between the first storage electrode E1 and the second storage electrode E2. By using the first gate electrode 155 of the drive transistor T1 as the second storage electrode E2 of the storage capacitor Cst, space for forming the storage capacitor Cst can be secured in a space that is narrowed due to the large area of ​​the channel of the drive transistor T1 occupying within the pixel PX.

[0141] The first storage electrode E1 of the first pixel PX1 receives the driving voltage ELVDD through the driving voltage connection line 172c. Therefore, the storage capacitor Cst stores charges corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 through the driving voltage connection line 172c and the gate voltage Vg of the first gate electrode 155.

[0142] However, the driving voltage line 172 is connected to the first storage electrode E1 of the second pixel PX2 through the contact hole 68. Therefore, the storage capacitor Cst of the second pixel PX2 stores charges corresponding to the difference between the driving voltage ELVDD transmitted to the first storage electrode E1 through the driving voltage line 172 and the gate voltage Vg of the first gate electrode 155.

[0143] The second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64. The first electrode (eg, Figure 16 191) shown in FIG. 1 is connected to the third data connection member 73 through the contact hole 81. The first electrode may be a pixel electrode of the pixel PX.

[0144] The parasitic capacitor control pattern 79 may be formed between the dual gate electrodes of the third transistor T3. A parasitic capacitor may exist inside the pixel PX, and if the voltage applied to the parasitic capacitor changes, the image quality characteristics of the display device may be degraded. Figure 15 In the first pixel PX1 shown in FIG, a common voltage line 741 is provided instead of the driving voltage line 172, and therefore, the driving voltage line 172 and the parasitic capacitor control pattern 79 are connected. However, in the second pixel PX2, the parasitic capacitor control pattern 79 and the driving voltage line 172 are connected through the contact hole 66. Therefore, it is possible to prevent the image quality characteristics from being deteriorated by applying the driving voltage ELVDD having a constant DC voltage to the parasitic capacitor. The parasitic capacitor control pattern 79 may be provided at a position corresponding to the driving voltage line 172. Figure 15 The parasitic capacitor control pattern 79 may be applied with a voltage other than the driving voltage ELVDD.

[0145] One terminal of the first data connection member 71 is connected to the first gate electrode 155 of the driving transistor T1 through the contact hole 61 , and the other terminal of the first data connection member 71 is connected to the second electrode D3 of the third transistor T3 and the second electrode D4 of the fourth transistor T4 through the contact hole 63 .

[0146] One terminal of the second data connection member 72 is connected to the first electrode S4 of the fourth transistor T4 through the contact hole 65 , and the other terminal of the second data connection member 72 is connected to the initialization voltage line 127 through the contact hole 64 .

[0147] The third data connection member 73 is connected to the second electrode D6 of the sixth transistor T6 via the contact hole 69 .

[0148] In the following, except for reference Figure 15 , also refer to Figure 16 A cross-sectional structure of a display device according to an exemplary embodiment is described in a stacking order.

[0149] The display device according to an exemplary embodiment includes a first substrate 110 .

[0150] The first substrate 110 may include a plastic layer and a barrier layer. In some embodiments, the plastic layer and the barrier layer may be alternately stacked.

[0151] The plastic layer may include one selected from the group consisting of polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), poly(ethylene terephthalate) (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), poly(arylene ether sulfone), and any combination thereof.

[0152] The barrier layer may include at least one of silicon oxide, silicon nitride, and aluminum oxide. The barrier layer may include an inorganic material, but is not limited thereto.

[0153] The buffer layer 112 is disposed on the first substrate 110, and an additional barrier layer 111 may be disposed between the buffer layer 112 and the first substrate 110. The buffer layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, and aluminum oxide, or an organic insulating material such as polyimide acryl.

[0154] A semiconductor layer 130 including a channel, a first electrode, and a second electrode of each of the plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 is disposed on the buffer layer 112 .

[0155] The first gate insulating layer 141 is disposed on the semiconductor layer 130 to cover the semiconductor layer 130. A first gate conductor layer including a first gate electrode 155, a scan line 151, a previous scan line 152, and a light emitting control line 153 is disposed on the first gate insulating layer 141.

[0156] The second gate insulating layer 142 is disposed on the first gate conductive layer to cover the first gate conductive layer. The first gate insulating layer 141 and the second gate insulating layer 142 may include an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide, as well as an organic insulating material.

[0157] A second gate conductor layer including the storage line 126 , the initialization voltage line 127 , and the parasitic capacitor control pattern 79 is disposed on the second gate insulating layer 142 .

[0158] The interlayer insulating layer 160 is disposed on the second gate conductor layer to cover the second gate conductor layer. The interlayer insulating layer 160 may include an inorganic insulating material such as silicon nitride, silicon oxide, and aluminum oxide, and may include an organic insulating material.

[0159] A data conductor layer including a data line 171, a driving voltage line 172, a first data connection member 71, a second data connection member 72, and a third data connection member 73 is disposed on the interlayer insulating layer 160. The first data connection member 71 may be connected to the first gate electrode 155 through the contact hole 61.

[0160] The passivation layer 180 is disposed on the data conductor layer to cover the data conductor layer. The passivation layer 180 may be a planarization layer and may include an organic insulating material or an inorganic insulating material.

[0161] The first electrode 191 is disposed on the passivation layer 180. The first electrode 191 is connected to the third data connection member 73 via a contact hole 81 formed in the passivation layer 180.

[0162] A partition layer 350 is disposed on the passivation layer 180 and the first electrode 191. The partition layer 350 has an opening 351 that overlaps with the first electrode 191. An emission layer 370 is disposed in the opening 351. A second electrode 270 is disposed on the emission layer 370 and the partition layer 350. The first electrode 191, the emission layer 370, and the second electrode 270 may form a light-emitting diode (LED). The first electrode 191 may be a pixel electrode, and the second electrode 270 may be a common electrode.

[0163] According to an exemplary embodiment, the pixel electrode may be an anode serving as a hole injection electrode, and the common electrode may be a cathode serving as an electron injection electrode. Conversely, the pixel electrode may be a cathode, and the common electrode may be an anode. When holes and electrons are injected from the pixel electrode and the common electrode into the emissive layer 370, excitons formed by the combination of the holes and electrons are emitted when they transition from an excited state to a ground state.

[0164] The encapsulation layer 400 for protecting the light emitting element LED is disposed on the second electrode 270. Figure 16 As shown in FIG, the encapsulation layer 400 may be in contact with the second electrode 270, or according to another exemplary embodiment, the encapsulation layer 400 may be spaced apart from the second electrode 270.

[0165] The encapsulation layer 400 may be a thin film encapsulation layer in which an inorganic film and an organic film are stacked, and may include three layers including an inorganic film, an organic film, and an inorganic film. According to an exemplary embodiment, a capping layer and / or a functional layer may be provided between the second electrode 270 and the encapsulation layer 400 .

[0166] Figure 17 FIG is a layout diagram of a pixel region of a display device according to an exemplary embodiment. Figure 17 The display device includes a plurality of signal lines 127, 151, 152, 153, 171, 172, and 741. The plurality of signal lines 127, 151, 152, 153, 171, 172, and 741 may include a scan line 151 arranged in a first direction DR1, a previous scan line 152, a light emitting control line 153, a data line 171 arranged in a second direction DR2, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741.

[0167] The display device includes a driving transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a storage capacitor Cst.

[0168] Each channel of the driving transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 is disposed in the semiconductor layer 130. At least a portion of the first and second electrodes of the plurality of transistors T1, T2, T3, T4, T5, and T6 may be disposed in the semiconductor layer 130.

[0169] Each of the plurality of signal lines 127 , 151 , 152 , 153 , 171 , 172 , and 741 and the semiconductor layer 130 are connected through a plurality of contact holes 82 , 83 , 84 , 85 , 86 , 87 , and 88 .

[0170] Each transistor and a plurality of signal lines 127, 151, 152, 153, 171, 172 and 741 are connected to Figure 15 The corresponding transistors and signal lines shown in FIG are similar, and detailed descriptions of the same constituent elements are omitted.

[0171] Reference Figure 17 , the common voltage line 741 is disposed outside the regions of the pixels PX1, PX2, and PX3. Figure 15 In the display device shown in FIG, the driving voltage line 172 of some pixels PX1 is replaced with a common voltage line 741, and the corresponding pixel PX1 receives the driving voltage ELVDD from the adjacent pixel through the driving voltage connection line 172c.

[0172] Return Reference Figure 17In the display device shown in FIG, the common voltage line 741 is separately provided outside the regions of the pixels PX1, PX2, and PX3. Therefore, the common voltage line 741 can be provided without removing any of the normal driving voltage lines 172 of the pixels PX1, PX2, and PX3.

[0173] Right now, Figure 15 Corresponding to the above description Figures 1 to 3 、 Figure 7 and Figure 8 An exemplary embodiment of the present invention, and Figure 17 Corresponding to the above description Figures 4 to 6 、 Figure 9 and Figure 10 An exemplary embodiment of .

[0174] Figure 17 and Figure 15 The difference is that the initialization voltage line 127 is arranged in the second direction DR2 instead of the first direction DR1. The initialization voltage line 127 may also be arranged in a region between adjacent pixels PX1, PX2, and PX3.

[0175] While the present disclosure has been described in conjunction with what are presently considered to be practical exemplary embodiments, it is to be understood that the present disclosure is not limited to the exemplary embodiments. On the contrary, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the present disclosure.

Claims

1. A display device, wherein: The display device includes: A substrate including a display area and a non-display area; An external common voltage line and an external driving voltage line are arranged in the non-display area; a plurality of pixels and common voltage lines, arranged in the display area; and a driving voltage line connected to each of the plurality of pixels, wherein, in a plan view, a subset of the plurality of pixels overlaps with the common voltage line in the display area, and Each of the external driving voltage line and the external common voltage line includes a plurality of portions separated from each other.

2. The display device according to claim 1, wherein The display device further includes: External initialization voltage line, and The external initialization voltage line includes a plurality of parts separated from each other.

3. The display device according to claim 1, wherein The external common voltage line is disposed around at least two edges of the display area.

4. The display device according to claim 1, wherein The common voltage lines further include a first common voltage line arranged in a first direction and a second common voltage line arranged in a second direction.

5. The display device according to claim 2, wherein Each of the external initialization voltage line, the external driving voltage line, and the external common voltage line has a multi-layer structure. The display device according to claim 2 , wherein: The display device further includes: an initialization voltage line, arranged in the display area, Wherein, the external initialization voltage line and the initialization voltage line are connected to each other.

7. The display device according to claim 5, wherein: Each of the external initialization voltage line, the external driving voltage line, and the external common voltage line includes a first layer and a second layer, The first layer is provided on the same layer as the first source / drain layer of the display area, and The second layer and the second source / drain layer of the display area are arranged on the same layer.

8. The display device according to claim 1, wherein Each pixel of the plurality of pixels includes a first electrode, an emission layer, and a second electrode, and The second electrode is provided across the entire panel of the plurality of pixels.

9. The display device according to claim 8, wherein The second electrode contacts the external common voltage line in the non-display area.

10. The display device according to claim 1, wherein The display device further includes: A driving voltage connection line is arranged in a first direction, Wherein, the common voltage line and the driving voltage line are arranged in the second direction, A width of the driving voltage connection line overlapping the common voltage line is narrower than a width of the driving voltage connection line overlapping the driving voltage line.

11. The display device according to claim 1, wherein Each of the plurality of portions of each of the external driving voltage line and the external common voltage line is connected to each other by a connection member.

12. The display device according to claim 1, wherein The driving voltage line is connected to the subset of the plurality of pixels via a driving voltage connection line.

13. The display device according to claim 1, wherein The external common voltage line is divided through the display area.

14. The display device according to claim 11, wherein The connecting member is disposed on the same layer as the gate line, the data line or the pixel electrode in the display area.

15. The display device according to claim 14, wherein The connection member includes a first connection member provided on the same layer as the gate line and a second connection member provided on the same layer as the pixel electrode, and The first connecting member and the second connecting member overlap each other in a plan view.

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