Display device and optical device

Abstract

A display device and an optical device are provided. The display device includes: a display element layer disposed on a substrate, the display element layer including a first electrode, a light emitting layer, and a second electrode; a retardation layer disposed on the display element layer, the retardation layer including at least a capping layer; and a wire grid polarizer disposed on the retardation layer, the wire grid polarizer including a wire grid pattern in which a metal pattern and a grid pattern are stacked on each other, the metal pattern disposed on the capping layer and having a thickness in a range of about 3 nm to about 7 nm.

Description

Technical Field

[0001] The present disclosure relates to a display device and an optical device. Background Art

[0002] A head-mounted display (HMD) is a device that is worn on the user's head in the form of glasses or a helmet to display images in focus at a close distance in front of the user's eyes. A head-mounted display can implement virtual reality (VR) or augmented reality (AR).

[0003] A head-mounted display magnifies an image displayed in a small display device by using a plurality of lenses, and displays the magnified image. Therefore, a display device applied to a head-mounted display needs to provide a high-resolution image, for example, an image with a resolution of 3000 PPI (pixels per inch) or higher. For this purpose, an organic light-emitting diode on silicon (OLEDoS), which is a small organic light-emitting display device with high resolution, is used as a display device applied to a head-mounted display. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is provided on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided.

[0004] It should be understood that this background section is intended, in part, to provide a useful background for understanding the technology. However, this background section may also include ideas, concepts, or cognitions that were not already known or understood by those skilled in the relevant art prior to the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0005] Aspects of the present disclosure provide a display device and an optical device capable of improving the adhesive strength of a wire grid polarizer.

[0006] However, the various aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0007] According to aspects of the present disclosure, a display device may include: a display element layer disposed on a substrate, the display element layer including a first electrode, a light-emitting layer, and a second electrode; a delay layer disposed on the display element layer, the delay layer including at least a capping layer; and a wire grid polarizer disposed on the delay layer, the wire grid polarizer including a wire grid pattern in which a metal pattern and a grid pattern are stacked on each other, wherein the metal pattern is disposed on the capping layer and has a thickness in the range of about 3 nm to about 7 nm.

[0008] In an embodiment, the capping layer may include any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0009] In an embodiment, the metal pattern may include any one of titanium (Ti), chromium (Cr), nickel (Ni), tantalum (Ta), and tungsten (W).

[0010] In an embodiment, the grid pattern may be disposed on the metal pattern, and a thickness of the grid pattern may be greater than a thickness of the metal pattern.

[0011] In an embodiment, the width of the grid pattern may be equal to the width of the metal pattern.

[0012] In an embodiment, a width of a lower surface of the metal pattern may be greater than a width of an upper surface of the metal pattern.

[0013] In an embodiment, the width of the upper surface of the metal pattern may be equal to the width of the grid pattern.

[0014] In an embodiment, the width of the metal pattern may gradually increase from an upper surface to a lower surface of the metal pattern.

[0015] In an embodiment, a side surface of the metal pattern may have an inclination, and an inner angle formed between the side surface of the metal pattern and a lower surface of the metal pattern may be greater than or equal to about 60 degrees and less than about 90 degrees.

[0016] In an embodiment, the display device may further include a planarization layer disposed on the wire grid polarizer, wherein the wire grid polarizer includes an air layer disposed in a region separated by the capping layer, the wire grid pattern, and the planarization layer.

[0017] According to aspects of the present disclosure, a display device may include: a display element layer disposed on a substrate, the display element layer including a first electrode, a light-emitting layer, and a second electrode; a delay layer disposed on the display element layer, the delay layer including at least a capping layer; and a wire grid polarizer disposed on the delay layer, the wire grid polarizer including a wire grid pattern in which a first metal pattern, a second metal pattern, and a grid pattern are stacked on each other, wherein the first metal pattern is disposed on the capping layer, the second metal pattern is disposed on the first metal pattern, and the grid pattern is disposed on the second metal pattern.

[0018] In an embodiment, the capping layer may include any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0019] In embodiments, the first metal pattern and the second metal pattern may include different materials.

[0020] In an embodiment, each of the first and second metal patterns may include any one of titanium (Ti), chromium (Cr), nickel (Ni), tantalum (Ta), and tungsten (W).

[0021] In an embodiment, the thickness of the first metal pattern and the thickness of the second metal pattern may be different from each other.

[0022] In an embodiment, the thickness of the first metal pattern may be greater than the thickness of the second metal pattern.

[0023] According to aspects of the present disclosure, an optical device may include a display device and an optical path changing component disposed on the display device, wherein the display device includes: a display element layer disposed on a substrate, the display element layer including a first electrode, a light-emitting layer, and a second electrode; a delay layer disposed on the display element layer, the delay layer including at least a capping layer; and a wire grid polarizer disposed on the delay layer, the wire grid polarizer including a wire grid pattern in which a metal pattern and a grid pattern are stacked on each other, wherein the metal pattern is disposed on the capping layer and has a thickness in the range of about 3 nm to about 7 nm.

[0024] In an embodiment, the capping layer may include any one of silicon nitride, silicon oxide, and silicon oxynitride.

[0025] In an embodiment, the width of the metal pattern may gradually increase from an upper surface to a lower surface of the metal pattern.

[0026] In an embodiment, the metal pattern may include a first metal pattern disposed on the capping layer and a second metal pattern disposed on the first metal pattern, and the grid pattern is disposed on the second metal pattern.

[0027] The display device and the optical device according to the embodiment may improve the adhesive strength between the retardation layer and the wire grid polarizer, and thus may prevent the occurrence of a film swelling defect.

[0028] However, the effects according to the embodiments of the present disclosure are not limited to the above-described effects, and various other effects are also incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0030] Figure 1 is an exploded schematic perspective view showing a display device according to an embodiment;

[0031] Figure 2 is a block diagram showing a display device according to an embodiment;

[0032] Figure 3 is a schematic diagram of an equivalent circuit of a first pixel according to an embodiment;

[0033] Figure 4 is a plan view showing an example of a display panel according to an embodiment;

[0034] Figure 5 It shows Figure 4 A plan view of an embodiment of a display area;

[0035] Figure 6 It is shown along Figure 5 A schematic cross-sectional view of an example of a display panel taken along line XX';

[0036] Figure 7 yes Figure 6 An enlarged schematic diagram of region A;

[0037] Figure 8 is a schematic cross-sectional view showing another example of a display panel according to an embodiment;

[0038] Figure 9 yes Figure 8 An enlarged schematic diagram of region B;

[0039] Figure 10 is a schematic cross-sectional view showing another example of a display panel according to an embodiment;

[0040] Figure 11 yes Figure 10 An enlarged schematic diagram of region C;

[0041] Figure 12 is a schematic plan view schematically illustrating a wire grid pattern;

[0042] Figure 13 yes Figure 11 An enlarged schematic diagram of region D;

[0043] Figure 14 is a schematic cross-sectional view showing an example of a display panel according to an embodiment;

[0044] Figure 15 is a schematic cross-sectional view showing an example of a display panel according to an embodiment;

[0045] Figure 16 is a schematic cross-sectional view showing an example of a display panel according to an embodiment;

[0046] Figure 17 is an image of the substrate according to Comparative Example 1 after the cross-cut adhesion strength test;

[0047] Figure 18 is an image of the substrate according to Example 1 after cross-cut adhesion strength testing;

[0048] Figure 19 is a graph showing cross-cut adhesive strength according to the thickness of the titanium layer;

[0049] Figure 20is a graph showing transmittance of a substrate according to the thickness of a titanium layer;

[0050] Figure 21 is an image of a display panel manufactured according to Comparative Example 2;

[0051] Figure 22 is an image of a display panel manufactured according to Example 3;

[0052] Figure 23 is a schematic perspective view showing a head-mounted display according to an embodiment;

[0053] Figure 24 It shows Figure 23 an exploded schematic perspective view of an example of a head-mounted display; and

[0054] Figure 25 is a schematic perspective view showing a head-mounted display according to the embodiment. DETAILED DESCRIPTION

[0055] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate embodiments. However, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0056] In the drawings, the size, thickness, ratio and magnitude of elements may be exaggerated for ease of description and clarity. Like numbers refer to like elements throughout.

[0057] As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0058] Throughout the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for purposes of its meaning and interpretation. For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or."

[0059] In the specification and claims, the phrase "at least one of" is intended to include, for purposes of its meaning and interpretation, the meaning of "at least one selected from the group of." For example, "at least one of A and B" may be understood to mean "A, B, or A and B."

[0060] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0061] The term "overlap" or "overlapped" means that a first object may be above or below a second object or located to one side of the second object, and vice versa. Additionally, the term "overlap" may include stacking, facing, extending over, covering, or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art.

[0062] The terms "facing" and "facing" mean that a first element can be directly or indirectly opposite to a second element. In the case where a third element is interposed between the first and second elements, although the first and second elements still face each other, the first and second elements can be understood to be indirectly opposite to each other.

[0063] When an element is described as “not overlapping” or “not overlapping” another element, this may include the elements being spaced apart, offset, or spaced apart from each other, or any other suitable terminology as would be appreciated and understood by one of ordinary skill in the art.

[0064] When the terms “comprises / comprising,” “includes / including,” and / or “has / have / having,” and variations thereof, are used in this specification, the terms “comprises / comprising,” “includes / including,” and / or “has / have / having,” indicate the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0065] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below may be named the second element without departing from the teachings of the present disclosure. Similarly, the second element may also be named the first element.

[0066] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0067] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0068] It will be understood that in this specification, when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, the element can be directly set on, connected to or coupled to the above-mentioned another element, or an intervening element may be set between the element and the above-mentioned another element.

[0069] It will be understood that the term "connected to" or "coupled to" may include a physical connection or coupling or an electrical connection or coupling.

[0070] Each of the multiple features of each embodiment can be combined or combined with each other in part or in whole. Each embodiment can be implemented independently of each other, or can be implemented together.

[0071] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0072] Figure 1 is an exploded schematic perspective view showing a display device according to an embodiment. Figure 2 is a block diagram illustrating a display device according to an embodiment.

[0073] Reference Figure 1 and Figure 2, the display device 10 according to the embodiment may be a device for displaying moving images or still images. Within the spirit and scope of the present disclosure, the display device 10 according to the embodiment may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 according to the embodiment may be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. For example, within the spirit and scope of the present disclosure, the display device 10 according to the embodiment may be applied to smart watches, watch phones, and head-mounted displays (HMDs) for realizing virtual reality and augmented reality.

[0074] The display device 10 according to the embodiment may include a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit (timing controller) 400 , and a power supply circuit (power supply unit) 500 .

[0075] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle at which the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be a right angle or a rounded angle with a selectable curvature. The planar shape of the display panel 100 is not limited to a quadrilateral and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may be consistent with the planar shape of the display panel 100, but the embodiment is not limited thereto.

[0076] The display panel 100 may include a display area DAA displaying an image and a non-display area NDA not displaying an image. Figure 2 As shown in .

[0077] The display area DAA may include a plurality of pixels, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0078] A plurality of pixels may be arranged or disposed in a matrix in a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 while being disposed in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 while being disposed in the first direction DR1.

[0079] The plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL may include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0080] Each of the plurality of unit pixels UPX may include a plurality of pixels PX1, PX2, and PX3. The plurality of pixels PX1, PX2, and PX3 may include Figure 3 The plurality of pixel transistors shown in FIG. 1 and FIG. 2 are formed by a semiconductor process and can be disposed on a semiconductor substrate SSUB (see FIG. 2 ). Figure 6 For example, the plurality of data transistors of the data driver 700 may be formed of a complementary metal oxide semiconductor (CMOS).

[0081] Each of the plurality of pixels PX1, PX2, and PX3 can be connected to any one of a plurality of write scan lines GWL, any one of a plurality of control scan lines GCL, any one of a plurality of bias scan lines GBL, any one of a plurality of first emission control lines EL1, any one of a plurality of second emission control lines EL2, and any one of a plurality of data lines DL. Each of the plurality of pixels PX1, PX2, and PX3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from the light-emitting element according to the data voltage.

[0082] The non-display area NDA may include a scan driver 610 , an emission driver 620 , and a data driver 700 .

[0083] The scan driver 610 may include a plurality of scan transistors, and the emission driver 620 may include a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 6 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors can be formed by CMOS. Although Figure 2 6 shows that the scan driver 610 is disposed on the left side of the display area DAA and the emission driver 620 is disposed on the right side of the display area DAA, but the embodiment is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on at least one of the left and right sides of the display area DAA.

[0084] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals based on the scan timing control signal SCS from the timing control circuit 400 and sequentially output them to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 may generate bias scan signals based on the scan timing control signal SCS and sequentially output them to the bias scan lines GBL.

[0085] The emission driver 620 may include a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate first emission control signals based on the emission timing control signal ECS and sequentially output them to the first emission control line EL1. The second emission control driver 622 may generate second emission control signals based on the emission timing control signal ECS and sequentially output them to the second emission control line EL2.

[0086] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 6 For example, the plurality of data transistors may be formed of CMOS.

[0087] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. For example, pixels PX1, PX2, and PX3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected pixels PX1, PX2, and PX3.

[0088] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface or a certain surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 may be used to dissipate heat generated from the display panel 100, or play a role in dissipating heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0089] The circuit board 300 may be electrically connected to the first pad portion PDA1 of the display panel 100 (see FIG. 1 ) by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. Although the circuit board 300 is Figure 1 Although shown as unfolded in FIG, the circuit board 300 may be bent. For example, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The one end of the circuit board 300 may be the first pad portion PDA1 of the circuit board 300 connected to the display panel 100 by using a conductive adhesive member (see FIG. Figure 4 ) of a plurality of first pads PD1 (see Figure 4 ) at the opposite end of the other end.

[0090] The timing control circuit 400 can receive digital video data DATA and timing signals input from the outside. In response to the timing signals, the timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0091] The power supply circuit 500 can generate a plurality of panel driving voltages according to the power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD and a third driving voltage VINT and supply them to the display panel 100. Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described.

[0092] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and attached to one surface or a certain surface of the circuit board 300. For example, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 may be supplied to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0093] For example, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be disposed in the non-display area NDA of the display panel 100. For example, the timing control circuit 400 may include a plurality of timing transistors, and each power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed on the semiconductor substrate SSUB (see FIG. 1 ) by a semiconductor process. Figure 6 ). For example, a plurality of timing transistors and a plurality of power transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply unit 500 may be provided between the data driver 700 and the first pad portion PDA1 (see Figure 4 )between.

[0094] Figure 3 is a schematic diagram of an equivalent circuit of a first pixel according to an embodiment.

[0095] Reference Figure 3 , the first pixel PX1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2 and the data line DL. The first pixel PX1 can be connected to a first driving voltage VSS (see FIG. 1 ) corresponding to a low potential voltage applied thereto. Figure 2 ) of the first driving voltage line VSL, to which a second driving voltage VDD corresponding to a high potential voltage is applied (see Figure 2 ) and applying a third driving voltage VINT corresponding to the initialization voltage (see Figure 2 ). For example, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. For example, the first drive voltage VSS may be lower than the third drive voltage VINT. The second drive voltage VDD may be higher than the third drive voltage VINT.

[0096] The first pixel PX1 may include a plurality of transistors T1 to T6 , a light emitting element LE, a first capacitor CP1 , and a second capacitor CP2 .

[0097] The light-emitting element LE emits light in response to the driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE may be proportional to the driving current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiment is not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0098] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (hereinafter referred to as "driving current Ids") flowing between a source electrode and a drain electrode of the first transistor T1 according to a voltage applied to the gate electrode of the first transistor T1. The first transistor T1 may include a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0099] The second transistor T2 may be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL may be applied to the one electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0100] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. As a result, the gate electrode and drain electrode of the first transistor T1 are connected, so the first transistor T1 can operate like a diode. The third transistor T3 may include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0101] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Thus, the driving current Ids of the first transistor T1 may be supplied to the light emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0102] The fifth transistor T5 may be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL may be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0103] The sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0104] The first capacitor CP1 may be formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0105] The second capacitor CP2 may be formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 may include one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0106] The first node N1 may be a junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and the one electrode of the second capacitor CP2. The second node N2 may be a junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 may be a junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0107] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the embodiment is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. For example, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0108] Despite Figure 3 FIG. 4 shows that the first pixel PX1 may include six transistors T1 to T6 and two capacitors CP1 and CP2 , but it should be noted that the equivalent circuit diagram of the first pixel PX1 is not limited to FIG. Figure 3 For example, the number of transistors and the number of capacitors of the first pixel PX1 are not limited to Figure 3 The example shown in .

[0109] The second pixel PX2 (see Figure 2 ) and the equivalent circuit diagram of the third pixel PX3 (see Figure 2 ) can be combined with the equivalent circuit diagram Figure 3 The equivalent circuit diagram of the first pixel PX1 is substantially the same as that described above. Therefore, in the specification, descriptions of the equivalent circuit diagram of the second pixel PX2 and the equivalent circuit diagram of the third pixel PX3 will be omitted.

[0110] Figure 4 is a plan view showing an example of a display panel according to an embodiment.

[0111] Reference Figure 4 The display area DAA of the display panel 100 according to the embodiment may include a plurality of pixels arranged or disposed in a matrix form. The non-display area NDA of the display panel 100 according to the embodiment may include a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0112] The scan driver 610 may be provided on a first side of the display area DAA, and the emission driver 620 may be provided on a second side of the display area DAA. For example, the scan driver 610 may be provided on one side of the display area DAA in the first direction DR1, and the emission driver 620 may be provided on the other side of the display area DAA in the first direction DR1. For example, the scan driver 610 may be provided on the left side of the display area DAA, and the emission driver 620 may be provided on the right side of the display area DAA. However, embodiments are not limited thereto, and the scan driver 610 and the emission driver 620 may be provided on at least one of the first side and the second side of the display area DAA.

[0113] The first pad portion PDA1 may include a portion connected to the circuit board 300 (see FIG. Figure 1 ) pads or raised plurality of first pads PD1. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2.

[0114] The first pad portion PDA1 may be disposed in the second direction DR2 outside the data driver 700. For example, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0115] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 is operating normally. The plurality of second pads PD2 may be connected to a jig or a probe during the inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0116] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 may distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, thereby reducing the number of the plurality of first pads PD1. The first distribution circuit 710 may be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be disposed on a side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 may be disposed on the lower side of the display area DAA.

[0117] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610 and the emission driver 620. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the plurality of pixels in the display area DAA. The second distribution circuit 720 can be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0118] Figure 5 It shows Figure 4 A plan view of an embodiment of a display area.

[0119] Reference Figure 5 Each of the plurality of unit pixels UPX may include a first emission area EA1 serving as an emission area for a first pixel PX1, a second emission area EA2 serving as an emission area for a second pixel PX2, and a third emission area EA3 serving as an emission area for a third pixel PX3. In other words, the unit pixel UPX may include a unit emission area UEA, and the unit emission area UEA may include the first emission area EA1, the second emission area EA2, and the third emission area EA3 described above.

[0120] Each of the plurality of pixels PX may include a first emission area EA1 as an emission area of ​​a first pixel PX1 , a second emission area EA2 as an emission area of ​​a second pixel PX2 , and a third emission area EA3 as an emission area of ​​a third pixel PX3 .

[0121] Each of the first, second, and third emission regions EA1, EA2, and EA3 may have a polygonal shape, a circular shape, an elliptical shape, or an irregular planar shape, but the shape of each of the emission regions EA1, EA2, and EA3 is not limited thereto.

[0122] The maximum lengths of the first emission area EA1, the second emission area EA2, and the third emission area EA3 in the first direction DR1 may be the same. However, the maximum length of the first emission area EA1 in the first direction DR1 may be smaller than the maximum lengths of the second emission area EA2 and the third emission area EA3 in the first direction DR1. The maximum lengths of the second emission area EA2 and the third emission area EA3 in the first direction DR1 may be substantially the same.

[0123] The maximum lengths of the first emission area EA1, the second emission area EA2, and the third emission area EA3 in the second direction DR2 may be the same. However, the maximum length of the first emission area EA1 in the second direction DR2 may be greater than the maximum lengths of the second emission area EA2 and the third emission area EA3 in the second direction DR2. The maximum length of the second emission area EA2 in the second direction DR2 may be greater than the maximum length of the third emission area EA3 in the second direction DR2. However, embodiments are not limited thereto, and the maximum length of the first emission area EA1 in the second direction DR2 may be less than the maximum length of the second emission area EA2 in the second direction DR2.

[0124] The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a shape as shown in a plan view. Figure 5 The first, second, and third emission areas EA1, EA2, and EA3 may have polygonal, circular, elliptical, or irregular shapes other than the hexagonal shape in a plan view.

[0125] like Figure 5 As shown in FIG, in each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The second emission area EA2 and the third emission area EA3 may be adjacent to each other in the second direction DR2. The area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be different.

[0126] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the first color light may be light in a red wavelength band, the second color light may be light in a green wavelength band, and the third color light may be light in a blue wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 380 nm to approximately 480 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0127] like Figure 5As described in , each of the plurality of pixels PX may include three emission areas EA1, EA2, and EA3, but the embodiment is not limited thereto. For example, each of the plurality of pixels PX may include four emission areas.

[0128] The layout of the emission areas of the plurality of pixels PX is not limited to Figure 5 For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged or disposed in a first direction DR1, a diamond structure in which the emission regions are arranged or disposed, or a structure in which the emission regions are arranged or disposed in a diamond shape. Structure or Figure 5 A hexagonal structure is shown in which emission areas having a hexagonal shape in a plan view are arranged or disposed side by side.

[0129] Figure 6 It is shown along Figure 5 Schematic cross-sectional view of an example of a display panel taken along line XX'. Figure 7 yes Figure 6 An enlarged schematic diagram of area A.

[0130] Reference Figure 6 and Figure 7 The display panel 100 may include a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation film TFE, and an optical layer OPL. The semiconductor backplane SBP and the light emitting element backplane EBP may be referred to as a substrate.

[0131] The semiconductor base plate SBP may include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR. Figure 3 The first to sixth transistors T1 to T6 are described.

[0132] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the aforementioned first-type impurities. For example, if the first-type impurities are p-type impurities, the second-type impurities may be n-type impurities. Alternatively, if the first-type impurities are n-type impurities, the second-type impurities may be p-type impurities.

[0133] Each of the plurality of well regions WA may include a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0134] The lower insulating film BINS may be provided between the gate electrode GE and the well area WA. The side insulating film SINS may be provided on the side surface of the gate electrode GE. The side insulating film SINS may be provided on the lower insulating film BINS.

[0135] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0136] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. Due to the lower insulating film BINS, the first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA. Due to the lower insulating film BINS, the second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased. Therefore, the length of the channel region CH of each of the multiple pixel transistors PTR can be increased, so that breakdown and hot carrier phenomena that may be caused by a short channel can be prevented.

[0137] The first semiconductor insulating film SINS1 may be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be made of silicon carbonitride (SiCN) or silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0138] The second semiconductor insulating film SINS2 may be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0139] A plurality of contact terminals CTE may be provided on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source area SA, and the drain area DA of each of the plurality of pixel transistors PTR through a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of these.

[0140] The third semiconductor insulating film SINS3 may be provided on a side surface of each of the plurality of contact terminals CTE. The top surface of each of the plurality of contact terminals CTE may be exposed and not covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0141] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as polyimide. For example, a thin film transistor (e.g., a pixel transistor PTR) can be provided on a glass substrate or a polymer resin substrate. A glass substrate can be a rigid substrate that does not bend, and a polymer resin substrate can be a flexible substrate that can be bent or curved.

[0142] The light emitting element base plate EBP may include a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9. The light emitting element base plate EBP may include a plurality of insulating films INS1 to INS9 disposed between the first to eighth conductive layers ML1 to ML8.

[0143] The first conductive layer ML1 to the eighth conductive layer ML8 can be used to connect a plurality of contact terminals CTE exposed from the semiconductor base plate SBP, thereby realizing Figure 3 For example, the circuit of the first pixel PX1 is combined with Figure 3 The first to sixth transistors T1 to T6 may be formed in the semiconductor base plate SBP, and the first to sixth transistors T1 to T6 may be connected to the first capacitor CP1 and the second capacitor CP2 via the first to eighth conductive layers ML1 to ML8. Connections between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light-emitting element LE may also be achieved via the first to eighth conductive layers ML1 to ML8.

[0144] The first insulating film INS1 may be provided on the semiconductor substrate SBP. Each of the plurality of first via holes VA1 may penetrate the first insulating film INS1 to connect to the contact terminal CTE exposed from the semiconductor substrate SBP. Each of the plurality of first conductive layers ML1 may be provided on the first insulating film INS1 and may be connected to the first via hole VA1.

[0145] The second insulating film INS2 may be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the plurality of second via holes VA2 may penetrate the second insulating film INS2 and be connected to the exposed first conductive layer ML1. Each of the plurality of second conductive layers ML2 may be disposed on the second insulating film INS2 and may be connected to the second via hole VA2.

[0146] The third insulating film INS3 may be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the plurality of third via holes VA3 may penetrate the third insulating film INS3 and be connected to the exposed second conductive layer ML2. Each of the plurality of third conductive layers ML3 may be disposed on the third insulating film INS3 and may be connected to the third via hole VA3.

[0147] The fourth insulating film INS4 may be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the plurality of fourth via holes VA4 may penetrate the fourth insulating film INS4 and be connected to the exposed third conductive layer ML3. Each of the plurality of fourth conductive layers ML4 may be disposed on the fourth insulating film INS4 and may be connected to the fourth via hole VA4.

[0148] The fifth insulating film INS5 may be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the plurality of fifth via holes VA5 may penetrate the fifth insulating film INS5 and be connected to the exposed fourth conductive layer ML4. Each of the plurality of fifth conductive layers ML5 may be disposed on the fifth insulating film INS5 and may be connected to the fifth via hole VA5.

[0149] The sixth insulating film INS6 may be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the plurality of sixth via holes VA6 may penetrate the sixth insulating film INS6 and be connected to the exposed fifth conductive layer ML5. Each of the plurality of sixth conductive layers ML6 may be disposed on the sixth insulating film INS6 and may be connected to the sixth via hole VA6.

[0150] The seventh insulating film INS7 may be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the plurality of seventh via holes VA7 may penetrate the seventh insulating film INS7 and be connected to the exposed sixth conductive layer ML6. Each of the plurality of seventh conductive layers ML7 may be disposed on the seventh insulating film INS7 and may be connected to the seventh via hole VA7.

[0151] The eighth insulating film INS8 may be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the plurality of eighth via holes VA8 may penetrate the eighth insulating film INS8 and be connected to the exposed seventh conductive layer ML7. Each of the plurality of eighth conductive layers ML8 may be disposed on the eighth insulating film INS8 and may be connected to the eighth via hole VA8.

[0152] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via hole VA1 to the eighth via hole VA8 may be formed of substantially the same material. The first conductive layer ML1 to the eighth conductive layer ML8 and the first via hole VA1 to the eighth via hole VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The first via hole VA1 to the eighth via hole VA8 may be made of substantially the same material. The first insulating film INS1 to the eighth insulating film INS8 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0153] The thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be respectively greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5 and the thickness of the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be about The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be about 100 Å. And the thickness of each of the first via hole VA1, the second via hole VA2, the third via hole VA3, the fourth via hole VA4, the fifth via hole VA5, and the sixth via hole VA6 may be about

[0154] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately The thickness of each of the seventh via hole VA7 and the eighth via hole VA8 may be about

[0155] The ninth insulating film INS9 may be provided on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0156] Each of the plurality of ninth via holes VA9 may penetrate the ninth insulating film INS9 and be connected to the exposed eighth conductive layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the ninth via hole VA9 may be about

[0157] The display element layer EML may be disposed on the light emitting element backplane EBP. The display element layer EML may include a light emitting element LE each including a first electrode AND, a light emitting stack ES, and a second electrode CAT, a reflective electrode layer RL, tenth and eleventh insulating films INS10 and INS11, a tenth via hole VA10, a pixel defining film PDL, and a plurality of trenches TRC.

[0158] The reflective electrode layer RL may be provided on the ninth insulating film INS9. The reflective electrode layer RL may include at least one of the reflective electrodes RL1, RL2, RL3, and RL4. Figure 6 As shown in , the reflective electrode layer RL may include a first reflective electrode RL1 , a second reflective electrode RL2 , a third reflective electrode RL3 , and a fourth reflective electrode RL4 .

[0159] Each of the plurality of first reflective electrodes RL1 may be disposed on the ninth insulating film INS9 and may be connected to the ninth via hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. Alternatively, the first reflective electrode RL1 may include titanium nitride (TiN).

[0160] Each of the plurality of second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. For example, the second reflective electrode RL2 may include aluminum (Al).

[0161] Each of the plurality of third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. Alternatively, the third reflective electrode RL3 may include titanium nitride (TiN).

[0162] A plurality of fourth reflective electrodes RL4 may be disposed on the plurality of third reflective electrodes RL3, respectively. The fourth reflective electrodes RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the fourth reflective electrodes RL4 may include titanium (Ti).

[0163] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be approximately And the thickness of the second reflective electrode RL2 may be about

[0164] The tenth insulating film INS10 may be provided on the ninth insulating film INS9. The tenth insulating film INS10 may be provided between the reflective electrode layers RL adjacent to each other in the horizontal direction. The tenth insulating film INS10 may be provided on the reflective electrode layer RL in the third pixel PX3. The tenth insulating film INS10 may be made of silicon oxide (SiO x )-based inorganic film is formed, but the embodiment is not limited thereto.

[0165] The eleventh insulating film INS11 may be provided on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 may be made of silicon oxide (SiO x The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RL passes among light emitted from the light emitting element LE.

[0166] In order to adjust the resonance distance of the light emitted from the light emitting element LE in at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the tenth insulating film INS10 and / or the eleventh insulating film INS11 may not be disposed below or under the first electrode AND of at least one pixel (e.g., the first pixel PX1). In one or more embodiments, the first electrode AND of the first pixel PX1 may be disposed directly on the reflective electrode layer RL. In one or more embodiments, the eleventh insulating film INS11 may be disposed below or under the first electrode AND of the second pixel PX2. In one or more embodiments, the tenth insulating film INS10 and the eleventh insulating film INS11 may be disposed below or under the first electrode AND of the third pixel PX3. However, as Figure 6 As shown in , in each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 , the eleventh insulating film INS11 may be disposed under the first electrode AND, and the tenth insulating film INS10 may not be disposed under the first electrode AND.

[0167] In summary, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the dominant wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 may be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, Figure 6] It is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third pixel PX3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 and the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, and the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, but the embodiment is not limited thereto.

[0168] Although the tenth insulating film INS10 and the eleventh insulating film INS11 are shown in the embodiment, a twelfth insulating film (not shown) disposed under or below the first electrode AND of the first pixel PX1 may be added. For example, the eleventh insulating film INS11 and the twelfth insulating film (not shown) may be disposed under or below the first electrode AND of the second pixel PX2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film (not shown) may be disposed under or below the first electrode AND of the third pixel PX3.

[0169] Each of the plurality of tenth via holes VA10 may penetrate the eleventh insulating film INS11 in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and may be connected to the exposed reflective electrode layer RL. The tenth via hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. The thickness of the tenth via hole VA10 in the second pixel PX2 may be smaller than the thickness of the tenth via hole VA10 in the third pixel PX3, and the thickness of the tenth via hole VA10 in the first pixel PX1 may be smaller than the thickness of the tenth via hole VA10 in the second pixel PX2.

[0170] The first electrode AND of each of the plurality of light-emitting elements LE may be disposed on the eleventh insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each of the plurality of light-emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light-emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of these. Alternatively, the first electrode AND of each of the plurality of light-emitting elements LE may be titanium nitride (TiN).

[0171] The pixel-defining film PDL may be disposed on a portion of the first electrode AND of each of the plurality of light-emitting elements LE. The pixel-defining film PDL may cover the edge of the first electrode AND of each of the plurality of light-emitting elements LE. The pixel-defining film PDL may be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0172] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting stack ES, and the second electrode CAT may be sequentially stacked with each other in the first pixel PX1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting stack ES, and the second electrode CAT may be sequentially stacked with each other in the second pixel PX2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting stack ES, and the second electrode CAT may be sequentially stacked with each other in the third pixel PX3 to emit light.

[0173] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be provided on the edge of the first electrode AND of each of the plurality of light emitting elements LE, the second pixel definition film PDL2 may be provided on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be provided on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of silicon oxide (SiO x )-based inorganic film, but the embodiment is not limited thereto. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have an Å of about Å. thickness.

[0174] When the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 are formed into one pixel defining film, the height of the pixel defining film increases, so that the first encapsulating inorganic film TFE1 may be cut due to step coverage. Step coverage (step coverage) refers to the ratio of the degree of film applied on the inclined portion to the degree of film applied on the flat portion. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0175] Therefore, to prevent the first encapsulating inorganic film TFE1 from being cut due to step overlap, the first, second, and third pixel defining films PDL1, PDL2, and PDL3 may have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining film PDL1 may be greater than the widths of the second and third pixel defining films PDL2, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined in the first and second directions DR1 and DR2.

[0176] Each of the plurality of trenches TRC may penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. In addition, each of the plurality of trenches TRC may penetrate the eleventh insulating film INS11. Although not shown, the tenth insulating film INS10 may be partially recessed at each of the plurality of trenches TRC.

[0177] At least one trench TRC may be provided between adjacent pixels PX1, PX2, and PX3. Figure 6 It is shown that two trenches TRC are disposed between adjacent pixels PX1 , PX2 , and PX3 , but the embodiment is not limited thereto.

[0178] The light emitting stack ES may include a plurality of intermediate layers. Figure 6 The light emitting stack ES is shown to have a three-series structure including the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3, but the embodiment is not limited thereto. For example, the light emitting stack ES may have a two-series structure including two intermediate layers.

[0179] In the triple-series structure, the light emitting stack ES may have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different lights. For example, the light emitting stack ES may include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a second color, and a third stack layer IL3 that emits light of a third color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 may be sequentially stacked one on top of the other.

[0180] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked with each other. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked with each other. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked with each other. For example, the light-emitting stack ES may emit white light in which a first color of light from the first organic light-emitting layer (e.g., red light), a second color of light from the second organic light-emitting layer (e.g., green light), and a third color of light from the third organic light-emitting layer (e.g., blue light) are mixed. Therefore, white light can be emitted from each of the first emission area EA1, the second emission area EA2, and the third emission area EA3. Here, white light having passed through the first emission area EA1 may be incident on the first color filter CF1, white light having passed through the second emission area EA2 may be incident on the second color filter CF2, and white light having passed through the third emission area EA3 may be incident on the third color filter CF3.

[0181] A first charge generation layer for supplying holes to the second stack layer IL2 and electrons to the first stack layer IL1 may be provided between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0182] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be provided between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0183] The first stacked layer IL1 can be arranged on the first electrode AND and the pixel defining film PDL, and can be arranged on the bottom surface of each groove TRC. Due to the groove TRC, the first stacked layer IL1 can be separated between adjacent pixels PX1, PX2 and PX3. The second stacked layer IL2 can be arranged on the first stacked layer IL1. Due to the groove TRC, the second stacked layer IL2 can be separated between adjacent pixels PX1, PX2 and PX3. A cavity ESS or empty space can be provided between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 can be provided on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the groove TRC and can be arranged to cover the second stacked layer IL2 in each of the multiple grooves TRC. For example, in a three-series structure, each of the multiple grooves TRC can be a structure for cutting off the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer and the second charge generation layer between the adjacent pixels PX1, PX2 and PX3 of the display element layer EML. In the two-tandem structure, each of the plurality of trenches TRC may be a structure for cutting off the charge generation layer and the lower intermediate layer provided between the lower intermediate layer and the upper intermediate layer.

[0184] In order to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2 and PX3, the height of each of the multiple grooves TRC may be greater than the height of the pixel defining film PDL. The height of each of the multiple grooves TRC refers to the length of each of the multiple grooves TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. In order to cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2 and PX3, another structure may be present instead of the groove TRC. For example, an inverted tapered partition wall may be provided in the pixel defining film PDL instead of the groove TRC.

[0185] The number of stacked layers IL1, IL2, and IL3 emitting different light is not limited to Figure 6 . For example, the light-emitting stack ES may include two intermediate layers. For example, one of the two intermediate layers may be substantially the same as the first stacked layer IL1, and the other of the two intermediate layers may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. For example, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be provided between the two intermediate layers.

[0186] Figure 6The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are shown to be arranged in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the embodiment is not limited thereto. For example, the first stacked layer IL1 may be arranged in the first emission area EA1, and may not be arranged in the second emission area EA2 and the third emission area EA3. In addition, the second stacked layer IL2 may be arranged in the second emission area EA2, and may not be arranged in the first emission area EA1 and the third emission area EA3. In addition, the third stacked layer IL3 may be arranged in the third emission area EA3, and may not be arranged in the first emission area EA1 and the second emission area EA2. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL may be omitted.

[0187] The second electrode CAT may be disposed on the third stacked layer IL3. The second electrode CAT may be disposed on the third stacked layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium and silver). When the second electrode CAT is formed of the semi-transmissive conductive material, the luminous efficiency of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be improved due to the microcavity effect.

[0188] The encapsulation film TFE may be provided on the display element layer EML. The encapsulation film TFE may include at least one of the inorganic films TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation film TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0189] The first encapsulation inorganic film TFE1 may be provided on the second electrode CAT. The first encapsulation inorganic film TFE1 may be formed of a material selected from silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and silicon oxide (SiO x ) may be formed of a plurality of layers in which one or more inorganic films are alternately stacked with each other. The first encapsulation inorganic film TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0190] The second encapsulation inorganic film TFE2 may be provided on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 may be made of titanium oxide (TiO x ) or aluminum oxide (AlO x) is formed, but the embodiment is not limited thereto. The second encapsulation inorganic film TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 may be less than the thickness of the first encapsulation inorganic film TFE1.

[0191] The display panel 100 may further include an organic film APL. The organic film APL may be a layer for increasing the interfacial adhesion between the encapsulation film TFE and the optical layer OPL. The organic film APL may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0192] The optical layer OPL may include a color filter layer CFL, a lens layer LSL, a filling layer FIL, a cover layer CVL, a retardation layer QWP, and a wire grid polarizer WGP.

[0193] The color filter layer CFL may include a plurality of color filters CF1, CF2, and CF3. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the organic film APL.

[0194] The first color filter CF1 may overlap with the first emission area EA1 (e.g., a red light emitting area) of the first pixel PX1 in the third direction DR3. The first color filter CF1 may transmit light of a first color, for example, light in a red wavelength band. The red wavelength band may be in the range of about 600 nm to about 750 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0195] The second color filter CF2 may overlap with the second emission area EA2 (e.g., the green emission area) of the second pixel PX2 in the third direction DR3. The second color filter CF2 may transmit light of a second color, for example, light in a green wavelength band. The green wavelength band may be in the range of about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0196] The third color filter CF3 may overlap with the third emission area EA3 (e.g., a blue emission area) of the third pixel PX3 in the third direction DR3. The third color filter CF3 may transmit light of a third color, for example, light in a blue wavelength band. The blue wavelength band may be in the range of approximately 380 nm to approximately 480 nm. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0197] The planarization layer PLL may be provided on the color filter layer CFL. The planarization layer PLL may play a role in planarizing the stepped portion at the lower portion. The planarization layer PLL may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0198] The lens layer LSL may be provided on the planarization layer PLL. The lens layer LSL may include a plurality of lenses LNS. The plurality of lenses LNS may be provided on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be for increasing the amount of light directed toward the display device 10 (see FIG. Figure 1 Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

[0199] The filling layer FIL can be disposed on the lens layer LSL. For example, the filling layer FIL can be disposed on the plurality of lenses LNS. The filling layer FIL can have a selectable refractive index such that light travels in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL can be a planarization layer. The filling layer FIL can be an organic film such as an acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0200] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin substrate. If the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. For example, the filling layer FIL may be used to bond the cover layer CVL. If the cover layer CVL is a glass substrate, the cover layer CVL may serve as an encapsulation substrate. If the cover layer CVL is a polymer resin substrate, the cover layer CVL may be directly applied to the filling layer FIL.

[0201] A retardation layer QWP (or retardation plate, or retardation film) may be provided on the color filter layer CFL. For example, the retardation layer QWP may be provided between the color filter layer CFL and the wire grid polarizer WGP. The retardation layer QWP may be a λ / 4 plate (quarter wave plate), but the embodiment is not limited thereto. The retardation layer QWP may be formed, for example, by a coating method.

[0202] In an embodiment, the retardation layer QWP may include an alignment film ALL, a liquid crystal layer LC disposed on the alignment film ALL, and a capping layer CPL disposed on the liquid crystal layer LC. The alignment film ALL may serve to align the liquid crystal layer LC disposed on the alignment film ALL. For example, the alignment film ALL may anisotropically undergo reactions such as photoisomerization and photocrosslinking when irradiated with polarized light, and thus may generate anisotropy on the polymer surface, which may induce molecular alignment of the liquid crystal in one direction or in a certain direction. The liquid crystal layer LC may be formed by coating a liquid crystal material including a reaction medium (RM) to be aligned on the alignment film ALL and polymerizing the liquid crystal material.

[0203] The capping layer CPL plays a role in protecting the liquid crystal layer LC. The capping layer CPL may include an inorganic insulating material. For example, the capping layer CPL may include silicon nitride (SiN x ), silicon oxynitride (SiO x N y ) and silicon oxide (SiO x ). The capping layer CPL may have a selectable thickness (e.g., a thickness in a range of about 50 nm to about 1000 nm) to protect the liquid crystal layer LC. In an embodiment, the capping layer CPL may have a thickness in a range of about 100 nm to about 500 nm.

[0204] The wire grid polarizer WGP may be disposed on the retardation layer QWP, for example, between the retardation layer QWP and the planarization layer PLL. The wire grid polarizer WGP and the retardation layer QWP may constitute a polarization member. For example, the polarization member according to an embodiment may include the retardation layer QWP and the wire grid polarizer WGP.

[0205] The wire grid polarizer WGP may include a plurality of wire grid patterns GP. Figure 5 As shown in , each wire grid pattern GP may have a rectangular shape extending along the second direction DR2. Figure 5 As shown in FIG, the wire grating patterns GP may be arranged or disposed along the first direction DR1. The wire grating patterns GP may be disposed to be spaced apart from each other in the first direction DR1.

[0206] A wire grid polarizer (WGP) can transmit light with a given polarization direction while reflecting light with a different polarization direction for recycling. Because it exhibits higher polarization separation performance than other polarizers, it is useful as a reflective polarizer. For example, a wire grid polarizer (WGP) can be a device that generates polarization using a conductive wire grid and can have a structure in which multiple wires made of a conductive material are periodically arranged on a nanometer scale or arranged parallel to each other on a retardation layer (QWP) to form a wire grid pattern (GP).

[0207] In a wire grid polarizer WGP comprising a plurality of wire grid patterns GP, if the period of the wire grid patterns GP is smaller than the wavelength of the incident light, no diffraction of the incident light occurs. Therefore, the wire grid polarizer WGP can transmit components of the incident light having a vibration direction orthogonal to the conductive wire grid patterns GP, such as transverse magnetic (TM) polarization (e.g., P-wave), while reflecting components having a vibration direction parallel to the wire grid patterns GP, such as transverse electric (TE) polarization (e.g., S-wave). In other words, when the arrangement period of the wire grid patterns GP is shorter than the wavelength of the electromagnetic wave incident on the wire grid polarizer WGP, the wire grid polarizer WGP can reflect polarization components parallel to the wire grid patterns GP (e.g., S-wave) while transmitting polarization components orthogonal to the wire grid patterns GP (e.g., P-wave). Because the wire grid polarizer WGP uses wire grid patterns GP made of metal, the light reflection efficiency of the wire grid polarizer WGP is very high. Therefore, since the reflected light can be re-reflected, the light can be recycled so that all the light becomes light of one polarization.

[0208] The wire grating patterns GP may be arranged to be spaced apart from each other at a first pitch P1 in a first direction DR1. The first pitch P1 may be a distance between the centers of adjacent wire grating patterns GP. The first pitch P1 of the wire grating patterns GP may be in a range of about 50 nm to about 150 nm. In an embodiment, the first pitch P1 of the wire grating patterns GP may be in a range of about 50 nm to about 100 nm. The first pitch P1 of the wire grating patterns GP may be the same in all the wire grating patterns GP, or may be different in some of the wire grating patterns GP.

[0209] The wire grating patterns GP may be arranged to be spaced apart from each other in the first direction DR1 by a separation distance equal to a second pitch P2. The second pitch P2 may be the distance between the side edges of the wire grating patterns GP adjacent to each other. The second pitch P2 of the wire grating patterns GP may be in a range of about 40 nm to about 100 nm. In an embodiment, the second pitch P2 of the wire grating patterns GP may be in a range of about 40 nm to about 50 nm. The second pitch P2 of the wire grating patterns GP may be the same in all the wire grating patterns GP, or may be different from each other in some of the wire grating patterns GP.

[0210] The wire grating pattern GP may have a selectable thickness in consideration of process properties or reflective characteristics, etc. The thickness TK1 of the wire grating pattern GP may be in a range of about 10 nm to about 1000 nm. In an embodiment, the thickness TK1 of the wire grating pattern GP may be in a range of about 100 nm to about 300 nm. The thickness TK1 of the wire grating pattern GP may be the same in all wire grating patterns GP, or may be different from each other in some wire grating patterns GP.

[0211] The wire grid pattern GP may include a grid pattern GPL and a metal pattern MPL.

[0212] The grid pattern GPL may form an upper layer of the wire grid pattern GP and may substantially perform the function of the wire grid pattern GP. The grid pattern GPL may be disposed between the metal pattern MPL and the planarization layer PLL. The grid pattern GPL may include a material having a high reflectivity to perform the aforementioned light reflection function. For example, the grid pattern GPL may include at least one of aluminum (Al), silver (Ag), and gold (Au). The thickness TK2 of the grid pattern GPL may be in the range of about 10 nm to about 1000 nm.

[0213] The metal pattern MPL may form a lower layer of the wire grid pattern GP and may function as a bond to the retardation layer QWP disposed thereunder. The metal pattern MPL may be disposed between the grid pattern GPL and the capping layer CPL of the retardation layer QWP. The metal pattern MPL may be disposed directly on the capping layer CPL of the retardation layer QWP to improve the bonding strength between the wire grid pattern GP and the capping layer CPL.

[0214] As in the embodiment described later, when the grid pattern GPL is directly provided on the capping layer CPL, the bonding strength with the capping layer CPL is relatively weak, so that problems such as bulging of the film may occur in subsequent processes. In the present disclosure, the bonding strength of the grid pattern GP can be improved by providing a metal pattern MPL between the grid pattern GPL and the capping layer CPL.

[0215] The metal pattern MPL may include a material having excellent adhesion strength with the capping layer CPL. For example, the metal pattern MPL may include any one of titanium (Ti), chromium (Cr), nickel (Ni), tantalum (Ta), and tungsten (W). The thickness TK3 of the metal pattern MPL may be in the range of about 1 nm to about 1000 nm. In an embodiment, considering adhesion strength, reliability, and transmittance, the thickness TK3 of the metal pattern MPL may be in the range of about 3 nm to about 7 nm.

[0216] The wire grid polarizer WGP may further include an air layer AIL. The air layer AIL may be disposed between the wire grid patterns GP. For example, the air layer AIL may be disposed in a region separated by the capping layer CPL, the wire grid pattern GP, ​​and the planarization layer PLL. The air layer AIL may be disposed between the wire grid patterns GP and extend parallel to the wire grid patterns GP in the second direction DR2. The air layers AIL may be spaced apart from each other in the first direction DR1, with the wire grid patterns GP disposed between the air layers AIL. The air layer AIL may serve as a transmission path for light emitted from the internal light emitting stack ES.

[0217] Figure 8is a schematic cross-sectional view showing another example of a display panel according to an embodiment. Figure 9 yes Figure 8 An enlarged schematic diagram of region B.

[0218] Reference Figure 8 and Figure 9 According to an embodiment, the wire grid polarizer WGP may include a plurality of metal patterns MPL1 and MPL2, which is similar to the above-mentioned Figure 6 and Figure 7 In the following description, redundant descriptions of the above-mentioned embodiments will be omitted while focusing on the differences.

[0219] Reference Figure 8 and Figure 9 , the wire grid polarizer WGP may include a plurality of metal patterns MPL1 and MPL2 in the wire grid pattern GP. The plurality of metal patterns MPL1 and MPL2 may include a first metal pattern MPL1 and a second metal pattern MPL2.

[0220] The first metal pattern MPL1 may form the lowermost layer of the wire grid pattern GP and may serve to bond to the retardation layer QWP disposed thereunder. The first metal pattern MPL1 may be disposed between the second metal pattern MPL2 and the capping layer CPL of the retardation layer QWP. The first metal pattern MPL1 may be disposed directly on the capping layer CPL of the retardation layer QWP to improve the bonding strength between the wire grid pattern GP and the capping layer CPL.

[0221] The first metal pattern MPL1 may include a material having excellent adhesion strength with the capping layer CPL. The first metal pattern MPL1 may include a material having excellent adhesion strength with the second metal pattern MPL2. For example, the first metal pattern MPL1 may include at least one of titanium (Ti), chromium (Cr), nickel (Ni), tantalum (Ta), and tungsten (W). The thickness TK4 of the first metal pattern MPL1 may be in the range of about 1 nm to about 1000 nm. In an embodiment, considering adhesion strength, reliability, and transmittance, the thickness TK4 of the first metal pattern MPL1 may be in the range of about 3 nm to about 7 nm.

[0222] The second metal pattern MPL2 may form a lower layer of the wire grid pattern GP and may serve to bond the first metal pattern MPL1 to the grid pattern GPL. The second metal pattern MPL2 may be disposed between the first metal pattern MPL1 and the grid pattern GPL. The second metal pattern MPL2 may be disposed directly on the first metal pattern MPL1 to improve the bonding strength between the grid pattern GPL and the first metal pattern MPL1.

[0223] The second metal pattern MPL2 may include a material having excellent adhesion strength with the grid pattern GPL and the first metal pattern MPL1. For example, the second metal pattern MPL2 may include at least one of titanium (Ti), chromium (Cr), nickel (Ni), tantalum (Ta), and tungsten (W). The thickness TK5 of the second metal pattern MPL2 may be in a range of about 1 nm to about 1000 nm. In an embodiment, considering adhesion strength, reliability, and transmittance, the thickness TK5 of the second metal pattern MPL2 may be in a range of about 3 nm to about 7 nm.

[0224] According to embodiments, the first metal pattern MPL1 and the second metal pattern MPL2 may include different materials. Each of the first metal pattern MPL1 and the second metal pattern MPL2 may be selected from titanium (Ti), chromium (Cr), nickel (Ni), tantalum (Ta), and tungsten (W), but may include different materials. For example, when the first metal pattern MPL1 may include titanium (Ti), the second metal pattern MPL2 may include chromium (Cr). In embodiments, when the first metal pattern MPL1 may include chromium (Cr), the second metal pattern MPL2 may include titanium (Ti).

[0225] The thickness TK4 of the first metal pattern MPL1 and the thickness TK5 of the second metal pattern MPL2 may be different from each other. For example, the thickness TK4 of the first metal pattern MPL1 may be greater than the thickness TK5 of the second metal pattern MPL2. The first metal pattern MPL1 may substantially perform the function of having an adhesive strength with the capping layer CPL, and by forming the thickness TK4 of the first metal pattern MPL1 to be greater than the thickness TK5 of the second metal pattern MPL2, this may further contribute to improving the adhesive strength between the wire grid pattern GP and the capping layer CPL.

[0226] Figure 10 is a schematic cross-sectional view showing another example of a display panel according to an embodiment. Figure 11 yes Figure 10 An enlarged schematic diagram of region C. Figure 12 is a schematic plan view schematically illustrating a wire grid pattern. Figure 13 yes Figure 11 An enlarged schematic diagram of region D.

[0227] Reference Figures 10 to 13 According to an embodiment, the width of the metal pattern MPL is greater than the width of the grid pattern GPL, which is consistent with the above Figure 6 and Figure 7 The embodiments are different.

[0228] The wire grid polarizer WGP may include a wire grid pattern GP, ​​and the wire grid pattern GP may include a grid pattern GPL and a metal pattern MPL.

[0229] Within the spirit and scope of the present disclosure, the grid pattern GPL may have a width W1 in consideration of transmittance or reflectance, etc. The width W1 of the grid pattern GPL may be in the range of about 1 nm to about 100 nm.

[0230] The metal pattern MPL may be disposed between the grid pattern GPL and the capping layer CPL. The metal pattern MPL may include a top surface MUS contacting the grid pattern GPL, a bottom surface MBS contacting the capping layer CPL, and a side surface MSS connecting the top surface MUS to the bottom surface MBS.

[0231] The width W2 of the top surface MUS of the metal pattern MPL may be the same as the width W1 of the grid pattern GPL. The width W3 of the bottom surface MBS of the metal pattern MPL may be greater than the width W2 of the top surface MUS of the metal pattern MPL. For example, the width W3 of the bottom surface MBS of the metal pattern MPL may be greater than the width W1 of the grid pattern GPL. As described above, the metal pattern MPL is intended to improve the bonding strength with the capping layer CPL, and in the case where the width W3 of the bottom surface MBS of the metal pattern MPL in contact with the capping layer CPL is large, the bonding strength with the capping layer CPL may be increased.

[0232] In an embodiment, the width of the metal pattern MPL may gradually increase from the top surface MUS to the bottom surface MBS of the metal pattern MPL. For example, the width of the metal pattern MPL may gradually increase as it gets closer to the retardation layer QWP.

[0233] The side surface MSS of the metal pattern MPL may have an inclination. The inner angle θ formed between the side surface MSS of the metal pattern MPL and the bottom surface MBS of the metal pattern MPL may be greater than or equal to about 60 degrees and less than about 90 degrees. When the inner angle θ formed between the side surface MSS of the metal pattern MPL and the bottom surface MBS of the metal pattern MPL is within the above range, the bonding strength between the capping layer CPL and the wire grid pattern GP can be improved, and a decrease in transmittance can be prevented.

[0234] In embodiments, by forming the width W3 of the bottom surface MBS of the metal pattern MPL to be greater than the width W1 of the grid pattern GPL, the adhesive strength with the capping layer CPL may be further improved.

[0235] Figure 14 is a schematic cross-sectional view showing an example of a display panel according to an embodiment.

[0236] Figure 14 The display device and the above Figure 6 The display device is different in that it does not include the above Figure 6 The color filter layer CFL in.

[0237] For example, Figure 6 The display panel 100 may be a “white-OLED” type display panel in which the light emitting stack ES of the pixels PX1, PX2, and PX3 included in the unit pixel UPX all provide white light. However, Figure 14 The display panel 100 may be an “RGB-OLED” type display panel in which the light emitting stack ES of the pixels PX1 , PX2 , and PX3 included in the unit pixel UPX respectively provides red light, green light, and blue light.

[0238] like Figure 14 As shown in FIG, since the display panel 100 does not include the color filter layer CFL, the organic film APL and the retardation layer QWP may contact each other.

[0239] According to an embodiment, Figure 14 The light-emitting stack ES can provide different colors of light for each pixel. For example, the light-emitting stack ES of the first pixel PX1 may include a red organic light-emitting layer that provides red light, the light-emitting stack ES of the second pixel PX2 may include a green organic light-emitting layer that provides green light, and the light-emitting stack ES of the third pixel PX3 may include a blue organic light-emitting layer that provides blue light. In other words, the light-emitting stack ES may include the above-mentioned red organic light-emitting layer in the first emission area EA1 of the first pixel PX1, the above-mentioned green organic light-emitting layer in the second emission area EA2 of the second pixel PX2, and the above-mentioned blue organic light-emitting layer in the third emission area EA3 of the third pixel PX3. Therefore, the first pixel PX1 can provide red light generated by the red organic light-emitting layer, the second pixel PX2 can provide green light generated by the green organic light-emitting layer, and the third pixel PX3 can provide blue light generated by the blue organic light-emitting layer.

[0240] Figure 15 is a schematic cross-sectional view showing an example of a display panel according to an embodiment.

[0241] Figure 15 The display device and the above Figure 6 The display device of is different in that the lens layer LSL described above is not included.

[0242] like Figure 15 As shown in FIG, since the display panel 100 does not include the lens layer LSL described above, the planarization layer PLL and the filling layer FIL may contact each other.

[0243] Figure 16 is a schematic cross-sectional view showing an example of a display panel according to an embodiment.

[0244] Figure 16The display device and the above Figure 6 The display device of FIG. 1 is different in that the color filter layer CFL and the lens layer LSL described above are not included.

[0245] like Figure 16 As shown in FIG, since the display panel 100 does not include the lens layer LSL described above, the planarization layer PLL may be in contact with the filling layer FIL.

[0246] In the experimental examples disclosed below, cross-cut adhesion strength tests and transmittance were measured to determine the adhesion strength between the silicon nitride layer and the titanium layer.

[0247] Comparative Example 1

[0248] The silicon nitride (SiN) layer having a thickness of about 300 nm was sequentially stacked on a glass substrate. x ) layer, an aluminum (Al) layer having a thickness of about 200 nm, and a silicon oxynitride (SiO x N y ) layer to make the sample substrate.

[0249] Example 1

[0250] In Example 1, a sample substrate was manufactured by additionally stacking a titanium (Ti) layer having a thickness of about 5 nm between a silicon nitride layer and an aluminum layer.

[0251] Example 2

[0252] In Example 2, sample substrates were manufactured with titanium (Ti) layers having different thicknesses of about 1 nm, about 2 nm, about 3 nm, about 7 nm, about 10 nm, and about 15 nm, respectively.

[0253] A cross-cut adhesive strength test was performed on each of the sample substrates manufactured in Comparative Example 1, Example 1, and Example 2, and the transmittance of the sample substrates manufactured in Example 1 and Example 2 was measured. In the cross-cut adhesive strength test, a fork according to ASTM standards was used to cross-cut the sample substrate in a 90-degree direction, and an adhesive tape was attached to the surface of the sample substrate and then peeled off.

[0254] Figure 17 is an image of the sample substrate according to Comparative Example 1 after the cross-cut adhesive strength test. Figure 18 is an image of a sample substrate according to Example 1 after cross-cut adhesion strength testing. Figure 19 is a graph showing the cross-cut adhesive strength according to the thickness of the titanium layer. Figure 20 is a graph showing the transmittance of a substrate according to the thickness of a titanium layer.

[0255] Reference Figure 17, wherein the sample substrate in which the silicon nitride layer and the aluminum layer were in direct contact according to Comparative Example 1 showed a large amount of film peeling, and the cross-cut adhesion strength test result value was 0B. On the other hand, Figure 18 , the sample substrate in which the silicon nitride layer and the titanium layer were in direct contact according to Example 1 showed that the film did not peel off, and the cross-cut adhesion strength test result value was 5B.

[0256] Reference Figure 19 , as the thickness of the titanium layer (Ti thickness) increases, the cross-cut adhesion strength test result value increases, and shows the same 5B value in the case where the thickness of the titanium layer is greater than or equal to about 5 nm.

[0257] Reference Figure 20 , when the titanium layer has a thickness in the range of about 1 nm to about 5 nm, the transmittance is about 100%, when the titanium layer has a thickness of about 7 nm, the transmittance is about 90%; when the titanium layer has a thickness of about 10 nm, the transmittance is about 80%, and when the titanium layer has a thickness of about 15 nm, the transmittance is about 60%.

[0258] These results confirm that inserting a titanium layer between the silicon nitride layer and the aluminum layer improves the adhesion strength of the sample substrate. It can be seen that the adhesion strength between the silicon nitride layer and the titanium layer is excellent. For example, in the present disclosure, it was confirmed that, when the thickness of the titanium layer is formed within a range of approximately 3 nm to approximately 7 nm, it is possible to achieve adhesion strength properties of 5B or higher and a transmittance of approximately 90% or higher.

[0259] Below, in Figure 6 and Figure 7 In the display panel 100 shown in , reliability tests and transmittances of a case where the wire grid pattern GP may include only the grid pattern GPL and a case where the wire grid pattern GP may include the grid pattern GPL and the metal pattern MPL were measured.

[0260] Comparative Example 2

[0261] exist Figure 6 In the display panel 100 shown in FIG, a wire grid polarizer WGP is manufactured, and components disposed above the wire grid polarizer WGP are omitted when manufacturing the display panel 100. In this case, the capping layer CPL of the retardation layer QWP is made of silicon nitride (SiN x ) is formed, and the wire grid pattern GP is formed into a grid pattern GPL including only aluminum (Al).

[0262] Example 3

[0263] In the same structure as that of Comparative Example 2, the display panel 100 is manufactured differently so that the wire grid pattern GP may include a grid pattern GPL and a metal pattern MPL including titanium (Ti).

[0264] After silicon oxynitride was stacked on the wire grid pattern GP of each of the display panels 100 manufactured according to Comparative Example 2 and Example 3, the display panel 100 was observed.

[0265] Figure 21 is an image of a display panel manufactured according to Comparative Example 2. Figure 22 is an image of a display panel manufactured according to Example 3.

[0266] Reference Figure 21 , in the display panel according to Comparative Example 2, the grid pattern including aluminum exhibited a film peeling phenomenon from the capping layer including silicon nitride, and bubbles were generated.

[0267] On the other hand, refer to Figure 22 , in the display panel 100 according to Example 3, the metal pattern MPL including titanium does not exhibit a film peeling phenomenon from the capping layer CPL including silicon nitride.

[0268] Through these results, it can be confirmed that the adhesive strength between the capping layer including silicon nitride and the metal pattern including titanium in the wire grid pattern is excellent.

[0269] Figure 23 is a schematic perspective view showing a head-mounted display according to the embodiment. Figure 24 It shows Figure 23 An exploded schematic perspective view of an example of a head-mounted display.

[0270] Reference Figure 23 and Figure 24 According to an embodiment, the head-mounted display 1000 may include a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, a middle frame 1400, a first optical member 1510, a second optical member 1520 and a control circuit board 1600.

[0271] The first display device 10_1 may provide an image to the left eye of the user, and the second display device 10_2 may provide an image to the right eye of the user. Figure 1 and Figure 2 The display devices 10 described are substantially the same, so descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0272] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0273] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 may be used to support and secure the first display device 10_1, the second display device 10_2, and the control circuit board 1600, or may function to support and secure the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0274] The control circuit board 1600 may be provided between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see Figure 2 ), and transmits the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connection member.

[0275] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. For example, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0276] The display device housing 1100 may be used to house the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600, or may serve to house the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 may be provided to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 provided at the user's left eye and a second eyepiece 1220 provided at the user's right eye. Figure 23 and Figure 24The first eyepiece 1210 and the second eyepiece 1220 are shown to be separately provided, but the embodiment is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0277] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, a user may view an image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may view an image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0278] The head-mounted strap 1300 can be used to secure the display device housing 1100 to the user's head or play a role in securing the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain positioned on the user's left eye and right eye, respectively. When the display device housing 1100 is implemented to be lightweight and compact, the head-mounted display 1000 can provide a user-friendly interface. Figure 25 The eyeglass frame shown in FIG. 1 is used instead of the headband 1300 .

[0279] The head-mounted display 1000 may further include a battery for power supply, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0280] Figure 25 is a schematic perspective view showing a head-mounted display according to the embodiment.

[0281] Reference Figure 25 The head-mounted display 1000_1 according to an embodiment may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to an embodiment may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and the display device housing 1200_1.

[0282] The display device housing 1200_1 may house the display device 10_3, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and provided to the right eye of the user through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user may view, through the right eye, an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right-eye lens 1020 are combined.

[0283] Figure 25 The display device housing 1200_1 is shown as being disposed at the right end of the support frame 1030, but the embodiment is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and an image of the display device 10_3 may be provided to the user's left eye. For example, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and the user may view an image displayed on the display device 10_3 through both the left eye and the right eye.

[0284] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications can be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments are used in a generic and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device includes: A display element layer is provided on the substrate, wherein the display element layer includes a first electrode, a light-emitting layer, and a second electrode; a retardation layer, disposed on the display element layer, the retardation layer comprising at least a capping layer; and a wire grid polarizer disposed on the retardation layer, the wire grid polarizer comprising a wire grid pattern in which a metal pattern and a grid pattern are stacked on each other, The metal pattern is disposed on the capping layer and has a thickness ranging from 3 nm to 7 nm.

2. The display device according to claim 1, wherein The capping layer includes any one of silicon nitride, silicon oxide and silicon oxynitride.

3. The display device according to claim 1, wherein The metal pattern includes any one of titanium, chromium, nickel, tantalum, and tungsten.

4. The display device according to claim 1, wherein The grid pattern is disposed on the metal pattern, and a thickness of the grid pattern is greater than the thickness of the metal pattern.

5. The display device according to claim 1, wherein The width of the grid pattern is equal to the width of the metal pattern. The display device according to claim 1 , wherein: A width of a lower surface of the metal pattern is greater than a width of an upper surface of the metal pattern.

7. The display device according to claim 6, wherein: The width of the upper surface of the metal pattern is equal to the width of the grid pattern.

8. The display device according to claim 1, wherein The width of the metal pattern gradually increases from the upper surface to the lower surface of the metal pattern.

9. The display device according to claim 1, wherein The side surface of the metal pattern has an inclination, and An inner angle formed between the side surface of the metal pattern and a lower surface of the metal pattern is greater than or equal to 60 degrees and less than 90 degrees.

10. The display device according to claim 1, wherein The display device further includes: a planarization layer disposed on the wire grid polarizer, The wire grid polarizer includes an air layer disposed in a region separated by the capping layer, the wire grid pattern, and the planarization layer.

11. A display device, wherein: The display device includes: A display element layer is provided on the substrate, wherein the display element layer includes a first electrode, a light-emitting layer, and a second electrode; a retardation layer, disposed on the display element layer, the retardation layer comprising at least a capping layer; and a wire grid polarizer disposed on the retardation layer, the wire grid polarizer comprising a wire grid pattern in which a first metal pattern, a second metal pattern, and a grid pattern are stacked on each other, wherein The first metal pattern is provided on the capping layer, The second metal pattern is disposed on the first metal pattern, and The grid pattern is disposed on the second metal pattern.

12. The display device according to claim 11, wherein The capping layer includes any one of silicon nitride, silicon oxide and silicon oxynitride.

13. The display device according to claim 11, wherein The first metal pattern and the second metal pattern include different materials.

14. The display device according to claim 13, wherein: Each of the first metal pattern and the second metal pattern includes any one of titanium, chromium, nickel, tantalum, and tungsten.

15. The display device according to claim 11, wherein A thickness of the first metal pattern and a thickness of the second metal pattern are different from each other.

16. The display device according to claim 15, wherein The thickness of the first metal pattern is greater than the thickness of the second metal pattern.

17. An optical device, wherein: The optical device comprises: display device; and The optical path changing member is provided on the display device, wherein: The display device includes: A display element layer is provided on the substrate, wherein the display element layer includes a first electrode, a light-emitting layer, and a second electrode; a retardation layer, disposed on the display element layer, the retardation layer comprising at least a capping layer; and a wire grid polarizer disposed on the retardation layer, the wire grid polarizer comprising a wire grid pattern in which a metal pattern and a grid pattern are stacked on each other, and The metal pattern is disposed on the capping layer and has a thickness in a range of 3 nm to 7 nm.

18. The optical device according to claim 17, wherein The capping layer includes any one of silicon nitride, silicon oxide and silicon oxynitride.

19. The optical device according to claim 17, wherein The width of the metal pattern gradually increases from the upper surface to the lower surface of the metal pattern.

20. The optical device according to claim 17, wherein The metal pattern includes a first metal pattern disposed on the capping layer and a second metal pattern disposed on the first metal pattern, and The grid pattern is disposed on the second metal pattern.

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