Display module

Abstract

The present application relates to a display module comprising: a substrate which may include a plurality of pixel regions; the driving circuit layer is arranged on the substrate; a light emitting layer disposed on the driving circuit layer and continuously extending across the pixel region; a plurality of color filters disposed on the light emitting layer and overlapping the pixel regions, respectively; a light blocking pattern disposed between the color filters and including a metal material having a multilayer structure; a phase retardation plate disposed on the color filter to retard the phase of the incident light; and a wire grid polarizer including a plurality of metal patterns spaced apart from each other by a distance.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0049919, filed on April 15, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display module including a light-blocking pattern and a display device including the display module. Background Technology

[0004] Electronic devices such as smartphones, laptops, navigation devices, and smart TVs that provide images to users include display devices for displaying images. Augmented reality devices, virtual reality devices, and video projection devices may include microdisplay devices. Microdisplay devices may include a CMOS chip and light-emitting diodes disposed on the CMOS chip to be driven at low power and also to display images with high brightness. Utility Model Content

[0005] This disclosure provides a display module that prevents color mixing and has improved light efficiency, and a display device including the display module.

[0006] Embodiments of this disclosure may provide a display module, comprising: a substrate including a plurality of pixel regions; a driving circuit layer disposed on the substrate; a light-emitting layer disposed on the driving circuit layer and extending continuously across the pixel regions; a plurality of color filters disposed on the light-emitting layer and overlapping the plurality of pixel regions respectively; light-blocking patterns disposed between the plurality of color filters and comprising a metal material having a multilayer structure; a phase retardation plate disposed on the plurality of color filters to delay the phase of incident light; and a wire grid polarizer disposed on the phase retardation plate and comprising a plurality of metal patterns spaced apart from each other by a certain distance (e.g., a predetermined or selectable distance).

[0007] In embodiments of this disclosure, the light-blocking pattern may include a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer.

[0008] In embodiments of this disclosure, among the first metal layer, the second metal layer, and the third metal layer, the third metal layer may be disposed closest to the phase delay plate, and the thickness of the third metal layer may be about 150 angstroms or less.

[0009] In embodiments of this disclosure, the thickness of the second metal layer may be about 1000 angstroms or greater.

[0010] In an embodiment of the disclosure, the second metal layer can have a reflectance of about 80% or more.

[0011] In an embodiment of the disclosure, the second metal layer can have a light transmittance of about 0%.

[0012] In an embodiment of the disclosure, the first metal layer can include at least one of titanium, molybdenum, and molybdenum-tantalum oxide (MoTaO).

[0013] In an embodiment of the disclosure, the second metal layer can include aluminum.

[0014] In an embodiment of the disclosure, the third metal layer can include titanium.

[0015] In an embodiment of the disclosure, the phase delay plate can include a λ / 4 phase delay plate.

[0016] In an embodiment of the disclosure, the light emitting layer can include a light emitting material that emits white light.

[0017] In an embodiment of the disclosure, the display module according to an embodiment of the disclosure can further include a cover window disposed on the wire grid polarizer.

[0018] In an embodiment of the disclosure, the display module according to an embodiment of the disclosure can further include a planarization layer covering the plurality of color filters and the light blocking pattern, the planarization layer can include a substantially planar upper surface.

[0019] In an embodiment of the disclosure, the phase delay plate can be disposed closer to the light blocking pattern than the wire grid polarizer.

[0020] In an embodiment of the disclosure, a minimum width of the light blocking pattern in a cross-section can be about 5 micrometers or less.

[0021] In an embodiment of the disclosure, a display device can include an eyepiece and a display module accommodation portion that provides an image to the eyepiece. The display module accommodation portion can include a substrate including a plurality of pixel regions, a driving circuit layer disposed on the substrate, a light emitting layer disposed on the driving circuit layer and continuously extending across the plurality of pixel regions, a plurality of color filters disposed on the light emitting layer and respectively overlapping the plurality of pixel regions, a light blocking pattern disposed between the plurality of color filters and including a metal material, a phase delay plate disposed on the plurality of color filters to delay a phase of incident light, and a wire grid polarizer disposed on the phase delay plate and including a plurality of metal patterns spaced apart from each other by a distance (e.g., a predetermined or selectable distance).

[0022] In an embodiment of the disclosure, the light blocking pattern can include a first metal layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer.

[0023] In an embodiment of the disclosure, among the first metal layer, the second metal layer, and the third metal layer, the third metal layer can be disposed closest to the phase delay plate, and the thickness of the third metal layer can be about 150 angstroms or less.

[0024] In an embodiment of the disclosure, the reflectance of the second metal layer can be about 80% or more.

[0025] In an embodiment of the disclosure, the light transmittance of the second metal layer can be about 0%. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0027] Figure 1 is a schematic perspective view of a display module according to an embodiment of the disclosure;

[0028] Figure 2 is a view showing an example of a schematic cross-section of a display device according to an embodiment of the disclosure;

[0029] Figure 3 is a schematic cross-sectional view taken along line I-I' according to an embodiment of the disclosure;

[0030] Figure 4 is a schematic cross-sectional view for explaining a recycling light generated in a display module according to an embodiment of the disclosure;

[0031] Figure 5 is a schematic cross-sectional view for explaining a recycling light generated in a display module according to an embodiment of the disclosure;

[0032] Figure 6 is a schematic cross-sectional view of a light emitting layer according to an embodiment of the disclosure;

[0033] Figure 7 is a schematic cross-sectional view of a light blocking pattern according to an embodiment of the disclosure;

[0034] Figure 8 is a graph showing reflectance with respect to wavelength for a wire grid polarizer according to an embodiment of the disclosure;

[0035] Figure 9 is a graph showing reflectance with respect to wavelength for a light blocking pattern according to an embodiment of the disclosure;

[0036] Figure 10is a graph showing reflectance with respect to thickness of a third metal layer according to an embodiment of the disclosure;

[0037] Figure 11 and Figure 12 is a schematic perspective view of a display device according to an embodiment of the disclosure; and

[0038] Figure 13 and Figure 14 is a side view of a display module housing portion according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0039] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of the apparatus or method disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the understanding of various embodiments.

[0040] Unless otherwise specified, the illustrated embodiments are to be understood as providing features of the present disclosure. Thus, unless otherwise specified, features, components, modules, layers, films, panels, regions, and / or aspects of the various embodiments (hereinafter referred to as "elements"), both individually and in combination, as well as steps, can be used in a variety of other embodiments and / or in other forms of the disclosure. Specifically, an illustrated embodiment need not include all of the features that are disclosed. An element of one embodiment can be combined with those of the other embodiments. An element or aspect of one embodiment can be eliminated. As such, the disclosure serves all possibilities that can be implied by any combination of the elements or aspects described.

[0041] The use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries, of the elements of the drawings. As such, neither cross-hatching nor shading is limiting of the particular materials, material properties, sizes, proportions, compositions, etc. of the elements being depicted. In addition, the use of any commonly understood abbreviations, acronyms, etc. is to be construed as commonly understood by one of ordinary skill in the art. Further, the elements in the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the embodiments. The embodiments can be implemented differently without departing from the scope of the present disclosure. A specific process sequence can be performed in an order different than described. For example, two sequentially described processes can be executed substantially concurrently, or in the reverse order that described. Additionally, like reference numerals and / or characters mentioned in the drawings denote like elements.

[0042] When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intermediate elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, there are no intermediate elements or layers present. To this end, the term “connected” can refer to physical, electrical, and / or fluidic connections having or not having intermediate elements having the same, none, or varied functions. Further, the axis in the first direction DR1, the axis in the second direction DR2, and the axis in the first direction DR3 are not limited to three axes such as x-axis, y-axis, and z-axis of a straight rectangular coordinate system, and can be interpreted in a broader sense. For example, the axis in the first direction DR1, the axis in the second direction DR2, and the axis in the first direction DR3 can be perpendicular to each other, or can be different directions that are not perpendicular to each other.

[0043] For the purpose of the present disclosure, “at least one of A and B” can be interpreted to mean only A, only B, or any combination of A and B. Also, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0044] Although the terms “first”, “second”, etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0045] Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper”, “on”, “over”, “side” (e.g., as in “sidewall”), and the like, can be used herein for ease of description to describe one element’s or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Well-known functions or constructions can not be described in detail for brevity.

[0046] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of the terms "including," "containing," "comprising," "having," and / or "including" when used in this specification are used to specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially," "approximately," and other like terms are used as synonyms for "about," and are employed to designate

[0047] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations of schematic views of implementations and / or intermediate structures. Consequently, variations to shapes of the regions illustrated in the drawings are to be expected from manufacturing techniques and / or tolerances. Therefore, embodiments disclosed herein should not necessarily be construed as limited to the particular shapes of regions as illustrated in the drawings, but are to include deviations in shapes that result, for example, from manufacturing. In this manner, regions illustrated in the drawings can be schematic in nature and the shapes of the regions can not reflect actual shapes of regions of devices and, as such, are not intended to limit the scope of the embodiments disclosed herein. In addition, the terms "exemplary," "for example," and "e.g." are used herein to mean "an example of." As used herein, "determining" is used to mean obtaining, creating, or calculating.

[0048] As is customary in the art, some of the example embodiments are described and illustrated with reference to functional blocks, units, and / or modules. A person skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by an electrical circuitry (or an optical circuitry), such as a logic circuit, a discrete component, a microprocessor, a hard-wired circuit, a memory element, a wiring connector, etc., which can be formed using semiconductor-based manufacturing techniques or other technologies. In the case of blocks, units and / or modules being implemented by a microprocessor or other similar hardware, they can be programmed and controlled by software (e.g., microcode) to perform various functions discussed herein, and can be driven selectively by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. In addition, each block, unit and / or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the concept of the present disclosure. Moreover, blocks, units and / or modules of some embodiments can be physically combined into more complex blocks, units and / or modules without departing from the scope of the concept of the present disclosure.

[0049] Unless otherwise defined or implied herein, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0051] Figure 1 is a schematic perspective view of a display module according to an embodiment of the present disclosure.

[0052] Referring to Figure 1 The display module DM according to the embodiment of the present disclosure can be parallel to a plane defined by the first direction DR1 and the second direction DR2. The display module DM can have a rectangular shape having a long side extending in the first direction DR1 and a short side extending in the second direction DR2 intersecting the first direction DR1. The display module DM can have a rectangular shape. However, the shape of the display module DM is not limited thereto, and the display module DM can have various shapes. For example, the display module DM can have various shapes such as a circular shape or a polygonal shape.

[0053] Figure 1 The following drawings illustrate the first direction DR1 to the third direction DR3, and the directions indicated by the first direction DR1 to the third direction DR3 used herein can be a relative concept and can change to other directions.

[0054] In the present disclosure, the first direction DR1 and the second direction DR2 can perpendicularly intersect each other, and the third direction DR3 can be orthogonal to a plane defined by the first direction DR1 and the second direction DR2.

[0055] A thickness direction of the display module DM can be a direction parallel to the third direction DR3 orthogonal to the plane defined by the first direction DR1 and the second direction DR2. In the present disclosure, a front surface (or an upper surface) and a rear surface (or a lower surface) of each of the members constituting the display module DM can be defined based on the third direction DR3.

[0056] The term "on a plane" used herein can mean a state in a plan view or when viewed on a plane parallel to the plane defined by the first direction DR1 and the second direction DR2. Unless otherwise defined, the term "overlap" used herein can mean overlapping on a plane.

[0057] An upper surface of the display module DM can be defined as a display surface DS, and can have a plane defined by the first direction DR1 and the second direction DR2. A user can be provided with an image generated through the display surface DS.

[0058] The display surface DS can include a display area DA and a non-display area NDA around the display area DA. The display area DA displays an image, and the non-display area NDA does not display an image. The non-display area NDA can surround the display area DA, but is not limited thereto. For example, the non-display area NDA can not be provided at one side (e.g., a single side) of the display area DA.

[0059] A plurality of pixel areas PX1, PX2, and PX3 can be provided in the display area DA. The pixel areas PX1, PX2, and PX3 can be provided in a matrix shape. The pixel areas PX1, PX2, and PX3 can each include a pixel circuit and a light emitting diode. All of the pixel areas PX1, PX2, and PX3 can generate light having the same color. In an embodiment of the present disclosure, the pixel areas PX1, PX2, and PX3 can include a plurality of groups generating light having different colors from each other.

[0060] Figure 2 is a view illustrating an example of a cross section of a display device according to an embodiment of the present disclosure.

[0061] Reference Figure 2The display module DM can include the circuit element layer 10, the light emitting element layer 20, and the lens layer 30. However, embodiments of the present disclosure are not limited thereto. For example, in embodiments of the present disclosure, the lens layer 30 can be omitted, or another functional layer can be further added.

[0062] The circuit element layer 10 can include a pixel circuit. The pixel circuit can control the operation of the light emitting element of the light emitting element layer 20 to be described later. The pixel circuit can include at least one transistor. The circuit element layer 10 can include a silicon substrate (or a substrate).

[0063] The light emitting element layer 20 can include a light emitting element disposed to overlap with the display area DA (see Figure 1 ). The light emitting element of the light emitting element layer 20 can be electrically connected to the driving element of the circuit element layer 10, and output light through the display area DA (see Figure 1 ) in response to a signal of the driving element. For example, the light emitting element included in the light emitting element layer 20 can include an organic light emitting element, an inorganic light emitting element, a quantum dot light emitting element, a micro LED light emitting element, or a nano LED light emitting element. However, embodiments of the present disclosure are not limited thereto, and the light emitting element can include various embodiments of the present disclosure as long as it can generate light in response to an electrical signal or the amount of light can be controllable. The light emitting element according to embodiments of the present disclosure is not limited thereto, and can include various embodiments of the present disclosure in which light can be generated in response to an electrical signal or the amount of light can be controllable.

[0064] The lens layer 30 can be disposed on the light emitting element layer 20, and include a lens. The lens can be disposed to correspond to the light emitting diode. The lens can collect light emitted from the light emitting diode. The light collected through the lens can be transmitted through the light guide portion.

[0065] Figure 3 is a schematic cross-sectional view taken along a line I-I' of Figure 1 according to an embodiment of the present disclosure.

[0066] Referring to Figure 3 , the display module DM according to an embodiment of the present disclosure can include a display panel DP, a phase delay plate QWP, a wire grid polarizer WGP, and a cover window CW. Here, the display panel DP can include a silicon substrate (or a substrate) BS, a driving circuit layer CL, an insulating layer IL, a first pixel electrode AE1, a second pixel electrode AE2, and a third pixel electrode AE3, a light emitting layer EL, a common electrode CE, a packaging layer TFE, a first color filter CF1, a second color filter CF2, and a third color filter CF3, a light blocking pattern BM, and a planarization layer PL.

[0067] Since the display module DM can include the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3, the silicon substrate BS can also include the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3. The silicon substrate BS can be a support member for supporting other components of the display module DM. For example, the silicon substrate BS can be a silicon wafer substrate.

[0068] The driving circuit layer CL can be disposed on the silicon substrate BS. The driving circuit layer CL can include various driving elements, lines, etc. for driving the light emitting elements. For example, the driving circuit layer CL can include various components such as transistors, storage capacitors, gate lines, and data lines.

[0069] The insulating layer IL can be disposed on the driving circuit layer CL. The insulating layer IL can limit contact between the first, second, and third pixel electrodes AE1, AE2, and AE3 and the driving circuit layer CL. The insulating layer IL can include an organic material and / or an inorganic material. For example, the insulating layer IL can include an inorganic material such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiO x N y ). However, the material of the insulating layer IL is not limited thereto, and the insulating layer IL can include various materials.

[0070] The first, second, and third pixel electrodes AE1, AE2, and AE3 can be disposed on the insulating layer IL. The first pixel electrode AE1 can overlap the first pixel area PX1. The second pixel electrode AE2 can overlap the second pixel area PX2. The third pixel electrode AE3 can overlap the third pixel area PX3. Each of the first, second, and third pixel electrodes AE1, AE2, and AE3 can be connected to the driving circuit layer CL through a contact hole passing through the insulating layer IL.

[0071] For example, each of the first, second, and third pixel electrodes AE1, AE2, and AE3 can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These materials can be used alone or in combination with each other. In an embodiment of the disclosure, each of the first, second, and third pixel electrodes AE1, AE2, and AE3 can be an anode electrode. Each of the first, second, and third pixel electrodes AE1, AE2, and AE3 can be a reflective electrode.

[0072] The light-emitting layer EL can be disposed on the insulating layer IL and the first pixel electrode AE1, the second pixel electrode AE2, and the third pixel electrode AE3. The light-emitting layer EL can continuously extend across the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. For example, the light-emitting layer EL can include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron injection layer, an electron transport layer, and the like. In an embodiment of the disclosure, the organic light-emitting layer can include a light-emitting material that emits white light. For example, the white light can be light in which blue light, green light, and red light can be mixed. Alternatively, the white light can be light in which blue light and yellow light can be mixed. Details will be described later with reference to FIG. 6. Figure 6 A detailed structure of the light-emitting layer EL is described.

[0073] The common electrode CE can be disposed on the light-emitting layer EL. The common electrode CE can continuously extend across the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. For example, the common electrode CE can include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, and the like. These materials can be used alone or in combination with each other. In an embodiment of the disclosure, the common electrode CE can be a cathode electrode. The common electrode CE can be a transmissive electrode or a semi-transmissive and semi-reflective electrode.

[0074] In the first pixel region PX1, the first pixel electrode AE1, the light-emitting layer EL, and the common electrode CE can constitute a first light-emitting element. In the second pixel region PX2, the second pixel electrode AE2, the light-emitting layer EL, and the common electrode CE can constitute a second light-emitting element. In the third pixel region PX3, the third pixel electrode AE3, the light-emitting layer EL, and the common electrode CE can constitute a third light-emitting element.

[0075] The encapsulation layer TFE can be disposed on the common electrode CE. The encapsulation layer TFE can continuously extend across the first pixel region PX1, the second pixel region PX2, and the third pixel region PX3. The encapsulation layer TFE can prevent impurities, moisture, and the like from being introduced from the outside into the first light-emitting element to the third light-emitting element. The encapsulation layer TFE can include at least one inorganic layer and at least one organic layer. For example, the inorganic layer can include silicon oxide, silicon nitride, silicon oxynitride, and the like. The inorganic layer of the encapsulation layer TFE can protect the light-emitting element from oxygen and moisture. The organic layer of the encapsulation layer TFE can protect the light-emitting element from dust and impurities. These can be used alone or in combination with each other. The organic layer can include a cured resin such as a polyacrylate.

[0076] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can be disposed on the encapsulation layer TFE. The first color filter CF1 can overlap the first pixel area PX1, the second color filter CF2 can overlap the second pixel area PX2, and the third color filter CF3 can overlap the third pixel area PX3. Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 can selectively transmit only light having a specific wavelength and absorb light having other wavelengths. For example, the first color filter CF1 can transmit red light, the second color filter CF2 can transmit green light, and the third color filter CF3 can transmit blue light. Accordingly, the first pixel area PX1 can emit red light, the second pixel area PX2 can emit green light, and the third pixel area PX3 can emit blue light. However, embodiments of the present disclosure are not limited thereto.

[0077] The light blocking pattern BM can be disposed on the encapsulation layer TFE. In a plan view, the light blocking pattern BM can be disposed between the first color filter CF1, the second color filter CF2, and the third color filter CF3 and not overlap the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3. The light blocking pattern BM can overlap the non-display area NDA.

[0078] The thickness THF of the encapsulation layer TFE in the third direction DR3 can be about 3 µm or less. In the case where the thickness THF of the encapsulation layer TFE is greater than about 3 µm, light LA2 emitted obliquely from the light emitting layer EL can reach the second color filter CF2 to cause color mixing of an image of the display module DM. Accordingly, the thickness THF of the encapsulation layer TFE can be reduced to prevent color mixing of an image of the display module DM. The thickness THF of the encapsulation layer TFE can be about 1.5 µm or less.

[0079] The light blocking pattern BM can block light incident on the light blocking pattern BM. Accordingly, color mixing between the first pixel area PX1, the second pixel area PX2, and the third pixel area PX3 can be prevented. The light blocking pattern BM can include a metal material having a multi-layer structure. The reflectivity of light can be about 50% or more. This will be described later with reference to FIG. 10. Here, the reflectivity can be a unit indicating light reflected from an object, measured in the case where the object receives light. Figure 7

[0080] ​A minimum width WDB of the light blocking pattern BM in a cross-section can be about 5 µm or less. A width WDB of the light blocking pattern BM in the first direction DR1 can be about 5 µm or less. As the resolution of the display module DM can increase, the distance between the color filters CF1, CF2, and CF3 can decrease. Accordingly, the light blocking pattern including the organic material can not be disposed between the color filters CF1, CF2, and CF3. In the light blocking pattern BM according to the embodiment of the disclosure, a preliminary light blocking layer including a metal material can be provided and then patterned to provide the light blocking pattern BM. Accordingly, although the distance between the color filters CF1, CF2, and CF3 is small, the light blocking pattern BM can be disposed between the color filters CF1, CF2, and CF3.

[0081] The light blocking pattern BM can have a light transmittance of about 0%. Accordingly, the light LA2 obliquely emitted from the light emitting layer EL can not pass through the light blocking pattern BM. Accordingly, the light LA2 obliquely emitted from the light emitting layer EL can be prevented from reaching the second color filter CF2 and causing color mixing. The light LA1 emitted from the light emitting layer EL in the third direction DR3 can pass through the first color filter CF1.

[0082] A planarization layer PL can be disposed on the color filters CF1, CF2, and CF3 and the light blocking pattern BM. The planarization layer PL can cover the color filters CF1, CF2, and CF3 and the light blocking pattern BM. The planarization layer PL can cover corresponding upper surfaces of the color filters CF1, CF2, and CF3 and the light blocking pattern BM, which can be different in height, and have a substantially planar upper surface. For example, the planarization layer PL can include an inorganic material and / or an organic material.

[0083] A phase delay plate QWP can be disposed on the display panel DP. Specifically, the phase delay plate QWP can be disposed on the color filters CF1, CF2, and CF3 and delay a phase of light passing through the phase delay plate QWP. The phase delay plate QWP can be in contact with the display panel DP. For example, the phase delay plate QWP can be of a film type or a liquid crystal coating type. For example, the phase delay plate QWP can be separately manufactured to be attached to the display panel DP or can be disposed on the display panel DP (e.g., directly on the display panel DP) through a semiconductor photolithography tool. In the embodiment of the disclosure, the phase delay plate QWP can include a λ / 4 phase delay plate. The phase delay plate QWP can delay a phase of light incident on the phase delay plate QWP by about λ / 4.

[0084] The wire grid polarizer WGP can be disposed on the phase delay plate QWP. Specifically, the wire grid polarizer WGP can be in contact with the phase delay plate QWP. The wire grid polarizer WGP can include a plurality of metal patterns spaced apart from each other by a certain distance (e.g., a predetermined or selectable distance). For example, the metal patterns can be spaced apart from each other in the first direction DR1. For example, the wire grid polarizer WGP can be of a film type or a liquid crystal coating type. For example, the wire grid polarizer WGP can be manufactured separately to be attached to the display panel DP, or can be disposed on the display panel DP (e.g., directly on the display panel DP) by a semiconductor photolithography machine.

[0085] The metal patterns of the wire grid polarizer WGP can extend in parallel to each other in one direction (e.g., the second direction DR2). For example, a component of the incident light polarized in a direction perpendicular to the extension direction of the wire grid polarizer WGP can pass through the wire grid polarizer WGP. Conversely, a component of the incident light polarized in a direction parallel to the extension direction of the wire grid polarizer WGP can be reflected by the wire grid polarizer WGP. The wire grid polarizer WGP can include a metal having a relatively high reflectivity. For example, the wire grid polarizer WGP can include a metal such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), chromium (Cr), iron (Fe), nickel (Ni), or a combination thereof. These metals can be used alone or in combination with each other.

[0086] The phase delay plate QWP can be disposed closer to the light blocking pattern BM than the wire grid polarizer WGP. The wire grid polarizer WGP can be disposed closer to the cover window CW than the phase delay plate QWP. The wire grid polarizer WGP can be in contact with the upper surface of the phase delay plate QWP. Due to the phase delay plate QWP and the wire grid polarizer WGP, a portion of the light emitted from the light emitting layer EL can be recycled. This will be described later with reference to FIG. 6. Figure 4

[0087] The cover window CW can be disposed on the wire grid polarizer WGP. The cover window CW can protect the display panel DP. For example, the cover window CW can include tempered glass, reinforced plastic, or the like. Alternatively, the cover window CW can be disposed as a single layer, or have a structure in which a plurality of functional layers can be stacked on each other.

[0088] The display module DM according to the embodiment of the disclosure can be a display device that displays an image. For example, the display module DM can be a display device such as an organic light emitting display device, a liquid crystal display device, an organic light emitting diode (OLEDos) on a silicon substrate, a liquid crystal (LCos) on a silicon substrate, or a light emitting diode (LEDos) on a silicon substrate. In the embodiment of the disclosure, the display module DM can be a display device such as the OLEDos.

[0089] Figure 4 ​is a schematic cross-sectional view for explaining a recycling light generated in a display module according to an embodiment of the disclosure.

[0090] Reference Figure 4 A portion of the light emitted from the light-emitting layer EL can be recycled due to the phase retardation plate QWP and the wire grid polarizer WGP. The first light L1 emitted from the light-emitting layer EL can pass through the phase retardation plate QWP. The phase of the first light L1 passing through the phase retardation plate QWP can be delayed by about λ / 4. The first light L1 passing through the phase retardation plate QWP can be incident on the wire grid polarizer WGP. A first linearly polarized light LP1 of the first light L1 incident on the wire grid polarizer WGP can be transmitted, and a second light L2, which can be a portion of the first light L1 incident on the wire grid polarizer WGP, can be reflected. The first linearly polarized light LP1 can correspond to a component of the incident light (i.e., the first light L1) polarized in a direction perpendicular to an extension direction of the wire grid polarizer WGP, and a second linearly polarized light LP2 of the second light L2 can correspond to a component of the incident light (i.e., the first light L1) polarized in a direction parallel to the extension direction of the wire grid polarizer WGP. The second light L2 reflected by the wire grid polarizer WGP can pass through the phase retardation plate QWP to be converted from the second linearly polarized light LP2 into a first circularly polarized light R with a phase delay of about λ / 4. The first circularly polarized light R can be a right-handed circularly polarized light.

[0091] The first circularly polarized light R can be incident on the common electrode CE, and a third light L3 reflected from the common electrode CE is converted into a second circularly polarized light L. The second circularly polarized light L can be a left-handed circularly polarized light. The second circularly polarized light L can pass through the phase retardation plate QWP to be converted into a first linearly polarized light LP1 with a phase delay of about λ / 4. The third light L3 converted into the first linearly polarized light LP1 can be incident on the wire grid polarizer WGP and pass through the wire grid polarizer WGP.

[0092] As a result, a portion of the light emitted from the light-emitting layer EL can be recycled instead of being blocked due to the phase retardation plate QWP and the wire grid polarizer WGP, which can be disposed on the display panel DP. An absorption polarizer blocking a portion of the light emitted from the light-emitting layer EL can not be disposed on the display panel DP. For example, the phase retardation plate QWP and the wire grid polarizer WGP can replace the absorption polarizer. Accordingly, the light efficiency of the display module DM can be improved.

[0093] Figure 5 is a schematic cross-sectional view for explaining a recycling light generated in a display module according to an embodiment of the disclosure. Hereinafter, components same / similar to those described with reference to Figures 1 to 4 components same / similar to those described with reference to

[0094] Reference Figure 5 Light that is emitted obliquely from the light-emitting layer EL and reflected from the light-blocking pattern BM can be recycled. First light L1' emitted from the light-emitting layer EL can pass through the phase delay plate QWP, and the phase of the first light L1' can be delayed by about λ / 4. The first light L1' that passes through the phase delay plate QWP can be incident on the wire grid polarizer WGP.

[0095] First linearly polarized light LP1 of the first light L1' that is incident on the wire grid polarizer WGP can pass through the wire grid polarizer WGP. Second light L2' that can be a portion of the first light L1' incident on the wire grid polarizer WGP can be reflected by the wire grid polarizer WGP. Second linearly polarized light LP2 of the second light L2' can travel toward the phase delay plate QWP. The first linearly polarized light LP1 can be a component of the incident light (i.e., the first light L1') that is polarized in a direction perpendicular to the direction of extension of the wire grid polarizer WGP, and the second linearly polarized light LP2 can be a component of the incident light (i.e., the first light L1') that is polarized in a direction parallel to the direction of extension of the wire grid polarizer WGP.

[0096] The second linearly polarized light LP2 of the second light L2' that is reflected by the wire grid polarizer WGP can pass through the phase delay plate QWP to be phase-delayed by about λ / 4, thereby being converted into first circularly polarized light R. The first circularly polarized light R can be right-handed circularly polarized light.

[0097] A portion of the first circularly polarized light R can be incident on the light-blocking pattern BM and reflected from the light-blocking pattern BM. The reflected third light L3' can travel toward the phase delay plate QWP. Here, the reflectivity of light of the light-blocking pattern BM can be at least about 50% or more. In the case where the reflectivity of light of the light-blocking pattern BM is less than about 50%, it can be less likely to recycle light reflected from the light-blocking pattern BM to improve efficiency. For example, light reflected from the light-blocking pattern BM can be less, and thus light efficiency can not be improved compared to a conventional display module. The reflectivity of the light-blocking pattern BM can be about 80% or more.

[0098] The first circularly polarized light R can be reflected from the light-blocking pattern BM to be converted into second circularly polarized light L. The second circularly polarized light L that is the third light L3' can be left-handed circularly polarized light. The second circularly polarized light L can pass through the phase delay plate QWP to be phase-delayed by about λ / 4, thereby being converted into first linearly polarized light LP1. The third light L3' that is converted into the first linearly polarized light LP1 can pass through the wire grid polarizer WGP.

[0099] As described above, light incident between the color filters CF1, CF2, and CF3, which is emitted obliquely from the light-emitting layer EL, can be reflected by the light-blocking pattern BM to be recycled to improve light efficiency. Here, the light efficiency can mean the amount of light with respect to power consumption. Light reflected from the light-blocking pattern BM can pass through the phase delay plate QWP to be phase-delayed by about λ / 4, thereby passing through the wire grid polarizer WGP. Accordingly, the light-blocking pattern BM having high reflectivity can reflect light to recycle a portion of the light, which would not be utilized if the light-blocking pattern BM is not included or the light-blocking pattern BM is a light-blocking pattern BM including an organic material.

[0100] Figure 6 is a schematic cross-sectional view of a light-emitting layer according to an embodiment of the disclosure.

[0101] Reference Figure 6 The light-emitting layer EL according to an embodiment of the disclosure can include a first emission layer EML1, a first charge generation layer CGL1, and a second emission layer EML2, which are sequentially stacked in a third direction DR3 and disposed between a pixel electrode AE and a common electrode CE. Figure 6 The pixel electrode AE shown in Figure 6 A tandem light-emitting element is shown as the light-emitting layer EL, but the structure of the light-emitting layer EL is not limited thereto. The structure of the light-emitting layer EL can be changed as needed.

[0102] For example, in Figure 3 The light-emitting layer EL can include a first light-emitting layer overlapping the first pixel region PX1, a second light-emitting layer overlapping the second pixel region PX2, and a third light-emitting layer overlapping the third pixel region PX3. The first to third light-emitting layers can emit red light, green light, and blue light, respectively. Each of the first to third light-emitting layers can be formed by a separate deposition process.

[0103] The pixel electrode AE and the common electrode CE can face each other. The first charge generation layer CGL1 can be disposed between the pixel electrode AE and the common electrode CE. The first emission layer EML1 can be disposed between the pixel electrode AE and the first charge generation layer CGL1. The second emission layer EML2 can be disposed between the first charge generation layer CGL1 and the common electrode CE.

[0104] The light-emitting layer EL according to an embodiment of the disclosure can be a light-emitting layer EL that provides white light. The light-emitting layer EL according to an embodiment of the disclosure can be an upper emission type. The pixel electrode AE can be a reflective electrode, and the common electrode CE can be a transmissive electrode or a semi-transmissive and semi-reflective electrode. In the upper emission type, a high aperture ratio can be ensured.

[0105] The light emitting layer EL according to the embodiment of the disclosure can be a tandem light emitting layer EL. As described above, the light emitting layer EL according to the embodiment of the disclosure can include a first charge generation layer CGL1 disposed between the pixel electrode AE and the common electrode CE. The light emitting layer EL according to the embodiment of the disclosure has a structure including a first stack and a second stack based on the first charge generation layer CGL1, the first stack can include a first emission layer EML1 disposed below the first charge generation layer CGL1, and the second stack can include a second emission layer EML2 disposed above the first charge generation layer CGL1. The first charge generation layer CGL1 can be disposed on the first stack. The first stack and the second stack can be sequentially stacked in the third direction DR3.

[0106] The first charge generation layer CGL1 can be used to inject charges into each of the emission layers EML1 and EML2. The first charge generation layer CGL1 can be used to adjust charge balance between the first stack and the second stack. The first charge generation layer CGL1 can include an n-type charge generation layer n-CGL1 and a p-type charge generation layer p-CGL1. The p-type charge generation layer p-CGL1 can be disposed on the n-type charge generation layer n-CGL1.

[0107] The first charge generation layer CGL1 can have a structure in which the n-type charge generation layer n-CGL1 and the p-type charge generation layer p-CGL1 can be joined to each other. The n-type charge generation layer n-CGL1 can be disposed closer to the pixel electrode AE than to the common electrode CE. The p-type charge generation layer p-CGL1 can be disposed closer to the common electrode CE than to the pixel electrode AE. The n-type charge generation layer n-CGL1 can provide electrons to the first emission layer EML1 adjacent to the pixel electrode AE, and the p-type charge generation layer p-CGL1 provides holes to the second emission layer EML2 included in the second stack. A buffer layer (not shown) can also be included between the n-type charge generation layer n-CGL1 and the p-type charge generation layer p-CGL1. Since the first charge generation layer CGL1 can be disposed between the first stack and the second stack to provide charges to each of the emission layers EML1 and EML2, luminance efficiency can be improved and driving voltage can be reduced.

[0108] The first stack can further include a first hole transport region HTR1 disposed between the pixel electrode AE and the first emission layer EML1. The first hole transport region HTR1 can include at least one of a hole injection layer and a hole transport layer. The first hole transport region HTR1 can further include at least one of a hole buffer layer and an electron blocking layer.

[0109] The first stack can further include a first electron transport region ETR1 disposed between the first emission layer EML1 and the first charge generation layer CGL1. The first electron transport region ETR1 can include at least one of a hole blocking layer, an electron transport layer, and an electron injection layer, but is not limited thereto.

[0110] The second stack can be disposed on the first charge generation layer CGL1. The second stack can further include a second hole transport region HTR2 disposed between the first charge generation layer CGL1 and a second emission layer EML2. The foregoing description of the first hole transport region HTR1 can be applicable to the second hole transport region HTR2. The first hole transport region HTR1 and the second hole transport region HTR2 can be the same as or different from each other.

[0111] The second stack can further include a second electron transport region ETR2 disposed between the second emission layer EML2 and the common electrode CE. The foregoing description of the first electron transport region ETR1 can be applicable to the second electron transport region ETR2, and thus the second electron transport region ETR2 will not be specifically described herein. The first electron transport region ETR1 and the second electron transport region ETR2 can be the same as or different from each other.

[0112] Figure 7 is a schematic cross-sectional view of a light blocking pattern according to an embodiment of the disclosure.

[0113] Referring to Figure 7 , the light blocking pattern BM can include a metal layer having a multi-layer structure. The light blocking pattern BM can include a first metal layer CIL1, a second metal layer CIL2, and a third metal layer CIL3. The first metal layer CIL1, the second metal layer CIL2, and the third metal layer CIL3 can be sequentially stacked with each other. The second metal layer CIL2 can be disposed on the first metal layer CIL1, and the third metal layer CIL3 can be disposed on the second metal layer CIL2.

[0114] The second metal layer CIL2 can be disposed between the first metal layer CIL1 and the third metal layer CIL3. Among the first metal layer CIL1, the second metal layer CIL2, and the third metal layer CIL3, the third metal layer CIL3 can be disposed to be closest to Figure 3 a phase delay plate QWP (see Figure 3 ) in the light emitting layer EL (see Figure 3 ). Figure 3

[0115] ​The reflectance of the light-blocking pattern BM can be about 50% or more. For example, a ratio of a sum of first reflected light OL1, which is reflected from a surface of the third metal layer CIL3, of light IL1 incident toward the light-blocking pattern BM and second reflected light OL2, which is reflected from a surface of the second metal layer CIL2, of the light IL1, can be about 50% or more.

[0116] The light transmittance of the light-blocking pattern BM can be substantially about 0%. For example, light IL1 incident toward the light-blocking pattern BM can not pass through the light-blocking pattern BM. Since the light-blocking pattern BM can be disposed between the color filters CF1, CF2, and CF3 (see Figure 3 ), in the case where the light transmittance is about 0%, color mixing between the color filters CF1, CF2, and CF3 (see Figure 3 ) can be prevented.

[0117] The third metal layer CIL3 can be disposed on (e.g., directly on) the second metal layer CIL2. A thickness TH2 of the third metal layer CIL3 in the third direction DR3 can be about 150 angstroms (or ) or less. As the thickness TH2 of the third metal layer CIL3 decreases, the reflectance of the light-blocking pattern BM increases. Thus, in the case where the thickness TH2 of the third metal layer CIL3 is greater than about 150 angstroms , the reflectance of the light-blocking pattern BM can decrease to less than about 50%, and thus the effect of increasing light efficiency can not be significant. This will be described later with reference to Figure 10 .

[0118] The third metal layer CIL3 can include titanium. The third metal layer CIL3 can prevent the second metal layer CIL2 from being corroded when the light-blocking pattern BM is patterned. However, since the third metal layer CIL3 can decrease the reflectance of the light-blocking pattern BM, the third metal layer CIL3 having a minimum thickness can be used.

[0119] The second metal layer CIL2 can be disposed between the first metal layer CIL1 and the third metal layer CIL3. The second metal layer CIL2 can include aluminum. A thickness TH1 of the second metal layer CIL2 in the third direction DR3 can be about 1000 angstroms or more. In the case where the thickness TH1 of the second metal layer CIL2 is less than about 1000 angstroms , the light transmittance of the light-blocking pattern BM can not be substantially about 0%, and the reflectance of the light-blocking pattern BM can be less than about 50%. The second metal layer CIL2 can have a thickness TH1 of about 1500 angstroms to about 2000 angstroms .

[0120] The light transmittance of the second metal layer CIL2 can be substantially about 0%. Since the thickness TH1 of the second metal layer CIL2 can be about 1000 angstroms or more, light can not pass through the second metal layer CIL2. Accordingly, color mixing of the display module DM (see Figure 3 ) can be prevented.

[0121] The reflectance of the second metal layer CIL2 can be about 80% or more. The second metal layer CIL2 can be a main component for recycling light. Accordingly, high reflectance can be required. In the case where the reflectance of the second metal layer CIL2 is less than about 80%, the reflectance of the light blocking pattern BM can be decreased to less than about 50%. Accordingly, the effect of increasing the light efficiency of the display module DM (see Figure 3 ) according to embodiments of the disclosure can not be significant.

[0122] The first metal layer CIL1 can include at least one of titanium, molybdenum, and molybdenum-tantalum oxide (MoTaO). The first metal layer CIL1 can be disposed on a lower surface of the second metal layer CIL2 (e.g., directly on the lower surface of the second metal layer CIL2). The first metal layer CIL1 can improve adhesion between the second metal layer CIL2 and the encapsulation layer TFE (see Figure 3 ).

[0123] Figure 8 is a graph showing reflectance with respect to wavelength for a wire grid polarizer according to embodiments of the disclosure.

[0124] Referring to Figure 3 and Figure 8 , the wire grid polarizer WGP (see Figure 3 ) can have a reflectance that can be constantly high regardless of wavelength. For example, about 85% of light incident toward the wire grid polarizer WGP can be reflected. Accordingly, in order to improve the light emission efficiency of the display module DM, it is required to recycle light reflected by the wire grid polarizer WGP.

[0125] Table 1 below shows a light efficiency increase ratio according to embodiments of the disclosure and comparative examples.

[0126] In Examples 1 to 3, titanium having a thickness of about 600 angstroms was used as the first metal layer CIL1 (see Figure 7 ), aluminum having a thickness of about 2000 angstroms was used as the second metal layer CIL2 (see Figure 7 ), and titanium was used as the third metal layer CIL3 (see Figure 7 ). Example 1 is a case where the thickness of the third metal layer CIL3 (see Figure 7 ) is about 30 angstroms Example 2 is a case where the thickness of the third metal layer CIL3 (see Figure 7 ) is about 50 angstroms Example 3 can be a case where the thickness of the third metal layer CIL3 (see Figure 7 ) is about 60 angstroms .

[0127] The comparative example is a case where a light-blocking pattern including an organic material is used. The light efficiency ratio indicates how much the light efficiency is increased in the case where the light-blocking pattern is applied, based on the assumption that the light efficiency ratio is about 100% in the case where there is no light-blocking pattern.

[0128] [Table 1]

[0129]

[0130] Referring to Figure 3 and Table 1, it can be confirmed that the reflectance of the cases where a metal material having a multi-layer structure including titanium / aluminum / titanium is used as the light-blocking pattern BM (Example 1, Example 2, and Example 3) is about 83%, about 78%, and about 76%, respectively, each of which is higher than about 4.5% of the reflectance of the case where an organic material is used as the light-blocking pattern BM (comparative example). In terms of the light efficiency ratio, it can be confirmed that each of Examples 1 to 3 has a higher light efficiency ratio than the comparative example in all cases of red light, blue light, green light, and white light. In Examples 1, 2, and 3, the reflectance of the light-blocking pattern BM is high, and thus the amount of recycled light can be large, resulting in an increase in the light efficiency ratio.

[0131] In the case of testing the light efficiency ratio (white), the comparative example has a value of about 114.8%, but Examples 1, 2, and 3 according to the embodiments of the disclosure have higher values of about 143%, about 138.1%, and about 136.7%, respectively. When Examples 1, 2, and 3 are compared with each other, Example 1 in which the third metal layer CIL3 (see Figure 7 ) has the smallest thickness has the highest light efficiency ratio of about 143%. Example 3 in which the third metal layer CIL3 (see Figure 7 ) has the largest thickness has the lowest light efficiency ratio of about 136.7%. For example, it can be determined that the light efficiency ratio increases as the thickness of the third metal layer CIL3 (see Figure 7 ) decreases. As described later with reference to Figure 9 , this is because the reflectance of the light-blocking pattern BM (see Figure 7 ) increases as the thickness of the third metal layer CIL3 (see Figure 7 ) decreases.

[0132] In particular, in red light, the light efficiency ratio of Example 2 is about 140.3%, and the light efficiency ratio of Example 3 is about 142.4%, which indicates that even though the third metal layer CIL3 (see Figure 7 ) has a greater thickness, Example 3 exhibits a higher light efficiency ratio than Example 2. However, Example 1, in which the third metal layer CIL3 (see Figure 7 ) has a smaller thickness than each of Examples 2 and 3, exhibits a light efficiency ratio of about 142.7% as a value greater than each of the values of Examples 2 and 3.

[0133] Except for the case of red light, the light efficiency ratios in the cases of green light and blue light each show a similar tendency to the light efficiency ratio in the case of white light. For example, Example 1, in which the third metal layer CIL3 (see Figure 7 ) has the smallest thickness, exhibits the highest light efficiency ratio, and Example 3, in which the third metal layer CIL3 (see Figure 7 ) has the greatest thickness, exhibits the lowest light efficiency ratio. Considering the results in Table 1, it can be confirmed that as the thickness of the third metal layer CIL3 (see Figure 7 ) of the light-blocking pattern BM decreases, the light efficiency ratio increases.

[0134] Figure 9 is a graph showing the reflectance with respect to wavelength for a light-blocking pattern according to an embodiment of the disclosure.

[0135] Referring to Figure 9 , line 1 shows the reflectance with respect to wavelength for the above-described Example 1, and line 2 shows the reflectance with respect to wavelength for the above-described Example 2. Examples 1 and 2 differ in that the thickness of the third metal layer CIL3 (see Figure 7 ) thereof is about 30 angstroms and about 50 angstroms , respectively. In Example 1, in which the third metal layer CIL3 (see Figure 7 ) has the smallest thickness, the reflectance with respect to the entire visible wavelength spectrum is about 80% or more and is higher than the reflectance of Example 2.

[0136] Figure 10 is a graph showing the reflectance with respect to thickness for a third metal layer according to an embodiment of the disclosure.

[0137] Referring to Figure 10 , the reflectance of a light-blocking pattern BM (see Figure 7 ) with respect to the thickness of a third metal layer CIL3 (see Figure 7 ) is shown. It can be generally confirmed that as the thickness of the third metal layer CIL3 (see Figure 7 ) decreases, the light-blocking pattern BM (seeFigure 7 ) increases.

[0138] In the case where the thickness of the third metal layer CIL3 (see Figure 7 ) is about 15 angstroms , the reflectance of the light blocking pattern BM (see Figure 7 ) can be about 86%. In the case where the thickness of the third metal layer CIL3 (see Figure 7 ) is about 30 angstroms , the reflectance of the light blocking pattern BM (see Figure 7 ) can be about 82%. In the case where the thickness of the third metal layer CIL3 (see Figure 7 ) is about 45 angstroms , the reflectance of the light blocking pattern BM (see Figure 7 ) can be about 78%. In the case where the thickness of the third metal layer CIL3 (see Figure 7 ) is about 60 angstroms , the reflectance of the light blocking pattern BM (see Figure 7 ) can be about 74%. The thickness of the third metal layer CIL3 (see Figure 7 ) and the reflectance of the light blocking pattern BM (see Figure 7 ) can have an inverse relationship with each other.

[0139] Although not shown in Figure 10 , in the case where the thickness of the third metal layer CIL3 (see Figure 7 ) is about 150 angstroms , the reflectance of the light blocking pattern BM (see Figure 7 ) can be about 50%. In the case where the reflectance of the light blocking pattern BM (see Figure 7 ) is less than about 50%, the light efficiency improvement effect of the display module DM (see Figure 3 ) can not be significant. Accordingly, the thickness of the third metal layer CIL3 (see Figure 7 ) can be about 150 angstroms or less.

[0140] Figure 11 and Figure 12 are schematic perspective views illustrating a display device according to an embodiment of the present disclosure.

[0141] Referring to Figure 11 and Figure 12 , the display device DD according to an embodiment of the present disclosure can include a display module accommodation portion 100, a first eyepiece 100a, a second eyepiece 100b, and an eyeglass temple 200. For example, the display device DD according to an embodiment of the present disclosure can be implemented as a head-mounted display. Accordingly, hereinafter, the head-mounted display will be described as an example of the display device DD.

[0142] The display module housing portion 100 can include a display module that displays an image and an optical member for providing the image displayed on the display module to the first eyepiece 100a and the second eyepiece 100b. Here, the display module can correspond to the display module DM illustrated in Figure 1 and Figures 3 to 5 The display module housing portion 100 will be described in detail later.

[0143] The first eyepiece 100a and the second eyepiece 100b can be disposed in a surface (e.g., a single surface) of the display module housing portion 100. In particular, the first eyepiece 100a and the second eyepiece 100b can be disposed in a lower surface of the display module housing portion 100. For example, the first eyepiece 100a can be a left eye lens in which a left eye of the user can be positioned, and the second eyepiece 100b can be a right eye lens in which a right eye of the user can be positioned. The user can view an image displayed by the display module of the display module housing portion 100 through the first eyepiece 100a and the second eyepiece 100b.

[0144] The display device DD can provide the user with an image displayed on the display module of the display module housing portion 100 through the first eyepiece 100a and the second eyepiece 100b. As a result, the display device DD can provide the user with a virtual image displayed by the display module of the display module housing portion 100. For example, the display device DD can implement virtual reality (VR).

[0145] The temple 200 can be a component that allows the user to easily put on or take off. However, embodiments of the present disclosure are not limited thereto, and the display device DD can include a head mounting band that can be seated on the head, instead of the temple 200.

[0146] Figure 13 and Figure 14 are side views of display module housing portions according to embodiments of the present disclosure.

[0147] Figure 13 are side views illustrating examples of display module housing portions of electronic devices in Figure 11 and Figure 12 Figure 14 are side views illustrating examples of display module housing portions of electronic devices in Figure 11 and Figure 12 For example, Figure 13 and Figure 14 illustrate components of the display module housing portion 100 for providing images to the first eyepiece 100a and the second eyepiece 100b of the display device DD in Figure 11 and Figure 12 ​​

[0148] Referring to Figure 13 and Figure 14 , the display module housing portion 100 of the display device DD according to the embodiment of the disclosure can include the display panel DP, the first phase delay plate QWP1, the wire grid polarizer WGP, the second phase delay plate QWP2, the half mirror HM, the third phase delay plate QWP3, and the reflective polarizer RP.

[0149] The wire grid polarizer WGP can be disposed between the display panel DP and the eyepieces 100a and 100b. The first phase delay plate QWP1 can be disposed between the wire grid polarizer WGP and the display panel DP, and adjacent to the wire grid polarizer WGP. Figure 13 and Figure 14 The first phase delay plate QWP1 and the wire grid polarizer WGP shown in Figures 3 to 5 may correspond to the phase delay plate QWP and the wire grid polarizer WGP shown in

[0150] In the embodiment of the disclosure, as shown in Figure 13 , the first phase delay plate QWP1 can be in contact with a surface (e.g., a single surface) of the display panel DP, the wire grid polarizer WGP can be in contact with a surface (e.g., a single surface) of the first phase delay plate QWP1, and the reflective polarizer RP can be in contact with a surface (e.g., a single surface) of the eyepieces 100a and 100b. The display panel DP, the first phase delay plate QWP1, the wire grid polarizer WGP, and the cover window (e.g., the cover window CW in Figure 3 ) can constitute the display module DM, and the display module DM can correspond to the display module DM shown in Figure 3 .

[0151] In the embodiment of the disclosure, as shown in Figure 14 , the wire grid polarizer WGP can be in contact with a surface of the eyepieces 100a and 100b, and the first phase delay plate QWP1 can be disposed between the wire grid polarizer WGP and the reflective polarizer RP. Specifically, a surface (e.g., a single surface) of the first phase delay plate QWP1 can be in contact with the wire grid polarizer WGP, and another surface of the first phase delay plate QWP1 can be in contact with the reflective polarizer RP. The display panel DP and the cover window can constitute the display module DM, and the display module DM can not include the first phase delay plate QWP1 and the wire grid polarizer WGP.

[0152] The second phase delay plate QWP2 can be disposed between the display panel DP and the eyepieces 100a and 100b. Specifically, the second phase delay plate QWP2 can be in contact with a surface (e.g., a single surface) of the half mirror HM. In an embodiment of the disclosure, the second phase delay plate QWP2 can include a λ / 4 phase delay plate. The second phase delay plate QWP2 can delay a phase of incident light by about λ / 4.

[0153] The half mirror HM can be disposed between the second phase delay plate QWP2 and the third phase delay plate QWP3. Specifically, a surface (e.g., a single surface) of the half mirror HM can be in contact with the second phase delay plate QWP2, and another surface of the half mirror HM can be in contact with the third phase delay plate QWP3.

[0154] The half mirror HM can include a semi-transmissive semi-reflective mirror that transmits a portion of light and reflects the other portion of light. For example, the half mirror HM can include glass having a surface (e.g., a single surface) on which a semi-transmissive semi-reflective metal film can be disposed. For example, the semi-transmissive semi-reflective metal film can include a semi-transmissive semi-reflective metal material such as magnesium (Mg), silver (Ag), an alloy containing magnesium (Mg) and silver (Ag), or a combination thereof. These materials can be used alone or in combination with each other.

[0155] The third phase delay plate QWP3 can be in contact with another surface of the half mirror HM. In an embodiment of the disclosure, the third phase delay plate QWP3 can include a λ / 4 phase delay plate. The third phase delay plate QWP3 can delay a phase of incident light by about λ / 4.

[0156] The reflective polarizer RP can be disposed between the eyepieces 100a and 100b and the second phase delay plate QWP2. Specifically, the reflective polarizer RP can be disposed between the eyepieces 100a and 100b and the third phase delay plate QWP3. The reflective polarizer RP can transmit first linearly polarized light of which a vertical vibration (or polarization in a vertical direction) is made, and reflect second linearly polarized light of which a horizontal vibration (or polarization in a horizontal direction) is made. For example, the reflective polarizer RP can be an advanced polarizing film (APF) or a dual brightness enhancement film (DBEF). However, embodiments of the disclosure are not limited thereto.

[0157] The eyepieces 100a and 100b can be convex lenses or Fresnel lenses. Since a polarizer (e.g., the reflective polarizer RP) or a wire grid polarizer WGP can be in contact with a surface (e.g., a single surface) of the eyepieces 100a and 100b, the surface (e.g., a single surface) of the eyepieces 100a and 100b can be disposed to be substantially flat to easily make contact with the polarizer. Convex lenses or Fresnel lenses can be disposed in the other surface of the eyepieces 100a and 100b.

[0158] Since the display module housing portion 100 can include the above components, an image can be provided to a user through the oculars 100a and 100b. For example, a portion of light emitted from the display module DM can pass through the second phase delay plate QWP2, the half mirror HM, and the third phase delay plate QWP3, and then be incident on the reflective polarizer RP. A portion of the light incident on the reflective polarizer RP can be reflected to be incident on the half mirror HM. A portion of the light incident on the half mirror HM can be reflected to be incident on the oculars 100a and 100b. Accordingly, an image displayed on the display module DM can be provided to the user.

[0159] In the display device DD according to the embodiment of the disclosure, a high-resolution display device DD in which, instead of using an organic light blocking pattern, a metal material having a multi-layer structure is used can be provided, and a light blocking pattern BM having a light reflectance of about 50% or more can be provided. Accordingly, light reflected by the wire grid polarizer WGP can be reflected again to improve light efficiency.

[0160] Further, since the light transmittance of the light blocking pattern BM can be about 0%, color mixing can be prevented.

[0161] Although the embodiments of the disclosure have been described, it is understood that the disclosure should not be limited to these embodiments of the disclosure, but various changes and modifications can be made by one of ordinary skill in the art within the spirit and scope of the disclosure as claimed by the appended claims. Accordingly, the technical scope of the disclosure is not limited to what is described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display module, characterized by Comprising: a substrate including a plurality of pixel regions; a driving circuit layer disposed on the substrate; a light emitting layer disposed on the driving circuit layer and continuously extending across the plurality of pixel regions; a plurality of color filters disposed on the light emitting layer and respectively overlapping the plurality of pixel regions; a light blocking pattern disposed between the plurality of color filters and including a metal material having a multi-layer structure; a phase delay plate disposed on the plurality of color filters to delay a phase of incident light; and a wire grid polarizer disposed on the phase delay plate and including a plurality of metal patterns spaced apart by a certain distance from each other. The light blocking pattern includes:

2. The display module of claim 1, wherein, a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. 3.The display module of claim 2, wherein: the third metal layer is disposed closest to the phase delay plate among the first metal layer, the second metal layer, and the third metal layer, and a thickness of the third metal layer is 150 angstroms or less. a thickness of the second metal layer is 1000 angstroms or more.

4. The display module of claim 2, wherein, a reflectivity of the second metal layer is 80% or more.

5. The display module of claim 2, wherein, a transmittance of the second metal layer is 0%.

6. The display module of claim 2, wherein, the first metal layer includes titanium, molybdenum, or molybdenum-tantalum oxide.

7. The display module of claim 2, wherein, the second metal layer includes aluminum.

8. The display module of claim 2, wherein, the third metal layer includes titanium.

9. The display module of claim 2, wherein, the phase delay plate includes a λ / 4 phase delay plate.

10. The display module of claim 1, wherein, ​

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