Magnetic memory device and semiconductor device

Abstract

A magnetic memory device and a semiconductor device are provided. The magnetic memory device may include: a lower electrode on a substrate; a magnetic tunnel junction pattern on the lower electrode; a capping pattern on the magnetic tunnel junction pattern; a stress inducing layer on the capping pattern and having a lattice constant less than that of tantalum; a boron trapping layer in contact with the stress inducing layer; and an upper electrode on the boron trapping layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0035432 filed on March 13, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device, and more particularly, to a magnetic memory device including a magnetic tunnel junction (MTJ) structure. Background Art

[0004] Magnetic memory devices may include magnetic tunnel junctions. A magnetic tunnel junction may include two magnets and an insulating film located therebetween. The resistance value of a magnetic tunnel junction can vary depending on the magnetization directions of the two magnets. For example, when the magnetization directions of the two magnets are antiparallel to each other, the magnetic tunnel junction may have a high resistance value, while when the magnetization directions of the two magnets are parallel to each other, the magnetic tunnel junction may have a low resistance value. By utilizing this difference in resistance value, data can be written and read. With the development of the electronics industry, magnetic memory devices with improved electrical characteristics and high reliability are helpful. Summary of the Invention

[0005] The inventive concept provides a magnetic memory device having improved electrical characteristics.

[0006] According to aspects of the present inventive concept, a magnetic memory device is provided, comprising: a lower electrode on a substrate; a magnetic tunnel junction pattern on the lower electrode; a capping pattern on the magnetic tunnel junction pattern; a stress-inducing layer on the capping pattern and having a lattice constant smaller than that of tantalum; a boron trapping layer in contact with the stress-inducing layer; and an upper electrode on the boron trapping layer.

[0007] According to aspects of the present inventive concept, a magnetic memory device is provided, the magnetic memory device including: a lower electrode located on a substrate; a magnetic tunnel junction pattern located on the lower electrode, the magnetic tunnel junction pattern including a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern; an upper electrode located on the magnetic tunnel junction pattern; a capping pattern located between the magnetic tunnel junction pattern and the upper electrode; a stress-inducing layer located between the capping pattern and the upper electrode; and a boron trapping layer located between the stress-inducing layer and the upper electrode, the boron trapping layer including boron. Each of the stress-inducing layer and the second magnetic pattern may include boron.

[0008] According to various aspects of the present invention, a semiconductor device is provided, which includes: a semiconductor substrate; a selection element located on the semiconductor substrate; a lower interlayer insulating layer located on the semiconductor substrate and the selection element; a conductive plug in the lower interlayer insulating layer and electrically connected to the selection element; an information storage structure located on the conductive plug; and a bit line located on the information storage structure. The information storage structure may include: a lower electrode electrically connected to a conductive plug; a magnetic tunnel junction pattern located on the lower electrode, the magnetic tunnel junction pattern including a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern; a first capping pattern located on an upper surface of the second magnetic pattern, the first capping pattern including a metal different from a metal included in the second magnetic pattern; a second capping pattern located on an upper surface of the second magnetic pattern, the second capping pattern including a metal different from a metal included in the second magnetic pattern and a metal included in the first capping pattern; a stress inducing layer located on an upper surface of the second capping pattern, the stress inducing layer having a lattice constant lower than that of tantalum; a boron capture layer located between the stress inducing layer and a bit line; and an upper electrode located between the boron capture layer and the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view for illustrating a semiconductor device according to some embodiments;

[0011] Figure 2 is a schematic diagram for explaining electrical connections of a semiconductor device according to some embodiments;

[0012] Figure 3 is a schematic diagram for illustrating a magnetic tunnel junction pattern of an information storage structure according to some embodiments;

[0013] Figure 4 is a schematic diagram for illustrating a magnetic tunnel junction pattern of an information storage structure according to another embodiment;

[0014] Figure 5A is a plan view of a semiconductor device according to some embodiments; and

[0015] Figure 5B It is along Figure 5A A cross-sectional view of the semiconductor device taken along line Ⅰ-Ⅰ'. DETAILED DESCRIPTION

[0016] In the present disclosure, like reference numerals denote like components. A semiconductor device according to the present inventive concept is described below.

[0017] Figure 1is a cross-sectional view for illustrating a semiconductor device according to some embodiments.

[0018] Reference Figure 1 The semiconductor device according to some embodiments may be a memory device such as a nonvolatile memory device. The nonvolatile memory device may include a variable resistance memory device. Figure 1 The semiconductor device may be a magnetic memory device 10. The magnetic memory device 10 may include a magnetoresistive random access memory (MRAM). As an example, the magnetic memory device 10 may include an embedded MRAM (eMRAM). As an example, the magnetic memory device 10 may include a perpendicular magnetic tunnel junction-spin transfer torque-MRAM (pMTJ-STT-MRAM).

[0019] The magnetic memory device 10 may include a substrate 100 , a selection element SE, a lower interlayer insulating layer 110 , a conductive plug 210 , an information storage structure DS, an upper interlayer insulating layer 120 , and a bit line BL.

[0020] A substrate 100 may be provided. The substrate 100 may include a memory cell region, and a plurality of memory cells may be provided in the memory cell region. Each of the memory cells may be connected to the memory cell region as described below. Figure 2 The memory cells MC described are substantially the same. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may include silicon, germanium, and / or silicon germanium. A first direction D1 may be parallel to the lower surface of the substrate 100. A second direction D2 may be parallel to the lower surface of the substrate 100 and may intersect with the first direction D1. For example, the second direction D2 may be perpendicular to the first direction D1. A third direction D3 may be substantially perpendicular to the lower surface of the substrate 100. The third direction D3 may be a vertical direction.

[0021] The selection element SE may be provided on the substrate 100. The selection element SE may include a transistor. The transistor may include a planar transistor, a fin field effect transistor (FinFET), a recessed channel array transistor (RCAT), a gate all around (GAA) type field effect transistor, a vertical transistor, a nanowire transistor, a multi-bridge channel (MBC) transistor, a three-dimensional transistor, a diode, or a combination thereof. Figure 2 Describe the operation and functionality of the selection element SE.

[0022] The lower interlayer insulating layer 110 is provided on the substrate 100 so as to be on the selection element SE (e.g., to cover the selection element SE). The lower interlayer insulating layer 110 may include an insulating material containing silicon. The insulating material containing silicon may include silicon oxide, silicon nitride, or silicon oxynitride. The lower interlayer insulating layer 110 may be a single layer or multiple layers.

[0023] The conductive plug 210 may be provided in the lower interlayer insulating layer 110 and may be electrically connected to the selection element SE. The electrical connection to the selection element SE may refer to an electrical connection to at least one of the source / drain or gate electrode of the selection element SE. As an example, the conductive plug 210 may be electrically connected to either the source / drain of the selection element SE. In the present disclosure, two components electrically connected to each other may include a direct connection or an indirect connection via another component.

[0024] The information storing structure DS may be disposed on the conductive plug 210 and the lower interlayer insulating layer 110 so as to be electrically connected to the conductive plug 210. Therefore, the information storing structure DS may be electrically connected to the selection element SE through the conductive plug 210.

[0025] The information storage structure DS may include a lower electrode BE, a magnetic tunnel junction (MTJ) pattern MTJ, a first capping pattern 321, a second capping pattern 322, a stress-inducing layer 350, a boron trapping layer 360, and an upper electrode TE. The lower electrode BE may be disposed between the conductive plug 210 and the magnetic tunnel junction pattern MTJ. The lower electrode BE may include a conductive material such as a metal material or a metal nitride. For example, the lower electrode BE may include tantalum (Ta), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or a combination thereof. The lower electrode BE may be a single layer or multiple layers.

[0026] The magnetic tunnel junction pattern MTJ may include a first magnetic pattern 311, a second magnetic pattern 312, and a tunnel barrier pattern 315. The first magnetic pattern 311, the tunnel barrier pattern 315, and the second magnetic pattern 312 may be stacked on the lower electrode BE. For example, the first magnetic pattern 311 may be disposed between the lower electrode BE and the second magnetic pattern 312. Either the first magnetic pattern 311 or the second magnetic pattern 312 may be a pinned layer, while the other may be a free layer. For example, the first magnetic pattern 311 may be a pinned layer, and the second magnetic pattern 312 may be a free layer. In another example, the first magnetic pattern 311 may be a free layer, and the second magnetic pattern 312 may be a pinned layer. Under typical usage conditions, the pinned layer may have a fixed magnetization direction regardless of an external magnetic field. The magnetization direction of the free layer may be freely changed by an external magnetic field.

[0027] The first magnetic pattern 311 may include a ferromagnetic material. The ferromagnetic material may include at least one of cobalt (Co), nickel (Ni), and iron (Fe). The first magnetic pattern 311 may also include boron (B), but the present disclosure is not limited thereto. For example, the first magnetic pattern 311 may include cobalt iron (CoFe), cobalt boride (CoB), cobalt iron boride (CoFeB), cobalt nickel (CoNi), cobalt chromium (CoCr), cobalt platinum (CoPt), iron boride (FeB), cobalt iron aluminum (CeFeAl), or a combination thereof. The first magnetic pattern 311 may have a crystalline structure. The first magnetic pattern 311 may be a single layer or a multilayer.

[0028] The tunnel barrier pattern 315 may be disposed between the first magnetic pattern 311 and the second magnetic pattern 312. The tunnel barrier pattern 315 may include a dielectric material. The tunnel barrier pattern 315 may include, for example, at least one of magnesium oxide, titanium oxide, aluminum oxide, magnesium zinc oxide, and magnesium boron oxide.

[0029] The second magnetic pattern 312 may be disposed on the tunnel barrier pattern 315. The second magnetic pattern 312 may be spaced apart from the first magnetic pattern 311 by the tunnel barrier pattern 315. The second magnetic pattern 312 may include a ferromagnetic material and boron. The ferromagnetic material is the same as described above. For example, the second magnetic pattern 312 may include CoB, CoFeB, FeB, cobalt nickel boride (CoNiB), cobalt chromium boride (CoCrB), cobalt platinum boride (CoPtB), cobalt iron aluminum (CoFeAl), or a combination thereof. The second magnetic pattern 312 may have a crystalline structure. The second magnetic pattern 312 may include boron (B) and may have desired magnetic properties and a crystalline structure. The second magnetic pattern 312 may be a single layer or a multilayer.

[0030] A capping pattern may be provided on the magnetic tunnel junction pattern MTJ to protect the magnetic tunnel junction pattern MTJ. The capping pattern may include a first capping pattern 321 and a second capping pattern 322. For example, the first capping pattern 321 and the second capping pattern 322 may be provided between the magnetic tunnel junction pattern MTJ and the stress-inducing layer 350. The first capping pattern 321 may be provided on the second magnetic pattern 312. As an example, the first capping pattern 321 may contact the upper surface of the second magnetic pattern 312. The first capping pattern 321 may include a first capping metal. The first capping metal may include a metal, a metal nitride, or a metal oxide. For example, the first capping metal may include tantalum (Ta), tantalum oxide (Ta2O5), and / or tantalum nitride (TaN). In another example, the first capping metal may include aluminum nitride (AlN), zirconium nitride (ZrN), and / or niobium nitride (NbN). In some embodiments, the first capping pattern 321 may include a metal different from the metal included in the first magnetic pattern 311 and / or the metal included in the second magnetic pattern 312. The first capping pattern 321 may further include boron (B). In this case, the content (ie, concentration) of boron in the first capping pattern 321 may be less than that of the first capping metal.

[0031] The second capping pattern 322 may be disposed on the first capping pattern 321. As an example, the second capping pattern 322 may contact the upper surface of the first capping pattern 321, but the present disclosure is not limited thereto. The second capping pattern 322 may include a second capping metal. The second capping metal may be different from the first capping metal. In other words, the second capping pattern 322 may include a metal different from the metal included in the first capping pattern 321. The second capping metal may be different from the material included in the first magnetic pattern 311 and the second magnetic pattern 312. For example, the second capping metal may include ruthenium, ruthenium oxide and / or a ruthenium alloy. In another example, the second capping metal may include Ru, Ta, Ti, TiN, TaN, W and / or a combination thereof. The second capping pattern 322 may also include boron (B). In this case, the content (i.e., concentration) of boron in the second capping pattern 322 may be less than the content (i.e., concentration) of the second capping metal.

[0032] The stress-inducing layer 350 may be disposed on the first capping pattern 321 and the second capping pattern 322. The stress-inducing layer 350 may be in contact with the upper surface of the second capping pattern 322, but the present disclosure is not limited thereto. The lattice constant of the stress-inducing layer 350 may be smaller than the lattice constant of tantalum (Ta). For example, the lattice constant of the stress-inducing layer 350 may be 3.3 angstroms. or less. The stress-inducing layer 350 may include a first metal material. The first metal material of the stress-inducing layer 350 may be different from the second capping metal. In other words, the stress-inducing layer 350 may include a metal different from the metal included in the second capping pattern 322. The first metal material may include, for example, molybdenum (Mo), tungsten (W), hafnium (Hf) and / or alloys thereof. The stress-inducing layer 350 may also include boron (B). Boron may be combined with the metal in the stress-inducing layer 350, but the present disclosure is not limited thereto. The stress-inducing layer 350 may include, for example, Mo, molybdenum boride (MoB), cobalt iron molybdenum (CoFeMo), CoFeMoB and / or a combination thereof. The content (i.e., concentration) of boron in the stress-inducing layer 350 may be less than the content (i.e., concentration) of the first metal material in the stress-inducing layer 350. The stress-inducing layer 350 may be formed by a deposition process.

[0033] The stress inducing layer 350 can apply stress such as compressive stress to the magnetic tunnel junction pattern MTJ. For example, the stress inducing layer 350 can apply compressive stress to the second magnetic pattern 312. Therefore, the magnetic tunnel junction pattern MTJ can have an interface perpendicular magnetic anisotropy (PMA) that is further improved by magnetostriction. The stress inducing layer 350 can prevent damage to the magnetic tunnel junction pattern MTJ. Damage to the magnetic tunnel junction pattern MTJ can include degradation at the interface between the tunnel barrier pattern 315 and the second magnetic pattern 312 and degradation at the interface between the second magnetic pattern 312 and the first capping pattern 321. Since the stress inducing layer 350 is provided, the magnetic and electrical characteristics of the magnetic tunnel junction pattern MTJ can be improved. The magnetic memory device 10 can have improved electrical characteristics. Since the stress inducing layer 350 has a lattice constant smaller than the lattice constant of tantalum (Ta), the stress inducing layer 350 can apply sufficient compressive stress to the second magnetic pattern 312. For example, since the lattice constant of the stress inducing layer 350 is smaller than Therefore, the magnetic tunnel junction pattern MTJ may have further improved perpendicular magnetic anisotropy characteristics.

[0034] The thickness T1 of the stress-inducing layer 350 may be in a range of about 0.001 nanometers (nm) to about 40 nm. When the thickness T1 of the stress-inducing layer 350 exceeds 40 nm, degradation of the magnetic tunnel junction pattern MTJ may occur. According to embodiments, when the thickness T1 of the stress-inducing layer 350 satisfies the conditions, sufficient stress may be applied to the magnetic tunnel junction pattern MTJ, and thus, degradation of the magnetic tunnel junction pattern MTJ may be prevented.

[0035] The boron trapping layer 360 may be disposed on the stress-inducing layer 350. The boron trapping layer 360 may be disposed between the stress-inducing layer 350 and the upper electrode TE. The boron trapping layer 360 may be in physical contact with the upper surface of the stress-inducing layer 350. The boron trapping layer 360 may include a second metal material and boron. In some embodiments, the content (i.e., concentration) of boron in the boron trapping layer 360 may be less than the content (i.e., concentration) of the second metal material in the boron trapping layer 360. The second metal material in the boron trapping layer 360 may include Ta, Mo, Hf, Ti, zirconium (Zr), Co, Fe, and / or alloys thereof. The second metal material of the boron trapping layer 360 may be different from the first metal material of the stress-inducing layer 350. When the second metal material is an alloy, the boron trapping layer 360 may include, for example, CoFe and / or CoFeB. The boron trapping layer 360 may be formed by a deposition process.

[0036] During the semiconductor device manufacturing process, boron in the magnetic tunnel junction pattern MTJ can migrate toward the stress-inducing layer 350. For example, boron in the second magnetic pattern 312 can migrate toward the stress-inducing layer 350 through the first capping pattern 321 and the second capping pattern 322. Therefore, the second magnetic pattern 312, the first capping pattern 321, and the second capping pattern 322 can all include boron (B). When the stress-inducing layer 350 includes boron exceeding a specific concentration / content, the magnetic tunnel junction pattern MTJ may have high resistance characteristics or may degrade. According to embodiments, the boron trapping layer 360 may have a boron affinity greater than that of the stress-inducing layer 350. Since the boron trapping layer 360 is disposed on the upper surface of the stress-inducing layer 350, boron in the stress-inducing layer 350 can migrate toward the boron trapping layer 360. Therefore, in addition to the second metal material, the boron trapping layer 360 may also include boron. The stress-inducing layer 350 may include boron at a specific concentration / content. In other embodiments, the stress-inducing layer 350 may not include boron (B). According to embodiments, the magnetic tunnel junction pattern MTJ can have further improved magnetic and electrical characteristics due to the provision of the boron trapping layer 360. For example, the magnetic tunnel junction pattern MTJ can have relatively low resistance due to the boron trapping layer 360. Due to the provision of the boron trapping layer 360, the perpendicular magnetic anisotropy characteristic of the magnetic tunnel junction pattern MTJ can meet a desired range.

[0037] The formation of the boron capture layer 360 may include forming an initial boron capture layer (not shown) through a deposition process and patterning the initial boron capture layer through an etching process. The thickness T2 of the boron capture layer 360 may be in the range of approximately 0.001 nm to approximately 40 nm. Since the boron capture layer 360 has a thickness T2 of 40 nm or less, the difficulty of the patterning process for forming the boron capture layer 360 can be reduced. In addition, after the etching process for forming the boron capture layer 360, the formation of excessive etching residues can be prevented. Since the thickness T2 of the boron capture layer 360 satisfies the above conditions, the magnetic memory device 10 can exhibit improved electrical characteristics.

[0038] The upper electrode TE may be disposed on the boron capture layer 360. The upper electrode TE may include a conductive material such as a metal material or a metal nitride. For example, the upper electrode TE may include Ta, Ru, Ti, TiN, TaN, W, or a combination thereof. The upper electrode TE may be a single layer or a multilayer. The upper electrode TE may be formed by a deposition process.

[0039] The upper interlayer insulating layer 120 may be disposed on the lower interlayer insulating layer 110 to be on the sidewalls of the information storage structure DS (e.g., to cover the sidewalls of the information storage structure DS). The upper interlayer insulating layer 120 may include a silicon-containing insulating material. The upper interlayer insulating layer 120 may be a single layer or multiple layers.

[0040] The bit line BL may be disposed on the upper interlayer insulating layer 120 and the information storage structure DS. From a two-dimensional perspective, the bit line BL may extend parallel to the first direction D1. The bit line BL may include a conductive material, such as a metal. The bit line BL may be electrically connected to the information storage structure DS. As an example, the bit line BL may contact the upper surface of the upper electrode TE and may be electrically connected to the upper electrode TE. The upper surface of the information storage structure DS may include the upper surface of the upper electrode TE. In another example, a bit line contact plug (not shown) may be disposed between the upper electrode TE and the bit line BL, and the bit line BL may be electrically connected to the upper electrode TE through the bit line contact plug.

[0041] Figure 2 is a schematic diagram for explaining electrical connections of a semiconductor device according to some embodiments.

[0042] Reference Figure 2 , the semiconductor device according to some embodiments may be a magnetic memory device 10. The magnetic memory device 10 may include a memory cell MC. In addition to the information storage structure DS, the selection element SE, and the bit line BL, the memory cell MC may further include a word line WL and a source line SL. Figure 1As described, the information storage structure DS may include a lower electrode BE, a magnetic tunnel junction pattern MTJ, a first capping pattern 321 , a second capping pattern 322 , a stress inducing layer 350 , a boron trapping layer 360 , and an upper electrode TE.

[0043] The selection element SE may include a switching element. The selection element SE may include a field effect transistor. The information storage structure DS may be connected to the first source / drain of the selection element SE. For example, the magnetic tunnel junction pattern MTJ may be electrically connected to the first source / drain of the selection element SE through the lower electrode BE. The source line SL may be connected to the second source / drain of the selection element SE. Therefore, the magnetic tunnel junction pattern MTJ may be connected to the source line SL through the lower electrode BE and the selection element SE. The word line WL may be connected to the gate of the selection element SE. The magnetic tunnel junction pattern MTJ may be electrically connected to the bit line BL through the upper electrode TE. Unlike what is shown, in other embodiments, the magnetic tunnel junction pattern MTJ may be connected to the bit line BL through the lower electrode BE and the selection element SE, and to the source line SL through the upper electrode TE.

[0044] According to some embodiments, the magnetic tunnel junction pattern MTJ can be selectively connected to the source line SL by turning on / off the selection element SE by controlling the voltage of the word line WL. During a write operation of the magnetic memory device 10, the selection element SE can be turned on by applying a voltage to the word line WL, and a write current can be applied between the bit line BL and the source line SL. In this state, the magnetization direction of the second magnetic pattern 312 can be determined according to the direction of the write current.

[0045] For a read operation of the magnetic memory device 10, the selection element SE can be turned on by applying a voltage to the word line WL, and data stored in the magnetic tunnel junction pattern MTJ can be identified by applying a read current between the bit line BL and the source line SL. In this state, since the read current is very small compared to the write current, the magnetization direction of the second magnetic pattern 312 is not changed by the read current.

[0046] Figure 3 is a schematic diagram for explaining a magnetic tunnel junction pattern MTJ of an information storage structure DS according to some embodiments.

[0047] Reference Figure 3 The information storage structure DS may include a lower electrode BE, a magnetic tunnel junction pattern MTJ, a first capping pattern 321, a second capping pattern 322, a stress inducing layer 350, a boron trapping layer 360, and an upper electrode TE. The magnetic tunnel junction pattern MTJ may include a first magnetic pattern 311, a tunnel barrier pattern 315, and a second magnetic pattern 312.

[0048] The first magnetic pattern 311 may be a pinned layer. The first magnetic pattern 311 may have a first magnetization direction M311 fixed in one direction. The second magnetic pattern 312 may have a second magnetization direction M312 that can be changed to be parallel or antiparallel to the fixed first magnetization direction M311. In this state, the first magnetization direction M311 of the first magnetic pattern 311 and the second magnetization direction M312 of the second magnetic pattern 312 may be substantially perpendicular to the surface of the tunnel barrier pattern 315 that contacts the second magnetic pattern 312. For example, the first magnetization direction M311 of the first magnetic pattern 311 and the second magnetization direction M312 of the second magnetic pattern 312 may be parallel or antiparallel to the third direction D3.

[0049] The first magnetic pattern 311 may be thicker than the second magnetic pattern 312 (eg, in the third direction D3), and the coercive force of the first magnetic pattern 311 may be greater than the coercive force of the second magnetic pattern 312. The tunnel barrier pattern 315 may be aligned with the reference Figure 1 The examples described are essentially the same.

[0050] As shown, the first magnetic pattern 311, the tunnel barrier pattern 315, and the second magnetic pattern 312 may be sequentially stacked above the lower electrode BE, and the upper electrode TE may be disposed on the second magnetic pattern 312. In other embodiments, the second magnetic pattern 312, the tunnel barrier pattern 315, and the first magnetic pattern 311 may be sequentially stacked above the lower electrode BE, and the upper electrode TE may be disposed on the first magnetic pattern 311.

[0051] Figure 4 is a schematic diagram for explaining a magnetic tunnel junction pattern MTJ of an information storage structure DS according to another embodiment.

[0052] Reference Figure 4 The information storage structure DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, a first capping pattern 321, a second capping pattern 322, a stress-inducing layer 350, a boron trapping layer 360, and an top electrode TE. In addition to the first magnetic pattern 311 and the second magnetic pattern 312, the magnetic tunnel junction pattern MTJ may further include a third magnetic pattern 313. The magnetic tunnel junction pattern MTJ may include a tunnel barrier pattern. The tunnel barrier pattern may include a first tunnel barrier pattern 315A and a second tunnel barrier pattern 315B.

[0053] The first magnetic pattern 311 and the second magnetic pattern 312 may be aligned with the reference Figures 1 to 3The described examples are substantially the same. The third magnetic pattern 313 may be disposed between the first magnetic pattern 311 and the second magnetic pattern 312. The third magnetic pattern 313 may include a ferromagnetic material. The third magnetic pattern 313 may also include boron (B), but the present disclosure is not limited thereto. For example, the third magnetic pattern 313 may include CoFe, CoB, CoFeB, CoNi, CoCr, CoPt, FeB, CeFeAl, or a combination thereof. The third magnetic pattern 313 may have a crystalline structure. The third magnetic pattern 313 may be a single layer or a multilayer. The first magnetization direction M311 of the first magnetic pattern 311, the second magnetization direction M312 of the second magnetic pattern 312, and the third magnetization direction M313 of the third magnetic pattern 313 may be parallel or antiparallel to the third direction D3. The first magnetic pattern 311 and the second magnetic pattern 312 may each serve as a pinned layer. The first magnetization direction M311 and the second magnetization direction M312 may be pinned in a direction parallel or antiparallel to the third direction D3. The third magnetic pattern 313 may be a free layer. The third magnetization direction M313 may be changed to be parallel or antiparallel to the first magnetization direction M311 .

[0054] When the first magnetization direction M311 of the first magnetic pattern 311 is fixed in a direction opposite to the third magnetization direction M313 of the third magnetic pattern 313, the first magnetization direction M311 of the first magnetic pattern 311 may be substantially offset by the third magnetization direction M313 of the third magnetic pattern 313. Therefore, the magnetic tunnel junction pattern MTJ according to an embodiment may perform a read operation by using a relatively small current.

[0055] The first tunnel barrier pattern 315A may be disposed between the first magnetic pattern 311 and the third magnetic pattern 313. The second tunnel barrier pattern 315B may be disposed between the third magnetic pattern 313 and the second magnetic pattern 312. The first tunnel barrier pattern 315A and the second tunnel barrier pattern 315B may each include a reference Figure 1 The material described in the example of the tunnel barrier pattern 315 described above. The second tunnel barrier pattern 315B may include a material that is the same as or different from that of the first tunnel barrier pattern 315A. Since the magnetic tunnel junction pattern MTJ according to the embodiment provides a relatively high resistance in a read operation due to the second tunnel barrier pattern 315B, a clear resistance value can be obtained.

[0056] The number of magnetic patterns 311, 312, and 313 and the number of tunnel barrier patterns 315A and 315B included in the magnetic tunnel junction pattern MTJ may be variously changed. For example, although not shown, the magnetic tunnel junction pattern MTJ may further include a fourth magnetic pattern and a third tunnel barrier pattern.

[0057] Figure 5A is a plan view of a semiconductor device according to some embodiments. Figure 5B It is along Figure 5A A cross-sectional view of the semiconductor device taken along line Ⅰ-Ⅰ'.

[0058] Reference Figure 5A and Figure 5B The semiconductor device according to some embodiments may be a magnetic memory device 10. The magnetic memory device may include a substrate 100, a selection element SE, a lower interlayer insulating layer 110, a conductive plug 210, an information storage structure DS, an upper interlayer insulating layer 120, and a bit line BL.

[0059] The substrate 100 may be Figure 1 The substrates described are substantially the same. For example, the substrate 100 may be a semiconductor substrate. The substrate 100 may include an active pattern AP. The active pattern AP may protrude from the upper surface of the substrate 100. From a two-dimensional perspective, the active pattern AP may extend parallel to the first direction D1. The active pattern AP may be formed of a semiconductor material. As an example, the active pattern AP may correspond to a portion of the substrate 100 (e.g., the upper portion of the substrate 100). In other words, the active pattern AP may be connected to the substrate 100 without a boundary surface. In another example, the active pattern AP may include an epitaxial layer grown from the substrate 100. The active pattern AP may also include a dopant.

[0060] The selection element SE may be provided on the substrate 100. The selection element SE may be a fin field effect transistor (FinFET), and the type of the selection element SE is not limited to that shown and may be variously changed. The selection element SE may include a first source / drain pattern SD1, a second source / drain pattern SD2, and a gate pattern 250.

[0061] The lower interlayer insulating layer 110 may be disposed on the substrate 100. The lower interlayer insulating layer 110 may include a first lower interlayer insulating layer 111 and a second lower interlayer insulating layer 112. The first lower interlayer insulating layer 111 may be disposed on the substrate 100 and may have an opening 119. The opening 119 may penetrate the first lower interlayer insulating layer 111 (i.e., extend into the first lower interlayer insulating layer 111) to expose the active pattern AP. The first lower interlayer insulating layer 111 and the second lower interlayer insulating layer 112 may each include a silicon-based insulating material. The first lower interlayer insulating layer 111 may be a single layer or multiple layers.

[0062] The gate pattern 250 may extend across the substrate 100 and the active pattern AP, crossing the active pattern AP. For example, from a two-dimensional perspective, the gate pattern 250 may extend in the second direction D2. Although not shown, the gate pattern 250 may be disposed on the upper surface and sidewalls of the active pattern AP. The gate pattern 250 may be disposed within the opening 119 of the first lower interlayer insulating layer 111. The gate pattern 250 may be formed by a replacement gate process. The gate pattern 250 may include a gate electrode of the selection element SE, and may also include a reference electrode. Figure 2 The gate pattern 250 may include, for example, at least one of a doped semiconductor, a conductive metal nitride, a metal silicide, and a metal.

[0063] The selection element SE may further include a gate capping pattern 255. The gate capping pattern 255 may be disposed on top of the gate pattern 250 to be on (e.g., cover) the upper surface of the gate pattern 250. The gate capping pattern 255 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or a combination thereof.

[0064] The gate insulating pattern 251 may be disposed within the opening 119 of the first lower interlayer insulating layer 111 and may be disposed between the gate pattern 250 and the active pattern AP and between the gate pattern 250 and the first lower interlayer insulating layer 111. The gate insulating pattern 251 may be on the lower surface and sidewalls of the gate pattern 250 (e.g., may cover the lower surface and sidewalls of the gate pattern 250). The gate insulating pattern 251 may have a U-shaped cross-section. The gate insulating pattern 251 may include a silicon-containing insulating material and a high-k dielectric material.

[0065] The selection element SE may further include a spacer pattern 253. The spacer pattern 253 may be provided on both (i.e., opposite) sidewalls of the gate pattern 250 so as to be on (e.g., cover) the gate insulating pattern 251. The opening 119 of the first lower interlayer insulating layer 111 may expose the inner wall of the spacer pattern 253. The spacer pattern 253 may include a silicon oxide film, a silicon nitride film, and / or a silicon carbonitride film.

[0066] The first source / drain pattern SD1 may be disposed on the active pattern AP on one side of the gate pattern 250. The second source / drain pattern SD2 may be disposed on the active pattern AP on the other side of the gate pattern 250. The other side of the gate pattern 250 may face the one side thereof (e.g., along the first direction D1). The active pattern AP may have a recessed portion. The first source / drain pattern SD1 and the second source / drain pattern SD2 may be disposed within the recessed portion. A portion of the active pattern AP between the first source / drain pattern SD1 and the second source / drain pattern SD2 may serve as a channel region of the selection element SE. The first source / drain pattern SD1 may be aligned with the reference electrode. Figure 2 The second source / drain pattern SD2 may correspond to the first source / drain of the selection element SE described above. Figure 2 The second source / drain of the select element SE described above corresponds to the first source / drain pattern SD1. The lower surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be located at a lower level than the upper surface of the active pattern AP. In other words, the lower surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be lower than the top surface of the active pattern AP in the third direction D3 (e.g., when measured relative to the lower surface of the substrate 100). The upper surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be located at a higher level than the upper surface of the active pattern AP. In other words, the upper surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surface of the active pattern AP in the third direction D3 (e.g., when measured relative to the lower surface of the substrate 100). In the present disclosure, the level of a particular component may refer to a vertical level measured in a vertical direction (e.g., in the third direction D3). The level difference between two components may be measured in a direction parallel to the third direction D3. The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns. An epitaxial pattern may refer to a pattern formed by an epitaxial growth process. The first source / drain pattern SD1 and the second source / drain pattern SD2 may each include a semiconductor material such as silicon, germanium, silicon germanium (SiGe), and / or silicon carbide (SiC).

[0067] The magnetic memory device 10 may further include a lower plug 220 and a conductive pattern 225. The lower plug 220 may be disposed in the first lower interlayer insulating layer 111 to be electrically connected to the second source / drain pattern SD2. The lower plug 220 may include a metal, a metal nitride, a metal silicide, and / or a combination thereof. The conductive pattern 225 may be disposed on the lower plug 220 to contact the lower plug 220. The conductive pattern 225 may include, for example, a metal.

[0068] The second lower interlayer insulating layer 112 may be disposed on the first lower interlayer insulating layer 111. The second lower interlayer insulating layer 112 may be on (eg, may cover) the conductive pattern 225. The second lower interlayer insulating layer 112 may be a single layer or multiple layers.

[0069] The conductive plug 210 may be disposed in the lower interlayer insulating layer 110. For example, the conductive plug 210 may penetrate the first lower interlayer insulating layer 111 and the second lower interlayer insulating layer 112. The conductive plug 210 may be disposed on the first source / drain pattern SD1 to be electrically connected to the first source / drain pattern SD1. The conductive plug 210 may be spaced apart from the lower plug 220 to be electrically separated therefrom (i.e., electrically isolated). The conductive plug 210 may include a metal, a metal nitride, a metal silicide, and / or a combination thereof.

[0070] The information storage structure DS may be disposed on the conductive plug 210 to be electrically connected to the first source / drain pattern SD1 through the conductive plug 210. The information storage structure DS may also extend over a portion of the upper surface of the second lower interlayer insulating layer 112. Figures 1 to 4 As described, the information storage structure DS may include a lower electrode BE, a magnetic tunnel junction pattern MTJ, a first capping pattern 321 , a second capping pattern 322 , a stress inducing layer 350 , a boron trapping layer 360 , and an upper electrode TE.

[0071] The information storage structure DS may be any one of a plurality of information storage structures DS. The information storage structure DS may be arranged two-dimensionally in the first direction D1 and the second direction D2, such as Figure 5A shown.

[0072] The upper interlayer insulating layer 120 may be disposed on the upper surface of the lower interlayer insulating layer 110. The upper interlayer insulating layer 120 may be on the sidewalls of the information storage structure DS (e.g., may cover the sidewalls of the information storage structure DS). The upper interlayer insulating layer 120 may be multi-layered, but the present disclosure is not limited thereto.

[0073] The bit line BL may be provided on the information storage structure DS to be electrically connected to the information storage structure DS. The bit line BL may extend above the upper surface of the upper interlayer insulating layer 120. Figure 5A As shown, from a two-dimensional perspective, the bit line BL may extend parallel to the first direction D1. The bit line BL may be any one of a plurality of bit lines BL. The bit lines BL may be spaced apart from each other in the second direction D2.

[0074] Hereinafter, with reference to comparative examples and experimental examples, the fabrication and characteristic evaluation results of the information storage structure DS according to some embodiments are described.

[0075] -Manufacturing of information storage structures-

[0076] [Comparative Example 1]

[0077] A lower electrode BE may be formed on the substrate 100. A magnetic tunnel junction pattern MTJ may be formed by sequentially depositing a CoFeB layer, a magnesium oxide (MgO) layer, and a CoFeB layer on the lower electrode BE. A first capping pattern 321 may be formed by depositing a Ta layer on the magnetic tunnel junction pattern MTJ, and a second capping pattern 322 may be formed by depositing a Ru layer on the first capping pattern 321. A third capping pattern (not shown) may be formed by depositing a Ta layer on the second capping pattern 322. An upper electrode TE may be formed by depositing a Ru layer on the third capping pattern.

[0078] [Comparative Example 2]

[0079] The information storage element is manufactured by the same method as Comparative Example 1. However, the stress inducing layer 350 may be formed by depositing a Mo layer on the second capping pattern 322 instead of the third capping pattern. The upper electrode TE may be formed on the Mo layer.

[0080] [Experimental example]

[0081] The information storage element is manufactured by the same method as in Comparative Example 1. However, the stress inducing layer 350 may be formed by depositing a Mo layer on the second capping pattern 322 instead of the third capping pattern. The boron trapping layer 360 may be formed by depositing a Ta layer on the Mo layer. The upper electrode TE may be formed on the Ta layer.

[0082] -Evaluation of information storage structure-

[0083] Table 1 shows the characteristic evaluation results of Comparative Example 1, Comparative Example 2, and Experimental Example. In this state, the spread of the anisotropic magnetic field was obtained by calculating the spread of the anisotropic magnetic field between a plurality of information storage elements manufactured from a single wafer.

[0084] [Table 1]

[0085] Comparative Example 1 Comparative Example 2 Experimental Example Anisotropy magnetic field (Oe) 6531 9499 7418 Diffusion of anisotropic magnetic field (Oe) 1175 1816 1033 <![CDATA[Resistance region (Ω / μm 2 )]]> 13.84 19.95 15.04

[0086] Referring to Table 1, Comparative Example 1 does not include the stress-inducing layer 350. Comparative Example 2 and the experimental example each include the stress-inducing layer 350 and exhibit an anisotropic magnetic field characteristic greater than that of Comparative Example 1. The interface perpendicular magnetic anisotropy characteristic can be evaluated by the anisotropic magnetic field. According to some embodiments, the information storage structure DS may include the stress-inducing layer 350 and may exhibit improved interface perpendicular magnetic anisotropy characteristics.

[0087] Comparative Example 2 does not include the boron trapping layer 360 and exhibits a relatively large diffusion of the anisotropic magnetic field. The experimental example includes the boron trapping layer 360 and exhibits a relatively small diffusion of the anisotropic magnetic field. The information storage structure DS of the experimental example includes the boron trapping layer 360 and exhibits uniform perpendicular magnetic anisotropy characteristics.

[0088] Although Comparative Example 2 has a high resistance region, Comparative Example 1 and the experimental example have relatively low resistance regions. The resistance regions of Comparative Example 1 and the experimental example meet the film resistivity requirements. The information storage structure DS of the experimental example includes the boron trapping layer 360, and therefore, the resistance increase effect caused by the stress-inducing layer 350 can be limited. The information storage structure DS of the experimental example can exhibit good electrical characteristics.

[0089] According to the present invention, an information storage structure can include a stress-inducing layer, have improved interface perpendicular magnetic anisotropy characteristics, and prevent degradation of a magnetic tunnel junction pattern. The information storage structure can include a boron trapping layer and exhibit uniform perpendicular magnetic anisotropy and low resistance characteristics. Consequently, the magnetic and electrical properties of the magnetic tunnel junction pattern can be improved. A magnetic memory device can exhibit improved magnetic and electrical properties.

[0090] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the appended claims.

[0091] As used herein, the terms "includes," "comprising," "containing," "having," "with," "having" and any other variations thereof specify the presence of stated features, steps, operations, elements, components, and / or groups, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0092] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. Instead, these terms are merely used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the scope of this disclosure.

Claims

1. A magnetic memory device comprising: a lower electrode located on the substrate; a magnetic tunnel junction pattern located on the lower electrode, the magnetic tunnel junction pattern comprising a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern; an upper electrode, located on the magnetic tunnel junction pattern; a capping pattern located between the magnetic tunnel junction pattern and the upper electrode; a stress-inducing layer located between the capping pattern and the upper electrode; as well as a boron trapping layer located between the stress-inducing layer and the upper electrode, the boron trapping layer comprising boron, Wherein, each of the stress inducing layer and the second magnetic pattern includes boron.

2. The magnetic memory device according to claim 1, wherein The capping pattern includes boron.

3. The magnetic memory device according to claim 1, wherein The capping pattern includes: a first cover pattern; and a second capping pattern located between the first capping pattern and the stress inducing layer, the second capping pattern including a metal different from the metal included in the first capping pattern and the metal included in the stress inducing layer.

4. The magnetic memory device according to claim 3, wherein Each of the first capping pattern and the second capping pattern includes boron.

5. The magnetic memory device according to claim 1, wherein The stress-inducing layer includes a first metal, wherein the boron capture layer comprises a second metal different from the first metal, wherein the boron content in the stress-inducing layer is less than the first metal content in the stress-inducing layer, and The content of boron in the boron capture layer is less than the content of the second metal in the boron capture layer.

6. The magnetic memory device according to claim 1, wherein The boron trapping layer contacts the stress inducing layer.

7. A magnetic memory device comprising: a lower electrode located on the substrate; a magnetic tunnel junction pattern located on the lower electrode; a capping pattern located on the magnetic tunnel junction pattern; a stress-inducing layer on the capping pattern and having a lattice constant smaller than that of tantalum; a boron trapping layer in contact with the stress inducing layer; as well as An upper electrode is located on the boron capture layer.

8. The magnetic memory device according to claim 7, wherein The lattice constant of the stress-inducing layer is or smaller.

9. The magnetic memory device according to claim 7, wherein The capping pattern includes a first capping pattern, and Wherein, the first capping pattern includes tantalum, tantalum oxide, tantalum nitride, aluminum nitride, zirconium nitride and / or niobium nitride.

10. The magnetic memory device according to claim 9, wherein The capping pattern further includes a second capping pattern located between the first capping pattern and the stress inducing layer, and The second capping pattern includes a metal different from the metal included in the first capping pattern and the metal included in the stress inducing layer.

11. The magnetic memory device according to claim 10, wherein The second capping pattern includes ruthenium, ruthenium oxide and / or a ruthenium alloy.

12. The magnetic memory device according to claim 7, wherein The stress-inducing layer comprises molybdenum, tungsten, hafnium and / or alloys thereof, wherein the boron capture layer comprises tantalum, molybdenum, hafnium, titanium, zirconium, cobalt iron, cobalt iron boride and / or alloys thereof, and The boron trapping layer includes a metal different from a metal included in the stress inducing layer.

13. The magnetic memory device according to claim 7, wherein The boron trapping layer is located between the stress inducing layer and the upper electrode.

14. The magnetic memory device according to claim 7, wherein The magnetic tunnel junction pattern includes a stacked first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern. wherein the second magnetic pattern is located between the tunnel barrier pattern and the capping pattern, wherein the second magnetic pattern comprises boron, and Wherein, the boron capture layer comprises boron.

15. The magnetic memory device according to claim 14, wherein The stress inducing layer includes boron.

16. The magnetic memory device according to claim 7, wherein The thickness of the stress-inducing layer is in the range of 0.001 nm to 40 nm, and Wherein, the thickness of the boron capture layer is in the range of 0.001 nm to 40 nm.

17. A semiconductor device comprising: semiconductor substrates; A selection element located on the semiconductor substrate; a lower interlayer insulating layer located on the semiconductor substrate and the selection element; a conductive plug in the lower interlayer insulating layer and electrically connected to the selection element; an information storage structure located on the conductive plug; as well as A bit line located on the information storage structure, Wherein, the information storage structure includes: a lower electrode electrically connected to the conductive plug; a magnetic tunnel junction pattern located on the lower electrode, the magnetic tunnel junction pattern comprising a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern; a first capping pattern located on an upper surface of the second magnetic pattern, the first capping pattern including a metal different from a metal included in the second magnetic pattern; a second capping pattern on an upper surface of the second magnetic pattern, the second capping pattern including a metal different from the metal included in the second magnetic pattern and the metal included in the first capping pattern; a stress-inducing layer on an upper surface of the second capping pattern, the stress-inducing layer having a lattice constant lower than that of tantalum; a boron trapping layer between the stress-inducing layer and the bit line; and An upper electrode is located between the boron trapping layer and the bit line.

18. The semiconductor device according to claim 17, wherein The semiconductor substrate includes an active pattern protruding from an upper surface of the semiconductor substrate, Wherein, the selection element includes: a gate pattern extending on the semiconductor substrate to intersect the active pattern; and source / drain patterns, the source / drain patterns being on opposite sides of the gate pattern, respectively, and Wherein, relative to the lower surface of the semiconductor substrate, the upper surface of the source / drain pattern is higher than the top surface of the active pattern in a vertical direction.

19. The semiconductor device according to claim 17, wherein the second magnetic pattern comprises ferromagnetic material and boron, Wherein, the stress-inducing layer includes a first metal and boron, wherein the boron capture layer comprises a second metal and boron, and The second metal is different from the first metal.

20. The semiconductor device according to claim 19, wherein The first capping pattern includes tantalum, tantalum oxide, tantalum nitride, aluminum nitride, zirconium nitride and / or niobium nitride, wherein the second capping pattern comprises ruthenium, tantalum, titanium, titanium nitride, tantalum nitride, tungsten and / or a combination thereof, wherein the first metal comprises molybdenum, tungsten, hafnium and / or their alloys, and The second metal includes tantalum, molybdenum, hafnium, titanium, zirconium, cobalt, iron and / or alloys thereof.

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