System and method for micro-architecture aware task scheduling

Abstract

This disclosure provides systems, methods, and devices for task assignment in a processor. In a first aspect, a method for assigning a task for execution by a processor includes calculating a first pause parameter for the task associated with a first central processing unit (CPU) of the processor, where the task is assigned to the first CPU of the processor; calculating a second pause parameter of the task associated with a second CPU of the processor; and assigning the task to the second CPU based on the first pause parameter and the second pause parameter. Other aspects and features are also claimed and described.

Description

Technical Field

[0001] Aspects of the present disclosure relate generally to processors, and more particularly, to methods and systems suitable for scheduling processing tasks across multiple CPUs of a processor. Background Art

[0002] The processor may be included in a variety of devices (such as wireless communication devices, personal computing devices, intelligent vehicles, camera devices and other devices) and may be configured to perform a variety of computing tasks. For example, the processor may be configured to perform image processing tasks, computing tasks, gaming tasks, graphics processing tasks and other tasks. Some processors may include multiple central processing units (CPUs). Some processors may include multiple CPU clusters, also referred to as cores, wherein each cluster includes one or more CPUs. Different clusters and different CPUs within the same cluster may be allocated different resources, such as different cache sizes. Summary of the Invention

[0003] The following summarizes some aspects of the present disclosure to provide a basic understanding of the technology discussed. This summary is not an exhaustive overview of all anticipated features of the present disclosure and is neither intended to identify key or important elements of all aspects of the present disclosure nor to delineate the scope of any or all aspects of the present disclosure. The sole purpose of this summary is to provide some concepts of one or more aspects of the present disclosure in a summarized form as a prelude to the more detailed description that will be presented later.

[0004] A task can be reassigned from a first CPU of a processor to a second CPU of the processor based on the number of stalls that occurred during a time period when the task was executed by the first CPU of the processor. Different CPUs of the processor can, for example, be assigned different resources and / or can operate at different performance levels in the front-end or back-end. Thus, for example, a task requiring more front-end resources can be executed with fewer stalls on a CPU that has been allocated more resources, thereby achieving better front-end performance than one or more other CPUs of the processor. The efficiency of the processor in executing a task can be enhanced by: monitoring the number of stalls when the task is executed by the first CPU of the processor; calculating the number of stalls if the task is executed by one or more other CPUs of the processor, or other stall parameters related to a predicted stall rate if the task is executed by one or more other CPUs; and assigning the task to a CPU that has a predicted number of stalls or other stall parameters of another CPU that is lower than the measured number of stalls or other stall parameters of the first CPU when the task is executed by the first CPU. As a specific example, this efficiency enhancement can enhance the device's execution of a gaming application, thereby providing increased frame rate and responsiveness, reduced power consumption, and other advantages.

[0005] In one aspect of the present disclosure, a method for assigning a task for execution by a processor includes: calculating a first stall parameter for the task associated with a first CPU of the processor, wherein the task is assigned to the first CPU of the processor; calculating a second stall parameter for the task associated with a second CPU of the processor; and assigning the task to the second CPU based on the first stall parameter and the second stall parameter.

[0006] In an additional aspect of the present disclosure, an apparatus includes a memory storing processor-readable code and at least one processor coupled to the memory. The at least one processor is configured to execute the processor-readable code to cause the at least one processor to perform operations including: calculating a first stall parameter for a task associated with a first CPU of the processor, wherein the task is assigned to the first CPU of the processor; calculating a second stall parameter for the task associated with a second CPU of the processor; and assigning the task to the second CPU based on the first stall parameter and the second stall parameter.

[0007] In an additional aspect of the present disclosure, an apparatus includes: means for calculating a first stall parameter for a task associated with a first central processing unit (CPU) of a processor, wherein the task is assigned to the first CPU of the processor; means for calculating a second stall parameter for a task associated with a second CPU of the processor; and means for assigning the task to the second CPU based on the first stall parameter and the second stall parameter.

[0008] In an additional aspect of the present disclosure, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform operations including: calculating a first stall parameter for a task associated with a first central processing unit (CPU) of the processor, wherein the task is assigned to the first CPU of the processor; calculating a second stall parameter for the task associated with a second CPU of the processor; and assigning the task to the second CPU based on the first stall parameter and the second stall parameter.

[0009] The features and technical advantages of the examples according to the present disclosure have been outlined quite broadly above so that the following detailed description may be better understood. Additional features and advantages will be described below. The concepts and specific examples disclosed may be readily used as a basis for modifying or designing other structures for achieving the same purposes of the present disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein (both their organization and method of operation) and the associated advantages will be better understood from the following description when considered in conjunction with the accompanying drawings. Each of the figures in the drawings is provided for the purpose of illustration and description and not as a definition of limitations to the claims.

[0010] Although various aspects and specific implementations are described in this application by way of illustration of some examples, it will be understood by those skilled in the art that additional specific implementations and use cases may be generated in many different arrangements and scenarios. The innovations described herein can be implemented across many different platform types, devices, systems, shapes, sizes, and packaging arrangements. For example, specific implementations or uses may be implemented via integrated chip implementations or other non-module component-based devices (e.g., end-user devices, vehicles, communication devices, computing devices, industrial equipment, retail devices or purchasing devices, medical devices, AI-enabled devices, etc.). Although some examples may or may not specifically relate to use cases or applications, the innovations described may have a wide variety of applicability.

[0011] Implementations may range from chip-level or modular components to non-modular, non-chip-level implementations, and further to aggregated, distributed, or original equipment manufacturer (OEM) devices or systems that incorporate one or more of the described aspects. In some practical environments, a device incorporating the various aspects and features described may also necessarily include additional components and features for implementing and practicing the claimed and described aspects. It is contemplated that the innovations described herein may be implemented in a wide variety of implementations of different sizes, shapes, and configurations, including both large and small devices, chip-level components, multi-component systems (e.g., radio frequency (RF) chains, communication interfaces, processors), distributed arrangements, end-user devices, and the like.

[0012] In the following description, a large number of specific details (such as examples of specific components, circuits and processes) are set forth to provide a thorough understanding of the present disclosure. As used herein, the term "coupled" means directly connected or connected through one or more intermediate components or circuits. In addition, in the following description and for the purpose of explanation, specific terms are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that these specific details may not be needed to practice the teachings disclosed herein. In other cases, in order to avoid blurring the teachings of the present disclosure, known circuits and devices are shown in block diagram form.

[0013] Some portions of the following detailed description are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. In this disclosure, a procedure, logic block, process, etc. is conceived as a self-consistent sequence of steps or instructions leading to a desired result. These steps are those requiring physical manipulations of physical quantities. Typically, though not necessarily, these physical quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system.

[0014] In the accompanying drawings, a single block may be described as performing one or more functions. The one or more functions performed by the block may be performed in a single component or across multiple components, and / or may be performed using hardware, software, or a combination of hardware and software. In order to clearly illustrate this interchangeability of hardware and software, various exemplary components, blocks, modules, circuits, and steps are generally described below in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as resulting in departure from the scope of this disclosure. Moreover, the example device may include components other than those shown, including well-known components such as processors, memories, etc.

[0015] Unless expressly stated otherwise from the following discussion, it should be understood that throughout this application, discussions using terms such as "access," "receive," "transmit," "use," "select," "determine," "normalize," "multiply," "average," "monitor," "compare," "apply," "update," "measure," "derive," "set," "generate," etc., refer to the actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and transform them into other data similarly represented as physical quantities within the computer system's registers, memories, or other such information storage, transmission, or display devices.

[0016] The terms "device" and "apparatus" are not limited to one or a specific number of physical objects (such as a smartphone, a camera controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that can implement at least some portions of the present disclosure. Although the following description and examples use the term "device" to describe various aspects of the present disclosure, the term "device" is not limited to a specific configuration, type, or number of objects. As used herein, an apparatus can include a device or a portion of a device for performing the described operations.

[0017] As used herein, including in the claims, the term "or" used in a list of two or more items means that any one of the listed items can be employed alone, or any combination of two or more of the listed items can be employed. For example, if a composition is described as containing components A, B, or C, the composition can contain A alone; B alone; C alone; A and B combined; A and C combined; B and C combined; or A, B, and C combined.

[0018] Additionally, as used herein, including in the claims, “or” as used in a list of items beginning with “at least one of” indicates a separate list, so that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) or any combination of any of these.

[0019] In addition, as used herein, the term "substantially" is defined as being largely, but not necessarily entirely, what is specified (and includes what is specified; for example, substantially 90 degrees includes 90 degrees, and substantially parallel includes parallel), as understood by one of ordinary skill in the art. In any disclosed embodiment, the term "substantially" may be replaced with "within [percentage] of what is specified," where a percentage includes 0.1%, 1%, 5%, or 10%.

[0020] In addition, as used herein, unless otherwise specified, relative terms may be understood as a certain amount relative to a reference. For example, terms such as "higher" or "lower" or "more" or "less" may be understood as a threshold amount higher, lower, more or less than a reference value. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] A further understanding of the nature and advantages of the present disclosure may be achieved by reference to the following drawings. In the drawings, similar components or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference numeral with a dash and a second reference numeral to distinguish between similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0022] Figure 1 is a block diagram of an example CPU according to one or more aspects of the present disclosure.

[0023] Figure 2 is a block diagram illustrating task assignment functionality of a processor according to one or more aspects of the present disclosure.

[0024] Figure 3 is a block diagram of the organization of a CPU cluster of a processor according to one or more aspects of the present disclosure.

[0025] Figure 4 is a flow chart illustrating an example method for task assignment in a processor based on power consumption according to one or more aspects of the present disclosure.

[0026] Figure 5 is an example power profile illustrating a CPU according to one or more aspects of the present disclosure.

[0027] Figure 6is an example table of pipeline capacities for multiple pipeline components of multiple CPUs according to one or more aspects of the present disclosure.

[0028] Figure 7 is an example graph of the number of stalls for processors performing different tasks according to one or more aspects of the present disclosure.

[0029] Figure 8 is a flow chart illustrating an example method for microarchitecture-aware task scheduling according to one or more aspects of the present disclosure.

[0030] Figure 9 is a flow chart illustrating an example method for microarchitecture-aware task scheduling according to one or more aspects of the present disclosure.

[0031] The same reference numbers and names in different drawings represent the same elements. DETAILED DESCRIPTION

[0032] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to limit the scope of the present disclosure. Instead, the detailed description includes specific details for providing a thorough understanding of the subject matter of the present invention. It will be apparent to those skilled in the art that these specific details are not required in every case, and in some cases, well-known structures and components are shown in block diagram form for clarity of presentation.

[0033] The present disclosure provides systems, devices, methods and computer-readable media that support micro-architecture-aware task scheduling in a processor. Tasks can be reassigned from a first CPU of a processor to a second CPU of a processor based on the number of pauses that occur during a time period when a task is performed by a first CPU of the processor. The multiple pauses that may occur when a task is performed by a processor can be related to the micro-architecture of the processor. Different CPUs of the processor can, for example, be assigned different resources and / or can operate at different performance levels in the front end or back end. Thus, for example, a task requiring more front-end resources can be performed with fewer pauses by a CPU that is allocated more resources to obtain better front-end performance than one or more other CPUs of the processor.

[0034] Specific implementations of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages or benefits. In some aspects, the present disclosure provides techniques for task assignment that may be particularly advantageous in gaming applications. For example, the efficiency with which a processor performs a task can be enhanced by: monitoring the number of stalls when the task is performed by a first CPU of the processor; calculating the number of stalls if the task were performed by one or more other CPUs of the processor; and assigning the task to a CPU having a predicted number of stalls that is lower than the measured number of stalls when the task is performed by the first CPU. Specifically, reassigning tasks to CPUs that are predicted to encounter fewer stalls can reduce the number of stalls encountered. This reduction can enhance computing efficiency and reduce power consumption. As a specific example, such efficiency enhancements can enhance the device's execution of a gaming application, thereby providing increased frame rate and responsiveness, reduced power consumption, and other advantages.

[0035] Figure 1An example CPU 100 is shown in FIG. The CPU 100 may be an example ARMv8 CPU and may be integrated into a system-on-chip (SOC) form factor. The front end 102 of the CPU 100 may include an L1 instruction cache, a macro OP (MOP) cache, a branch predictor unit, an instruction fetch module, an instruction translation lookaside buffer (TLB), a decode queue, a 5-way decoder, and other components. The memory subsystem 104 may interact with the front end 102 or the back end 106 of the CPU and may include an L2 cache, an L1 data cache, and other components. In some embodiments, the memory subsystem 104 may be considered part of the front end 102 or the back end 106 of the CPU. For example, in some embodiments, the L2 cache of the memory subsystem 104 may interact with the front end 102 of the CPU 100 and the back end 106 of the CPU, while the L1 data cache may interact with the back end 106 of the CPU 100. The back end 106 of the CPU may be referred to as an execution engine and may include a rename / allocation / commit / reorder buffer, a dispatch module, one or more queues, one or more branch units, one or more arithmetic logic units (ALUs), one or more address generation units (AGUs), one or more data storage units, a load store unit (LSU), and one or more other components. In some cases, multiple CPUs 100 may be included in a processor. Some of the CPUs included in the processor may have different MOP cache sizes, different L1 cache sizes, different L2 cache sizes, and different L3 cache sizes. In addition, different CPUs may have different sizes of fetch modules, decode queues, ld_st numbers, and tlb_entry numbers. Specifically, different CPUs 100 of the processor may be designed to have different caches, buffer sizes, and other parameters to achieve different performance and power consumption characteristics. This design can be extensively tuned for benchmark testing.

[0036] In some embodiments, some CPUs may be tuned for enhanced front-end 102 performance, while other CPUs may be tuned for enhanced back-end 106 performance. Different tasks (such as those to be performed when executing different applications) may require different front-end and back-end resources when being transferred to the CPU 100. When there are not enough resources available to complete a task in a cycle, a stall may occur, thereby delaying the completion of the task. For example, in some scenarios, the CPU front-end 102 may fetch multiple instructions per cycle and push such instructions to the back-end 106 for execution. This CPU pipeline allows for instruction-level parallelism. When there are not enough resources available to fetch and / or execute the fetched tasks in a given cycle, a stall may occur because the CPU may be required to wait for resource availability to fetch or execute the task. Such stalls may reduce the benefits of parallelism, thereby resulting in reduced execution efficiency. Some tasks may be more likely to encounter stalls at the front-end 102 of the CPU 100, while other tasks may be more likely to encounter stalls at the back-end 106 of the CPU 100. A greater number of pauses can result in longer CPU activity times, requiring more time to complete tasks and resulting in increased power consumption. Such pauses can negatively impact the performance of the device, such as reducing the frame rate of gaming applications and / or shortening battery life.

[0037] One or more top-down performance monitoring unit (PMU) counters may be used to monitor the CPU (such as Figure 1The number of stalls of the CPU 100 (of the CPU 100) is counted. For example, the stall may occur in the front end 102 of the CPU 100. Stalls associated with or occurring in the front end 102 of the CPU 100 may include memory-bound stalls (such as stalls associated with or occurring in the L1 instruction cache, the L2 cache, the front end memory, or the front end TLB), and CPU-bound stalls (such as stalls associated with the stream function of the front end 102 or the rename function of the front end 102). Similarly, stalls associated with or occurring in the back end 106 of the CPU 100 may include memory-bound stalls (such as stalls associated with or occurring in the L1 data cache, the L2 cache, the back end memory, or the back end TLB), and CPU-bound stalls (such as stalls associated with the back end busy function, the back end ilock function, or the back end rename function). Such stalls may be monitored by one or more PMUs to determine the total number of front-end stalls and the total number of back-end stalls that occurred during a period of time when tasks were executed by CPU 100. Other stalls may include bad speculation stalls and retired-bound stalls. In some embodiments, stalls may be monitored and counted for various pipeline components of CPU 100, as discussed herein.

[0038] Multiple CPUs may be included in a processor, and such CPUs may be organized into CPU clusters, also referred to as cores. Figure 2208B, which may have a greater capacity and overall power performance than each of the CPUs in the gold cluster 208B. Each of the CPUs in the gold cluster 208B may have a greater capacity and overall power performance than each of the CPUs in the silver cluster 208A. Tasks may be assigned to clusters 208A-208C based on the task load of each cluster. Specifically, if the task load of a cluster (such as silver cluster 208A) exceeds a predetermined threshold, tasks may be assigned to a higher-ranked cluster, such as gold cluster 208B. For example, if a task is to be assigned to each respective CPU cluster, scheduler 204 may assign the task to CPU clusters 208A-208C based on the task load that would be placed on each respective CPU cluster. In some embodiments, the task may be assigned to a cluster in the plurality of clusters based on the current task load on each cluster in the plurality of clusters, without regard to any changes in the task load that may be caused by adding the task to the run queue of the cluster.

[0039] As an example, if the task load is less than 85% of the capacity of silver CPU cluster 208A, the task may be assigned by scheduler 204 to silver cluster 208A and may be queued in the silver core run queue by task placement module 206. Similarly, if the task load is greater than 85% of the capacity of silver CPU cluster 208A but less than 85% of the capacity of gold CPU cluster 208B, the task may be assigned by scheduler 204 to gold cluster 208B and may be queued in the gold core run queue by task placement module 206. Similarly, if the task load is greater than 85% of the capacity of gold CPU cluster 208B, the task may be assigned by scheduler 204 to master cluster 208C and may be queued in the master core run queue by task placement module 206. Thus, tasks may be assigned to be executed by CPUs in a particular cluster based on task load. In some cases, task assignment may be based on affinity, CPU utilization, and load balancing in addition to predicted task load.

[0040] Different CPU clusters may have different resources (such as different amounts of L1 and L2 memory, different re-order buffer (ROB) sizes, and different MOP sizes) for completing tasks. Furthermore, different CPUs within a particular cluster may have different resources (such as different amounts of L1 and L2 memory, different ROB sizes, and different MOP sizes) for completing tasks. Figure 3 An example processor 300 may include a main CPU cluster 306, a gold CPU cluster 304, and a silver CPU cluster 302. The main CPU cluster 306 may include a first CPU 310 assigned 64 kB of L1 data and instruction cache memory and 1 MB of L2 memory. The gold CPU cluster 304 may include a first CPU 308A, a second CPU 308B, a third CPU 308C, and a fourth CPU 308D, each of which may be assigned 32 kB of L1 data and instruction cache memory and 512 kB of L2 memory. The silver CPU cluster 302 may include a first CPU 312A having 32 kB of L1 data and instruction cache memory and 128 kB of L2 memory. The silver CPU cluster 302 may also include a second CPU 312B and a third CPU 312C having 32 kB of L1 data and instruction cache memory and 256 kB of L2 memory. Thus, the second CPU 312B and the third CPU 312C can be allocated a larger amount of L2 memory than the first CPU 312A in the silver CPU cluster 302. The processor 300 may also include a bus interface 314 and an L3 memory having a capacity of 8MB for use by the CPUs 310, 308A-308D, 312A-312C. The processor 300 may also include one or more globally distributed head switches (GDHS).

[0041] As a specific example, different CPUs of processor 300 can operate at different stall rates, regardless of whether the CPUs are assigned the same amount of memory. For example, first CPU 308A and second CPU 308B in gold cluster 304 can be of the first type, while third CPU 308C and fourth CPU 308D in gold cluster 304 can be of the second type. For example, first CPU 308A and second CPU 308B can lack a MOP cache, while third CPU 308C and fourth CPU 308D can have stronger load data / store data (LD / SD) performance and / or better memory access. First CPU 308A and second CPU 308B can have a higher front-end stall rate and a higher misspeculation stall rate, while third CPU 308A and fourth CPU 308B can have a higher back-end stall rate. Therefore, if the scheduler assigns tasks to CPUs in the cluster based solely on power consumption and does not consider other performance characteristics of the different CPUs in the cluster (such as the number of stalls), more stalls may occur when executing tasks than if the scheduler assigns tasks based on the predicted number of stalls for each of the CPUs in the cluster.

[0042] Processors in the same cluster (such as Figure 3 The CPUs of the processor 300) can be considered to have the same characteristics even when the characteristics (such as the amount of memory assigned to the CPU) are different within the cluster. Figure 4 An example method 400 for assigning tasks to be performed by CPUs of a processor is shown in a flowchart of FIG. The method 400 may include, at block 402, predicting a task load and assigning tasks to a first CPU cluster based on the task load. For example, a device such as a processor may predict the task load that a particular task (such as a task of a gaming application) may place on the CPUs in different clusters if assigned to the clusters, as described in relation to FIG. Figure 2 In making such predictions, the device may treat CPUs within a cluster as having the same characteristics (such as the same amount of assigned resources) even when such CPUs are assigned different resources, such as with respect to Figure 3 Based on the predicted task load, tasks can be assigned to the first CPU cluster. For example, tasks can be assigned to the silver CPU cluster, the gold CPU cluster, or the master CPU cluster, as described in relation to Figure 2 described.

[0043] At block 404, the device may predict the power consumption of each CPU in the first CPU cluster if the task were to be executed by each corresponding CPU. For example, the device may multiply the power optimization curve by the quotient of the utilization of each CPU in the cluster and the capacity of each CPU in the cluster. Figure 5Graph 500 shows example power optimization curves 502, 504 for two different CPUs. The power optimization curves 502, 504 may represent the different power consumption of the two different CPUs based on the operating frequencies of the two different CPUs. Specifically, the x-axis of graph 500 may represent the CPU operating frequency, and the y-axis may represent the power of the CPU. An increase in the task load on the CPU will result in an increase in the CPU operating frequency. An increase in the CPU operating frequency will result in an increase in the power consumption of the CPU. As the operating frequency increases to the right, the power usage of each CPU also increases. Therefore, the power consumption value of the power optimization curve (such as curve 502) of the CPU at a specific utilization rate can be multiplied by the quotient of the CPU utilization and the CPU capacity to determine the predicted power consumption of the CPU. However, Figure 5 The power optimization curves 502 and 504 may represent the power consumed when a synthetic workload is placed on the CPU. In the implementation of real-world tasks rather than synthetic workloads such as benchmarks, different usage, stalls, and wasted cycles may result in different power consumption than the power optimization curves generated using synthetic workloads.

[0044] At block 406, the device may determine the CPU with the lowest predicted power consumption.For example, the values ​​predicted for each CPU at block 404 may be compared to determine the CPU with the lowest predicted power consumption.

[0045] At block 408, the device (such as a task scheduler of the device) may assign the task to the CPU with the lowest predicted power consumption. Thus, the task may be assigned to the CPU with the lowest predicted power consumption in the cluster to which the task was assigned at block 402, and the CPU may execute the task.

[0046] However, as regards Figure 4 The described assignment of tasks based on task load and power consumption can lead to inefficiencies. For example, even when a task is assigned to the primary CPU cluster, the task experiences a large number of stall cycles (e.g., 80% stall cycles) and a high cache miss rate. Figure 4 In the method 400, such tasks can still be assigned to and remain assigned to the primary CPU cluster. However, such tasks may cause the CPUs in the primary CPU cluster to operate at a higher frequency and consume a higher amount of power. Furthermore, assigning such tasks to the primary CPU cluster may monopolize primary CPU cluster resources that could be used to execute other tasks with higher efficiency. Therefore, efficiency, power consumption, and performance can be enhanced by assigning such tasks to the gold or silver CPU clusters based on the large number of pauses that would occur if the tasks were assigned to the primary CPU cluster.

[0047] In order to enhance the efficiency when executing tasks, tasks can be assigned to CPUs based on the pause parameters of tasks associated with the CPUs in the cluster to which the tasks are assigned and / or CPUs in other clusters. For example, the number of pauses when a task is executed by a first CPU can be monitored and used to calculate a normalized pause percentage value for the first CPU. Specifically, the number of pauses can be multiplied by a normalized pipeline capacity value as described herein to generate a normalized pause percentage value. The normalized pause percentage value can be compared with the predicted normalized pause percentage values ​​of other CPUs in the same cluster and / or different clusters as the CPU, and the CPU with the lowest predicted pause percentage value can be selected for the execution of the task. A pipeline capacity value can be determined for the CPU of a processor to determine the normalized pause percentage value. Figure 6, an example table 600 is shown that illustrates calculated normalized pipeline capacities for multiple pipeline components for multiple CPUs of a processor. A first column 602 may include a list of CPU sections (such as the front end and the back end). A second column 604 may include a list of pipelines for each section. A third column 606 may include a list of components for each pipeline. A fourth column 608 may include pipeline capacity values ​​determined for each pipeline component of a first CPU. A fifth column 610 may include pipeline capacity values ​​determined for each pipeline component of a second CPU. A sixth column 612 may include pipeline capacity values ​​determined for each pipeline component of a third CPU. In some embodiments, additional pipeline capacity values ​​may be determined for additional CPUs and / or additional pipeline components. The pipeline capacity values ​​may be normalized based on the CPU determined to have the best performance. For example, the CPU determined to have the best performance (such as the CPU in the master cluster) may be given a pipeline capacity value of 1, while all other CPUs may be given normalized pipeline capacity values ​​related to the pipeline capacity of the best CPU. Thus, for example, if the CPU in column 608 is the CPU with the best performance, the pipeline capacity values ​​for the other CPUs (such as the CPUs in columns 610 and 612) may represent the pipeline capacity of the other CPUs as a percentage of the pipeline capacity of the CPU with the best performance. To determine the pipeline capacity values ​​for the CPUs of a processor, the processor may execute a comprehensive power case (such as a benchmark program) and may use one or more PMU counters to measure the number of stalls that occur across all CPUs. In some embodiments, the measured number of stalls that occur across all CPUs can be determined at a further granularity, such as by determining the number of stalls that occur in association with each pipeline component of each CPU while running the benchmark program. The CPU with the best performance (e.g., the lowest number of stalls) can be determined based on the measured number of stalls, and the measured number of stalls for each CPU or each corresponding pipeline of each CPU can be compared with the number of stalls for the CPU or corresponding pipeline component with the best performance to determine a percentage pipeline capacity value for each CPU and / or each pipeline component of each CPU. Thus, a normalized pipeline capacity value for each pipeline component of each CPU of the processor can be determined, and a CPU pipeline capacity value of 1 can be assigned to the CPU with the best performance.

[0048] Figure 7An example graph 700 illustrates the number of instructions per cycle (IPC) for a processor while executing various tasks. Higher front_bound and backend_bound values ​​may indicate a greater number of stalls and / or wasted CPU cycles. When running a first benchmark such as speck2k6 702, front-end stalls, misspeculation stalls, and back-end-bound stalls may be relatively low, while retirement-bound tasks may be high, resulting in a high IPC of approximately 2.4. When running a second benchmark such as gb5 704, front-end stalls, misspeculation stalls, and back-end-bound stalls may be relatively low, while retirement-bound tasks may be high, resulting in a high IPC of approximately 2.1. When running a third benchmark such as dhrystone 706, front-end stalls and misspeculation stalls may be zero, and back-end-bound stalls may be relatively low, while retirement-bound tasks may be high, resulting in a high IPC of approximately 4.5. However, such benchmark values ​​may differ significantly from the performance of a processor when executing tasks from real-world applications. For example, when running image processing application 708, front-end-bound and back-end-bound stalls may be relatively high, while retirement-bound tasks may be low, resulting in a low IPC of approximately 0.3. Similarly, when running gaming application 710, front-end-bound and back-end-bound stalls may be relatively high, while retirement-bound tasks may be low, resulting in a low IPC of approximately 0.7. Therefore, benchmarks used to tune the performance of a processor's CPU (such as benchmarks 702-706) may not be accurate in predicting the performance of the CPU under real workloads (such as workloads 708-710).

[0049] Figure 8 One approach to microarchitecture-aware task scheduling described in this article is shown in FIG. Figure 8is a flow chart illustrating an example method 800 for microarchitecture-aware task scheduling. Method 800 includes, at block 802, calculating a first stall parameter for a task associated with a first CPU of a processor, wherein the task is assigned to the first CPU of the processor. The task may, for example, be a task associated with an application executed by the processor, such as a task of a gaming application. The first stall parameter may, for example, be a normalized stall percentage value, a number of stalls that occurred during a time period when the task was executed by the first CPU, or another stall parameter. In some embodiments, calculating the first stall parameter may include calculating a stall parameter for each of a plurality of pipeline components of the first CPU, as described herein. In some embodiments, calculating the first stall parameter may include measuring a first number of stalls within a first time period when the task was executed by the first CPU, and multiplying the first number of stalls by a first normalized pipeline capacity of the first CPU, as described herein. In some embodiments, calculating the first stall parameter may include: measuring the number of stalls of multiple pipeline components of the first CPU, multiplying the number of stalls by the corresponding pipeline capacity of the pipeline components, and summing the products of the number of stalls and the corresponding pipeline capacity. This sum may be referred to as the stall percentage value of the first CPU. As a specific example, measuring the number of stalls of multiple pipeline components of the first CPU may include: measuring the number of stalls associated with the front end of the first CPU and measuring the number of stalls associated with the back end of the first CPU. In some embodiments, calculating the first stall parameter may also include: multiplying the power curve parameter of the first CPU by the product of the first number of stalls of the first CPU and the first pipeline capacity, or multiplying the power curve parameter of the first CPU by the sum of the products of the number of stalls of the pipeline components of the first CPU and the pipeline capacity of the pipeline components. Therefore, a first stall parameter of a first CPU executing a task may be determined based on: a number of stalls occurring during a threshold time period when the task is executed by the first CPU, or a plurality of stalls associated with a plurality of pipeline components of the first CPU occurring during a threshold time period when the task is executed by the first CPU, a normalized pipeline capacity of the first CPU, or a plurality of normalized pipeline capacities of a plurality of pipeline components of the first CPU, and / or a power curve parameter of the first CPU.

[0050] At block 804, a second pause parameter for the task associated with the second CPU of the processor may be calculated. The second pause parameter may be, for example, a normalized pause percentage value, a number of pauses predicted to occur during a time period if the task is executed by the second CPU, or another pause parameter. In some embodiments, calculating the second pause parameter may include calculating a pause parameter for each of a plurality of pipeline components of the second CPU, as described herein. In some embodiments, calculating the second pause parameter may include multiplying the first number of pauses determined at block 802 by a pipeline capacity value (such as a normalized pipeline capacity value) of the second CPU, as described herein. In some embodiments, calculating the second pause parameter may include multiplying the first number of pauses of the plurality of pipeline components of the first CPU by the corresponding pipeline capacity (such as a normalized pipeline capacity value) of the pipeline components of the second CPU, and summing the products of the first number of pauses and the corresponding pipeline capacity. This sum may be referred to as the pause percentage value for the first CPU. In some embodiments, calculating the second stall parameter may further include: multiplying the power curve parameter of the second CPU by the product of the first stall number of the second CPU and the first pipeline capacity, or multiplying the power curve parameter of the second CPU by the sum of the products of the stall number of the pipeline component of the first CPU and the corresponding normalized pipeline capacity of the pipeline component of the second CPU.

[0051] In some embodiments, the first CPU and the second CPU may be located in the same cluster, while in other embodiments, the first CPU and the second CPU may be located in different clusters. For example, when the first CPU and the second CPU are located in different clusters and / or the default CPU selection mode is selected, the first power curve parameter and the second power curve parameter may be used to determine the first pause parameter and the second pause parameter because the power performance of CPUs in different clusters may vary more than that of CPUs in the same cluster. In some embodiments, when the performance CPU selection mode is selected, the first power curve parameter and the second power curve parameter may not be used to determine the first pause parameter and the second pause parameter, even when the second CPU is located in a different cluster than the first CPU. In some embodiments, the pause parameters of additional CPUs may be determined. For example, the pause parameters of all CPUs of the processor may be determined, or the pause parameters of all qualified CPUs of the processor may be determined. Therefore, in some embodiments, the processor may determine which CPUs are qualified CPUs before determining the pause parameters of the corresponding qualified CPUs.

[0052] At box 806, the task can be assigned to the second CPU based on the first pause parameter and the second pause parameter. For example, the processor may determine that the pause parameter of the second CPU (such as, the pause percentage of the second CPU) has a lower value than the pause parameter of the first CPU (such as, the pause percentage of the first CPU), and may determine to transfer the task to the second CPU based on this determination. In some embodiments, the pause parameters (such as, the pause percentage) of multiple CPUs can be compared, and the CPU with the lowest pause parameter value can be determined. The task can be assigned to the CPU with the lowest pause parameter value. In some embodiments, such as when determining the pause parameters based on the power curve parameters of CPUs in different clusters, in addition to the normalized pipeline capacity of the CPU and the measured number of pauses when executing the task on the first CPU, the task can also be assigned to the second CPU based on the power curve parameters of the first CPU, the second CPU, and the other CPUs. For example, if the default mode is selected, a first stall parameter may be determined by multiplying the first number of stalls for the first CPU by the pipeline capacity value of the first CPU and the power curve parameter of the first CPU, and a second stall parameter may be determined by multiplying the first number of stalls by the pipeline capacity value of the second CPU and the power curve parameter of the second CPU. This multiplication may be performed to determine the stall parameters of the additional CPUs, and the CPU with the lowest stall parameter may be selected for assignment of the first task. If the performance mode is selected and / or if all CPUs considered for executing the task are located in the same cluster, the stall parameter may be determined based on multiplying the number of stalls for the first CPU when executing the task or the number of stalls associated with the pipeline component of the first CPU when executing the task by the normalized pipeline capacity of the corresponding CPU or the pipeline component of the corresponding CPU, and the CPU may be selected for assignment of the task without considering the power curve parameter of the CPU. In some embodiments, method 800 may be repeated for multiple tasks of one or more applications executed by the processor. For example, in some embodiments, method 800 may be performed for the top multiple (such as 16 or another number) tasks ranked by resource consumption of the application. Thus, tasks may be assigned to CPUs that are least likely to encounter stalls while executing the tasks based on the number of stalls calculated for the first CPU and the normalized pipeline capacity values ​​for the first CPU and the other CPUs. This assignment may allow tasks that require a large amount of front-end capacity to be assigned to CPUs with a large amount of front-end capacity, while tasks that require a large amount of back-end capacity to be assigned to CPUs with a large amount of back-end capacity. In particular, this assignment may allow for enhanced performance and reduced power consumption in games and other applications.

[0053] Figure 9 One approach to microarchitecture-aware task scheduling described in this article is shown in FIG. Figure 9is a flow chart illustrating an example method 900 for microarchitecture-aware task scheduling. The method 900 includes, at block 902, measuring pipeline capacity of each of a plurality of CPUs of a processor. In some embodiments, pipeline capacity may be measured for a plurality of pipeline components of each of a plurality of CPUs of the processor. To measure pipeline capacity, the processor may run a synthetic power task routine (such as a benchmark) on one or more applicable CPUs and may measure a number of stalls that occur on each of the CPUs or on each of the pipeline components of each of the CPUs in the CPUs, such as a count of the number of stalls that occur on each of the CPUs or on each of the pipeline components of each of the CPUs in the CPUs. Figure 6 As described. The CPU with the highest pipeline capacity (such as the CPU that encounters the lowest number of stalls when executing the integrated power task routine) may be assigned a normalized pipeline capacity value of 1, while other CPUs may be assigned normalized pipeline capacity values ​​based on the relationship between the number of stalls encountered by the other CPUs and the number of stalls encountered by the CPU with the highest pipeline capacity. For example, the other CPUs may be assigned a value that represents a percentage of the pipeline capacity value of the CPU with the highest pipeline capacity, the percentage being calculated by dividing the number of stalls encountered by each respective CPU during a time period when executing the integrated power task routine by the number of stalls encountered by the CPU with the highest pipeline capacity when executing the integrated power task routine. In some embodiments, a normalized pipeline capacity value may be calculated for each of a plurality of pipeline components of each CPU based on the number of stalls encountered associated with different pipeline components.

[0054] At block 904, a task for an application to be executed by a processor may be determined. Figure 4 The described process or another process assigns tasks of the application executed by the processor to the initial CPU. As a specific example, the processor may determine a number of tasks (such as the first number of tasks set) of an application (such as a gaming application) for monitoring stalls and reassign tasks based on the monitored stalls. In some embodiments, the processor may use a counter to determine the first 16 tasks of the application. Thus, block 904 and blocks 906-912 may be repeated and executed for multiple tasks of the application. In some embodiments, blocks 904-912 may be executed at runtime.

[0055] At block 906, the number of CPU stalls for the task may be monitored over a time period while the task is being executed by the CPU. For example, a PMU counter may be used to determine the number of stalls that occurred while the task was being executed by the CPU. The time period may, for example, begin when the task is scheduled into the CPU and end when the task is scheduled out of the CPU. For example, the PMU counter may be read or summed when the task is scheduled out of the CPU. If the time has not yet reached a threshold (such as a threshold number of seconds to monitor the execution of the task), the monitoring may be repeated on subsequent executions of the task until the stalls of the task have been monitored for a predetermined time period. In some embodiments, such monitoring may be performed for multiple pipeline components while executing the task to determine the number of stalls that occurred in association with each pipeline component during the time period. In some embodiments, the operation of block 906 may be performed as Figure 8 is performed as part of the operations of block 802.

[0056] At block 908, a stall parameter of the CPU may be calculated. For example, the stall parameter of the CPU may be calculated based on the number of stalls that occurred while executing tasks by the CPU and, in some embodiments, the pipeline capacity value of the CPU, such as the value of the CPU's pipeline capacity. Figure 8 802 of . In some embodiments, a stall parameter, such as a stall percentage, may be calculated for each of the plurality of pipeline components of the CPU. In some embodiments, such as when one or more CPUs in a cluster different from the cluster of the CPU performing the task at block 906 are considered for transfer of tasks and / or when a default mode is selected for task assignment, the stall parameter may be determined based on the number of stalls, the pipeline capacity value of the CPU, and the power curve parameter of the CPU. This determination may allow tasks to be assigned based on both power consumption and performance. In some embodiments, such as when only CPUs in the same cluster as the CPU performing the task are considered for transfer of tasks and / or when a performance mode is selected for task assignment, the stall parameter (such as a stall percentage) may be determined based on the number of stalls and the pipeline capacity value of the CPU, without considering the power curve parameter of the CPU.

[0057] At block 910, stall parameters may be calculated for the other CPUs of the processor. For example, stall parameters for the other CPUs of the processor may be calculated based on the number of stalls that occurred while executing tasks by the CPU and based on normalized pipeline capacity values ​​of the other CPUs, such as those for Figure 8Such calculation may include estimating a stall percentage value for each of the other CPUs of the processor by multiplying the number of stalls encountered by the CPU executing the task at block 906 by the normalized pipeline capacity of the other CPUs, such as by multiplying the number of stalls for each pipeline component of the CPU executing the task by the corresponding pipeline capacity value of each corresponding pipeline component of each of the other CPUs, and summing the products for each corresponding CPU to determine a stall parameter for each CPU. In some embodiments, the stall parameter may be calculated for each of the plurality of pipeline components of the CPU. In some embodiments, such as when one or more CPUs in a cluster different from the cluster of the CPU executing the task are considered for task transfer and / or a default mode is selected for task assignment, the stall parameters for the other CPUs may be determined based on the number of stalls encountered by the CPU executing the first task, the pipeline capacity value of the corresponding CPU, and the power curve parameter of the corresponding CPU. In some embodiments, such as when only CPUs in the same cluster as the CPU performing the task are considered for task transfer and / or selection of a performance mode for task assignment, a pause parameter may be determined based on the number of pauses encountered by the CPU performing the task and the corresponding pipeline capacity value of the CPU, without considering the power curve parameter of the CPU. In some embodiments, the pause parameter may be calculated for all other CPUs in the same cluster as the CPU performing the task, and the identification of such CPUs may be obtained from the scheduler. In some embodiments, in addition to or instead of a CPU from the same cluster as the CPU performing the task, the pause parameter may be calculated for CPUs in different clusters, and the identification of such CPUs may be obtained from the scheduler.

[0058] At block 912, a CPU may be selected for execution of the task. For example, the CPU with the lowest stall parameter value may be selected to execute the task, and the task may be transferred to be executed by the selected CPU. Thus, based on a prediction that the number of stalls will be lower if the task is executed by another CPU, and in some embodiments, further based on the predicted power consumption of the candidate CPU for executing the task, the task may be transferred to another CPU of the processor.

[0059] It should be noted that reference Figure 4 and Figures 8 and 9 One or more blocks (or operations) described in one figure may be combined with one or more blocks (or operations) described with reference to another figure. Figure 8 One or more boxes (or operations) of Figure 9 As another example, with one or more boxes (or operations) of Figure 8 One or more boxes associated with Figure 4Groups one or more boxes that are related.

[0060] In one or more aspects, the technology for supporting vehicle operations may include additional aspects, such as any single aspect or any combination of aspects described below or in combination with one or more other processes or devices described elsewhere herein. In a first aspect, a method for assigning a task for execution by a processor may include: calculating a first pause parameter for the task associated with a first CPU of the processor, wherein the task is assigned to the first CPU of the processor; calculating a second pause parameter for the task associated with a second CPU of the processor; and assigning the task to the second CPU based on the first pause parameter and the second pause parameter. In some specific implementations, the device may include at least one processor and a memory coupled to the processor. The processor may be configured to perform the operations described herein with respect to the device. In some other specific implementations, the device may include a non-transitory computer-readable medium having program code recorded thereon, and the program code may be executable by a computer to cause the computer to perform the operations described herein with reference to the device. In some specific implementations, the device may include one or more components configured to perform the operations described herein. In some implementations, a method can include one or more of the operations described herein with reference to the apparatus.

[0061] In a second aspect, in combination with the first aspect, calculating the first stall parameter includes measuring a first stall number in a first time period when the task is executed by the first CPU, and multiplying the first stall number by a first pipeline capacity of the first CPU.

[0062] In a third aspect, in combination with one or more of the first or second aspects, calculating the second stall parameter includes: multiplying the first stall quantity by a second pipeline capacity of the second CPU.

[0063] In a fourth aspect, in combination with one or more of the first to third aspects, calculating the first pause parameter further includes: multiplying a first product of the first number of pauses and the first pipeline capacity by a first power curve parameter of the first CPU, and calculating the second pause parameter further includes: multiplying a second product of the first number of pauses and the second pipeline capacity by a second power curve parameter of the second CPU.

[0064] In a fifth aspect, in combination with one or more of the first to fourth aspects, measuring the first number of pauses in the first time period includes: measuring the second number of pauses associated with the front end of the first CPU, and measuring the third number of pauses associated with the back end of the first CPU.

[0065] In a sixth aspect, in combination with one or more of the first to fifth aspects, the method further comprises: measuring a first pipeline capacity of the first CPU, and measuring a second pipeline capacity of the second CPU, wherein calculating the second pause parameter is based on the first pipeline capacity and the second pipeline capacity.

[0066] In a seventh aspect, in combination with one or more of the first to sixth aspects, the first CPU and the second CPU are located in the same cluster.

[0067] In an eighth aspect, in combination with one or more of the first to seventh aspects, the first CPU and the second CPU are located in different clusters.

[0068] This article is about Figures 1 to 4 The components, functional blocks, and modules described herein include processors, electronic devices, hardware devices, electronic components, logic circuits, memories, software codes, firmware codes, and the like, or any combination thereof. Software should be broadly interpreted to mean instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, processes, and / or functions, and the like, whether referred to as software, firmware, middleware, microcode, hardware description languages, or other terms. In addition, the features discussed herein may be implemented via dedicated processor circuits, via executable instructions, or a combination thereof.

[0069] It will be further understood by those skilled in the art that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the disclosure herein may be implemented as electronic hardware, computer software, or a combination thereof. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art may implement the functionality described in different ways for each specific application, but such specific implementation decisions should not be interpreted as resulting in departure from the scope of this disclosure. It will also be readily appreciated that the order or combination of components, methods, or interactions described herein are merely examples, and that the components, methods, or interactions of various aspects of this disclosure may be combined or performed in ways other than those illustrated and described herein.

[0070] The various illustrative logical components, logic blocks, modules, circuits, and algorithmic processes described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. The interchangeability of hardware and software has been generally described in terms of functionality and exemplified in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0071] The hardware and data processing apparatus for implementing the various illustrative logic components, logic blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed using a general-purpose single-chip or multi-chip processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, or any conventional processor, controller, microcontroller, or state machine. In some implementations, a processor may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. In some implementations, a particular process and method may be performed by circuits specific to a given function.

[0072] In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents, or any combination thereof. Implementations of the subject matter described in this specification may also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on computer storage media for execution by, or for controlling the operation of, data processing apparatus.

[0073] If implemented in software, the function may be stored as one or more instructions or codes on a computer-readable medium or sent via a computer-readable medium. The process of the method or algorithm disclosed herein may be implemented in a processor-executable software module that may reside on a computer-readable medium. Computer-readable media include both computer storage media and communication media, and the communication media include any media that can be implemented to transfer a computer program from one place to another. The storage medium can be any available medium that a computer can access. As an example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to store the required program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection may be appropriately referred to as a computer-readable medium. Disks and optical disks as used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks and blue-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically with lasers. The above combination should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as a code and instruction set, or any combination of code and instruction sets, on a machine-readable medium or computer-readable medium, which may be incorporated into a computer program product.

[0074] Various modifications to the specific implementations described in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other specific implementations without departing from the spirit or scope of this disclosure. Therefore, the claims are not intended to be limited to the specific implementations shown herein but are to be accorded the widest scope consistent with this disclosure, the principles and novel features disclosed herein.

[0075] Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations, either individually or in any suitable subcombination. Furthermore, while features may be described above as functioning in certain combinations and even initially claimed as such, in some cases one or more features of that combination may be deleted from the claimed combination, and the claimed combination may involve subcombinations or variations of subcombinations.

[0076] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the particular order shown or in a sequential order, or to perform all illustrated operations to achieve the desired result. In addition, the accompanying drawings may schematically depict one or more example processes in the form of flow charts. However, other operations not depicted may be incorporated into the schematically illustrated example processes. For example, one or more additional operations may be performed before, after, simultaneously with, or between any of the illustrated operations. In some cases, multitasking and parallel processing are advantageous. In addition, the separation of various system components in the specific implementations described above should not be understood as requiring such separation in all specific implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. In addition, some other specific implementations also fall within the scope of the appended claims. In some cases, the actions recited in the claims can be performed in different orders and still achieve the desired result.

[0077] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Therefore, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for assigning tasks for execution by a processor, the method comprising: calculating a first stall parameter for the task associated with a first central processing unit (CPU) of the processor, wherein the task is assigned to the first CPU of the processor; calculating a second stall parameter for the task associated with a second CPU of the processor; and The task is assigned to the second CPU based on the first stall parameter and the second stall parameter.

2. The method of claim 1 , wherein calculating the first pause parameter comprises: measuring a first number of pauses during a first time period when the task is executed by the first CPU; as well as The first stall number is multiplied by a first pipeline capacity of the first CPU.

3. The method of claim 2 , wherein calculating the second pause parameter comprises: The first stall number is multiplied by a second pipeline capacity of the second CPU.

4. The method according to claim 3, wherein calculating the first pause parameter further comprises: A first product of the first number of stalls and the first pipeline capacity is multiplied by a first power curve parameter of the first CPU, and wherein calculating the second stall parameter further comprises: multiplying a second product of the first number of stalls and the second pipeline capacity by a second power curve parameter of the second CPU.

5. The method of claim 2, wherein measuring the first number of pauses within the first time period comprises: measuring a second number of stalls associated with a front end of the first CPU; as well as A third number of stalls associated with a back end of the first CPU is measured.

6. The method according to claim 1, further comprising: measuring a first pipeline capacity of the first CPU; as well as measuring the second pipeline capacity of the second CPU, The second pause parameter is calculated based on the first pipeline capacity and the second pipeline capacity. The method according to claim 1 , wherein the first CPU and the second CPU are located in the same cluster. The method according to claim 1 , wherein the first CPU and the second CPU are located in different clusters.

9. A device comprising: a memory storing processor-readable code; and at least one processor coupled to the memory, the at least one processor configured to execute the processor-readable code to cause the at least one processor to perform operations comprising: calculating a first stall parameter for a task associated with a first central processing unit (CPU) of the processor, wherein the task is assigned to the first CPU of the processor; calculating a second stall parameter for the task associated with a second CPU of the processor; and The task is assigned to the second CPU based on the first stall parameter and the second stall parameter.

10. The apparatus of claim 9, wherein calculating the first pause parameter comprises: measuring a first number of pauses during a first time period when the task is executed by the first CPU; as well as The first stall number is multiplied by a first pipeline capacity of the first CPU.

11. The apparatus of claim 10, wherein calculating the second pause parameter comprises: The first stall number is multiplied by a second pipeline capacity of the second CPU.

12. The apparatus of claim 11, wherein calculating the first pause parameter further comprises: A first product of the first number of stalls and the first pipeline capacity is multiplied by a first power curve parameter of the first CPU, and wherein calculating the second stall parameter further comprises: multiplying a second product of the first number of stalls and the second pipeline capacity by a second power curve parameter of the second CPU.

13. The apparatus of claim 10, wherein measuring the first number of pauses within the first time period comprises: measuring a second number of stalls associated with a front end of the first CPU; as well as A third number of stalls associated with a back end of the first CPU is measured.

14. The apparatus of claim 9, wherein the at least one processor is further configured to execute the processor-readable code to cause the at least one processor to perform operations comprising: measuring a first pipeline capacity of the first CPU; as well as measuring the second pipeline capacity of the second CPU, The second pause parameter is calculated based on the first pipeline capacity and the second pipeline capacity.

15. The apparatus of claim 9, wherein the first CPU and the second CPU are located in the same cluster.

16. The apparatus of claim 9, wherein the first CPU and the second CPU are located in different clusters.

17. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising: calculating a first stall parameter for a task associated with a first central processing unit (CPU) of the processor, wherein the task is assigned to the first CPU of the processor; calculating a second stall parameter for the task associated with a second CPU of the processor; and The task is assigned to the second CPU based on the first stall parameter and the second stall parameter.

18. The non-transitory computer-readable medium of claim 17, wherein calculating the first pause parameter comprises: measuring a first number of pauses during a first time period when the task is executed by the first CPU; as well as The first stall number is multiplied by a first pipeline capacity of the first CPU.

19. The non-transitory computer-readable medium of claim 18, wherein calculating the second pause parameter comprises: The first stall number is multiplied by a second pipeline capacity of the second CPU.

20. The non-transitory computer-readable medium of claim 19, wherein calculating the first pause parameter further comprises: A first product of the first number of stalls and the first pipeline capacity is multiplied by a first power curve parameter of the first CPU, and wherein calculating the second stall parameter further comprises: multiplying a second product of the first number of stalls and the second pipeline capacity by a second power curve parameter of the second CPU.

21. The non-transitory computer-readable medium of claim 18, wherein measuring the first number of stalls within the first time period comprises: measuring a second number of stalls associated with a front end of the first CPU; as well as A third number of stalls associated with a back end of the first CPU is measured.

22. The non-transitory computer-readable medium of claim 17, further storing instructions that, when executed by a processor, cause the processor to perform operations comprising: measuring a first pipeline capacity of the first CPU; as well as measuring the second pipeline capacity of the second CPU, The second pause parameter is calculated based on the first pipeline capacity and the second pipeline capacity.

23. The non-transitory computer-readable medium of claim 17, wherein the first CPU and the second CPU are located in the same cluster.

24. The non-transitory computer-readable medium of claim 17, wherein the first CPU and the second CPU are located in different clusters.

25. A device comprising: means for calculating a first stall parameter for a task associated with a first central processing unit (CPU) of a processor, wherein the task is assigned to the first CPU of the processor; means for calculating a second stall parameter for the task associated with a second CPU of the processor; and Means for assigning the task to the second CPU based on the first stall parameter and the second stall parameter.

26. The apparatus of claim 25, wherein the means for calculating the first pause parameter comprises: means for measuring a first number of stalls within a first time period when executing the task by the first CPU; and means for multiplying the first number of stalls by a first pipeline capacity of the first CPU.

27. The apparatus of claim 26, wherein the means for calculating the second pause parameter comprises: means for multiplying the first number of stalls by a second pipeline capacity of the second CPU.

28. The apparatus of claim 27, wherein the means for calculating the first stall parameter further comprises means for multiplying a first product of the first number of stalls and the first pipeline capacity by a first power curve parameter of the first CPU, and wherein the means for calculating the second stall parameter further comprises means for multiplying a second product of the first number of stalls and the second pipeline capacity by a second power curve parameter of the second CPU.

29. The apparatus of claim 26, wherein the means for measuring the first number of pauses within the first time period comprises: means for measuring a second number of stalls associated with a front end of said first CPU; and Means for measuring a third number of stalls associated with a back end of the first CPU.

30. The apparatus of claim 25, further comprising: a component for measuring a first pipeline capacity of the first CPU; and a component for measuring a second pipeline capacity of the second CPU, The means for calculating the second stall parameter includes means for calculating the second stall parameter based on the first pipeline capacity and the second pipeline capacity.

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