Current-to-voltage converter including common mode circuit

Abstract

In one example, a system includes a current-to-voltage converter to generate a differential voltage from a differential current including a first current and a second current, the current-to-voltage converter including: a first bit line to provide the first current; a second bit line for providing the second current; a first regulator for applying a first voltage to the first bit line; a second regulator for applying a second voltage to the second bit line; a regulation circuit including a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltage; and a common mode circuit.

Description

[0001] Priority Declaration

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 442,810, filed on February 2, 2023, entitled “Common Mode Circuit Decoupled From Bitlines In Neural Network Array,” and U.S. Patent Application No. 18 / 137,370, filed on April 20, 2023, entitled “Current-To-Voltage Converter Comprising Common Mode Circuit.” Technical Field

[0003] A number of examples of current-to-voltage converters including common-mode circuits are disclosed. The current-to-voltage converters can be used in output blocks of a neural network array, where the common-mode circuits are decoupled from the bit lines of the neural network array. Background Art

[0004] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] Figure 1 An artificial neural network is illustrated, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the input and learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, that is, very high computational parallelism. In principle, this complexity can be achieved using digital supercomputers or clusters of dedicated graphics processing units. However, in addition to being high-cost, these approaches are also mediocre in energy efficiency compared to biological networks, which consume less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0007] Applicants previously disclosed an artificial (simulated) neural network utilizing one or more nonvolatile memory arrays as synapses in U.S. Patent Application Publication 2017 / 0337466A1, which is incorporated herein by reference. The nonvolatile memory array operates as an analog neural memory and includes nonvolatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region spaced apart formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0008] Non-volatile memory cells

[0009] Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such a memory cell 210 is Figure 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls its electrical conductivity), and is formed over a portion of the source region 14. A wordline terminal 22 (which is typically coupled to a wordline) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls its electrical conductivity), and a second portion extending upward and over the floating gate 20. The floating gate 20 and the wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0010] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on wordline terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim (FN) tunneling from floating gate 20 to wordline terminal 22.

[0011] The memory cell 210 is programmed by source side injection (SSI) with hot electrons by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14 (where electrons are placed on the floating gate). Electrons flow from the drain region 16 to the source region 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, they accelerate and become heated. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons are injected through the gate oxide onto the floating gate 20.

[0012] Memory cell 210 is read by placing a positive read voltage across drain region 16 and wordline terminal 22 (which turns on the portion of channel region 18 below the wordline terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also turned on, and current will flow through channel region 18, which is sensed as an erased state or a "1" state. If floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through channel region 18, which is sensed as a programmed state or a "0" state.

[0013] Table 1 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 210 for performing read, erase, and program operations:

[0014] Table 1: Figure 2 Operation of the flash memory unit 210

[0015] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 10.5μA-3μA 9V-10V

[0016] Other split gate memory cell configurations are known as other types of flash memory cells. For example, Figure 3 A quad-gate memory cell 310 is depicted, comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating, meaning they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0017] Table 2 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read, erase, and program operations:

[0018] Table 2: Figure 3 Operation of the flash memory unit 310

[0019] WL / SG BL CG EG SL Read 1.0V-2V 0.6V-2V 0V-2.6V 0V-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8V-12V 0V programming 1V 0.1μA-1μA 8V-11V 4.5V-9V 4.5V-5V

[0020] Figure 4 Depicted is a tri-gate memory cell 410, which is another type of flash memory cell. Figure 3 The memory cell 310 is identical to the memory cell 410 except that the memory cell 410 does not have a separate control gate. Except that no control gate bias is applied, the erase operation (thus erasing by using the erase gate) and the read operation are the same as Figure 3 The programming operation is also completed without a control gate bias, and therefore, a higher voltage is applied on the source line during the programming operation to compensate for the lack of control gate bias.

[0021] Table 3 depicts typical voltage and current ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations:

[0022] Table 3: Figure 4 Operation of the flash memory unit 410

[0023] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0V-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 0.2μA-3μA 4.5V 7V-9V

[0024] Figure 5 Depicted is a stacked gate memory cell 510, which is another type of flash memory cell. Figure 2 18 and drain region 16. Memory cell 210 is similar to that of FIG10 , except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be coupled to a word line) extends over floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection at the region between channel 18 and drain region 16, by electrons flowing from source region 14 toward drain region 16, and read operations are similar to memory cell 210 with a higher control gate voltage.

[0025] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 510 and the substrate 12 for performing read, erase, and program operations:

[0026] Table 4: Figure 5 Operation of the flash memory unit 510

[0027] CG BL SL substrate Read 2V-5V 0.6V-2V 0V 0V Erase -8V to -10V / 0V FLT FLT 8V-10V / 15V-20V programming 8V-12V 3V-5V 0V 0V

[0028] The methods and devices described herein can be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), CT (charge trapping) memory, CN (carbon tube) memory, OTP (two-level or multi-level one-time programmable) and CeRAM (correlated electron RAM), etc.

[0029] In order to utilize a memory array comprising one of the above-described types of nonvolatile memory cells in an artificial neural network, two modifications were made. First, the circuitry was configured so that each memory cell could be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as explained further below. Second, continuous (analog) programming of the memory cells was provided.

[0030] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage device is effectively analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all the memory cells in the memory array, and makes the memory array ideal for storing and fine-tuning the synaptic weights of neural networks.

[0031] Neural Networks Using Nonvolatile Memory Cell Arrays

[0032] Figure 6 This example conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a non-volatile memory array-based neural network.

[0033] For this example, S0 is the input layer, which is a 32x32 pixel RGB image with 5 bits of precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, the values ​​of 9 pixels in a 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of these multiplications, a single output value is determined and provided by the first synapse of CB1 for use in generating a pixel in one of the feature maps for layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of three pixels on the right is added and a column of three pixels on the left is released), whereby the nine pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) across the entire 32x32 pixel image of the input layer S0. This process is then repeated using different sets of weights to generate different feature maps for layer C1 until all feature maps for layer C1 have been calculated.

[0034] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 is composed of a two-dimensional array of 16 layers (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as edge identification. For example, a first map (generated using a first set of weights, shared by all scans used to generate it) can identify circular edges, a second map (generated using a second set of weights different from the first) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0035] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of pooling function P1 is to average the values ​​of adjacent locations (or a max function can be used), for example to reduce dependencies at edge locations, and to reduce the size of the data before entering the next stage. At layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays, each with 15x15 pixels). Synapse CB2 from layer S1 to layer C2 scans the maps in layer S1 using a 4x4 filter, with the filter shifted by 1 pixel. At layer C2, there are 22 12x12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 22 6x6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse on CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, that is, every neuron in layer C3 is connected to every neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, this output can indicate the identification or classification of the content of the original image.

[0036] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0037] Figure 7 A block diagram of an array that can be used for this purpose is shown in FIG. The vector-matrix multiplication (VMM) array 32 includes non-volatile memory cells and serves as a synapse between one layer and the next (such as Figure 6 CB1, CB2, CB3, and CB4 in FIG. 1 ). Specifically, the VMM array 32 includes a nonvolatile memory cell array 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the corresponding inputs of the nonvolatile memory cell array 33. The inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0038] The non-volatile memory cell array 33 serves two purposes. First, it stores weights to be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33, and each output line (source line or bit line) adds them together to produce an output, which will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the non-volatile memory cell array 33 eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient due to its in-situ memory calculations.

[0039] The output of the non-volatile memory cell array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform the summation of positive and negative weights.

[0040] The summed output value of the difference summer 38 is then provided to the activation function block 39, which modifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The modified output value of the activation function block 39 becomes the next layer (e.g., Figure 6 The elements of the feature map of layer C1 in the image processing unit are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from existing neuron layers or from an input layer such as an image database), and the summing operational amplifier 38 and the activation function block 39 constitute a plurality of neurons.

[0041] Figure 7 The inputs to the VMM array 32 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0042] Figure 8 FIG. 1 is a block diagram illustrating the use of multiple layers of VMM arrays 32, labeled here as VMM arrays 32a, 32b, 32c, 32d, and 32e. Figure 8As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be a voltage or a current. The first level of input D / A conversion can be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog levels of the matrix multiplier of the input VMM array 32a. Input conversion can also be accomplished by an analog-to-analog (A / A) converter to convert the external analog input into a mapped analog input to the input VMM array 32a.

[0043] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as input to the next VMM array (hidden level 2) 32c, and so on. The layers of VMM array 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a separate physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. Figure 8 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may include more than two hidden layers and more than two fully connected layers.

[0044] Vector-Matrix Multiplication (VMM) Array

[0045] Figure 9 Depicted is a neuron VMM array 900, which is particularly suitable for Figure 3 The memory cells 310 shown are used as synapses and components for neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of nonvolatile memory cells and a reference array 902 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

[0046] In VMM array 900, control gate lines (such as control gate line 903) extend in the vertical direction (so reference array 902 is orthogonal to control gate line 903 in the row direction), and erase gate lines (such as erase gate line 904) extend in the horizontal direction. Here, the inputs to VMM array 900 are provided on control gate lines (CG0, CG1, CG2, CG3), and the outputs of VMM array 900 appear on source lines (SL0, SL1). In one example, only even-numbered rows are used, and in another example, only odd-numbered rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summation function of all currents from the memory cells connected to that particular source line.

[0047] As described herein for neural networks, the non-volatile memory cells of VMM array 900 (ie, memory cells 310 of VMM array 900 ) may be configured to operate in a sub-threshold region.

[0048] The nonvolatile reference memory cell and the nonvolatile memory cell described herein are biased in weak inversion (subthreshold region):

[0049] Ids=Io*e (Vg-Vth) / nVt =w*Io*e (Vg) / nVt ,

[0050] where w = e (-Vth) / nVt

[0051] Where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is the product of (Wt / L)*u*Cox*(n-1)*Vt 2 is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0052] For an I-to-V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert the input current into an input voltage:

[0053] Vg=n*Vt*log[Ids / wp*Io]

[0054] Wherein, wp is w of the reference memory cell or the peripheral memory cell.

[0055] For a memory array used as a vector matrix multiplier VMM array with current input, the output current is:

[0056] Iout=wa*Io*e (Vg) / nVt ,Right now

[0057] Iout=(wa / wp)*Iin=W*Iin

[0058] W=e (Vthp-Vtha) / nVt

[0059] Here, wa = w for each memory cell in the memory array.

[0060] Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of the transistor is a function of the substrate body bias voltage, and the substrate body bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at this temperature. The threshold voltage Vth can be expressed as:

[0061]

[0062] where Vth0 is the threshold voltage with zero substrate bias, is the surface potential, and γ is the bulk effect parameter.

[0063] The word line or control gate may be used as the input to the memory cell for the input voltage.

[0064] Alternatively, the flash memory cells of the VMM array described herein may be configured to operate in the linear region:

[0065] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*Wt / L

[0066] W=α(Vgs-Vth)

[0067] Meaning that the weight W in the linear region is proportional to (Vgs-Vth)

[0068] The word line or control gate or bit line or source line can serve as the input of the memory cell operating in the linear region. The bit line or source line can serve as the output of the memory cell.

[0069] For an IV linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0070] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region:

[0071] Ids=1 / 2*β*(Vgs-Vth) 2 ;β=u*Cox*Wt / L

[0072] Wα(Vgs-Vth) 2 , which means the weight W and (Vgs-Vth) 2 Proportional

[0073] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region. The bit line or source line can be used as the output of an output neuron.

[0074] Alternatively, the memory cells of the VMM array described herein may be used for all regions or combinations thereof (subthreshold, linear, or saturation regions) of each layer or multiple layers of a neural network.

[0075] US Patent No. 10,748,630 describes Figure 7 Other examples of VMM arrays 32 are described in conjunction with FIG. , which is incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0076] Figure 10 Depicted is a neuron VMM array 1000, which is particularly suitable for Figure 2 Memory cell 210 is shown and serves as a synapse between the input layer and the next layer. VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. Reference arrays 1001 and 1002, arranged in the column direction of the array, are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected via a multiplexer 1014 (only partially depicted), into which the current inputs flow. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0077] The memory array 1003 serves two purposes. First, it stores the weights that the VMM array 1000 will use on its corresponding memory cells. Second, the memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1001 and 1002 convert into input voltages to provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication logic circuits and addition logic circuits and is also highly power-efficient. Here, the voltage inputs are provided on word lines WL0, WL1, WL2, and WL3, and the outputs appear on the corresponding bit lines BL0-BLN during a read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0078] Table 5 depicts the operating voltages and currents for VMM array 1000. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0079] Table 5: Figure 10 Operation of the VMM array 1000 :

[0080] WL WL-Not selected BL BL-Not selected SL SL-Not selected Read 1V-3.5V -0.5V / 0V 0.6V-2V(Ineuron) 0.6V-2V / 0V 0V 0V Erase About 5V-13V 0V 0V 0V 0V 0V programming 1V-2V -0.5V / 0V 0.1uA-3uA Vinh~2.5V 4V-10V 0V-1V / FLT

[0081] Figure 11 Depicted is a neuron VMM array 1100 particularly suitable for use in Figure 2Memory cell 210 is shown and serves as a synapse and component for neurons between the input layer and the next layer. VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. Reference arrays 1101 and 1102 extend in the row direction of VMM array 1100. The VMM array is similar to VMM 1000, except that in VMM array 1100, the word lines extend in the vertical direction. Here, inputs are provided on word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0082] Table 6 depicts the operating voltages and currents for the VMM array 1100. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0083] Table 6: Figure 11 Operation of the VMM array 1100

[0084] WL WL-Not selected BL BL-Not selected SL SL-Not selected Read 1V-3.5V -0.5V / 0V 0.6V-2V 0.6V-2V / 0V About 0.3V-1V (Ineuron) 0V Erase About 5V-13V 0V 0V 0V 0V SL-suppression (about 4-8V) programming 1V-2V -0.5V / 0V 0.1uA-3uA Vinh~2.5V 4V-10V 0V-1V / FLT

[0085] Figure 12 Depicted is a neuron VMM array 1200, which is particularly suitable for Figure 3 Memory cell 310 is shown and serves as a synapse and component of neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected via a multiplexer 1212 (only partially shown), with the current input flowing into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a corresponding multiplexer 1205 and a cascode transistor 1204 to ensure a constant voltage on a bit line (such as BLR0) for each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0086] The memory array 1203 serves two purposes. First, it stores the weights that will be used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert into input voltages to provide to the control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array and then adds all the results (cell currents) to produce the output, which appears at BL0-BLN and will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current placed on each bit line performs a summing function of all the currents from the memory cells connected to that particular bit line.

[0087] The VMM array 1200 implements unidirectional tuning of the nonvolatile memory cells in the memory array 1203. That is, each nonvolatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the cell is erased and the sequence of partial programming operations begins again. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (this is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0088] Table 7 depicts the operating voltages and currents for the VMM array 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0089] Table 7: Figure 12 Operation of the VMM array 1200

[0090]

[0091] Figure 13 Depicted is a neuron VMM array 1300, which is particularly suitable for Figure 3Memory cell 310 is shown and serves as a synapse and component of neurons between the input layer and the next layer. VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bidirectional tuning, whereby each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired charge on the floating gate due to the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of diode-connected reference cells via multiplexer 1314). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from the nonvolatile memory cells connected to that particular bit line.

[0092] Table 8 depicts the operating voltages and currents for the VMM array 1300. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0093] Table 8: Figure 13 Operation of the VMM array 1300

[0094]

[0095] Figure 14 Depicted is a VMM array 1400, which is particularly suitable for Figure 2 The memory cell 210 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In the VMM array 1400, the inputs INPUT0, ..., INPUT N On bit lines BL0, BL N The signals are received on the source lines SL0, SL1, SL2 and SL3, and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on the source lines SL0, SL1, SL2 and SL3, respectively.

[0096] Figure 15 Depicted is a VMM array 1500, which is particularly suitable for Figure 2 The memory cell 210 is shown and serves as a synapse and component of the neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2 and INPUT3 are received on source lines SL0, SL1, SL2 and SL3 respectively, and outputs OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0097] Figure 16 Depicted is a VMM array 1600, which is particularly suitable for Figure 2 The memory unit 210 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M is received and output OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0098] Figure 17 Depicted is a VMM array 1700, which is particularly suitable for Figure 3 The memory unit 310 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M is received and output OUTPUT0, ..., OUTPUT N On the bit lines BL0, BL N Generate on.

[0099] Figure 18 Depicted is a VMM array 1800, which is particularly suitable for Figure 4 The memory unit 410 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT n On the vertical control gate lines CG0, CG N The signals are received on the source lines SL0 and SL1, and outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0100] Figure 19 Depicted is a VMM array 1900, which is particularly suitable for Figure 4 The memory unit 410 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT N are received at the gates of bit line control gates 1901-1, 1901-2, ..., 1901-(N-1), and 1901-N, which are coupled to bit lines BL0, ..., BL N Example outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0101] Figure 20 Depicted is a VMM array 2000, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M is received and output OUTPUT0, ..., OUTPUT N On bit lines BL0, BL N Generate on.

[0102] Figure 21 Depicted is a VMM array 2100, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On the control gate lines CG0, CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical source lines SL0, SL N On the generation, each source line SL i The source line coupled to all memory cells in column i.

[0103] Figure 22 Depicted is a VMM array 2200, which is particularly suitable for Figure 3The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and a component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On the control gate lines CG0, CG M OUTPUT0, OUTPUT1, OUTPUT2, OUTPUT3, OUTPUT4 N On the vertical bit lines BL0, BL N On the generated, where each bit line BL i The bit line coupled to all memory cells in column i.

[0104] The inputs to the VMM array can be analog levels, binary levels, pulses, time-modulated pulses, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, timed pulses, pulses, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0105] Generally speaking, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two hybrid memory cells (the average of the two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W=W+-W-). In the case of two hybrid memory cells, two memory cells are required to implement the weight W as the average of the two cells.

[0106] Figure 23A VMM system 2300 is depicted (the VMM system includes a VMM array 2301 and summing circuits 2301 and 2302). In some examples, the weights W stored in the VMM array are stored as a differential pair of W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). In the VMM system 2300, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. The subtraction operation is performed by a summing circuit (such as summing circuit 2301 and summing circuit 2302), which receives current from the W+ line and the W- line. The output of the W+ line and the output of the W- are combined to effectively give W=W+-W- for each (W+, W-) cell pair for all (W+, W-) line pairs. While described above with respect to W− lines interspersed among W+ lines in an alternating manner, in other examples, the W+ lines and W− lines may be arbitrarily located anywhere in the array.

[0107] Figure 24 Another example is depicted in a VMM system 2410 where positive weights W+ are implemented in a first array 2411 and negative weights W− are implemented in a second array 2412 that is separate from the first array, and the resulting weights are appropriately combined via a summing circuit 2413 .

[0108] Figure 25A VMM system 2500 is depicted, in which weights W stored in a VMM array are stored as a differential pair of W+ (positive weight) and W- (negative weight), where W=(W+)-(W-). VMM system 2500 includes array 2501 and array 2502. Half of the bit lines in each of arrays 2501 and 2502 are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines in each of arrays 2501 and 2502 are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are interspersed between the W+ lines in an alternating manner. Subtraction operations are performed by summing circuits (such as summing circuits 2503, 2504, 2505, and 2506), which receive current from the W+ lines and the W- lines. The outputs of the W+ lines and the W- lines from each array 2501, 2502, respectively, are combined to effectively give W = W+ - W- for each (W+, W-) element pair for all (W+, W-) line pairs. Additionally, the W values ​​from each array 2501 and array 2502 can be further combined by summing circuits 2507 and 2508 so that each W value is the result of subtracting the W value from array 2502 from the W value from array 2501, meaning that the final result from summing circuits 2507 and 2508 is the difference of two differences.

[0109] Each nonvolatile memory cell used in an analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0110] The output block should preferably be able to perform verify and read operations accurately and consistently, since each cell can hold one of N different values. Figure 26 As shown in Figure 1, the input to the output block varies in voltage depending on the current drawn by the memory array. This figure depicts the relationship between the change in bitline voltage and the change in current drawn by the bitline through the memory cells coupled to that bitline. As can be seen, the bitline voltage varies significantly with changes in bitline current. This leads to inaccuracies and also to an asymmetric condition between the verify operation when one or a few cells are being read and the neural read operation when all cells are being read. Summary of the Invention

[0111] Many examples of current-to-voltage converters including common-mode circuits are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0112] Figure 1 A diagram illustrating an artificial neural network.

[0113] Figure 2 A prior art split-gate flash memory cell is depicted.

[0114] Figure 3 Another prior art split-gate flash memory cell is depicted.

[0115] Figure 4 Another prior art split-gate flash memory cell is depicted.

[0116] Figure 5 Another prior art split-gate flash memory cell is depicted.

[0117] Figure 6 A diagram illustrating different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.

[0118] Figure 7 FIG. 1 is a block diagram illustrating a VMM system.

[0119] Figure 8 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems.

[0120] Figure 9 Another example of a VMM system is depicted.

[0121] Figure 10 Another example of a VMM system is depicted.

[0122] Figure 11 Another example of a VMM system is depicted.

[0123] Figure 12 Another example of a VMM system is depicted.

[0124] Figure 13 Another example of a VMM system is depicted.

[0125] Figure 14 Another example of a VMM array is depicted.

[0126] Figure 15 Another example of a VMM array is depicted.

[0127] Figure 16 Another example of a VMM array is depicted.

[0128] Figure 17 Another example of a VMM array is depicted.

[0129] Figure 18 Another example of a VMM array is depicted.

[0130] Figure 19 Another example of a VMM system is depicted.

[0131] Figure 20 Another example of a VMM array is depicted.

[0132] Figure 21 Another example of a VMM array is depicted.

[0133] Figure 22 Another example of a VMM array is depicted.

[0134] Figure 23 Another example of a VMM system is depicted.

[0135] Figure 24 Another example of a VMM system is depicted.

[0136] Figure 25 Another example of a VMM system is depicted.

[0137] Figure 26 The variation of the voltage of the bit line according to the bit line current in the prior art is depicted.

[0138] Figure 27 Depicts the VMM system.

[0139] Figure 28 Depicts the output blocks in the VMM system.

[0140] Figure 29 A current-to-voltage converter is depicted.

[0141] Figure 30 A current-to-voltage converter is depicted.

[0142] Figure 31 A current-to-voltage converter is depicted.

[0143] Figure 32 Depicted is a common-mode circuit for a current-to-voltage converter.

[0144] Figure 33 Depicted is a common-mode circuit for a current-to-voltage converter.

[0145] Figure 34 Depicted is a common-mode circuit for a current-to-voltage converter.

[0146] Figure 35 Depicted is a common-mode circuit for a current-to-voltage converter.

[0147] Figure 36 Depicted is a common-mode circuit for a current-to-voltage converter.

[0148] Figure 37 A current-to-voltage converter is depicted.

[0149] Figure 38 Depicted is the bit line conditioning circuit.

[0150] Figure 39 Depicted is the bit line conditioning circuit.

[0151] Figure 40 A bit line metal layer coupled to a current-to-voltage converter is depicted.

[0152] Figure 41 A bit line metal layer coupled to a current-to-voltage converter is depicted.

[0153] Figure 42 An operational amplifier is depicted.

[0154] Figure 43 Depicted is the portion of a current-to-voltage converter including an operational amplifier.

[0155] Figure 44 Depicts the output block.

[0156] Figure 45 Depicts the output block. DETAILED DESCRIPTION

[0157] VMM system architecture

[0158] Figure 27A block diagram of a VMM system 2700 is depicted. The VMM system 2700 includes a VMM array 2701, a redundant array 2719A (row redundant array) and a redundant array 2719B (column redundant array), a row decoder 2702, a high voltage decoder 2703, a column decoder 2704, a bit line driver 2705 (such as a bit line control circuit for programming), an input circuit 2706, an output circuit 2707, a control logic unit 2708, and a bias generator 2709. The VMM system 2700 also includes a high voltage generation block 2710, which includes a charge pump 2711, a charge pump regulator 2712, and a high voltage level generator 2713. The VMM system 2700 also includes a (program / erase or weight tuning) algorithm controller 2714, an analog circuit 2715, a control engine 2716 (which may include special functions such as arithmetic functions, activation functions, embedded microcontroller logic, but is not limited thereto), a test control logic component 2717, and a static random access memory (SRAM) block 2718 to store intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data, partial and output neuron data) or data used for programming (such as data for an entire row or multiple rows). Here, redundant arrays 2719A and 2719B are shown as being part of the same physical array as the VMM array 2701, but one of ordinary skill in the art will understand that the redundant arrays 2719A and 2719B and the VMM array 2701 may alternatively be located in separate physical arrays.

[0159] Input circuitry 2706 may include circuitry such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. Input circuitry 2706 may implement one or more of normalization, linear or nonlinear up / down scaling functions, or arithmetic functions. Input circuitry 2706 may implement a temperature compensation function for the input levels. Input circuitry 2706 may implement an activation function, such as a ReLU or a sigmoid. Input circuitry 2706 may store digital activation data to be applied as an input signal or combined with an input signal during programming or read operations. The digital activation data may be stored in registers. Input circuitry 2706 may include circuitry for driving array terminals, such as the CG, WL, EG, and SL lines, which may include sample-and-hold circuitry and buffers. The DAC may be used to convert the digital activation data into an analog input voltage to be applied to the array.

[0160] Output circuitry 2707 may include circuitry such as an ITV (current-voltage circuit), an ADC (analog-to-digital converter for converting analog neuron outputs into digital bits), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), an APC (analog-to-pulse converter or an analog-to-time modulated pulse converter), or any other type of converter. Output circuitry 2707 may convert the array output into activation data. Output circuitry 2707 may implement an activation function, such as a rectified linear activation function (ReLU) or a sigmoid. Output circuitry 2707 may implement one or more of statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for the neuron output. Output circuitry 2707 may implement a temperature compensation function for the neuron output or array output (such as a bitline output) to maintain approximately constant power consumption of the array or to improve the accuracy of the array (neuron) output, such as by maintaining approximately the same IV slope over temperature. The output circuit 2707 may include a register for storing output data.

[0161] Figure 28An output block 2800 is depicted, which receives analog signals from a VMM array and generates digital outputs. Columns in the VMM array are paired together, with one column providing a current BLW+ from a bit line W+ (which may be referred to herein as a first bit line) and one column providing a current BLW- from a bit line W- (which may be referred to herein as a second bit line). There are i column pairs, labeled column pairs 2801-1, ..., 2801-i, each pair including a W+ bit line and a W- bit line. Current-to-voltage converters 2802-1, ..., 2802-i convert the current received from the corresponding column pairs 2801-1, ..., 2801-i into corresponding voltage pairs V+ and V-. Analog-to-digital converters 2803-1, ..., 2803-i receive the voltage pairs V+ and V- from the current-to-voltage converters 2802-1, ..., 2802-i, respectively, and generate corresponding digital outputs DOUT1, ..., DOUTi. The use of differential cells (one storing a W+ value and the other storing a W value, which together store the value W according to the formula W=W+-W-) is disclosed in U.S. patent application No. 17 / 875,281 filed on July 27, 2022, which is published as US 2022 / 0374699A1 and is entitled "Precise Data Tuning Method and Apparatus for Analog Neural Memory in an Artificial Neural Network", which is incorporated herein by reference.

[0162] Figure 29 、 Figure 30 and Figure 31 Publicly available for use Figure 28 Three examples of current-to-voltage converters are shown in the output block 2800 of FIG. The inputs are currents BLW+ and BLW- from the bit lines W+ and W-, respectively, and the outputs are voltages V+ and V-. V+ and V- are complementary, which means that at the output common-mode voltage V CM (which may be ground or another voltage) around one being positive and the other being negative. The inverting and non-inverting inputs of operational amplifiers 2904, 3004, and 3106 are maintained at a common reference voltage indicated by common mode circuits 2903, 3003, and 3105, respectively.

[0163] Figure 29A current-to-voltage converter 2900 is depicted, comprising a variable resistor 2901, a variable resistor 2902, a common-mode circuit 2903, and an operational amplifier 2904. A first output of common-mode circuit 2903 is coupled to node 2905, which is coupled to the non-inverting input of operational amplifier 2904, and a second output of common-mode circuit 2903 is coupled to node 2906, which is coupled to the inverting input of operational amplifier 2904. Common-mode circuit 2903 maintains the same voltage at nodes 2905 and 2906, meaning that the voltages at the non-inverting and inverting inputs of operational amplifier 2904 are equal. Common-mode circuit 2903 receives a reference voltage VCIMREF and outputs a current Iout+ into node 2905 and a current Iout− into node 2906, where Iout+ and Iout− are equal. The equal voltages at nodes 2905 and 2906 and the equal currents Iout+ and Iout- result in a common-mode component V in the output voltage. CM , V+ and V- are centered around this common-mode component. Current-to-voltage converter 2900 converts currents BLW+ and BLW- into voltages V+ and V-. The output voltages minus the common-mode component, dV+ = V+ - VCIMREF and dV- = V- - VCIMREF, are proportional to half the difference between BLW+ and BLW- multiplied by the resistance of the corresponding feedback resistors (2901 / 2902), as follows:

[0164] dV+={(BLW+-BLW-) / 2}*R_2901, and

[0165] dV-={(BLW--BLW+) / 2}*R_2902

[0166] Figure 30A current-to-voltage converter 3000 is depicted, comprising a variable capacitor 3001, a variable capacitor 3002, a common-mode circuit 3003, and an operational amplifier 3004. A first output of the common-mode circuit 3003 is coupled to a node 3005, which is coupled to the non-inverting input of the operational amplifier 3004, and a second output of the common-mode circuit 3003 is coupled to a node 3006, which is coupled to the inverting input of the operational amplifier 2904. Common-mode circuit 3003 maintains the same voltage at nodes 3005 and 3006, meaning that the voltages at the non-inverting and inverting inputs of the operational amplifier 3004 are equal. Common-mode circuit 3003 receives a reference voltage VCIMREF and outputs a current Iout+ into node 3005 and a current Iout- into node 3006, where Iout+ = Iout-. The equal voltages at nodes 3005 and 3006 and the equal currents Iout+ and Iout- result in a common-mode component V in the output voltage. CM , V+ and V- are centered around this common-mode component. Current-to-voltage converter 3000 converts currents BLW+ and BLW- into voltages V+ and V-. The output voltages minus the common-mode component (dV+ = V+ - VCIMREF) and dV- = V- - VCIMREF) are proportional to half the difference between BLW+ and BLW- multiplied by the capacitance of the feedback capacitors (3001 / 3002), as follows:

[0167] dV+={(BLW+-BLW-) / 2}*C_3001, and

[0168] dV-={(BLW--BLW+) / 2}*C_3003

[0169] Figure 31A current-to-voltage converter 3100 is depicted, comprising a variable capacitor 3101, a variable capacitor 3102, a variable resistor 3103, a variable resistor 3104, a common-mode circuit 3105, and an operational amplifier 3106. A first output of the common-mode circuit 3105 is coupled to a node 3107, which is coupled to the non-inverting input of the operational amplifier 3106, and a second output of the common-mode circuit 3105 is coupled to a node 3108, which is coupled to the inverting input of the operational amplifier 3106. Common-mode circuit 3105 maintains the same voltage at nodes 3107 and 3108, meaning that the voltages at the non-inverting and inverting inputs of the operational amplifier 3106 are equal. Common-mode circuit 3105 receives a reference voltage VCIMREF and outputs a current Iout+ into node 3107 and a current Iout- into node 3108, where Iout+ = Iout-. The equal voltages at nodes 3107 and 3108 and the equal currents Iout+ and Iout- result in a common-mode component V in the output voltage. CM , V+ and V- are centered around this common-mode component. Current-to-voltage converter 3100 converts currents BLW+ and BLW- into voltages V+ and V-. The output voltages minus the common-mode component, dV+ = V+ - VCIMREF and dV- = V- - VCIMREF, are proportional to half the difference between BLW+ and BLW- multiplied by the resistance of the feedback resistors (3103 / 3104), as follows:

[0170] dV+={(BLW+-BLW-) / 2}*R_3101, and

[0171] dV-={(BLW--BLW+) / 2}*R_3102

[0172] Therefore, the resistors 3103 and 3104 convert the current into a voltage. After the conversion is completed, the resistors 3103 and 3104 are cut off by a switch (not shown), and the capacitors 3101 and 3102 are used to hold the converted voltage.

[0173] Figures 32 to 36 Describes the Figures 29 to 31 An example of a common-mode circuit of the common-mode circuits 2903, 3003, and 3105 in the current-voltage converters 2900, 3000, and 3100 in FIG.

[0174] Figure 32 A common mode circuit 3200 is depicted, which includes an operational amplifier 3201 (which is an example of a regulation circuit), a current source 3202, a current source 3203, a node 3204 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2905, 3005, and 3107 in ) and node 3205 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2906, 3006, and 3108 in FIG. Operational amplifier 3201 receives voltage VCIMREF as input at its non-inverting input and the voltage at node 3205 at its inverting input. Due to the high input impedance of operational amplifier 3201, no current flows from BLw- into operational amplifier 3201. Operational amplifier 3201 generates a voltage output, Vbias (voltage bias), which is applied as a bias signal to current source 3202 and current source 3203 to control their current magnitudes, Iout+ and Iout-, respectively. Operational amplifier 3201 adjusts Vbias until the voltage of bit line W- (which is the voltage at node 3205) equals VCIMREF.

[0175] Figure 33 A common mode circuit 3300 is depicted, which includes an operational amplifier 3301 (which is an example of a conditioning circuit), a variable resistor 3302, a variable resistor 3303, a node 3304 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2905, 3005, and 3107 in ) and node 3305 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2906, 3006, and 3108 in FIG. 3 are connected to the circuit breaker 3301. Vbias (voltage bias) is applied to the node between variable resistor 3302 and variable resistor 3303. The currents flowing through variable resistor 3302 and variable resistor 3303 are Iout+ and Iout-, respectively, where Iout+ = Iout-. The variable resistors are set during configuration mode to ensure that the voltages at node 3304 and node 3305 are equal, which will also cause Iout+ and Iout- to be equal. Operational amplifier 3301 receives voltage VCIMREF as an input at its non-inverting input and receives the voltage at node 3305 at its inverting input. Due to the high input impedance of operational amplifier 3301, no current flows from node 3305 (or bit line W-) into operational amplifier 3301. Operational amplifier 3301 generates a voltage output, Vbias, and will adjust Vbias until the voltage of bit line W- (which is the voltage at node 3305) is equal to VCIMREF.

[0176] Figure 34A common mode circuit 3400 is depicted, which includes an operational amplifier 3401 (which is an example of a regulation circuit), a PMOS transistor 3402, a PMOS transistor 3403, a node 3404 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2905, 3005, and 3107 in ) and node 3405 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2906, 3006, and 3108 in FIG. 1 ). Vbias (voltage bias) is applied to the nodes coupled to the gates of PMOS transistor 3402 and PMOS transistor 3403, thereby generating currents Iout+ and Iout-, where Iout+ = Iout-. The voltages at nodes 3404 and 3405 are equal. Operational amplifier 3401 receives voltage VCIMREF as an input at its non-inverting input and receives the voltage of node 3405 at its inverting input. Due to the high input impedance of operational amplifier 3401, no current flows from node 3405 (or bit line W-) into operational amplifier 3401. Operational amplifier 3401 generates a voltage output, Vbias, and will adjust Vbias until the voltage of bit line W- (which is the voltage at node 3405) is equal to VCIMREF.

[0177] Figure 35 A common mode circuit 3500 is depicted, which includes an operational amplifier 3501 (which is an example of a regulation circuit), an NMOS transistor 3502, an NMOS transistor 3503, a node 3504 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2905, 3005, and 3107 in ) and node 3505 (which corresponds to Figure 29 、 Figure 30 and Figure 31Nodes 2906, 3006, and 3108 in FIG. 1 ). Vbias (voltage bias) is applied at the node between NMOS transistor 3502 and NMOS transistor 3503, and VB is the bias voltage applied during operation to turn on NMOS transistor 3502 and NMOS transistor 3503, thereby generating currents Iout+ and Iout-, where Iout+ = Iout-. The voltages at nodes 3504 and 3505 are equal. Operational amplifier 3501 receives voltage VCIMREF as an input at its non-inverting input and receives the voltage at node 3505 at its inverting input. Due to the high input impedance of operational amplifier 3501, no current flows from node 3505 (or bit line W-) into operational amplifier 3501. Operational amplifier 3501 generates a voltage output, Vbias, and will adjust Vbias until the voltage of bit line W- (which is the voltage at node 3505) equals VREF.

[0178] Figure 36 A common mode circuit 3600 is depicted, which includes an operational amplifier 3601 (which is an example of a conditioning circuit), a variable capacitor 3602, a variable capacitor 3603, a node 3604 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2905, 3005, and 3107 in ) and node 3605 (which corresponds to Figure 29 、 Figure 30 and Figure 31 Nodes 2906, 3006, and 3108 in FIG. 1 ). Vbias (voltage bias) is applied to the node between variable capacitor 3602 and variable capacitor 3603. The currents flowing out of variable capacitor 3602 and variable capacitor 3603 are Iout+ and Iout-, respectively, where Iout+ = Iout-. The variable capacitors are set during configuration mode to ensure that the voltages at node 3604 and node 3605 are equal, which will also cause Iout+ and Iout- to be equal. Operational amplifier 3601 receives voltage VCIMREF as an input at its non-inverting input and the voltage at node 3605 at its inverting input. Due to the high input impedance of operational amplifier 3601, no current flows from node 3605 (or bit line W-) into operational amplifier 3601. Operational amplifier 3601 generates a voltage output, Vbias, and will adjust Vbias until the voltage of bit line W- (which is the voltage at node 3605) is equal to VCIMREF.

[0179] Figure 37Depicted is an example output block for column pair 3700. Only one output block of column pair 3700 is shown, but it should be understood that an instantiation of the output block of column pair 3700 will be used for each pair of columns in VMM array 2701. The output block of column pair 3700 receives current BLW+ (a first current) from one column in VMM array 2701 and current BLW- (a second current) from the other column and generates DOUTx (a digital output).

[0180] The output block of column pair 3700 includes a current-to-voltage (ITV) converter 3701 and an analog-to-digital converter (ADC) 3702. Current-to-voltage converter 3701 includes a regulator 3703 (first regulator), a regulator 3704 (second regulator), a common-mode circuit 3713, a switch 3709, a switch 3710, an NMOS transistor 3711, an NMOS transistor 3712, an operational amplifier (which may be referred to as an opamp) (an example of a regulation circuit) 3714, a switched capacitor 3715 (first capacitor), a switched resistor 3716 (first resistor), a switched resistor 3717 (second resistor), and a switched capacitor 3718 (second capacitor). Operational amplifier 3713 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing a differential voltage.

[0181] Switched capacitors 3715 and 3718 can be variable capacitors or fixed capacitors. Switched resistors 3716 and 3717 can be variable resistors or fixed resistors. Alternatively, switched capacitor 3715 and switched capacitor 3718 can be removed. Alternatively, switched resistor 3716 and switched resistor 3717 can be removed. Regulator 3703 includes switch 3706 and operational amplifier 3705 (which is an example of a regulation circuit). Regulator 3704 includes switch 3708 and operational amplifier 3707 (which is an example of a regulation circuit). BL+ regulation circuit 3720A includes regulator 3703, switch 3709, and NMOS transistor 3711. BL- regulation circuit 3720B includes regulator 3704, switch 3710, and NMOS transistor 3712.

[0182] For the circuit path connecting bit line BL+ (the first bit line), switch 3709 and switch 3706 are the portion of the column multiplexer that multiplexes the bit line from VMM array 2701 into current-to-voltage converter 3701. Specifically, the column multiplexer selects bit line BL+ by closing both switch 3706 and switch 3709. Conventional column multiplexers simply use the equivalent of switch 3709, which conducts the bit line current from VMM array 2701 to current-to-voltage converter 3701 (which may also be referred to as output circuitry or sense circuitry). The example shown here adds switch 3706, which is the portion of the sense multiplexer (YMUX-S) that does not carry current due to the high impedance of op amp 3705. In this configuration, switch 3706 and switch 3709 will have the same voltage, but switch 3709 will carry current while switch 3706 will not. When switches 3706 and 3709 are closed, the voltage of the bit line will initially be below VBLRD, which causes the output of operational amplifier 3705 to increase and turn on NMOS transistor 3711. The increase in voltage on the gate of NMOS transistor 3711 causes the voltage at the source of NMOS transistor 3711 to also increase until the voltage of the bit line equals VBLRD.

[0183] Regarding the circuit path connecting bit line BL- (the second bit line), switch 3710 and switch 3708 are the portion of the column multiplexer that multiplexes the bit line from VMM array 2701 into current-to-voltage converter 3701. Specifically, the column multiplexer selects bit line BL- by closing both switch 3708 and switch 3710. Conventional column multiplexers simply use the equivalent of switch 3710, which conducts the bit line current from VMM array 2701 to current-to-voltage converter 3701 (which may also be referred to as output circuitry or sense circuitry). The example shown here adds switch 3708, which is the portion of the sense multiplexer (YMUX-S) that does not carry current due to the high impedance of op amp 3707. In this configuration, switch 3708 and switch 3710 will have the same voltage, but switch 3710 will carry current while switch 3708 will not. When switches 3708 and 3710 are closed, the voltage of the bit line will initially be below VBLRD, which causes the output of operational amplifier 3707 to increase and turn on NMOS transistor 3712. The increase in voltage on the gate of NMOS transistor 3712 causes the voltage at the source of NMOS transistor 3712 to also increase until the voltage of the bit line equals VBLRD.

[0184] Alternatively, transistors 3711 and 3712 may be PMOS transistors instead of NMOS transistors.

[0185] Common-mode circuit 3713 specifically decouples bit line BL+ and bit line BL- via NMOS transistor 3711 and NMOS transistor 3712 (which may be referred to as bit line regulating transistors or bit line isolation transistors). Common-mode circuit 3713 will equalize the voltages provided to the inverting and non-inverting inputs of operational amplifier 3714. In contrast, without BL+ regulating circuit 3720A, BL- regulating circuit 3720B, and common-mode circuit 3713, the voltages on the lines carrying BL+ and BL- will change as the current flowing through each line changes based on the value in the attached memory cell, as shown in FIG. Figure 26 The use of BL+ regulation circuit 3720A, BL- regulation circuit 3720B, and common mode circuit 3713 results in greater accuracy in generating voltages V+ and V- from currents BL+ and BL-. It also reduces the asymmetry that would otherwise exist between verify operations (where one or a few memory cells draw current) and neural read operations (where many or all memory cells may draw current).

[0186] Figure 38 Depicted is a BL regulation circuit 3800 that can be used as Figure 37 BL regulation circuit 3800 is a replacement for one or more of BL regulation circuit 3720A and BL regulation circuit 3970B in FIG. BL regulation circuit 3800 includes regulator 3801, switch 3804, intrinsic NMOS transistor 3805, enhancement mode NMOS transistor 3806, and switch 3807. Regulator 3801 includes switch 3803 and operational amplifier 3802 (which is an example of a regulation circuit). Switches 3804 and 3803 are part of a column multiplexer that selects a particular bit line. Specifically, the column multiplexer selects the bit line by closing switch 3804 and switch 3803. Intrinsic NMOS transistor 3805 and enhancement mode NMOS transistor 3806 are enabled by the output of operational amplifier 3802 and are used for different current ranges on the bit line. For example, enhancement mode NMOS transistor 3806 may be used for low current levels in the nA range (such as during a verify operation) to limit leakage, and intrinsic NMOS transistor 3805 may be used for high current levels in the uA range (such as during a neural read operation) where many rows in the VMM are enabled.

[0187] Figure 39 Depicted is a BL regulation circuit 3900 that can be used as Figure 37BL regulation circuit 3900 is a replacement for one or more of BL regulation circuit 3720A and BL regulation circuit 3970B in FIG. BL regulation circuit 3900 includes regulator 3901, switch 3904, intrinsic NMOS transistor 3905, enhancement mode NMOS transistor 3906, and switch 3907. Regulator 3901 includes switch 3903 and operational amplifier 3902 (which is an example of a regulation circuit). Switches 3904 and 3903 are part of a column multiplexer that selects a particular bit line. Specifically, the column multiplexer selects the bit line by closing switch 3904 and switch 3903. Intrinsic NMOS transistor 3905 and enhancement mode NMOS transistor 3906 are enabled by the output of operational amplifier 3902 and are used for different current ranges on the bit line. For example, enhancement mode NMOS transistor 3906 may be used for low current levels in the nA range (such as during a verify operation) to limit leakage, and intrinsic NMOS transistor 3905 may be used for high current levels in the uA range (such as during a neural read operation) where many rows in the VMM are enabled.

[0188] Figure 40 Depicts details on how the previous example connects to the bit lines in the VMM array 2701. Here, the bit line metal layer 4010 in the VMM array 2701 is connected to the bit line in the VMM array 2701. Figure 37 Regulator 3703, switch 3709 and NMOS transistor 3711 are shown to provide BL+ or BL-.

[0189] Figure 41 Depicts details on how the VMM array 2701 can be connected to a variation of the previous example. Here, the bit line sense metal line 4111 does not carry current due to the high input impedance of the operational amplifier 4103 (which is an example of a regulation circuit) and is provided to achieve accurate bit line regulation. The bottom bit line metal layer 4110 (which is coupled to the top bit line metal layer) provides the current BL+ or BL- from the selected cell to the NMOS transistor 4105 through the switch 4104. Here, the regulator 4101 (which includes the operational amplifier 4103 and the switch 4102), the switch 4104 and the NMOS transistor 4105 replace Figure 37 Regulator 3703, switch 3709 and NMOS transistor 3711 in. Similar components are connected to Figure 37 BL- in.

[0190] Figure 42 An operational amplifier 4201 is disclosed as an example of a conditioning circuit that can be used to Figure 37 Operational amplifiers 3705, 3707, and 3714, Figure 38 and Figure 39 Operational amplifier 3802 and operational amplifier 3902 and Figure 41The operational amplifier 4201 is an example of the operational amplifier 4103 in FIG. The operational amplifier 4201 includes PMOS transistors 4202 and 4203 and NMOS transistors 4204, 4205, and 4206. The non-inverting input terminal of the operational amplifier 4201 is INP, the inverting input terminal is INN, and the output terminal is OUT.

[0191] Figure 43 Disclose how to Figure 37 An example of using an operational amplifier 4201 (which is an example of a regulating circuit) is shown here connected to a Figure 37 Switch 3706 (sense multiplexer) and switch 3709 (current carrying multiplexer) and transistor 3711 (BL adjustment transistor).

[0192] Figure 44 An example output block of a column pair 4400 that may be used during a verify operation or a read neural operation is depicted. Only one output block of column pair 4400 is shown, but it should be understood that an instantiation of the output block of column pair 4400 will be used for each pair of columns in VMM array 2701. The output block of column pair 4400 includes a current-to-voltage converter 3701 and an analog-to-digital converter 3702, which have been previously described with reference to FIG. Figure 37 4405. The output block of column pair 4400 also includes an ADC 4402, which includes a comparator 4401 and switches 4403, 4404, and 4405. ADC 3702 is used to read neural operations, and ADC 4402 is used to verify operations. Optionally, ADC 3702 and ADC 4402 can share common components such as comparator 4401 to save die space.

[0193] During a read neural operation, the output block of column pair 4400 receives current BL+ from one column and current BL- from the other column in VMM array 2701 and generates DOUTx (digital output) from ADC 3702. Regulator 3703 (first regulator) provides a first input to regulation circuit 3714, and regulation circuit 3704 (second regulator) provides a second input to regulation circuit 3714.

[0194] During a verify operation of one or more cells coupled to BL+, regulator 3703 (a first regulator) provides a first input to regulation circuit 3714, and switch 4403 is closed and switch 4404 is open, causing comparator 4401 to compare V+ with VREF_VFY, which is a reference voltage against which verification is performed, wherein the output VER_OUT from ADC 4402 indicates whether the verify operation was successful. During a verify operation of one or more cells coupled to BL-, regulator 3704 (a second regulator) provides a second input to regulation circuit 3714, and switch 4403 is open and switch 4404 is closed, causing comparator 4401 to compare V- with VREF_VFY, wherein VER_OUT indicates whether the verify operation was successful.

[0195] In this way, any offset in the conditioning circuit 3705 or conditioning circuit 3707 is replicated during the verification operation to be identical to the neural read operations for BL+ and BL-, respectively. Various systems and methods for verification are disclosed in U.S. patent application Ser. No. 18 / 080,545, filed Dec. 13, 2022, entitled "Verification Method and System in Artificial Neural Network Array," which is incorporated herein by reference.

[0196] Figure 45 An example output block of a column pair 4500 used during a verify operation is depicted. Only one output block of the column pair 4500 is shown, but it should be understood that an instantiation of the output block of the column pair 4500 will be used for each pair of columns in the VMM array 2701. The output block of the column pair 4500 receives a current BLW+ (a first current) from one column in the VMM array 2701 and a current BLW- (a second current) from the other column and generates DOUTx (a digital output). The output block of the column pair 4500 includes a current-to-voltage converter 4501, an ADC 3702 (as shown in FIG. 2 ), and a digital output. Figure 37) and ADC 4502. Current-to-voltage converter 4501 includes many of the same components as current-to-voltage converter 3701. These components have the same functions as in current-to-voltage converter 3701 and will not be described again for the sake of efficiency. Current-to-voltage converter 4501 also includes switches 4507, 4508, 4509, 4510, 4511, and 4512. ADC 3702 is used during the read neural operation, and ADC 4502 is used during the verify operation. ADC 4502 includes comparator 4503 and switch 4504. Optionally, ADC 3702 and ADC 4502 can share common components such as comparator 4503 to save die space. Alternatively, Figure 44 or Figure 45 The ADC 3702 in FIG. 3 can be used for verification operation. In this case, the digital output bits DOUTx of the ADC 3702 are used as the verification target.

[0197] During a read neural operation, the output block of column pair 4500 receives current BL+ from one column and current BL- from the other column in VMM array 2701 and generates DOUTx (digital output) from ADC 3702. Regulator 4521 (first regulator) provides a first input to regulation circuit 3714, and regulator 4522 (second regulator) provides a second input to regulation circuit 3714.

[0198] During a verification operation of one or more cells coupled to BL+, regulator 4521 (first regulator) provides a first input to the regulation circuit 3714, and switches 4504, 4505, 4507, 4508, 4511, and 4512 are closed, and switches 4506, 4509, and 4510 are open, so that comparator 4503 compares V+ with VREF_VFY, which is a reference voltage against which verification is performed, where the output VER_OUT from ADC 4502 indicates whether the verification operation is successful.

[0199] During a verify operation of one or more cells coupled to BL-, regulator 4522 (second regulator) provides a second input to regulation circuit 3714, and switches 4504, 4506, 4508, 4509, 4510, and 4512 are closed, and switches 4505, 4507, and 4511 are open, causing comparator 4503 to compare V- with VREF_VFY, where VER_OUT indicates whether the verify operation was successful.

[0200] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly on" (intervening materials, elements, or spaces disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly adjacent" (intervening materials, elements, or spaces disposed therebetween), "mounted to" includes "directly mounted to" (no intervening materials, elements, or spaces disposed therebetween) and "indirectly mounted to" (intervening materials, elements, or spaces disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (no intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (intervening materials or elements electrically connecting the elements together). For example, forming an element "above" a substrate may include forming the element directly on the substrate without intervening materials / elements therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A system, comprising: A current-voltage converter for generating a differential voltage from a differential current including a first current and a second current, the current-voltage converter comprising: a first bit line, the first bit line being configured to provide the first current; a second bit line, the second bit line being configured to provide the second current; a first regulator configured to apply a first voltage to the first bit line; a second regulator configured to apply a second voltage to the second bit line; a regulation circuit comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltage; and a common mode circuit comprising a first terminal coupled to the first bit line and the first input terminal of the regulation circuit and a second terminal coupled to the second bit line and the second input terminal of the regulation circuit ， The common mode circuit maintains the same voltage at the first terminal and the second terminal.

2. The system according to claim 1, comprising: An analog-to-digital converter is configured to convert the generated differential voltage into a digital output.

3. The system of claim 1, wherein the conditioning circuit is an operational amplifier.

4. The system according to claim 3, comprising: a first resistor coupled between the first input terminal of the operational amplifier and the first output terminal of the operational amplifier; and A second resistor is coupled between the second input terminal of the operational amplifier and the second output terminal of the operational amplifier. 5 . The system of claim 4 , wherein the first resistor is a fixed resistor and the second resistor is a fixed resistor. 6 . The system of claim 4 , wherein the first resistor is a first variable resistor and the second resistor is a second variable resistor.

7. The system according to claim 4, comprising: a first capacitor coupled between the first input terminal of the operational amplifier and the first output terminal of the operational amplifier; and A second capacitor is coupled between the second input terminal of the operational amplifier and the second output terminal of the operational amplifier.

8. The system of claim 7, wherein the first capacitor is a first fixed capacitor and the second capacitor is a second fixed capacitor.

9. The system of claim 7, wherein the first capacitor is a first variable capacitor and the second capacitor is a second variable capacitor.

10. The system according to claim 3, comprising: a first capacitor coupled between the first input terminal of the operational amplifier and the first output terminal of the operational amplifier; and A second capacitor is coupled between the second input terminal of the operational amplifier and the second output terminal of the operational amplifier.

11. The system of claim 10, wherein the first capacitor is a first fixed capacitor and the second capacitor is a second fixed capacitor.

12. The system of claim 10, wherein the first capacitor is a first variable capacitor and the second capacitor is a second variable capacitor.

13. The system of claim 1, wherein the common mode circuit comprises a first current source for receiving a bias voltage and a second current source for receiving the bias voltage.

14. The system of claim 1, wherein the common mode circuit comprises a first variable resistor and a second variable resistor, the first variable resistor and the second variable resistor configured to receive a bias voltage. 15 . The system of claim 1 , wherein the common mode circuit comprises a first PMOS transistor and a second PMOS transistor, the first PMOS transistor and the second PMOS transistor configured to receive a bias voltage. 16 . The system of claim 1 , wherein the common mode circuit comprises a first NMOS transistor and a second NMOS transistor, the first NMOS transistor and the second NMOS transistor configured to receive a bias voltage.

17. The system of claim 1, wherein the common mode circuit comprises a first capacitor and a second capacitor, the first capacitor and the second capacitor configured to receive a bias voltage.

18. A system comprising: A bit line regulation circuit, the bit line regulation circuit comprising: a first set of switches coupled to the bit lines; and a second set of switches coupled to the bit line; The bit line conditioning circuit receives a first input from the first set of switches and a second input from the second set of switches, the first input including a voltage and a current and the second input including a voltage and not including a current.

19. The system of claim 18, wherein the bit line conditioning circuit comprises an enhancement mode NMOS transistor.

20. The system of claim 18, wherein the bit line conditioning circuit comprises a native NMOS transistor.

21. The system of claim 18, wherein the bit line conditioning circuit comprises an enhancement mode NMOS transistor, an intrinsic NMOS transistor, and a PMOS transistor for receiving different ranges of current from the bit line.

22. The system of claim 18, wherein the system includes a current-to-voltage converter and the bit line conditioning circuit is part of the current-to-voltage converter.

23. The system of claim 22, comprising an analog-to-digital converter.

24. The system of claim 22, comprising a neural memory array.

25. The system of claim 24, wherein the bit line conditioning circuit is used during a verify operation of the neural memory array using the first input or the second input.

26. A system comprising: An array of memory cells arranged in rows and columns includes bit lines coupled to respective columns in the array, the respective bit lines including a sensing bit line metal layer and a current carrying metal layer, wherein the sensing bit line metal layer does not carry current.

27. The system of claim 26, comprising a bit line conditioning circuit coupled to the sensing bit line metal layer and the current carrying metal layer.

28. The system of claim 27, comprising an analog-to-digital converter.

29. A system comprising: An output block, the output block comprising: a first regulator comprising a first operational amplifier and a first set of switches coupled to a first bit line, the first regulator configured to receive a W+ value; a second regulator comprising a second operational amplifier and a second set of switches coupled to a second bit line, the second regulator configured to receive a W-value, wherein a weight W=W+-W-; and a regulation circuit to receive a first input from the first regulator and a second input from the second regulator and comprising one or more of a feedback resistor and a feedback capacitor; wherein the first regulator provides the regulating circuit with a voltage level during a verify operation of one or more memory cells coupled to the first bit line. The first input, and the second regulator provides the second input to the regulation circuit during a verify operation of one or more memory cells coupled to the second bit line; and During a read neural operation, the first regulator provides the first input to the regulation circuit, and the second regulator provides the second input to the regulation circuit.

30. The system of claim 29, wherein during a verify operation of one or more memory cells coupled to the first bit line, the first operational amplifier is coupled to the regulating circuit through a first bit line regulating transistor, and during a verify operation of one or more memory cells coupled to the second bit line, the second operational amplifier is coupled to the regulating circuit through the first bit line regulating transistor.

31. The system of claim 29, wherein the conditioning circuit comprises a differential operational amplifier.

32. A method comprising: coupling the first bit line to a first operational amplifier, and coupling the first operational amplifier to a differential amplifier through a first regulating transistor, during a verify operation of one or more memory cells coupled to the first bit line; and During a verify operation of one or more memory cells coupled to a second bit line, the second bit line is coupled to a second operational amplifier, and the second operational amplifier is coupled to the differential amplifier through the first regulating transistor.

33. The method of claim 32, comprising: During a neural read operation, coupling the first bit line to the first operational amplifier, and coupling the first operational amplifier to the differential amplifier through the first regulating transistor; and During the neural read operation, the second bit line is coupled to the second operational amplifier, and the second operational amplifier is coupled to the differential amplifier through a second regulating transistor.

Images